KVM: Call ack notifiers from PIC when guest OS acks an IRQ.
[linux-3.10.git] / arch / x86 / kvm / i8259.c
1 /*
2  * 8259 interrupt controller emulation
3  *
4  * Copyright (c) 2003-2004 Fabrice Bellard
5  * Copyright (c) 2007 Intel Corporation
6  *
7  * Permission is hereby granted, free of charge, to any person obtaining a copy
8  * of this software and associated documentation files (the "Software"), to deal
9  * in the Software without restriction, including without limitation the rights
10  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11  * copies of the Software, and to permit persons to whom the Software is
12  * furnished to do so, subject to the following conditions:
13  *
14  * The above copyright notice and this permission notice shall be included in
15  * all copies or substantial portions of the Software.
16  *
17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23  * THE SOFTWARE.
24  * Authors:
25  *   Yaozu (Eddie) Dong <Eddie.dong@intel.com>
26  *   Port from Qemu.
27  */
28 #include <linux/mm.h>
29 #include <linux/bitops.h>
30 #include "irq.h"
31
32 #include <linux/kvm_host.h>
33 #include "trace.h"
34
35 static void pic_lock(struct kvm_pic *s)
36         __acquires(&s->lock)
37 {
38         spin_lock(&s->lock);
39 }
40
41 static void pic_unlock(struct kvm_pic *s)
42         __releases(&s->lock)
43 {
44         spin_unlock(&s->lock);
45 }
46
47 static void pic_clear_isr(struct kvm_kpic_state *s, int irq)
48 {
49         s->isr &= ~(1 << irq);
50         s->isr_ack |= (1 << irq);
51         if (s != &s->pics_state->pics[0])
52                 irq += 8;
53         kvm_notify_acked_irq(s->pics_state->kvm, SELECT_PIC(irq), irq);
54 }
55
56 void kvm_pic_clear_isr_ack(struct kvm *kvm)
57 {
58         struct kvm_pic *s = pic_irqchip(kvm);
59         pic_lock(s);
60         s->pics[0].isr_ack = 0xff;
61         s->pics[1].isr_ack = 0xff;
62         pic_unlock(s);
63 }
64
65 /*
66  * set irq level. If an edge is detected, then the IRR is set to 1
67  */
68 static inline int pic_set_irq1(struct kvm_kpic_state *s, int irq, int level)
69 {
70         int mask, ret = 1;
71         mask = 1 << irq;
72         if (s->elcr & mask)     /* level triggered */
73                 if (level) {
74                         ret = !(s->irr & mask);
75                         s->irr |= mask;
76                         s->last_irr |= mask;
77                 } else {
78                         s->irr &= ~mask;
79                         s->last_irr &= ~mask;
80                 }
81         else    /* edge triggered */
82                 if (level) {
83                         if ((s->last_irr & mask) == 0) {
84                                 ret = !(s->irr & mask);
85                                 s->irr |= mask;
86                         }
87                         s->last_irr |= mask;
88                 } else
89                         s->last_irr &= ~mask;
90
91         return (s->imr & mask) ? -1 : ret;
92 }
93
94 /*
95  * return the highest priority found in mask (highest = smallest
96  * number). Return 8 if no irq
97  */
98 static inline int get_priority(struct kvm_kpic_state *s, int mask)
99 {
100         int priority;
101         if (mask == 0)
102                 return 8;
103         priority = 0;
104         while ((mask & (1 << ((priority + s->priority_add) & 7))) == 0)
105                 priority++;
106         return priority;
107 }
108
109 /*
110  * return the pic wanted interrupt. return -1 if none
111  */
112 static int pic_get_irq(struct kvm_kpic_state *s)
113 {
114         int mask, cur_priority, priority;
115
116         mask = s->irr & ~s->imr;
117         priority = get_priority(s, mask);
118         if (priority == 8)
119                 return -1;
120         /*
121          * compute current priority. If special fully nested mode on the
122          * master, the IRQ coming from the slave is not taken into account
123          * for the priority computation.
124          */
125         mask = s->isr;
126         if (s->special_fully_nested_mode && s == &s->pics_state->pics[0])
127                 mask &= ~(1 << 2);
128         cur_priority = get_priority(s, mask);
129         if (priority < cur_priority)
130                 /*
131                  * higher priority found: an irq should be generated
132                  */
133                 return (priority + s->priority_add) & 7;
134         else
135                 return -1;
136 }
137
138 /*
139  * raise irq to CPU if necessary. must be called every time the active
140  * irq may change
141  */
142 static void pic_update_irq(struct kvm_pic *s)
143 {
144         int irq2, irq;
145
146         irq2 = pic_get_irq(&s->pics[1]);
147         if (irq2 >= 0) {
148                 /*
149                  * if irq request by slave pic, signal master PIC
150                  */
151                 pic_set_irq1(&s->pics[0], 2, 1);
152                 pic_set_irq1(&s->pics[0], 2, 0);
153         }
154         irq = pic_get_irq(&s->pics[0]);
155         if (irq >= 0)
156                 s->irq_request(s->irq_request_opaque, 1);
157         else
158                 s->irq_request(s->irq_request_opaque, 0);
159 }
160
161 void kvm_pic_update_irq(struct kvm_pic *s)
162 {
163         pic_lock(s);
164         pic_update_irq(s);
165         pic_unlock(s);
166 }
167
168 int kvm_pic_set_irq(void *opaque, int irq, int level)
169 {
170         struct kvm_pic *s = opaque;
171         int ret = -1;
172
173         pic_lock(s);
174         if (irq >= 0 && irq < PIC_NUM_PINS) {
175                 ret = pic_set_irq1(&s->pics[irq >> 3], irq & 7, level);
176                 pic_update_irq(s);
177                 trace_kvm_pic_set_irq(irq >> 3, irq & 7, s->pics[irq >> 3].elcr,
178                                       s->pics[irq >> 3].imr, ret == 0);
179         }
180         pic_unlock(s);
181
182         return ret;
183 }
184
185 /*
186  * acknowledge interrupt 'irq'
187  */
188 static inline void pic_intack(struct kvm_kpic_state *s, int irq)
189 {
190         s->isr |= 1 << irq;
191         if (s->auto_eoi) {
192                 if (s->rotate_on_auto_eoi)
193                         s->priority_add = (irq + 1) & 7;
194                 pic_clear_isr(s, irq);
195         }
196         /*
197          * We don't clear a level sensitive interrupt here
198          */
199         if (!(s->elcr & (1 << irq)))
200                 s->irr &= ~(1 << irq);
201 }
202
203 int kvm_pic_read_irq(struct kvm *kvm)
204 {
205         int irq, irq2, intno;
206         struct kvm_pic *s = pic_irqchip(kvm);
207
208         pic_lock(s);
209         irq = pic_get_irq(&s->pics[0]);
210         if (irq >= 0) {
211                 pic_intack(&s->pics[0], irq);
212                 if (irq == 2) {
213                         irq2 = pic_get_irq(&s->pics[1]);
214                         if (irq2 >= 0)
215                                 pic_intack(&s->pics[1], irq2);
216                         else
217                                 /*
218                                  * spurious IRQ on slave controller
219                                  */
220                                 irq2 = 7;
221                         intno = s->pics[1].irq_base + irq2;
222                         irq = irq2 + 8;
223                 } else
224                         intno = s->pics[0].irq_base + irq;
225         } else {
226                 /*
227                  * spurious IRQ on host controller
228                  */
229                 irq = 7;
230                 intno = s->pics[0].irq_base + irq;
231         }
232         pic_update_irq(s);
233         pic_unlock(s);
234
235         return intno;
236 }
237
238 void kvm_pic_reset(struct kvm_kpic_state *s)
239 {
240         int irq, irqbase, n;
241         struct kvm *kvm = s->pics_state->irq_request_opaque;
242         struct kvm_vcpu *vcpu0 = kvm->bsp_vcpu;
243
244         if (s == &s->pics_state->pics[0])
245                 irqbase = 0;
246         else
247                 irqbase = 8;
248
249         for (irq = 0; irq < PIC_NUM_PINS/2; irq++) {
250                 if (vcpu0 && kvm_apic_accept_pic_intr(vcpu0))
251                         if (s->irr & (1 << irq) || s->isr & (1 << irq)) {
252                                 n = irq + irqbase;
253                                 kvm_notify_acked_irq(kvm, SELECT_PIC(n), n);
254                         }
255         }
256         s->last_irr = 0;
257         s->irr = 0;
258         s->imr = 0;
259         s->isr = 0;
260         s->isr_ack = 0xff;
261         s->priority_add = 0;
262         s->irq_base = 0;
263         s->read_reg_select = 0;
264         s->poll = 0;
265         s->special_mask = 0;
266         s->init_state = 0;
267         s->auto_eoi = 0;
268         s->rotate_on_auto_eoi = 0;
269         s->special_fully_nested_mode = 0;
270         s->init4 = 0;
271 }
272
273 static void pic_ioport_write(void *opaque, u32 addr, u32 val)
274 {
275         struct kvm_kpic_state *s = opaque;
276         int priority, cmd, irq;
277
278         addr &= 1;
279         if (addr == 0) {
280                 if (val & 0x10) {
281                         kvm_pic_reset(s);       /* init */
282                         /*
283                          * deassert a pending interrupt
284                          */
285                         s->pics_state->irq_request(s->pics_state->
286                                                    irq_request_opaque, 0);
287                         s->init_state = 1;
288                         s->init4 = val & 1;
289                         if (val & 0x02)
290                                 printk(KERN_ERR "single mode not supported");
291                         if (val & 0x08)
292                                 printk(KERN_ERR
293                                        "level sensitive irq not supported");
294                 } else if (val & 0x08) {
295                         if (val & 0x04)
296                                 s->poll = 1;
297                         if (val & 0x02)
298                                 s->read_reg_select = val & 1;
299                         if (val & 0x40)
300                                 s->special_mask = (val >> 5) & 1;
301                 } else {
302                         cmd = val >> 5;
303                         switch (cmd) {
304                         case 0:
305                         case 4:
306                                 s->rotate_on_auto_eoi = cmd >> 2;
307                                 break;
308                         case 1: /* end of interrupt */
309                         case 5:
310                                 priority = get_priority(s, s->isr);
311                                 if (priority != 8) {
312                                         irq = (priority + s->priority_add) & 7;
313                                         pic_clear_isr(s, irq);
314                                         if (cmd == 5)
315                                                 s->priority_add = (irq + 1) & 7;
316                                         pic_update_irq(s->pics_state);
317                                 }
318                                 break;
319                         case 3:
320                                 irq = val & 7;
321                                 pic_clear_isr(s, irq);
322                                 pic_update_irq(s->pics_state);
323                                 break;
324                         case 6:
325                                 s->priority_add = (val + 1) & 7;
326                                 pic_update_irq(s->pics_state);
327                                 break;
328                         case 7:
329                                 irq = val & 7;
330                                 s->priority_add = (irq + 1) & 7;
331                                 pic_clear_isr(s, irq);
332                                 pic_update_irq(s->pics_state);
333                                 break;
334                         default:
335                                 break;  /* no operation */
336                         }
337                 }
338         } else
339                 switch (s->init_state) {
340                 case 0:         /* normal mode */
341                         s->imr = val;
342                         pic_update_irq(s->pics_state);
343                         break;
344                 case 1:
345                         s->irq_base = val & 0xf8;
346                         s->init_state = 2;
347                         break;
348                 case 2:
349                         if (s->init4)
350                                 s->init_state = 3;
351                         else
352                                 s->init_state = 0;
353                         break;
354                 case 3:
355                         s->special_fully_nested_mode = (val >> 4) & 1;
356                         s->auto_eoi = (val >> 1) & 1;
357                         s->init_state = 0;
358                         break;
359                 }
360 }
361
362 static u32 pic_poll_read(struct kvm_kpic_state *s, u32 addr1)
363 {
364         int ret;
365
366         ret = pic_get_irq(s);
367         if (ret >= 0) {
368                 if (addr1 >> 7) {
369                         s->pics_state->pics[0].isr &= ~(1 << 2);
370                         s->pics_state->pics[0].irr &= ~(1 << 2);
371                 }
372                 s->irr &= ~(1 << ret);
373                 pic_clear_isr(s, ret);
374                 if (addr1 >> 7 || ret != 2)
375                         pic_update_irq(s->pics_state);
376         } else {
377                 ret = 0x07;
378                 pic_update_irq(s->pics_state);
379         }
380
381         return ret;
382 }
383
384 static u32 pic_ioport_read(void *opaque, u32 addr1)
385 {
386         struct kvm_kpic_state *s = opaque;
387         unsigned int addr;
388         int ret;
389
390         addr = addr1;
391         addr &= 1;
392         if (s->poll) {
393                 ret = pic_poll_read(s, addr1);
394                 s->poll = 0;
395         } else
396                 if (addr == 0)
397                         if (s->read_reg_select)
398                                 ret = s->isr;
399                         else
400                                 ret = s->irr;
401                 else
402                         ret = s->imr;
403         return ret;
404 }
405
406 static void elcr_ioport_write(void *opaque, u32 addr, u32 val)
407 {
408         struct kvm_kpic_state *s = opaque;
409         s->elcr = val & s->elcr_mask;
410 }
411
412 static u32 elcr_ioport_read(void *opaque, u32 addr1)
413 {
414         struct kvm_kpic_state *s = opaque;
415         return s->elcr;
416 }
417
418 static int picdev_in_range(gpa_t addr)
419 {
420         switch (addr) {
421         case 0x20:
422         case 0x21:
423         case 0xa0:
424         case 0xa1:
425         case 0x4d0:
426         case 0x4d1:
427                 return 1;
428         default:
429                 return 0;
430         }
431 }
432
433 static inline struct kvm_pic *to_pic(struct kvm_io_device *dev)
434 {
435         return container_of(dev, struct kvm_pic, dev);
436 }
437
438 static int picdev_write(struct kvm_io_device *this,
439                          gpa_t addr, int len, const void *val)
440 {
441         struct kvm_pic *s = to_pic(this);
442         unsigned char data = *(unsigned char *)val;
443         if (!picdev_in_range(addr))
444                 return -EOPNOTSUPP;
445
446         if (len != 1) {
447                 if (printk_ratelimit())
448                         printk(KERN_ERR "PIC: non byte write\n");
449                 return 0;
450         }
451         pic_lock(s);
452         switch (addr) {
453         case 0x20:
454         case 0x21:
455         case 0xa0:
456         case 0xa1:
457                 pic_ioport_write(&s->pics[addr >> 7], addr, data);
458                 break;
459         case 0x4d0:
460         case 0x4d1:
461                 elcr_ioport_write(&s->pics[addr & 1], addr, data);
462                 break;
463         }
464         pic_unlock(s);
465         return 0;
466 }
467
468 static int picdev_read(struct kvm_io_device *this,
469                        gpa_t addr, int len, void *val)
470 {
471         struct kvm_pic *s = to_pic(this);
472         unsigned char data = 0;
473         if (!picdev_in_range(addr))
474                 return -EOPNOTSUPP;
475
476         if (len != 1) {
477                 if (printk_ratelimit())
478                         printk(KERN_ERR "PIC: non byte read\n");
479                 return 0;
480         }
481         pic_lock(s);
482         switch (addr) {
483         case 0x20:
484         case 0x21:
485         case 0xa0:
486         case 0xa1:
487                 data = pic_ioport_read(&s->pics[addr >> 7], addr);
488                 break;
489         case 0x4d0:
490         case 0x4d1:
491                 data = elcr_ioport_read(&s->pics[addr & 1], addr);
492                 break;
493         }
494         *(unsigned char *)val = data;
495         pic_unlock(s);
496         return 0;
497 }
498
499 /*
500  * callback when PIC0 irq status changed
501  */
502 static void pic_irq_request(void *opaque, int level)
503 {
504         struct kvm *kvm = opaque;
505         struct kvm_vcpu *vcpu = kvm->bsp_vcpu;
506         struct kvm_pic *s = pic_irqchip(kvm);
507         int irq = pic_get_irq(&s->pics[0]);
508
509         s->output = level;
510         if (vcpu && level && (s->pics[0].isr_ack & (1 << irq))) {
511                 s->pics[0].isr_ack &= ~(1 << irq);
512                 kvm_vcpu_kick(vcpu);
513         }
514 }
515
516 static const struct kvm_io_device_ops picdev_ops = {
517         .read     = picdev_read,
518         .write    = picdev_write,
519 };
520
521 struct kvm_pic *kvm_create_pic(struct kvm *kvm)
522 {
523         struct kvm_pic *s;
524         int ret;
525
526         s = kzalloc(sizeof(struct kvm_pic), GFP_KERNEL);
527         if (!s)
528                 return NULL;
529         spin_lock_init(&s->lock);
530         s->kvm = kvm;
531         s->pics[0].elcr_mask = 0xf8;
532         s->pics[1].elcr_mask = 0xde;
533         s->irq_request = pic_irq_request;
534         s->irq_request_opaque = kvm;
535         s->pics[0].pics_state = s;
536         s->pics[1].pics_state = s;
537
538         /*
539          * Initialize PIO device
540          */
541         kvm_iodevice_init(&s->dev, &picdev_ops);
542         ret = kvm_io_bus_register_dev(kvm, &kvm->pio_bus, &s->dev);
543         if (ret < 0) {
544                 kfree(s);
545                 return NULL;
546         }
547
548         return s;
549 }