2 * SGI RTC clock/timer routines.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 * Copyright (c) 2009 Silicon Graphics, Inc. All Rights Reserved.
19 * Copyright (c) Dimitri Sivanich
21 #include <linux/clockchips.h>
23 #include <asm/uv/uv_mmrs.h>
24 #include <asm/uv/uv_hub.h>
25 #include <asm/uv/bios.h>
26 #include <asm/uv/uv.h>
30 #define RTC_NAME "sgi_rtc"
32 static cycle_t uv_read_rtc(struct clocksource *cs);
33 static int uv_rtc_next_event(unsigned long, struct clock_event_device *);
34 static void uv_rtc_timer_setup(enum clock_event_mode,
35 struct clock_event_device *);
37 static struct clocksource clocksource_uv = {
41 .mask = (cycle_t)UVH_RTC_REAL_TIME_CLOCK_MASK,
43 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
46 static struct clock_event_device clock_event_device_uv = {
48 .features = CLOCK_EVT_FEAT_ONESHOT,
52 .set_next_event = uv_rtc_next_event,
53 .set_mode = uv_rtc_timer_setup,
54 .event_handler = NULL,
57 static DEFINE_PER_CPU(struct clock_event_device, cpu_ced);
59 /* There is one of these allocated per node */
60 struct uv_rtc_timer_head {
62 /* next cpu waiting for timer, local node relative: */
64 /* number of cpus on this node: */
67 int lcpu; /* systemwide logical cpu number */
68 u64 expires; /* next timer expiration for this cpu */
73 * Access to uv_rtc_timer_head via blade id.
75 static struct uv_rtc_timer_head **blade_info __read_mostly;
77 static int uv_rtc_enable;
78 static int uv_rtc_evt_enable;
81 * Hardware interface routines
84 /* Send IPIs to another node */
85 static void uv_rtc_send_IPI(int cpu)
87 unsigned long apicid, val;
90 apicid = cpu_physical_id(cpu);
91 pnode = uv_apicid_to_pnode(apicid);
92 val = (1UL << UVH_IPI_INT_SEND_SHFT) |
93 (apicid << UVH_IPI_INT_APIC_ID_SHFT) |
94 (GENERIC_INTERRUPT_VECTOR << UVH_IPI_INT_VECTOR_SHFT);
96 uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
99 /* Check for an RTC interrupt pending */
100 static int uv_intr_pending(int pnode)
102 return uv_read_global_mmr64(pnode, UVH_EVENT_OCCURRED0) &
103 UVH_EVENT_OCCURRED0_RTC1_MASK;
106 /* Setup interrupt and return non-zero if early expiration occurred. */
107 static int uv_setup_intr(int cpu, u64 expires)
110 int pnode = uv_cpu_to_pnode(cpu);
112 uv_write_global_mmr64(pnode, UVH_RTC1_INT_CONFIG,
113 UVH_RTC1_INT_CONFIG_M_MASK);
114 uv_write_global_mmr64(pnode, UVH_INT_CMPB, -1L);
116 uv_write_global_mmr64(pnode, UVH_EVENT_OCCURRED0_ALIAS,
117 UVH_EVENT_OCCURRED0_RTC1_MASK);
119 val = (GENERIC_INTERRUPT_VECTOR << UVH_RTC1_INT_CONFIG_VECTOR_SHFT) |
120 ((u64)cpu_physical_id(cpu) << UVH_RTC1_INT_CONFIG_APIC_ID_SHFT);
122 /* Set configuration */
123 uv_write_global_mmr64(pnode, UVH_RTC1_INT_CONFIG, val);
124 /* Initialize comparator value */
125 uv_write_global_mmr64(pnode, UVH_INT_CMPB, expires);
127 if (uv_read_rtc(NULL) <= expires)
130 return !uv_intr_pending(pnode);
134 * Per-cpu timer tracking routines
137 static __init void uv_rtc_deallocate_timers(void)
141 for_each_possible_blade(bid) {
142 kfree(blade_info[bid]);
147 /* Allocate per-node list of cpu timer expiration times. */
148 static __init int uv_rtc_allocate_timers(void)
152 blade_info = kmalloc(uv_possible_blades * sizeof(void *), GFP_KERNEL);
155 memset(blade_info, 0, uv_possible_blades * sizeof(void *));
157 for_each_present_cpu(cpu) {
158 int nid = cpu_to_node(cpu);
159 int bid = uv_cpu_to_blade_id(cpu);
160 int bcpu = uv_cpu_hub_info(cpu)->blade_processor_id;
161 struct uv_rtc_timer_head *head = blade_info[bid];
164 head = kmalloc_node(sizeof(struct uv_rtc_timer_head) +
165 (uv_blade_nr_possible_cpus(bid) *
169 uv_rtc_deallocate_timers();
172 spin_lock_init(&head->lock);
173 head->ncpus = uv_blade_nr_possible_cpus(bid);
175 blade_info[bid] = head;
178 head->cpu[bcpu].lcpu = cpu;
179 head->cpu[bcpu].expires = ULLONG_MAX;
185 /* Find and set the next expiring timer. */
186 static void uv_rtc_find_next_timer(struct uv_rtc_timer_head *head, int pnode)
188 u64 lowest = ULLONG_MAX;
192 for (c = 0; c < head->ncpus; c++) {
193 u64 exp = head->cpu[c].expires;
200 head->next_cpu = bcpu;
201 c = head->cpu[bcpu].lcpu;
202 if (uv_setup_intr(c, lowest))
203 /* If we didn't set it up in time, trigger */
206 uv_write_global_mmr64(pnode, UVH_RTC1_INT_CONFIG,
207 UVH_RTC1_INT_CONFIG_M_MASK);
212 * Set expiration time for current cpu.
214 * Returns 1 if we missed the expiration time.
216 static int uv_rtc_set_timer(int cpu, u64 expires)
218 int pnode = uv_cpu_to_pnode(cpu);
219 int bid = uv_cpu_to_blade_id(cpu);
220 struct uv_rtc_timer_head *head = blade_info[bid];
221 int bcpu = uv_cpu_hub_info(cpu)->blade_processor_id;
222 u64 *t = &head->cpu[bcpu].expires;
226 spin_lock_irqsave(&head->lock, flags);
228 next_cpu = head->next_cpu;
231 /* Will this one be next to go off? */
232 if (next_cpu < 0 || bcpu == next_cpu ||
233 expires < head->cpu[next_cpu].expires) {
234 head->next_cpu = bcpu;
235 if (uv_setup_intr(cpu, expires)) {
237 uv_rtc_find_next_timer(head, pnode);
238 spin_unlock_irqrestore(&head->lock, flags);
243 spin_unlock_irqrestore(&head->lock, flags);
248 * Unset expiration time for current cpu.
250 * Returns 1 if this timer was pending.
252 static int uv_rtc_unset_timer(int cpu, int force)
254 int pnode = uv_cpu_to_pnode(cpu);
255 int bid = uv_cpu_to_blade_id(cpu);
256 struct uv_rtc_timer_head *head = blade_info[bid];
257 int bcpu = uv_cpu_hub_info(cpu)->blade_processor_id;
258 u64 *t = &head->cpu[bcpu].expires;
262 spin_lock_irqsave(&head->lock, flags);
264 if ((head->next_cpu == bcpu && uv_read_rtc(NULL) >= *t) || force)
269 /* Was the hardware setup for this timer? */
270 if (head->next_cpu == bcpu)
271 uv_rtc_find_next_timer(head, pnode);
274 spin_unlock_irqrestore(&head->lock, flags);
281 * Kernel interface routines.
287 static cycle_t uv_read_rtc(struct clocksource *cs)
289 return (cycle_t)uv_read_local_mmr(UVH_RTC);
293 * Program the next event, relative to now
295 static int uv_rtc_next_event(unsigned long delta,
296 struct clock_event_device *ced)
298 int ced_cpu = cpumask_first(ced->cpumask);
300 return uv_rtc_set_timer(ced_cpu, delta + uv_read_rtc(NULL));
304 * Setup the RTC timer in oneshot mode
306 static void uv_rtc_timer_setup(enum clock_event_mode mode,
307 struct clock_event_device *evt)
309 int ced_cpu = cpumask_first(evt->cpumask);
312 case CLOCK_EVT_MODE_PERIODIC:
313 case CLOCK_EVT_MODE_ONESHOT:
314 case CLOCK_EVT_MODE_RESUME:
315 /* Nothing to do here yet */
317 case CLOCK_EVT_MODE_UNUSED:
318 case CLOCK_EVT_MODE_SHUTDOWN:
319 uv_rtc_unset_timer(ced_cpu, 1);
324 static void uv_rtc_interrupt(void)
326 int cpu = smp_processor_id();
327 struct clock_event_device *ced = &per_cpu(cpu_ced, cpu);
329 if (!ced || !ced->event_handler)
332 if (uv_rtc_unset_timer(cpu, 0) != 1)
335 ced->event_handler(ced);
338 static int __init uv_enable_rtc(char *str)
344 __setup("uvrtc", uv_enable_rtc);
346 static int __init uv_enable_evt_rtc(char *str)
348 uv_rtc_evt_enable = 1;
352 __setup("uvrtcevt", uv_enable_evt_rtc);
354 static __init void uv_rtc_register_clockevents(struct work_struct *dummy)
356 struct clock_event_device *ced = &__get_cpu_var(cpu_ced);
358 *ced = clock_event_device_uv;
359 ced->cpumask = cpumask_of(smp_processor_id());
360 clockevents_register_device(ced);
363 static __init int uv_rtc_setup_clock(void)
367 if (!uv_rtc_enable || !is_uv_system() || generic_interrupt_extension)
370 clocksource_uv.mult = clocksource_hz2mult(sn_rtc_cycles_per_second,
371 clocksource_uv.shift);
373 rc = clocksource_register(&clocksource_uv);
375 printk(KERN_INFO "UV RTC clocksource failed rc %d\n", rc);
377 printk(KERN_INFO "UV RTC clocksource registered freq %lu MHz\n",
378 sn_rtc_cycles_per_second/(unsigned long)1E6);
380 if (rc || !uv_rtc_evt_enable)
383 /* Setup and register clockevents */
384 rc = uv_rtc_allocate_timers();
388 generic_interrupt_extension = uv_rtc_interrupt;
390 clock_event_device_uv.mult = div_sc(sn_rtc_cycles_per_second,
391 NSEC_PER_SEC, clock_event_device_uv.shift);
393 clock_event_device_uv.min_delta_ns = NSEC_PER_SEC /
394 sn_rtc_cycles_per_second;
396 clock_event_device_uv.max_delta_ns = clocksource_uv.mask *
397 (NSEC_PER_SEC / sn_rtc_cycles_per_second);
399 rc = schedule_on_each_cpu(uv_rtc_register_clockevents);
401 generic_interrupt_extension = NULL;
402 uv_rtc_deallocate_timers();
406 printk(KERN_INFO "UV RTC clockevents registered\n");
411 clocksource_unregister(&clocksource_uv);
412 printk(KERN_INFO "UV RTC clockevents failed rc %d\n", rc);
416 arch_initcall(uv_rtc_setup_clock);