Merge branch 'driver-core-next' of git://git.kernel.org/pub/scm/linux/kernel/git...
[linux-3.10.git] / arch / x86 / kernel / hpet.c
1 #include <linux/clocksource.h>
2 #include <linux/clockchips.h>
3 #include <linux/interrupt.h>
4 #include <linux/export.h>
5 #include <linux/delay.h>
6 #include <linux/errno.h>
7 #include <linux/i8253.h>
8 #include <linux/slab.h>
9 #include <linux/hpet.h>
10 #include <linux/init.h>
11 #include <linux/cpu.h>
12 #include <linux/pm.h>
13 #include <linux/io.h>
14
15 #include <asm/fixmap.h>
16 #include <asm/hpet.h>
17 #include <asm/time.h>
18
19 #define HPET_MASK                       CLOCKSOURCE_MASK(32)
20
21 /* FSEC = 10^-15
22    NSEC = 10^-9 */
23 #define FSEC_PER_NSEC                   1000000L
24
25 #define HPET_DEV_USED_BIT               2
26 #define HPET_DEV_USED                   (1 << HPET_DEV_USED_BIT)
27 #define HPET_DEV_VALID                  0x8
28 #define HPET_DEV_FSB_CAP                0x1000
29 #define HPET_DEV_PERI_CAP               0x2000
30
31 #define HPET_MIN_CYCLES                 128
32 #define HPET_MIN_PROG_DELTA             (HPET_MIN_CYCLES + (HPET_MIN_CYCLES >> 1))
33
34 /*
35  * HPET address is set in acpi/boot.c, when an ACPI entry exists
36  */
37 unsigned long                           hpet_address;
38 u8                                      hpet_blockid; /* OS timer block num */
39 u8                                      hpet_msi_disable;
40
41 #ifdef CONFIG_PCI_MSI
42 static unsigned long                    hpet_num_timers;
43 #endif
44 static void __iomem                     *hpet_virt_address;
45
46 struct hpet_dev {
47         struct clock_event_device       evt;
48         unsigned int                    num;
49         int                             cpu;
50         unsigned int                    irq;
51         unsigned int                    flags;
52         char                            name[10];
53 };
54
55 inline struct hpet_dev *EVT_TO_HPET_DEV(struct clock_event_device *evtdev)
56 {
57         return container_of(evtdev, struct hpet_dev, evt);
58 }
59
60 inline unsigned int hpet_readl(unsigned int a)
61 {
62         return readl(hpet_virt_address + a);
63 }
64
65 static inline void hpet_writel(unsigned int d, unsigned int a)
66 {
67         writel(d, hpet_virt_address + a);
68 }
69
70 #ifdef CONFIG_X86_64
71 #include <asm/pgtable.h>
72 #endif
73
74 static inline void hpet_set_mapping(void)
75 {
76         hpet_virt_address = ioremap_nocache(hpet_address, HPET_MMAP_SIZE);
77 #ifdef CONFIG_X86_64
78         __set_fixmap(VSYSCALL_HPET, hpet_address, PAGE_KERNEL_VVAR_NOCACHE);
79 #endif
80 }
81
82 static inline void hpet_clear_mapping(void)
83 {
84         iounmap(hpet_virt_address);
85         hpet_virt_address = NULL;
86 }
87
88 /*
89  * HPET command line enable / disable
90  */
91 static int boot_hpet_disable;
92 int hpet_force_user;
93 static int hpet_verbose;
94
95 static int __init hpet_setup(char *str)
96 {
97         if (str) {
98                 if (!strncmp("disable", str, 7))
99                         boot_hpet_disable = 1;
100                 if (!strncmp("force", str, 5))
101                         hpet_force_user = 1;
102                 if (!strncmp("verbose", str, 7))
103                         hpet_verbose = 1;
104         }
105         return 1;
106 }
107 __setup("hpet=", hpet_setup);
108
109 static int __init disable_hpet(char *str)
110 {
111         boot_hpet_disable = 1;
112         return 1;
113 }
114 __setup("nohpet", disable_hpet);
115
116 static inline int is_hpet_capable(void)
117 {
118         return !boot_hpet_disable && hpet_address;
119 }
120
121 /*
122  * HPET timer interrupt enable / disable
123  */
124 static int hpet_legacy_int_enabled;
125
126 /**
127  * is_hpet_enabled - check whether the hpet timer interrupt is enabled
128  */
129 int is_hpet_enabled(void)
130 {
131         return is_hpet_capable() && hpet_legacy_int_enabled;
132 }
133 EXPORT_SYMBOL_GPL(is_hpet_enabled);
134
135 static void _hpet_print_config(const char *function, int line)
136 {
137         u32 i, timers, l, h;
138         printk(KERN_INFO "hpet: %s(%d):\n", function, line);
139         l = hpet_readl(HPET_ID);
140         h = hpet_readl(HPET_PERIOD);
141         timers = ((l & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT) + 1;
142         printk(KERN_INFO "hpet: ID: 0x%x, PERIOD: 0x%x\n", l, h);
143         l = hpet_readl(HPET_CFG);
144         h = hpet_readl(HPET_STATUS);
145         printk(KERN_INFO "hpet: CFG: 0x%x, STATUS: 0x%x\n", l, h);
146         l = hpet_readl(HPET_COUNTER);
147         h = hpet_readl(HPET_COUNTER+4);
148         printk(KERN_INFO "hpet: COUNTER_l: 0x%x, COUNTER_h: 0x%x\n", l, h);
149
150         for (i = 0; i < timers; i++) {
151                 l = hpet_readl(HPET_Tn_CFG(i));
152                 h = hpet_readl(HPET_Tn_CFG(i)+4);
153                 printk(KERN_INFO "hpet: T%d: CFG_l: 0x%x, CFG_h: 0x%x\n",
154                        i, l, h);
155                 l = hpet_readl(HPET_Tn_CMP(i));
156                 h = hpet_readl(HPET_Tn_CMP(i)+4);
157                 printk(KERN_INFO "hpet: T%d: CMP_l: 0x%x, CMP_h: 0x%x\n",
158                        i, l, h);
159                 l = hpet_readl(HPET_Tn_ROUTE(i));
160                 h = hpet_readl(HPET_Tn_ROUTE(i)+4);
161                 printk(KERN_INFO "hpet: T%d ROUTE_l: 0x%x, ROUTE_h: 0x%x\n",
162                        i, l, h);
163         }
164 }
165
166 #define hpet_print_config()                                     \
167 do {                                                            \
168         if (hpet_verbose)                                       \
169                 _hpet_print_config(__FUNCTION__, __LINE__);     \
170 } while (0)
171
172 /*
173  * When the hpet driver (/dev/hpet) is enabled, we need to reserve
174  * timer 0 and timer 1 in case of RTC emulation.
175  */
176 #ifdef CONFIG_HPET
177
178 static void hpet_reserve_msi_timers(struct hpet_data *hd);
179
180 static void hpet_reserve_platform_timers(unsigned int id)
181 {
182         struct hpet __iomem *hpet = hpet_virt_address;
183         struct hpet_timer __iomem *timer = &hpet->hpet_timers[2];
184         unsigned int nrtimers, i;
185         struct hpet_data hd;
186
187         nrtimers = ((id & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT) + 1;
188
189         memset(&hd, 0, sizeof(hd));
190         hd.hd_phys_address      = hpet_address;
191         hd.hd_address           = hpet;
192         hd.hd_nirqs             = nrtimers;
193         hpet_reserve_timer(&hd, 0);
194
195 #ifdef CONFIG_HPET_EMULATE_RTC
196         hpet_reserve_timer(&hd, 1);
197 #endif
198
199         /*
200          * NOTE that hd_irq[] reflects IOAPIC input pins (LEGACY_8254
201          * is wrong for i8259!) not the output IRQ.  Many BIOS writers
202          * don't bother configuring *any* comparator interrupts.
203          */
204         hd.hd_irq[0] = HPET_LEGACY_8254;
205         hd.hd_irq[1] = HPET_LEGACY_RTC;
206
207         for (i = 2; i < nrtimers; timer++, i++) {
208                 hd.hd_irq[i] = (readl(&timer->hpet_config) &
209                         Tn_INT_ROUTE_CNF_MASK) >> Tn_INT_ROUTE_CNF_SHIFT;
210         }
211
212         hpet_reserve_msi_timers(&hd);
213
214         hpet_alloc(&hd);
215
216 }
217 #else
218 static void hpet_reserve_platform_timers(unsigned int id) { }
219 #endif
220
221 /*
222  * Common hpet info
223  */
224 static unsigned long hpet_freq;
225
226 static void hpet_legacy_set_mode(enum clock_event_mode mode,
227                           struct clock_event_device *evt);
228 static int hpet_legacy_next_event(unsigned long delta,
229                            struct clock_event_device *evt);
230
231 /*
232  * The hpet clock event device
233  */
234 static struct clock_event_device hpet_clockevent = {
235         .name           = "hpet",
236         .features       = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
237         .set_mode       = hpet_legacy_set_mode,
238         .set_next_event = hpet_legacy_next_event,
239         .irq            = 0,
240         .rating         = 50,
241 };
242
243 static void hpet_stop_counter(void)
244 {
245         unsigned long cfg = hpet_readl(HPET_CFG);
246         cfg &= ~HPET_CFG_ENABLE;
247         hpet_writel(cfg, HPET_CFG);
248 }
249
250 static void hpet_reset_counter(void)
251 {
252         hpet_writel(0, HPET_COUNTER);
253         hpet_writel(0, HPET_COUNTER + 4);
254 }
255
256 static void hpet_start_counter(void)
257 {
258         unsigned int cfg = hpet_readl(HPET_CFG);
259         cfg |= HPET_CFG_ENABLE;
260         hpet_writel(cfg, HPET_CFG);
261 }
262
263 static void hpet_restart_counter(void)
264 {
265         hpet_stop_counter();
266         hpet_reset_counter();
267         hpet_start_counter();
268 }
269
270 static void hpet_resume_device(void)
271 {
272         force_hpet_resume();
273 }
274
275 static void hpet_resume_counter(struct clocksource *cs)
276 {
277         hpet_resume_device();
278         hpet_restart_counter();
279 }
280
281 static void hpet_enable_legacy_int(void)
282 {
283         unsigned int cfg = hpet_readl(HPET_CFG);
284
285         cfg |= HPET_CFG_LEGACY;
286         hpet_writel(cfg, HPET_CFG);
287         hpet_legacy_int_enabled = 1;
288 }
289
290 static void hpet_legacy_clockevent_register(void)
291 {
292         /* Start HPET legacy interrupts */
293         hpet_enable_legacy_int();
294
295         /*
296          * Start hpet with the boot cpu mask and make it
297          * global after the IO_APIC has been initialized.
298          */
299         hpet_clockevent.cpumask = cpumask_of(smp_processor_id());
300         clockevents_config_and_register(&hpet_clockevent, hpet_freq,
301                                         HPET_MIN_PROG_DELTA, 0x7FFFFFFF);
302         global_clock_event = &hpet_clockevent;
303         printk(KERN_DEBUG "hpet clockevent registered\n");
304 }
305
306 static int hpet_setup_msi_irq(unsigned int irq);
307
308 static void hpet_set_mode(enum clock_event_mode mode,
309                           struct clock_event_device *evt, int timer)
310 {
311         unsigned int cfg, cmp, now;
312         uint64_t delta;
313
314         switch (mode) {
315         case CLOCK_EVT_MODE_PERIODIC:
316                 hpet_stop_counter();
317                 delta = ((uint64_t)(NSEC_PER_SEC/HZ)) * evt->mult;
318                 delta >>= evt->shift;
319                 now = hpet_readl(HPET_COUNTER);
320                 cmp = now + (unsigned int) delta;
321                 cfg = hpet_readl(HPET_Tn_CFG(timer));
322                 /* Make sure we use edge triggered interrupts */
323                 cfg &= ~HPET_TN_LEVEL;
324                 cfg |= HPET_TN_ENABLE | HPET_TN_PERIODIC |
325                        HPET_TN_SETVAL | HPET_TN_32BIT;
326                 hpet_writel(cfg, HPET_Tn_CFG(timer));
327                 hpet_writel(cmp, HPET_Tn_CMP(timer));
328                 udelay(1);
329                 /*
330                  * HPET on AMD 81xx needs a second write (with HPET_TN_SETVAL
331                  * cleared) to T0_CMP to set the period. The HPET_TN_SETVAL
332                  * bit is automatically cleared after the first write.
333                  * (See AMD-8111 HyperTransport I/O Hub Data Sheet,
334                  * Publication # 24674)
335                  */
336                 hpet_writel((unsigned int) delta, HPET_Tn_CMP(timer));
337                 hpet_start_counter();
338                 hpet_print_config();
339                 break;
340
341         case CLOCK_EVT_MODE_ONESHOT:
342                 cfg = hpet_readl(HPET_Tn_CFG(timer));
343                 cfg &= ~HPET_TN_PERIODIC;
344                 cfg |= HPET_TN_ENABLE | HPET_TN_32BIT;
345                 hpet_writel(cfg, HPET_Tn_CFG(timer));
346                 break;
347
348         case CLOCK_EVT_MODE_UNUSED:
349         case CLOCK_EVT_MODE_SHUTDOWN:
350                 cfg = hpet_readl(HPET_Tn_CFG(timer));
351                 cfg &= ~HPET_TN_ENABLE;
352                 hpet_writel(cfg, HPET_Tn_CFG(timer));
353                 break;
354
355         case CLOCK_EVT_MODE_RESUME:
356                 if (timer == 0) {
357                         hpet_enable_legacy_int();
358                 } else {
359                         struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt);
360                         hpet_setup_msi_irq(hdev->irq);
361                         disable_irq(hdev->irq);
362                         irq_set_affinity(hdev->irq, cpumask_of(hdev->cpu));
363                         enable_irq(hdev->irq);
364                 }
365                 hpet_print_config();
366                 break;
367         }
368 }
369
370 static int hpet_next_event(unsigned long delta,
371                            struct clock_event_device *evt, int timer)
372 {
373         u32 cnt;
374         s32 res;
375
376         cnt = hpet_readl(HPET_COUNTER);
377         cnt += (u32) delta;
378         hpet_writel(cnt, HPET_Tn_CMP(timer));
379
380         /*
381          * HPETs are a complete disaster. The compare register is
382          * based on a equal comparison and neither provides a less
383          * than or equal functionality (which would require to take
384          * the wraparound into account) nor a simple count down event
385          * mode. Further the write to the comparator register is
386          * delayed internally up to two HPET clock cycles in certain
387          * chipsets (ATI, ICH9,10). Some newer AMD chipsets have even
388          * longer delays. We worked around that by reading back the
389          * compare register, but that required another workaround for
390          * ICH9,10 chips where the first readout after write can
391          * return the old stale value. We already had a minimum
392          * programming delta of 5us enforced, but a NMI or SMI hitting
393          * between the counter readout and the comparator write can
394          * move us behind that point easily. Now instead of reading
395          * the compare register back several times, we make the ETIME
396          * decision based on the following: Return ETIME if the
397          * counter value after the write is less than HPET_MIN_CYCLES
398          * away from the event or if the counter is already ahead of
399          * the event. The minimum programming delta for the generic
400          * clockevents code is set to 1.5 * HPET_MIN_CYCLES.
401          */
402         res = (s32)(cnt - hpet_readl(HPET_COUNTER));
403
404         return res < HPET_MIN_CYCLES ? -ETIME : 0;
405 }
406
407 static void hpet_legacy_set_mode(enum clock_event_mode mode,
408                         struct clock_event_device *evt)
409 {
410         hpet_set_mode(mode, evt, 0);
411 }
412
413 static int hpet_legacy_next_event(unsigned long delta,
414                         struct clock_event_device *evt)
415 {
416         return hpet_next_event(delta, evt, 0);
417 }
418
419 /*
420  * HPET MSI Support
421  */
422 #ifdef CONFIG_PCI_MSI
423
424 static DEFINE_PER_CPU(struct hpet_dev *, cpu_hpet_dev);
425 static struct hpet_dev  *hpet_devs;
426
427 void hpet_msi_unmask(struct irq_data *data)
428 {
429         struct hpet_dev *hdev = data->handler_data;
430         unsigned int cfg;
431
432         /* unmask it */
433         cfg = hpet_readl(HPET_Tn_CFG(hdev->num));
434         cfg |= HPET_TN_FSB;
435         hpet_writel(cfg, HPET_Tn_CFG(hdev->num));
436 }
437
438 void hpet_msi_mask(struct irq_data *data)
439 {
440         struct hpet_dev *hdev = data->handler_data;
441         unsigned int cfg;
442
443         /* mask it */
444         cfg = hpet_readl(HPET_Tn_CFG(hdev->num));
445         cfg &= ~HPET_TN_FSB;
446         hpet_writel(cfg, HPET_Tn_CFG(hdev->num));
447 }
448
449 void hpet_msi_write(struct hpet_dev *hdev, struct msi_msg *msg)
450 {
451         hpet_writel(msg->data, HPET_Tn_ROUTE(hdev->num));
452         hpet_writel(msg->address_lo, HPET_Tn_ROUTE(hdev->num) + 4);
453 }
454
455 void hpet_msi_read(struct hpet_dev *hdev, struct msi_msg *msg)
456 {
457         msg->data = hpet_readl(HPET_Tn_ROUTE(hdev->num));
458         msg->address_lo = hpet_readl(HPET_Tn_ROUTE(hdev->num) + 4);
459         msg->address_hi = 0;
460 }
461
462 static void hpet_msi_set_mode(enum clock_event_mode mode,
463                                 struct clock_event_device *evt)
464 {
465         struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt);
466         hpet_set_mode(mode, evt, hdev->num);
467 }
468
469 static int hpet_msi_next_event(unsigned long delta,
470                                 struct clock_event_device *evt)
471 {
472         struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt);
473         return hpet_next_event(delta, evt, hdev->num);
474 }
475
476 static int hpet_setup_msi_irq(unsigned int irq)
477 {
478         if (arch_setup_hpet_msi(irq, hpet_blockid)) {
479                 destroy_irq(irq);
480                 return -EINVAL;
481         }
482         return 0;
483 }
484
485 static int hpet_assign_irq(struct hpet_dev *dev)
486 {
487         unsigned int irq;
488
489         irq = create_irq_nr(0, -1);
490         if (!irq)
491                 return -EINVAL;
492
493         irq_set_handler_data(irq, dev);
494
495         if (hpet_setup_msi_irq(irq))
496                 return -EINVAL;
497
498         dev->irq = irq;
499         return 0;
500 }
501
502 static irqreturn_t hpet_interrupt_handler(int irq, void *data)
503 {
504         struct hpet_dev *dev = (struct hpet_dev *)data;
505         struct clock_event_device *hevt = &dev->evt;
506
507         if (!hevt->event_handler) {
508                 printk(KERN_INFO "Spurious HPET timer interrupt on HPET timer %d\n",
509                                 dev->num);
510                 return IRQ_HANDLED;
511         }
512
513         hevt->event_handler(hevt);
514         return IRQ_HANDLED;
515 }
516
517 static int hpet_setup_irq(struct hpet_dev *dev)
518 {
519
520         if (request_irq(dev->irq, hpet_interrupt_handler,
521                         IRQF_TIMER | IRQF_DISABLED | IRQF_NOBALANCING,
522                         dev->name, dev))
523                 return -1;
524
525         disable_irq(dev->irq);
526         irq_set_affinity(dev->irq, cpumask_of(dev->cpu));
527         enable_irq(dev->irq);
528
529         printk(KERN_DEBUG "hpet: %s irq %d for MSI\n",
530                          dev->name, dev->irq);
531
532         return 0;
533 }
534
535 /* This should be called in specific @cpu */
536 static void init_one_hpet_msi_clockevent(struct hpet_dev *hdev, int cpu)
537 {
538         struct clock_event_device *evt = &hdev->evt;
539
540         WARN_ON(cpu != smp_processor_id());
541         if (!(hdev->flags & HPET_DEV_VALID))
542                 return;
543
544         if (hpet_setup_msi_irq(hdev->irq))
545                 return;
546
547         hdev->cpu = cpu;
548         per_cpu(cpu_hpet_dev, cpu) = hdev;
549         evt->name = hdev->name;
550         hpet_setup_irq(hdev);
551         evt->irq = hdev->irq;
552
553         evt->rating = 110;
554         evt->features = CLOCK_EVT_FEAT_ONESHOT;
555         if (hdev->flags & HPET_DEV_PERI_CAP)
556                 evt->features |= CLOCK_EVT_FEAT_PERIODIC;
557
558         evt->set_mode = hpet_msi_set_mode;
559         evt->set_next_event = hpet_msi_next_event;
560         evt->cpumask = cpumask_of(hdev->cpu);
561
562         clockevents_config_and_register(evt, hpet_freq, HPET_MIN_PROG_DELTA,
563                                         0x7FFFFFFF);
564 }
565
566 #ifdef CONFIG_HPET
567 /* Reserve at least one timer for userspace (/dev/hpet) */
568 #define RESERVE_TIMERS 1
569 #else
570 #define RESERVE_TIMERS 0
571 #endif
572
573 static void hpet_msi_capability_lookup(unsigned int start_timer)
574 {
575         unsigned int id;
576         unsigned int num_timers;
577         unsigned int num_timers_used = 0;
578         int i;
579
580         if (hpet_msi_disable)
581                 return;
582
583         if (boot_cpu_has(X86_FEATURE_ARAT))
584                 return;
585         id = hpet_readl(HPET_ID);
586
587         num_timers = ((id & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT);
588         num_timers++; /* Value read out starts from 0 */
589         hpet_print_config();
590
591         hpet_devs = kzalloc(sizeof(struct hpet_dev) * num_timers, GFP_KERNEL);
592         if (!hpet_devs)
593                 return;
594
595         hpet_num_timers = num_timers;
596
597         for (i = start_timer; i < num_timers - RESERVE_TIMERS; i++) {
598                 struct hpet_dev *hdev = &hpet_devs[num_timers_used];
599                 unsigned int cfg = hpet_readl(HPET_Tn_CFG(i));
600
601                 /* Only consider HPET timer with MSI support */
602                 if (!(cfg & HPET_TN_FSB_CAP))
603                         continue;
604
605                 hdev->flags = 0;
606                 if (cfg & HPET_TN_PERIODIC_CAP)
607                         hdev->flags |= HPET_DEV_PERI_CAP;
608                 hdev->num = i;
609
610                 sprintf(hdev->name, "hpet%d", i);
611                 if (hpet_assign_irq(hdev))
612                         continue;
613
614                 hdev->flags |= HPET_DEV_FSB_CAP;
615                 hdev->flags |= HPET_DEV_VALID;
616                 num_timers_used++;
617                 if (num_timers_used == num_possible_cpus())
618                         break;
619         }
620
621         printk(KERN_INFO "HPET: %d timers in total, %d timers will be used for per-cpu timer\n",
622                 num_timers, num_timers_used);
623 }
624
625 #ifdef CONFIG_HPET
626 static void hpet_reserve_msi_timers(struct hpet_data *hd)
627 {
628         int i;
629
630         if (!hpet_devs)
631                 return;
632
633         for (i = 0; i < hpet_num_timers; i++) {
634                 struct hpet_dev *hdev = &hpet_devs[i];
635
636                 if (!(hdev->flags & HPET_DEV_VALID))
637                         continue;
638
639                 hd->hd_irq[hdev->num] = hdev->irq;
640                 hpet_reserve_timer(hd, hdev->num);
641         }
642 }
643 #endif
644
645 static struct hpet_dev *hpet_get_unused_timer(void)
646 {
647         int i;
648
649         if (!hpet_devs)
650                 return NULL;
651
652         for (i = 0; i < hpet_num_timers; i++) {
653                 struct hpet_dev *hdev = &hpet_devs[i];
654
655                 if (!(hdev->flags & HPET_DEV_VALID))
656                         continue;
657                 if (test_and_set_bit(HPET_DEV_USED_BIT,
658                         (unsigned long *)&hdev->flags))
659                         continue;
660                 return hdev;
661         }
662         return NULL;
663 }
664
665 struct hpet_work_struct {
666         struct delayed_work work;
667         struct completion complete;
668 };
669
670 static void hpet_work(struct work_struct *w)
671 {
672         struct hpet_dev *hdev;
673         int cpu = smp_processor_id();
674         struct hpet_work_struct *hpet_work;
675
676         hpet_work = container_of(w, struct hpet_work_struct, work.work);
677
678         hdev = hpet_get_unused_timer();
679         if (hdev)
680                 init_one_hpet_msi_clockevent(hdev, cpu);
681
682         complete(&hpet_work->complete);
683 }
684
685 static int hpet_cpuhp_notify(struct notifier_block *n,
686                 unsigned long action, void *hcpu)
687 {
688         unsigned long cpu = (unsigned long)hcpu;
689         struct hpet_work_struct work;
690         struct hpet_dev *hdev = per_cpu(cpu_hpet_dev, cpu);
691
692         switch (action & 0xf) {
693         case CPU_ONLINE:
694                 INIT_DELAYED_WORK_ONSTACK(&work.work, hpet_work);
695                 init_completion(&work.complete);
696                 /* FIXME: add schedule_work_on() */
697                 schedule_delayed_work_on(cpu, &work.work, 0);
698                 wait_for_completion(&work.complete);
699                 destroy_timer_on_stack(&work.work.timer);
700                 break;
701         case CPU_DEAD:
702                 if (hdev) {
703                         free_irq(hdev->irq, hdev);
704                         hdev->flags &= ~HPET_DEV_USED;
705                         per_cpu(cpu_hpet_dev, cpu) = NULL;
706                 }
707                 break;
708         }
709         return NOTIFY_OK;
710 }
711 #else
712
713 static int hpet_setup_msi_irq(unsigned int irq)
714 {
715         return 0;
716 }
717 static void hpet_msi_capability_lookup(unsigned int start_timer)
718 {
719         return;
720 }
721
722 #ifdef CONFIG_HPET
723 static void hpet_reserve_msi_timers(struct hpet_data *hd)
724 {
725         return;
726 }
727 #endif
728
729 static int hpet_cpuhp_notify(struct notifier_block *n,
730                 unsigned long action, void *hcpu)
731 {
732         return NOTIFY_OK;
733 }
734
735 #endif
736
737 /*
738  * Clock source related code
739  */
740 static cycle_t read_hpet(struct clocksource *cs)
741 {
742         return (cycle_t)hpet_readl(HPET_COUNTER);
743 }
744
745 static struct clocksource clocksource_hpet = {
746         .name           = "hpet",
747         .rating         = 250,
748         .read           = read_hpet,
749         .mask           = HPET_MASK,
750         .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
751         .resume         = hpet_resume_counter,
752 #ifdef CONFIG_X86_64
753         .archdata       = { .vclock_mode = VCLOCK_HPET },
754 #endif
755 };
756
757 static int hpet_clocksource_register(void)
758 {
759         u64 start, now;
760         cycle_t t1;
761
762         /* Start the counter */
763         hpet_restart_counter();
764
765         /* Verify whether hpet counter works */
766         t1 = hpet_readl(HPET_COUNTER);
767         rdtscll(start);
768
769         /*
770          * We don't know the TSC frequency yet, but waiting for
771          * 200000 TSC cycles is safe:
772          * 4 GHz == 50us
773          * 1 GHz == 200us
774          */
775         do {
776                 rep_nop();
777                 rdtscll(now);
778         } while ((now - start) < 200000UL);
779
780         if (t1 == hpet_readl(HPET_COUNTER)) {
781                 printk(KERN_WARNING
782                        "HPET counter not counting. HPET disabled\n");
783                 return -ENODEV;
784         }
785
786         clocksource_register_hz(&clocksource_hpet, (u32)hpet_freq);
787         return 0;
788 }
789
790 /**
791  * hpet_enable - Try to setup the HPET timer. Returns 1 on success.
792  */
793 int __init hpet_enable(void)
794 {
795         unsigned long hpet_period;
796         unsigned int id;
797         u64 freq;
798         int i;
799
800         if (!is_hpet_capable())
801                 return 0;
802
803         hpet_set_mapping();
804
805         /*
806          * Read the period and check for a sane value:
807          */
808         hpet_period = hpet_readl(HPET_PERIOD);
809
810         /*
811          * AMD SB700 based systems with spread spectrum enabled use a
812          * SMM based HPET emulation to provide proper frequency
813          * setting. The SMM code is initialized with the first HPET
814          * register access and takes some time to complete. During
815          * this time the config register reads 0xffffffff. We check
816          * for max. 1000 loops whether the config register reads a non
817          * 0xffffffff value to make sure that HPET is up and running
818          * before we go further. A counting loop is safe, as the HPET
819          * access takes thousands of CPU cycles. On non SB700 based
820          * machines this check is only done once and has no side
821          * effects.
822          */
823         for (i = 0; hpet_readl(HPET_CFG) == 0xFFFFFFFF; i++) {
824                 if (i == 1000) {
825                         printk(KERN_WARNING
826                                "HPET config register value = 0xFFFFFFFF. "
827                                "Disabling HPET\n");
828                         goto out_nohpet;
829                 }
830         }
831
832         if (hpet_period < HPET_MIN_PERIOD || hpet_period > HPET_MAX_PERIOD)
833                 goto out_nohpet;
834
835         /*
836          * The period is a femto seconds value. Convert it to a
837          * frequency.
838          */
839         freq = FSEC_PER_SEC;
840         do_div(freq, hpet_period);
841         hpet_freq = freq;
842
843         /*
844          * Read the HPET ID register to retrieve the IRQ routing
845          * information and the number of channels
846          */
847         id = hpet_readl(HPET_ID);
848         hpet_print_config();
849
850 #ifdef CONFIG_HPET_EMULATE_RTC
851         /*
852          * The legacy routing mode needs at least two channels, tick timer
853          * and the rtc emulation channel.
854          */
855         if (!(id & HPET_ID_NUMBER))
856                 goto out_nohpet;
857 #endif
858
859         if (hpet_clocksource_register())
860                 goto out_nohpet;
861
862         if (id & HPET_ID_LEGSUP) {
863                 hpet_legacy_clockevent_register();
864                 return 1;
865         }
866         return 0;
867
868 out_nohpet:
869         hpet_clear_mapping();
870         hpet_address = 0;
871         return 0;
872 }
873
874 /*
875  * Needs to be late, as the reserve_timer code calls kalloc !
876  *
877  * Not a problem on i386 as hpet_enable is called from late_time_init,
878  * but on x86_64 it is necessary !
879  */
880 static __init int hpet_late_init(void)
881 {
882         int cpu;
883
884         if (boot_hpet_disable)
885                 return -ENODEV;
886
887         if (!hpet_address) {
888                 if (!force_hpet_address)
889                         return -ENODEV;
890
891                 hpet_address = force_hpet_address;
892                 hpet_enable();
893         }
894
895         if (!hpet_virt_address)
896                 return -ENODEV;
897
898         if (hpet_readl(HPET_ID) & HPET_ID_LEGSUP)
899                 hpet_msi_capability_lookup(2);
900         else
901                 hpet_msi_capability_lookup(0);
902
903         hpet_reserve_platform_timers(hpet_readl(HPET_ID));
904         hpet_print_config();
905
906         if (hpet_msi_disable)
907                 return 0;
908
909         if (boot_cpu_has(X86_FEATURE_ARAT))
910                 return 0;
911
912         for_each_online_cpu(cpu) {
913                 hpet_cpuhp_notify(NULL, CPU_ONLINE, (void *)(long)cpu);
914         }
915
916         /* This notifier should be called after workqueue is ready */
917         hotcpu_notifier(hpet_cpuhp_notify, -20);
918
919         return 0;
920 }
921 fs_initcall(hpet_late_init);
922
923 void hpet_disable(void)
924 {
925         if (is_hpet_capable() && hpet_virt_address) {
926                 unsigned int cfg = hpet_readl(HPET_CFG);
927
928                 if (hpet_legacy_int_enabled) {
929                         cfg &= ~HPET_CFG_LEGACY;
930                         hpet_legacy_int_enabled = 0;
931                 }
932                 cfg &= ~HPET_CFG_ENABLE;
933                 hpet_writel(cfg, HPET_CFG);
934         }
935 }
936
937 #ifdef CONFIG_HPET_EMULATE_RTC
938
939 /* HPET in LegacyReplacement Mode eats up RTC interrupt line. When, HPET
940  * is enabled, we support RTC interrupt functionality in software.
941  * RTC has 3 kinds of interrupts:
942  * 1) Update Interrupt - generate an interrupt, every sec, when RTC clock
943  *    is updated
944  * 2) Alarm Interrupt - generate an interrupt at a specific time of day
945  * 3) Periodic Interrupt - generate periodic interrupt, with frequencies
946  *    2Hz-8192Hz (2Hz-64Hz for non-root user) (all freqs in powers of 2)
947  * (1) and (2) above are implemented using polling at a frequency of
948  * 64 Hz. The exact frequency is a tradeoff between accuracy and interrupt
949  * overhead. (DEFAULT_RTC_INT_FREQ)
950  * For (3), we use interrupts at 64Hz or user specified periodic
951  * frequency, whichever is higher.
952  */
953 #include <linux/mc146818rtc.h>
954 #include <linux/rtc.h>
955 #include <asm/rtc.h>
956
957 #define DEFAULT_RTC_INT_FREQ    64
958 #define DEFAULT_RTC_SHIFT       6
959 #define RTC_NUM_INTS            1
960
961 static unsigned long hpet_rtc_flags;
962 static int hpet_prev_update_sec;
963 static struct rtc_time hpet_alarm_time;
964 static unsigned long hpet_pie_count;
965 static u32 hpet_t1_cmp;
966 static u32 hpet_default_delta;
967 static u32 hpet_pie_delta;
968 static unsigned long hpet_pie_limit;
969
970 static rtc_irq_handler irq_handler;
971
972 /*
973  * Check that the hpet counter c1 is ahead of the c2
974  */
975 static inline int hpet_cnt_ahead(u32 c1, u32 c2)
976 {
977         return (s32)(c2 - c1) < 0;
978 }
979
980 /*
981  * Registers a IRQ handler.
982  */
983 int hpet_register_irq_handler(rtc_irq_handler handler)
984 {
985         if (!is_hpet_enabled())
986                 return -ENODEV;
987         if (irq_handler)
988                 return -EBUSY;
989
990         irq_handler = handler;
991
992         return 0;
993 }
994 EXPORT_SYMBOL_GPL(hpet_register_irq_handler);
995
996 /*
997  * Deregisters the IRQ handler registered with hpet_register_irq_handler()
998  * and does cleanup.
999  */
1000 void hpet_unregister_irq_handler(rtc_irq_handler handler)
1001 {
1002         if (!is_hpet_enabled())
1003                 return;
1004
1005         irq_handler = NULL;
1006         hpet_rtc_flags = 0;
1007 }
1008 EXPORT_SYMBOL_GPL(hpet_unregister_irq_handler);
1009
1010 /*
1011  * Timer 1 for RTC emulation. We use one shot mode, as periodic mode
1012  * is not supported by all HPET implementations for timer 1.
1013  *
1014  * hpet_rtc_timer_init() is called when the rtc is initialized.
1015  */
1016 int hpet_rtc_timer_init(void)
1017 {
1018         unsigned int cfg, cnt, delta;
1019         unsigned long flags;
1020
1021         if (!is_hpet_enabled())
1022                 return 0;
1023
1024         if (!hpet_default_delta) {
1025                 uint64_t clc;
1026
1027                 clc = (uint64_t) hpet_clockevent.mult * NSEC_PER_SEC;
1028                 clc >>= hpet_clockevent.shift + DEFAULT_RTC_SHIFT;
1029                 hpet_default_delta = clc;
1030         }
1031
1032         if (!(hpet_rtc_flags & RTC_PIE) || hpet_pie_limit)
1033                 delta = hpet_default_delta;
1034         else
1035                 delta = hpet_pie_delta;
1036
1037         local_irq_save(flags);
1038
1039         cnt = delta + hpet_readl(HPET_COUNTER);
1040         hpet_writel(cnt, HPET_T1_CMP);
1041         hpet_t1_cmp = cnt;
1042
1043         cfg = hpet_readl(HPET_T1_CFG);
1044         cfg &= ~HPET_TN_PERIODIC;
1045         cfg |= HPET_TN_ENABLE | HPET_TN_32BIT;
1046         hpet_writel(cfg, HPET_T1_CFG);
1047
1048         local_irq_restore(flags);
1049
1050         return 1;
1051 }
1052 EXPORT_SYMBOL_GPL(hpet_rtc_timer_init);
1053
1054 static void hpet_disable_rtc_channel(void)
1055 {
1056         unsigned long cfg;
1057         cfg = hpet_readl(HPET_T1_CFG);
1058         cfg &= ~HPET_TN_ENABLE;
1059         hpet_writel(cfg, HPET_T1_CFG);
1060 }
1061
1062 /*
1063  * The functions below are called from rtc driver.
1064  * Return 0 if HPET is not being used.
1065  * Otherwise do the necessary changes and return 1.
1066  */
1067 int hpet_mask_rtc_irq_bit(unsigned long bit_mask)
1068 {
1069         if (!is_hpet_enabled())
1070                 return 0;
1071
1072         hpet_rtc_flags &= ~bit_mask;
1073         if (unlikely(!hpet_rtc_flags))
1074                 hpet_disable_rtc_channel();
1075
1076         return 1;
1077 }
1078 EXPORT_SYMBOL_GPL(hpet_mask_rtc_irq_bit);
1079
1080 int hpet_set_rtc_irq_bit(unsigned long bit_mask)
1081 {
1082         unsigned long oldbits = hpet_rtc_flags;
1083
1084         if (!is_hpet_enabled())
1085                 return 0;
1086
1087         hpet_rtc_flags |= bit_mask;
1088
1089         if ((bit_mask & RTC_UIE) && !(oldbits & RTC_UIE))
1090                 hpet_prev_update_sec = -1;
1091
1092         if (!oldbits)
1093                 hpet_rtc_timer_init();
1094
1095         return 1;
1096 }
1097 EXPORT_SYMBOL_GPL(hpet_set_rtc_irq_bit);
1098
1099 int hpet_set_alarm_time(unsigned char hrs, unsigned char min,
1100                         unsigned char sec)
1101 {
1102         if (!is_hpet_enabled())
1103                 return 0;
1104
1105         hpet_alarm_time.tm_hour = hrs;
1106         hpet_alarm_time.tm_min = min;
1107         hpet_alarm_time.tm_sec = sec;
1108
1109         return 1;
1110 }
1111 EXPORT_SYMBOL_GPL(hpet_set_alarm_time);
1112
1113 int hpet_set_periodic_freq(unsigned long freq)
1114 {
1115         uint64_t clc;
1116
1117         if (!is_hpet_enabled())
1118                 return 0;
1119
1120         if (freq <= DEFAULT_RTC_INT_FREQ)
1121                 hpet_pie_limit = DEFAULT_RTC_INT_FREQ / freq;
1122         else {
1123                 clc = (uint64_t) hpet_clockevent.mult * NSEC_PER_SEC;
1124                 do_div(clc, freq);
1125                 clc >>= hpet_clockevent.shift;
1126                 hpet_pie_delta = clc;
1127                 hpet_pie_limit = 0;
1128         }
1129         return 1;
1130 }
1131 EXPORT_SYMBOL_GPL(hpet_set_periodic_freq);
1132
1133 int hpet_rtc_dropped_irq(void)
1134 {
1135         return is_hpet_enabled();
1136 }
1137 EXPORT_SYMBOL_GPL(hpet_rtc_dropped_irq);
1138
1139 static void hpet_rtc_timer_reinit(void)
1140 {
1141         unsigned int delta;
1142         int lost_ints = -1;
1143
1144         if (unlikely(!hpet_rtc_flags))
1145                 hpet_disable_rtc_channel();
1146
1147         if (!(hpet_rtc_flags & RTC_PIE) || hpet_pie_limit)
1148                 delta = hpet_default_delta;
1149         else
1150                 delta = hpet_pie_delta;
1151
1152         /*
1153          * Increment the comparator value until we are ahead of the
1154          * current count.
1155          */
1156         do {
1157                 hpet_t1_cmp += delta;
1158                 hpet_writel(hpet_t1_cmp, HPET_T1_CMP);
1159                 lost_ints++;
1160         } while (!hpet_cnt_ahead(hpet_t1_cmp, hpet_readl(HPET_COUNTER)));
1161
1162         if (lost_ints) {
1163                 if (hpet_rtc_flags & RTC_PIE)
1164                         hpet_pie_count += lost_ints;
1165                 if (printk_ratelimit())
1166                         printk(KERN_WARNING "hpet1: lost %d rtc interrupts\n",
1167                                 lost_ints);
1168         }
1169 }
1170
1171 irqreturn_t hpet_rtc_interrupt(int irq, void *dev_id)
1172 {
1173         struct rtc_time curr_time;
1174         unsigned long rtc_int_flag = 0;
1175
1176         hpet_rtc_timer_reinit();
1177         memset(&curr_time, 0, sizeof(struct rtc_time));
1178
1179         if (hpet_rtc_flags & (RTC_UIE | RTC_AIE))
1180                 get_rtc_time(&curr_time);
1181
1182         if (hpet_rtc_flags & RTC_UIE &&
1183             curr_time.tm_sec != hpet_prev_update_sec) {
1184                 if (hpet_prev_update_sec >= 0)
1185                         rtc_int_flag = RTC_UF;
1186                 hpet_prev_update_sec = curr_time.tm_sec;
1187         }
1188
1189         if (hpet_rtc_flags & RTC_PIE &&
1190             ++hpet_pie_count >= hpet_pie_limit) {
1191                 rtc_int_flag |= RTC_PF;
1192                 hpet_pie_count = 0;
1193         }
1194
1195         if (hpet_rtc_flags & RTC_AIE &&
1196             (curr_time.tm_sec == hpet_alarm_time.tm_sec) &&
1197             (curr_time.tm_min == hpet_alarm_time.tm_min) &&
1198             (curr_time.tm_hour == hpet_alarm_time.tm_hour))
1199                         rtc_int_flag |= RTC_AF;
1200
1201         if (rtc_int_flag) {
1202                 rtc_int_flag |= (RTC_IRQF | (RTC_NUM_INTS << 8));
1203                 if (irq_handler)
1204                         irq_handler(rtc_int_flag, dev_id);
1205         }
1206         return IRQ_HANDLED;
1207 }
1208 EXPORT_SYMBOL_GPL(hpet_rtc_interrupt);
1209 #endif