c2d56b34830dc851b4d14781b231fa7380f38181
[linux-3.10.git] / arch / x86 / include / asm / vmx.h
1 #ifndef VMX_H
2 #define VMX_H
3
4 /*
5  * vmx.h: VMX Architecture related definitions
6  * Copyright (c) 2004, Intel Corporation.
7  *
8  * This program is free software; you can redistribute it and/or modify it
9  * under the terms and conditions of the GNU General Public License,
10  * version 2, as published by the Free Software Foundation.
11  *
12  * This program is distributed in the hope it will be useful, but WITHOUT
13  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
15  * more details.
16  *
17  * You should have received a copy of the GNU General Public License along with
18  * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
19  * Place - Suite 330, Boston, MA 02111-1307 USA.
20  *
21  * A few random additions are:
22  * Copyright (C) 2006 Qumranet
23  *    Avi Kivity <avi@qumranet.com>
24  *    Yaniv Kamay <yaniv@qumranet.com>
25  *
26  */
27
28 #define VMX_EXIT_REASONS_FAILED_VMENTRY         0x80000000
29
30 #define EXIT_REASON_EXCEPTION_NMI       0
31 #define EXIT_REASON_EXTERNAL_INTERRUPT  1
32 #define EXIT_REASON_TRIPLE_FAULT        2
33
34 #define EXIT_REASON_PENDING_INTERRUPT   7
35 #define EXIT_REASON_NMI_WINDOW          8
36 #define EXIT_REASON_TASK_SWITCH         9
37 #define EXIT_REASON_CPUID               10
38 #define EXIT_REASON_HLT                 12
39 #define EXIT_REASON_INVD                13
40 #define EXIT_REASON_INVLPG              14
41 #define EXIT_REASON_RDPMC               15
42 #define EXIT_REASON_RDTSC               16
43 #define EXIT_REASON_VMCALL              18
44 #define EXIT_REASON_VMCLEAR             19
45 #define EXIT_REASON_VMLAUNCH            20
46 #define EXIT_REASON_VMPTRLD             21
47 #define EXIT_REASON_VMPTRST             22
48 #define EXIT_REASON_VMREAD              23
49 #define EXIT_REASON_VMRESUME            24
50 #define EXIT_REASON_VMWRITE             25
51 #define EXIT_REASON_VMOFF               26
52 #define EXIT_REASON_VMON                27
53 #define EXIT_REASON_CR_ACCESS           28
54 #define EXIT_REASON_DR_ACCESS           29
55 #define EXIT_REASON_IO_INSTRUCTION      30
56 #define EXIT_REASON_MSR_READ            31
57 #define EXIT_REASON_MSR_WRITE           32
58 #define EXIT_REASON_INVALID_STATE       33
59 #define EXIT_REASON_MWAIT_INSTRUCTION   36
60 #define EXIT_REASON_MONITOR_INSTRUCTION 39
61 #define EXIT_REASON_PAUSE_INSTRUCTION   40
62 #define EXIT_REASON_MCE_DURING_VMENTRY  41
63 #define EXIT_REASON_TPR_BELOW_THRESHOLD 43
64 #define EXIT_REASON_APIC_ACCESS         44
65 #define EXIT_REASON_EPT_VIOLATION       48
66 #define EXIT_REASON_EPT_MISCONFIG       49
67 #define EXIT_REASON_WBINVD              54
68 #define EXIT_REASON_XSETBV              55
69 #define EXIT_REASON_INVPCID             58
70
71 #define VMX_EXIT_REASONS \
72         { EXIT_REASON_EXCEPTION_NMI,         "EXCEPTION_NMI" }, \
73         { EXIT_REASON_EXTERNAL_INTERRUPT,    "EXTERNAL_INTERRUPT" }, \
74         { EXIT_REASON_TRIPLE_FAULT,          "TRIPLE_FAULT" }, \
75         { EXIT_REASON_PENDING_INTERRUPT,     "PENDING_INTERRUPT" }, \
76         { EXIT_REASON_NMI_WINDOW,            "NMI_WINDOW" }, \
77         { EXIT_REASON_TASK_SWITCH,           "TASK_SWITCH" }, \
78         { EXIT_REASON_CPUID,                 "CPUID" }, \
79         { EXIT_REASON_HLT,                   "HLT" }, \
80         { EXIT_REASON_INVLPG,                "INVLPG" }, \
81         { EXIT_REASON_RDPMC,                 "RDPMC" }, \
82         { EXIT_REASON_RDTSC,                 "RDTSC" }, \
83         { EXIT_REASON_VMCALL,                "VMCALL" }, \
84         { EXIT_REASON_VMCLEAR,               "VMCLEAR" }, \
85         { EXIT_REASON_VMLAUNCH,              "VMLAUNCH" }, \
86         { EXIT_REASON_VMPTRLD,               "VMPTRLD" }, \
87         { EXIT_REASON_VMPTRST,               "VMPTRST" }, \
88         { EXIT_REASON_VMREAD,                "VMREAD" }, \
89         { EXIT_REASON_VMRESUME,              "VMRESUME" }, \
90         { EXIT_REASON_VMWRITE,               "VMWRITE" }, \
91         { EXIT_REASON_VMOFF,                 "VMOFF" }, \
92         { EXIT_REASON_VMON,                  "VMON" }, \
93         { EXIT_REASON_CR_ACCESS,             "CR_ACCESS" }, \
94         { EXIT_REASON_DR_ACCESS,             "DR_ACCESS" }, \
95         { EXIT_REASON_IO_INSTRUCTION,        "IO_INSTRUCTION" }, \
96         { EXIT_REASON_MSR_READ,              "MSR_READ" }, \
97         { EXIT_REASON_MSR_WRITE,             "MSR_WRITE" }, \
98         { EXIT_REASON_MWAIT_INSTRUCTION,     "MWAIT_INSTRUCTION" }, \
99         { EXIT_REASON_MONITOR_INSTRUCTION,   "MONITOR_INSTRUCTION" }, \
100         { EXIT_REASON_PAUSE_INSTRUCTION,     "PAUSE_INSTRUCTION" }, \
101         { EXIT_REASON_MCE_DURING_VMENTRY,    "MCE_DURING_VMENTRY" }, \
102         { EXIT_REASON_TPR_BELOW_THRESHOLD,   "TPR_BELOW_THRESHOLD" }, \
103         { EXIT_REASON_APIC_ACCESS,           "APIC_ACCESS" }, \
104         { EXIT_REASON_EPT_VIOLATION,         "EPT_VIOLATION" }, \
105         { EXIT_REASON_EPT_MISCONFIG,         "EPT_MISCONFIG" }, \
106         { EXIT_REASON_WBINVD,                "WBINVD" }
107
108 #ifdef __KERNEL__
109
110 #include <linux/types.h>
111
112 /*
113  * Definitions of Primary Processor-Based VM-Execution Controls.
114  */
115 #define CPU_BASED_VIRTUAL_INTR_PENDING          0x00000004
116 #define CPU_BASED_USE_TSC_OFFSETING             0x00000008
117 #define CPU_BASED_HLT_EXITING                   0x00000080
118 #define CPU_BASED_INVLPG_EXITING                0x00000200
119 #define CPU_BASED_MWAIT_EXITING                 0x00000400
120 #define CPU_BASED_RDPMC_EXITING                 0x00000800
121 #define CPU_BASED_RDTSC_EXITING                 0x00001000
122 #define CPU_BASED_CR3_LOAD_EXITING              0x00008000
123 #define CPU_BASED_CR3_STORE_EXITING             0x00010000
124 #define CPU_BASED_CR8_LOAD_EXITING              0x00080000
125 #define CPU_BASED_CR8_STORE_EXITING             0x00100000
126 #define CPU_BASED_TPR_SHADOW                    0x00200000
127 #define CPU_BASED_VIRTUAL_NMI_PENDING           0x00400000
128 #define CPU_BASED_MOV_DR_EXITING                0x00800000
129 #define CPU_BASED_UNCOND_IO_EXITING             0x01000000
130 #define CPU_BASED_USE_IO_BITMAPS                0x02000000
131 #define CPU_BASED_USE_MSR_BITMAPS               0x10000000
132 #define CPU_BASED_MONITOR_EXITING               0x20000000
133 #define CPU_BASED_PAUSE_EXITING                 0x40000000
134 #define CPU_BASED_ACTIVATE_SECONDARY_CONTROLS   0x80000000
135 /*
136  * Definitions of Secondary Processor-Based VM-Execution Controls.
137  */
138 #define SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES 0x00000001
139 #define SECONDARY_EXEC_ENABLE_EPT               0x00000002
140 #define SECONDARY_EXEC_RDTSCP                   0x00000008
141 #define SECONDARY_EXEC_ENABLE_VPID              0x00000020
142 #define SECONDARY_EXEC_WBINVD_EXITING           0x00000040
143 #define SECONDARY_EXEC_UNRESTRICTED_GUEST       0x00000080
144 #define SECONDARY_EXEC_PAUSE_LOOP_EXITING       0x00000400
145 #define SECONDARY_EXEC_ENABLE_INVPCID           0x00001000
146
147
148 #define PIN_BASED_EXT_INTR_MASK                 0x00000001
149 #define PIN_BASED_NMI_EXITING                   0x00000008
150 #define PIN_BASED_VIRTUAL_NMIS                  0x00000020
151
152 #define VM_EXIT_SAVE_DEBUG_CONTROLS             0x00000002
153 #define VM_EXIT_HOST_ADDR_SPACE_SIZE            0x00000200
154 #define VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL      0x00001000
155 #define VM_EXIT_ACK_INTR_ON_EXIT                0x00008000
156 #define VM_EXIT_SAVE_IA32_PAT                   0x00040000
157 #define VM_EXIT_LOAD_IA32_PAT                   0x00080000
158 #define VM_EXIT_SAVE_IA32_EFER                  0x00100000
159 #define VM_EXIT_LOAD_IA32_EFER                  0x00200000
160 #define VM_EXIT_SAVE_VMX_PREEMPTION_TIMER       0x00400000
161
162 #define VM_ENTRY_LOAD_DEBUG_CONTROLS            0x00000002
163 #define VM_ENTRY_IA32E_MODE                     0x00000200
164 #define VM_ENTRY_SMM                            0x00000400
165 #define VM_ENTRY_DEACT_DUAL_MONITOR             0x00000800
166 #define VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL     0x00002000
167 #define VM_ENTRY_LOAD_IA32_PAT                  0x00004000
168 #define VM_ENTRY_LOAD_IA32_EFER                 0x00008000
169
170 /* VMCS Encodings */
171 enum vmcs_field {
172         VIRTUAL_PROCESSOR_ID            = 0x00000000,
173         GUEST_ES_SELECTOR               = 0x00000800,
174         GUEST_CS_SELECTOR               = 0x00000802,
175         GUEST_SS_SELECTOR               = 0x00000804,
176         GUEST_DS_SELECTOR               = 0x00000806,
177         GUEST_FS_SELECTOR               = 0x00000808,
178         GUEST_GS_SELECTOR               = 0x0000080a,
179         GUEST_LDTR_SELECTOR             = 0x0000080c,
180         GUEST_TR_SELECTOR               = 0x0000080e,
181         HOST_ES_SELECTOR                = 0x00000c00,
182         HOST_CS_SELECTOR                = 0x00000c02,
183         HOST_SS_SELECTOR                = 0x00000c04,
184         HOST_DS_SELECTOR                = 0x00000c06,
185         HOST_FS_SELECTOR                = 0x00000c08,
186         HOST_GS_SELECTOR                = 0x00000c0a,
187         HOST_TR_SELECTOR                = 0x00000c0c,
188         IO_BITMAP_A                     = 0x00002000,
189         IO_BITMAP_A_HIGH                = 0x00002001,
190         IO_BITMAP_B                     = 0x00002002,
191         IO_BITMAP_B_HIGH                = 0x00002003,
192         MSR_BITMAP                      = 0x00002004,
193         MSR_BITMAP_HIGH                 = 0x00002005,
194         VM_EXIT_MSR_STORE_ADDR          = 0x00002006,
195         VM_EXIT_MSR_STORE_ADDR_HIGH     = 0x00002007,
196         VM_EXIT_MSR_LOAD_ADDR           = 0x00002008,
197         VM_EXIT_MSR_LOAD_ADDR_HIGH      = 0x00002009,
198         VM_ENTRY_MSR_LOAD_ADDR          = 0x0000200a,
199         VM_ENTRY_MSR_LOAD_ADDR_HIGH     = 0x0000200b,
200         TSC_OFFSET                      = 0x00002010,
201         TSC_OFFSET_HIGH                 = 0x00002011,
202         VIRTUAL_APIC_PAGE_ADDR          = 0x00002012,
203         VIRTUAL_APIC_PAGE_ADDR_HIGH     = 0x00002013,
204         APIC_ACCESS_ADDR                = 0x00002014,
205         APIC_ACCESS_ADDR_HIGH           = 0x00002015,
206         EPT_POINTER                     = 0x0000201a,
207         EPT_POINTER_HIGH                = 0x0000201b,
208         GUEST_PHYSICAL_ADDRESS          = 0x00002400,
209         GUEST_PHYSICAL_ADDRESS_HIGH     = 0x00002401,
210         VMCS_LINK_POINTER               = 0x00002800,
211         VMCS_LINK_POINTER_HIGH          = 0x00002801,
212         GUEST_IA32_DEBUGCTL             = 0x00002802,
213         GUEST_IA32_DEBUGCTL_HIGH        = 0x00002803,
214         GUEST_IA32_PAT                  = 0x00002804,
215         GUEST_IA32_PAT_HIGH             = 0x00002805,
216         GUEST_IA32_EFER                 = 0x00002806,
217         GUEST_IA32_EFER_HIGH            = 0x00002807,
218         GUEST_IA32_PERF_GLOBAL_CTRL     = 0x00002808,
219         GUEST_IA32_PERF_GLOBAL_CTRL_HIGH= 0x00002809,
220         GUEST_PDPTR0                    = 0x0000280a,
221         GUEST_PDPTR0_HIGH               = 0x0000280b,
222         GUEST_PDPTR1                    = 0x0000280c,
223         GUEST_PDPTR1_HIGH               = 0x0000280d,
224         GUEST_PDPTR2                    = 0x0000280e,
225         GUEST_PDPTR2_HIGH               = 0x0000280f,
226         GUEST_PDPTR3                    = 0x00002810,
227         GUEST_PDPTR3_HIGH               = 0x00002811,
228         HOST_IA32_PAT                   = 0x00002c00,
229         HOST_IA32_PAT_HIGH              = 0x00002c01,
230         HOST_IA32_EFER                  = 0x00002c02,
231         HOST_IA32_EFER_HIGH             = 0x00002c03,
232         HOST_IA32_PERF_GLOBAL_CTRL      = 0x00002c04,
233         HOST_IA32_PERF_GLOBAL_CTRL_HIGH = 0x00002c05,
234         PIN_BASED_VM_EXEC_CONTROL       = 0x00004000,
235         CPU_BASED_VM_EXEC_CONTROL       = 0x00004002,
236         EXCEPTION_BITMAP                = 0x00004004,
237         PAGE_FAULT_ERROR_CODE_MASK      = 0x00004006,
238         PAGE_FAULT_ERROR_CODE_MATCH     = 0x00004008,
239         CR3_TARGET_COUNT                = 0x0000400a,
240         VM_EXIT_CONTROLS                = 0x0000400c,
241         VM_EXIT_MSR_STORE_COUNT         = 0x0000400e,
242         VM_EXIT_MSR_LOAD_COUNT          = 0x00004010,
243         VM_ENTRY_CONTROLS               = 0x00004012,
244         VM_ENTRY_MSR_LOAD_COUNT         = 0x00004014,
245         VM_ENTRY_INTR_INFO_FIELD        = 0x00004016,
246         VM_ENTRY_EXCEPTION_ERROR_CODE   = 0x00004018,
247         VM_ENTRY_INSTRUCTION_LEN        = 0x0000401a,
248         TPR_THRESHOLD                   = 0x0000401c,
249         SECONDARY_VM_EXEC_CONTROL       = 0x0000401e,
250         PLE_GAP                         = 0x00004020,
251         PLE_WINDOW                      = 0x00004022,
252         VM_INSTRUCTION_ERROR            = 0x00004400,
253         VM_EXIT_REASON                  = 0x00004402,
254         VM_EXIT_INTR_INFO               = 0x00004404,
255         VM_EXIT_INTR_ERROR_CODE         = 0x00004406,
256         IDT_VECTORING_INFO_FIELD        = 0x00004408,
257         IDT_VECTORING_ERROR_CODE        = 0x0000440a,
258         VM_EXIT_INSTRUCTION_LEN         = 0x0000440c,
259         VMX_INSTRUCTION_INFO            = 0x0000440e,
260         GUEST_ES_LIMIT                  = 0x00004800,
261         GUEST_CS_LIMIT                  = 0x00004802,
262         GUEST_SS_LIMIT                  = 0x00004804,
263         GUEST_DS_LIMIT                  = 0x00004806,
264         GUEST_FS_LIMIT                  = 0x00004808,
265         GUEST_GS_LIMIT                  = 0x0000480a,
266         GUEST_LDTR_LIMIT                = 0x0000480c,
267         GUEST_TR_LIMIT                  = 0x0000480e,
268         GUEST_GDTR_LIMIT                = 0x00004810,
269         GUEST_IDTR_LIMIT                = 0x00004812,
270         GUEST_ES_AR_BYTES               = 0x00004814,
271         GUEST_CS_AR_BYTES               = 0x00004816,
272         GUEST_SS_AR_BYTES               = 0x00004818,
273         GUEST_DS_AR_BYTES               = 0x0000481a,
274         GUEST_FS_AR_BYTES               = 0x0000481c,
275         GUEST_GS_AR_BYTES               = 0x0000481e,
276         GUEST_LDTR_AR_BYTES             = 0x00004820,
277         GUEST_TR_AR_BYTES               = 0x00004822,
278         GUEST_INTERRUPTIBILITY_INFO     = 0x00004824,
279         GUEST_ACTIVITY_STATE            = 0X00004826,
280         GUEST_SYSENTER_CS               = 0x0000482A,
281         HOST_IA32_SYSENTER_CS           = 0x00004c00,
282         CR0_GUEST_HOST_MASK             = 0x00006000,
283         CR4_GUEST_HOST_MASK             = 0x00006002,
284         CR0_READ_SHADOW                 = 0x00006004,
285         CR4_READ_SHADOW                 = 0x00006006,
286         CR3_TARGET_VALUE0               = 0x00006008,
287         CR3_TARGET_VALUE1               = 0x0000600a,
288         CR3_TARGET_VALUE2               = 0x0000600c,
289         CR3_TARGET_VALUE3               = 0x0000600e,
290         EXIT_QUALIFICATION              = 0x00006400,
291         GUEST_LINEAR_ADDRESS            = 0x0000640a,
292         GUEST_CR0                       = 0x00006800,
293         GUEST_CR3                       = 0x00006802,
294         GUEST_CR4                       = 0x00006804,
295         GUEST_ES_BASE                   = 0x00006806,
296         GUEST_CS_BASE                   = 0x00006808,
297         GUEST_SS_BASE                   = 0x0000680a,
298         GUEST_DS_BASE                   = 0x0000680c,
299         GUEST_FS_BASE                   = 0x0000680e,
300         GUEST_GS_BASE                   = 0x00006810,
301         GUEST_LDTR_BASE                 = 0x00006812,
302         GUEST_TR_BASE                   = 0x00006814,
303         GUEST_GDTR_BASE                 = 0x00006816,
304         GUEST_IDTR_BASE                 = 0x00006818,
305         GUEST_DR7                       = 0x0000681a,
306         GUEST_RSP                       = 0x0000681c,
307         GUEST_RIP                       = 0x0000681e,
308         GUEST_RFLAGS                    = 0x00006820,
309         GUEST_PENDING_DBG_EXCEPTIONS    = 0x00006822,
310         GUEST_SYSENTER_ESP              = 0x00006824,
311         GUEST_SYSENTER_EIP              = 0x00006826,
312         HOST_CR0                        = 0x00006c00,
313         HOST_CR3                        = 0x00006c02,
314         HOST_CR4                        = 0x00006c04,
315         HOST_FS_BASE                    = 0x00006c06,
316         HOST_GS_BASE                    = 0x00006c08,
317         HOST_TR_BASE                    = 0x00006c0a,
318         HOST_GDTR_BASE                  = 0x00006c0c,
319         HOST_IDTR_BASE                  = 0x00006c0e,
320         HOST_IA32_SYSENTER_ESP          = 0x00006c10,
321         HOST_IA32_SYSENTER_EIP          = 0x00006c12,
322         HOST_RSP                        = 0x00006c14,
323         HOST_RIP                        = 0x00006c16,
324 };
325
326 /*
327  * Interruption-information format
328  */
329 #define INTR_INFO_VECTOR_MASK           0xff            /* 7:0 */
330 #define INTR_INFO_INTR_TYPE_MASK        0x700           /* 10:8 */
331 #define INTR_INFO_DELIVER_CODE_MASK     0x800           /* 11 */
332 #define INTR_INFO_UNBLOCK_NMI           0x1000          /* 12 */
333 #define INTR_INFO_VALID_MASK            0x80000000      /* 31 */
334 #define INTR_INFO_RESVD_BITS_MASK       0x7ffff000
335
336 #define VECTORING_INFO_VECTOR_MASK              INTR_INFO_VECTOR_MASK
337 #define VECTORING_INFO_TYPE_MASK                INTR_INFO_INTR_TYPE_MASK
338 #define VECTORING_INFO_DELIVER_CODE_MASK        INTR_INFO_DELIVER_CODE_MASK
339 #define VECTORING_INFO_VALID_MASK               INTR_INFO_VALID_MASK
340
341 #define INTR_TYPE_EXT_INTR              (0 << 8) /* external interrupt */
342 #define INTR_TYPE_NMI_INTR              (2 << 8) /* NMI */
343 #define INTR_TYPE_HARD_EXCEPTION        (3 << 8) /* processor exception */
344 #define INTR_TYPE_SOFT_INTR             (4 << 8) /* software interrupt */
345 #define INTR_TYPE_SOFT_EXCEPTION        (6 << 8) /* software exception */
346
347 /* GUEST_INTERRUPTIBILITY_INFO flags. */
348 #define GUEST_INTR_STATE_STI            0x00000001
349 #define GUEST_INTR_STATE_MOV_SS         0x00000002
350 #define GUEST_INTR_STATE_SMI            0x00000004
351 #define GUEST_INTR_STATE_NMI            0x00000008
352
353 /* GUEST_ACTIVITY_STATE flags */
354 #define GUEST_ACTIVITY_ACTIVE           0
355 #define GUEST_ACTIVITY_HLT              1
356 #define GUEST_ACTIVITY_SHUTDOWN         2
357 #define GUEST_ACTIVITY_WAIT_SIPI        3
358
359 /*
360  * Exit Qualifications for MOV for Control Register Access
361  */
362 #define CONTROL_REG_ACCESS_NUM          0x7     /* 2:0, number of control reg.*/
363 #define CONTROL_REG_ACCESS_TYPE         0x30    /* 5:4, access type */
364 #define CONTROL_REG_ACCESS_REG          0xf00   /* 10:8, general purpose reg. */
365 #define LMSW_SOURCE_DATA_SHIFT 16
366 #define LMSW_SOURCE_DATA  (0xFFFF << LMSW_SOURCE_DATA_SHIFT) /* 16:31 lmsw source */
367 #define REG_EAX                         (0 << 8)
368 #define REG_ECX                         (1 << 8)
369 #define REG_EDX                         (2 << 8)
370 #define REG_EBX                         (3 << 8)
371 #define REG_ESP                         (4 << 8)
372 #define REG_EBP                         (5 << 8)
373 #define REG_ESI                         (6 << 8)
374 #define REG_EDI                         (7 << 8)
375 #define REG_R8                         (8 << 8)
376 #define REG_R9                         (9 << 8)
377 #define REG_R10                        (10 << 8)
378 #define REG_R11                        (11 << 8)
379 #define REG_R12                        (12 << 8)
380 #define REG_R13                        (13 << 8)
381 #define REG_R14                        (14 << 8)
382 #define REG_R15                        (15 << 8)
383
384 /*
385  * Exit Qualifications for MOV for Debug Register Access
386  */
387 #define DEBUG_REG_ACCESS_NUM            0x7     /* 2:0, number of debug reg. */
388 #define DEBUG_REG_ACCESS_TYPE           0x10    /* 4, direction of access */
389 #define TYPE_MOV_TO_DR                  (0 << 4)
390 #define TYPE_MOV_FROM_DR                (1 << 4)
391 #define DEBUG_REG_ACCESS_REG(eq)        (((eq) >> 8) & 0xf) /* 11:8, general purpose reg. */
392
393
394 /*
395  * Exit Qualifications for APIC-Access
396  */
397 #define APIC_ACCESS_OFFSET              0xfff   /* 11:0, offset within the APIC page */
398 #define APIC_ACCESS_TYPE                0xf000  /* 15:12, access type */
399 #define TYPE_LINEAR_APIC_INST_READ      (0 << 12)
400 #define TYPE_LINEAR_APIC_INST_WRITE     (1 << 12)
401 #define TYPE_LINEAR_APIC_INST_FETCH     (2 << 12)
402 #define TYPE_LINEAR_APIC_EVENT          (3 << 12)
403 #define TYPE_PHYSICAL_APIC_EVENT        (10 << 12)
404 #define TYPE_PHYSICAL_APIC_INST         (15 << 12)
405
406 /* segment AR */
407 #define SEGMENT_AR_L_MASK (1 << 13)
408
409 #define AR_TYPE_ACCESSES_MASK 1
410 #define AR_TYPE_READABLE_MASK (1 << 1)
411 #define AR_TYPE_WRITEABLE_MASK (1 << 2)
412 #define AR_TYPE_CODE_MASK (1 << 3)
413 #define AR_TYPE_MASK 0x0f
414 #define AR_TYPE_BUSY_64_TSS 11
415 #define AR_TYPE_BUSY_32_TSS 11
416 #define AR_TYPE_BUSY_16_TSS 3
417 #define AR_TYPE_LDT 2
418
419 #define AR_UNUSABLE_MASK (1 << 16)
420 #define AR_S_MASK (1 << 4)
421 #define AR_P_MASK (1 << 7)
422 #define AR_L_MASK (1 << 13)
423 #define AR_DB_MASK (1 << 14)
424 #define AR_G_MASK (1 << 15)
425 #define AR_DPL_SHIFT 5
426 #define AR_DPL(ar) (((ar) >> AR_DPL_SHIFT) & 3)
427
428 #define AR_RESERVD_MASK 0xfffe0f00
429
430 #define TSS_PRIVATE_MEMSLOT                     (KVM_MEMORY_SLOTS + 0)
431 #define APIC_ACCESS_PAGE_PRIVATE_MEMSLOT        (KVM_MEMORY_SLOTS + 1)
432 #define IDENTITY_PAGETABLE_PRIVATE_MEMSLOT      (KVM_MEMORY_SLOTS + 2)
433
434 #define VMX_NR_VPIDS                            (1 << 16)
435 #define VMX_VPID_EXTENT_SINGLE_CONTEXT          1
436 #define VMX_VPID_EXTENT_ALL_CONTEXT             2
437
438 #define VMX_EPT_EXTENT_INDIVIDUAL_ADDR          0
439 #define VMX_EPT_EXTENT_CONTEXT                  1
440 #define VMX_EPT_EXTENT_GLOBAL                   2
441
442 #define VMX_EPT_EXECUTE_ONLY_BIT                (1ull)
443 #define VMX_EPT_PAGE_WALK_4_BIT                 (1ull << 6)
444 #define VMX_EPTP_UC_BIT                         (1ull << 8)
445 #define VMX_EPTP_WB_BIT                         (1ull << 14)
446 #define VMX_EPT_2MB_PAGE_BIT                    (1ull << 16)
447 #define VMX_EPT_1GB_PAGE_BIT                    (1ull << 17)
448 #define VMX_EPT_AD_BIT                              (1ull << 21)
449 #define VMX_EPT_EXTENT_CONTEXT_BIT              (1ull << 25)
450 #define VMX_EPT_EXTENT_GLOBAL_BIT               (1ull << 26)
451
452 #define VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT      (1ull << 9) /* (41 - 32) */
453 #define VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT      (1ull << 10) /* (42 - 32) */
454
455 #define VMX_EPT_DEFAULT_GAW                     3
456 #define VMX_EPT_MAX_GAW                         0x4
457 #define VMX_EPT_MT_EPTE_SHIFT                   3
458 #define VMX_EPT_GAW_EPTP_SHIFT                  3
459 #define VMX_EPT_AD_ENABLE_BIT                   (1ull << 6)
460 #define VMX_EPT_DEFAULT_MT                      0x6ull
461 #define VMX_EPT_READABLE_MASK                   0x1ull
462 #define VMX_EPT_WRITABLE_MASK                   0x2ull
463 #define VMX_EPT_EXECUTABLE_MASK                 0x4ull
464 #define VMX_EPT_IPAT_BIT                        (1ull << 6)
465 #define VMX_EPT_ACCESS_BIT                              (1ull << 8)
466 #define VMX_EPT_DIRTY_BIT                               (1ull << 9)
467
468 #define VMX_EPT_IDENTITY_PAGETABLE_ADDR         0xfffbc000ul
469
470
471 #define ASM_VMX_VMCLEAR_RAX       ".byte 0x66, 0x0f, 0xc7, 0x30"
472 #define ASM_VMX_VMLAUNCH          ".byte 0x0f, 0x01, 0xc2"
473 #define ASM_VMX_VMRESUME          ".byte 0x0f, 0x01, 0xc3"
474 #define ASM_VMX_VMPTRLD_RAX       ".byte 0x0f, 0xc7, 0x30"
475 #define ASM_VMX_VMREAD_RDX_RAX    ".byte 0x0f, 0x78, 0xd0"
476 #define ASM_VMX_VMWRITE_RAX_RDX   ".byte 0x0f, 0x79, 0xd0"
477 #define ASM_VMX_VMWRITE_RSP_RDX   ".byte 0x0f, 0x79, 0xd4"
478 #define ASM_VMX_VMXOFF            ".byte 0x0f, 0x01, 0xc4"
479 #define ASM_VMX_VMXON_RAX         ".byte 0xf3, 0x0f, 0xc7, 0x30"
480 #define ASM_VMX_INVEPT            ".byte 0x66, 0x0f, 0x38, 0x80, 0x08"
481 #define ASM_VMX_INVVPID           ".byte 0x66, 0x0f, 0x38, 0x81, 0x08"
482
483 struct vmx_msr_entry {
484         u32 index;
485         u32 reserved;
486         u64 value;
487 } __aligned(16);
488
489 /*
490  * Exit Qualifications for entry failure during or after loading guest state
491  */
492 #define ENTRY_FAIL_DEFAULT              0
493 #define ENTRY_FAIL_PDPTE                2
494 #define ENTRY_FAIL_NMI                  3
495 #define ENTRY_FAIL_VMCS_LINK_PTR        4
496
497 /*
498  * VM-instruction error numbers
499  */
500 enum vm_instruction_error_number {
501         VMXERR_VMCALL_IN_VMX_ROOT_OPERATION = 1,
502         VMXERR_VMCLEAR_INVALID_ADDRESS = 2,
503         VMXERR_VMCLEAR_VMXON_POINTER = 3,
504         VMXERR_VMLAUNCH_NONCLEAR_VMCS = 4,
505         VMXERR_VMRESUME_NONLAUNCHED_VMCS = 5,
506         VMXERR_VMRESUME_AFTER_VMXOFF = 6,
507         VMXERR_ENTRY_INVALID_CONTROL_FIELD = 7,
508         VMXERR_ENTRY_INVALID_HOST_STATE_FIELD = 8,
509         VMXERR_VMPTRLD_INVALID_ADDRESS = 9,
510         VMXERR_VMPTRLD_VMXON_POINTER = 10,
511         VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID = 11,
512         VMXERR_UNSUPPORTED_VMCS_COMPONENT = 12,
513         VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT = 13,
514         VMXERR_VMXON_IN_VMX_ROOT_OPERATION = 15,
515         VMXERR_ENTRY_INVALID_EXECUTIVE_VMCS_POINTER = 16,
516         VMXERR_ENTRY_NONLAUNCHED_EXECUTIVE_VMCS = 17,
517         VMXERR_ENTRY_EXECUTIVE_VMCS_POINTER_NOT_VMXON_POINTER = 18,
518         VMXERR_VMCALL_NONCLEAR_VMCS = 19,
519         VMXERR_VMCALL_INVALID_VM_EXIT_CONTROL_FIELDS = 20,
520         VMXERR_VMCALL_INCORRECT_MSEG_REVISION_ID = 22,
521         VMXERR_VMXOFF_UNDER_DUAL_MONITOR_TREATMENT_OF_SMIS_AND_SMM = 23,
522         VMXERR_VMCALL_INVALID_SMM_MONITOR_FEATURES = 24,
523         VMXERR_ENTRY_INVALID_VM_EXECUTION_CONTROL_FIELDS_IN_EXECUTIVE_VMCS = 25,
524         VMXERR_ENTRY_EVENTS_BLOCKED_BY_MOV_SS = 26,
525         VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID = 28,
526 };
527
528 #endif
529
530 #endif