Remove obsolete #include <linux/config.h>
[linux-3.10.git] / arch / sparc64 / mm / init.c
1 /*  $Id: init.c,v 1.209 2002/02/09 19:49:31 davem Exp $
2  *  arch/sparc64/mm/init.c
3  *
4  *  Copyright (C) 1996-1999 David S. Miller (davem@caip.rutgers.edu)
5  *  Copyright (C) 1997-1999 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
6  */
7  
8 #include <linux/module.h>
9 #include <linux/kernel.h>
10 #include <linux/sched.h>
11 #include <linux/string.h>
12 #include <linux/init.h>
13 #include <linux/bootmem.h>
14 #include <linux/mm.h>
15 #include <linux/hugetlb.h>
16 #include <linux/slab.h>
17 #include <linux/initrd.h>
18 #include <linux/swap.h>
19 #include <linux/pagemap.h>
20 #include <linux/poison.h>
21 #include <linux/fs.h>
22 #include <linux/seq_file.h>
23 #include <linux/kprobes.h>
24 #include <linux/cache.h>
25 #include <linux/sort.h>
26
27 #include <asm/head.h>
28 #include <asm/system.h>
29 #include <asm/page.h>
30 #include <asm/pgalloc.h>
31 #include <asm/pgtable.h>
32 #include <asm/oplib.h>
33 #include <asm/iommu.h>
34 #include <asm/io.h>
35 #include <asm/uaccess.h>
36 #include <asm/mmu_context.h>
37 #include <asm/tlbflush.h>
38 #include <asm/dma.h>
39 #include <asm/starfire.h>
40 #include <asm/tlb.h>
41 #include <asm/spitfire.h>
42 #include <asm/sections.h>
43 #include <asm/tsb.h>
44 #include <asm/hypervisor.h>
45 #include <asm/prom.h>
46
47 extern void device_scan(void);
48
49 #define MAX_PHYS_ADDRESS        (1UL << 42UL)
50 #define KPTE_BITMAP_CHUNK_SZ    (256UL * 1024UL * 1024UL)
51 #define KPTE_BITMAP_BYTES       \
52         ((MAX_PHYS_ADDRESS / KPTE_BITMAP_CHUNK_SZ) / 8)
53
54 unsigned long kern_linear_pte_xor[2] __read_mostly;
55
56 /* A bitmap, one bit for every 256MB of physical memory.  If the bit
57  * is clear, we should use a 4MB page (via kern_linear_pte_xor[0]) else
58  * if set we should use a 256MB page (via kern_linear_pte_xor[1]).
59  */
60 unsigned long kpte_linear_bitmap[KPTE_BITMAP_BYTES / sizeof(unsigned long)];
61
62 /* A special kernel TSB for 4MB and 256MB linear mappings.  */
63 struct tsb swapper_4m_tsb[KERNEL_TSB4M_NENTRIES];
64
65 #define MAX_BANKS       32
66
67 static struct linux_prom64_registers pavail[MAX_BANKS] __initdata;
68 static struct linux_prom64_registers pavail_rescan[MAX_BANKS] __initdata;
69 static int pavail_ents __initdata;
70 static int pavail_rescan_ents __initdata;
71
72 static int cmp_p64(const void *a, const void *b)
73 {
74         const struct linux_prom64_registers *x = a, *y = b;
75
76         if (x->phys_addr > y->phys_addr)
77                 return 1;
78         if (x->phys_addr < y->phys_addr)
79                 return -1;
80         return 0;
81 }
82
83 static void __init read_obp_memory(const char *property,
84                                    struct linux_prom64_registers *regs,
85                                    int *num_ents)
86 {
87         int node = prom_finddevice("/memory");
88         int prop_size = prom_getproplen(node, property);
89         int ents, ret, i;
90
91         ents = prop_size / sizeof(struct linux_prom64_registers);
92         if (ents > MAX_BANKS) {
93                 prom_printf("The machine has more %s property entries than "
94                             "this kernel can support (%d).\n",
95                             property, MAX_BANKS);
96                 prom_halt();
97         }
98
99         ret = prom_getproperty(node, property, (char *) regs, prop_size);
100         if (ret == -1) {
101                 prom_printf("Couldn't get %s property from /memory.\n");
102                 prom_halt();
103         }
104
105         /* Sanitize what we got from the firmware, by page aligning
106          * everything.
107          */
108         for (i = 0; i < ents; i++) {
109                 unsigned long base, size;
110
111                 base = regs[i].phys_addr;
112                 size = regs[i].reg_size;
113
114                 size &= PAGE_MASK;
115                 if (base & ~PAGE_MASK) {
116                         unsigned long new_base = PAGE_ALIGN(base);
117
118                         size -= new_base - base;
119                         if ((long) size < 0L)
120                                 size = 0UL;
121                         base = new_base;
122                 }
123                 regs[i].phys_addr = base;
124                 regs[i].reg_size = size;
125         }
126
127         for (i = 0; i < ents; i++) {
128                 if (regs[i].reg_size == 0UL) {
129                         int j;
130
131                         for (j = i; j < ents - 1; j++) {
132                                 regs[j].phys_addr =
133                                         regs[j+1].phys_addr;
134                                 regs[j].reg_size =
135                                         regs[j+1].reg_size;
136                         }
137
138                         ents--;
139                         i--;
140                 }
141         }
142
143         *num_ents = ents;
144
145         sort(regs, ents, sizeof(struct linux_prom64_registers),
146              cmp_p64, NULL);
147 }
148
149 unsigned long *sparc64_valid_addr_bitmap __read_mostly;
150
151 /* Kernel physical address base and size in bytes.  */
152 unsigned long kern_base __read_mostly;
153 unsigned long kern_size __read_mostly;
154
155 /* get_new_mmu_context() uses "cache + 1".  */
156 DEFINE_SPINLOCK(ctx_alloc_lock);
157 unsigned long tlb_context_cache = CTX_FIRST_VERSION - 1;
158 #define CTX_BMAP_SLOTS (1UL << (CTX_NR_BITS - 6))
159 unsigned long mmu_context_bmap[CTX_BMAP_SLOTS];
160
161 /* References to special section boundaries */
162 extern char  _start[], _end[];
163
164 /* Initial ramdisk setup */
165 extern unsigned long sparc_ramdisk_image64;
166 extern unsigned int sparc_ramdisk_image;
167 extern unsigned int sparc_ramdisk_size;
168
169 struct page *mem_map_zero __read_mostly;
170
171 unsigned int sparc64_highest_unlocked_tlb_ent __read_mostly;
172
173 unsigned long sparc64_kern_pri_context __read_mostly;
174 unsigned long sparc64_kern_pri_nuc_bits __read_mostly;
175 unsigned long sparc64_kern_sec_context __read_mostly;
176
177 int bigkernel = 0;
178
179 kmem_cache_t *pgtable_cache __read_mostly;
180
181 static void zero_ctor(void *addr, kmem_cache_t *cache, unsigned long flags)
182 {
183         clear_page(addr);
184 }
185
186 extern void tsb_cache_init(void);
187
188 void pgtable_cache_init(void)
189 {
190         pgtable_cache = kmem_cache_create("pgtable_cache",
191                                           PAGE_SIZE, PAGE_SIZE,
192                                           SLAB_HWCACHE_ALIGN |
193                                           SLAB_MUST_HWCACHE_ALIGN,
194                                           zero_ctor,
195                                           NULL);
196         if (!pgtable_cache) {
197                 prom_printf("Could not create pgtable_cache\n");
198                 prom_halt();
199         }
200         tsb_cache_init();
201 }
202
203 #ifdef CONFIG_DEBUG_DCFLUSH
204 atomic_t dcpage_flushes = ATOMIC_INIT(0);
205 #ifdef CONFIG_SMP
206 atomic_t dcpage_flushes_xcall = ATOMIC_INIT(0);
207 #endif
208 #endif
209
210 inline void flush_dcache_page_impl(struct page *page)
211 {
212         BUG_ON(tlb_type == hypervisor);
213 #ifdef CONFIG_DEBUG_DCFLUSH
214         atomic_inc(&dcpage_flushes);
215 #endif
216
217 #ifdef DCACHE_ALIASING_POSSIBLE
218         __flush_dcache_page(page_address(page),
219                             ((tlb_type == spitfire) &&
220                              page_mapping(page) != NULL));
221 #else
222         if (page_mapping(page) != NULL &&
223             tlb_type == spitfire)
224                 __flush_icache_page(__pa(page_address(page)));
225 #endif
226 }
227
228 #define PG_dcache_dirty         PG_arch_1
229 #define PG_dcache_cpu_shift     24UL
230 #define PG_dcache_cpu_mask      (256UL - 1UL)
231
232 #if NR_CPUS > 256
233 #error D-cache dirty tracking and thread_info->cpu need fixing for > 256 cpus
234 #endif
235
236 #define dcache_dirty_cpu(page) \
237         (((page)->flags >> PG_dcache_cpu_shift) & PG_dcache_cpu_mask)
238
239 static __inline__ void set_dcache_dirty(struct page *page, int this_cpu)
240 {
241         unsigned long mask = this_cpu;
242         unsigned long non_cpu_bits;
243
244         non_cpu_bits = ~(PG_dcache_cpu_mask << PG_dcache_cpu_shift);
245         mask = (mask << PG_dcache_cpu_shift) | (1UL << PG_dcache_dirty);
246
247         __asm__ __volatile__("1:\n\t"
248                              "ldx       [%2], %%g7\n\t"
249                              "and       %%g7, %1, %%g1\n\t"
250                              "or        %%g1, %0, %%g1\n\t"
251                              "casx      [%2], %%g7, %%g1\n\t"
252                              "cmp       %%g7, %%g1\n\t"
253                              "membar    #StoreLoad | #StoreStore\n\t"
254                              "bne,pn    %%xcc, 1b\n\t"
255                              " nop"
256                              : /* no outputs */
257                              : "r" (mask), "r" (non_cpu_bits), "r" (&page->flags)
258                              : "g1", "g7");
259 }
260
261 static __inline__ void clear_dcache_dirty_cpu(struct page *page, unsigned long cpu)
262 {
263         unsigned long mask = (1UL << PG_dcache_dirty);
264
265         __asm__ __volatile__("! test_and_clear_dcache_dirty\n"
266                              "1:\n\t"
267                              "ldx       [%2], %%g7\n\t"
268                              "srlx      %%g7, %4, %%g1\n\t"
269                              "and       %%g1, %3, %%g1\n\t"
270                              "cmp       %%g1, %0\n\t"
271                              "bne,pn    %%icc, 2f\n\t"
272                              " andn     %%g7, %1, %%g1\n\t"
273                              "casx      [%2], %%g7, %%g1\n\t"
274                              "cmp       %%g7, %%g1\n\t"
275                              "membar    #StoreLoad | #StoreStore\n\t"
276                              "bne,pn    %%xcc, 1b\n\t"
277                              " nop\n"
278                              "2:"
279                              : /* no outputs */
280                              : "r" (cpu), "r" (mask), "r" (&page->flags),
281                                "i" (PG_dcache_cpu_mask),
282                                "i" (PG_dcache_cpu_shift)
283                              : "g1", "g7");
284 }
285
286 static inline void tsb_insert(struct tsb *ent, unsigned long tag, unsigned long pte)
287 {
288         unsigned long tsb_addr = (unsigned long) ent;
289
290         if (tlb_type == cheetah_plus || tlb_type == hypervisor)
291                 tsb_addr = __pa(tsb_addr);
292
293         __tsb_insert(tsb_addr, tag, pte);
294 }
295
296 unsigned long _PAGE_ALL_SZ_BITS __read_mostly;
297 unsigned long _PAGE_SZBITS __read_mostly;
298
299 void update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t pte)
300 {
301         struct mm_struct *mm;
302         struct tsb *tsb;
303         unsigned long tag, flags;
304         unsigned long tsb_index, tsb_hash_shift;
305
306         if (tlb_type != hypervisor) {
307                 unsigned long pfn = pte_pfn(pte);
308                 unsigned long pg_flags;
309                 struct page *page;
310
311                 if (pfn_valid(pfn) &&
312                     (page = pfn_to_page(pfn), page_mapping(page)) &&
313                     ((pg_flags = page->flags) & (1UL << PG_dcache_dirty))) {
314                         int cpu = ((pg_flags >> PG_dcache_cpu_shift) &
315                                    PG_dcache_cpu_mask);
316                         int this_cpu = get_cpu();
317
318                         /* This is just to optimize away some function calls
319                          * in the SMP case.
320                          */
321                         if (cpu == this_cpu)
322                                 flush_dcache_page_impl(page);
323                         else
324                                 smp_flush_dcache_page_impl(page, cpu);
325
326                         clear_dcache_dirty_cpu(page, cpu);
327
328                         put_cpu();
329                 }
330         }
331
332         mm = vma->vm_mm;
333
334         tsb_index = MM_TSB_BASE;
335         tsb_hash_shift = PAGE_SHIFT;
336
337         spin_lock_irqsave(&mm->context.lock, flags);
338
339 #ifdef CONFIG_HUGETLB_PAGE
340         if (mm->context.tsb_block[MM_TSB_HUGE].tsb != NULL) {
341                 if ((tlb_type == hypervisor &&
342                      (pte_val(pte) & _PAGE_SZALL_4V) == _PAGE_SZHUGE_4V) ||
343                     (tlb_type != hypervisor &&
344                      (pte_val(pte) & _PAGE_SZALL_4U) == _PAGE_SZHUGE_4U)) {
345                         tsb_index = MM_TSB_HUGE;
346                         tsb_hash_shift = HPAGE_SHIFT;
347                 }
348         }
349 #endif
350
351         tsb = mm->context.tsb_block[tsb_index].tsb;
352         tsb += ((address >> tsb_hash_shift) &
353                 (mm->context.tsb_block[tsb_index].tsb_nentries - 1UL));
354         tag = (address >> 22UL);
355         tsb_insert(tsb, tag, pte_val(pte));
356
357         spin_unlock_irqrestore(&mm->context.lock, flags);
358 }
359
360 void flush_dcache_page(struct page *page)
361 {
362         struct address_space *mapping;
363         int this_cpu;
364
365         if (tlb_type == hypervisor)
366                 return;
367
368         /* Do not bother with the expensive D-cache flush if it
369          * is merely the zero page.  The 'bigcore' testcase in GDB
370          * causes this case to run millions of times.
371          */
372         if (page == ZERO_PAGE(0))
373                 return;
374
375         this_cpu = get_cpu();
376
377         mapping = page_mapping(page);
378         if (mapping && !mapping_mapped(mapping)) {
379                 int dirty = test_bit(PG_dcache_dirty, &page->flags);
380                 if (dirty) {
381                         int dirty_cpu = dcache_dirty_cpu(page);
382
383                         if (dirty_cpu == this_cpu)
384                                 goto out;
385                         smp_flush_dcache_page_impl(page, dirty_cpu);
386                 }
387                 set_dcache_dirty(page, this_cpu);
388         } else {
389                 /* We could delay the flush for the !page_mapping
390                  * case too.  But that case is for exec env/arg
391                  * pages and those are %99 certainly going to get
392                  * faulted into the tlb (and thus flushed) anyways.
393                  */
394                 flush_dcache_page_impl(page);
395         }
396
397 out:
398         put_cpu();
399 }
400
401 void __kprobes flush_icache_range(unsigned long start, unsigned long end)
402 {
403         /* Cheetah and Hypervisor platform cpus have coherent I-cache. */
404         if (tlb_type == spitfire) {
405                 unsigned long kaddr;
406
407                 for (kaddr = start; kaddr < end; kaddr += PAGE_SIZE)
408                         __flush_icache_page(__get_phys(kaddr));
409         }
410 }
411
412 void show_mem(void)
413 {
414         printk("Mem-info:\n");
415         show_free_areas();
416         printk("Free swap:       %6ldkB\n",
417                nr_swap_pages << (PAGE_SHIFT-10));
418         printk("%ld pages of RAM\n", num_physpages);
419         printk("%d free pages\n", nr_free_pages());
420 }
421
422 void mmu_info(struct seq_file *m)
423 {
424         if (tlb_type == cheetah)
425                 seq_printf(m, "MMU Type\t: Cheetah\n");
426         else if (tlb_type == cheetah_plus)
427                 seq_printf(m, "MMU Type\t: Cheetah+\n");
428         else if (tlb_type == spitfire)
429                 seq_printf(m, "MMU Type\t: Spitfire\n");
430         else if (tlb_type == hypervisor)
431                 seq_printf(m, "MMU Type\t: Hypervisor (sun4v)\n");
432         else
433                 seq_printf(m, "MMU Type\t: ???\n");
434
435 #ifdef CONFIG_DEBUG_DCFLUSH
436         seq_printf(m, "DCPageFlushes\t: %d\n",
437                    atomic_read(&dcpage_flushes));
438 #ifdef CONFIG_SMP
439         seq_printf(m, "DCPageFlushesXC\t: %d\n",
440                    atomic_read(&dcpage_flushes_xcall));
441 #endif /* CONFIG_SMP */
442 #endif /* CONFIG_DEBUG_DCFLUSH */
443 }
444
445 struct linux_prom_translation {
446         unsigned long virt;
447         unsigned long size;
448         unsigned long data;
449 };
450
451 /* Exported for kernel TLB miss handling in ktlb.S */
452 struct linux_prom_translation prom_trans[512] __read_mostly;
453 unsigned int prom_trans_ents __read_mostly;
454
455 /* Exported for SMP bootup purposes. */
456 unsigned long kern_locked_tte_data;
457
458 /* The obp translations are saved based on 8k pagesize, since obp can
459  * use a mixture of pagesizes. Misses to the LOW_OBP_ADDRESS ->
460  * HI_OBP_ADDRESS range are handled in ktlb.S.
461  */
462 static inline int in_obp_range(unsigned long vaddr)
463 {
464         return (vaddr >= LOW_OBP_ADDRESS &&
465                 vaddr < HI_OBP_ADDRESS);
466 }
467
468 static int cmp_ptrans(const void *a, const void *b)
469 {
470         const struct linux_prom_translation *x = a, *y = b;
471
472         if (x->virt > y->virt)
473                 return 1;
474         if (x->virt < y->virt)
475                 return -1;
476         return 0;
477 }
478
479 /* Read OBP translations property into 'prom_trans[]'.  */
480 static void __init read_obp_translations(void)
481 {
482         int n, node, ents, first, last, i;
483
484         node = prom_finddevice("/virtual-memory");
485         n = prom_getproplen(node, "translations");
486         if (unlikely(n == 0 || n == -1)) {
487                 prom_printf("prom_mappings: Couldn't get size.\n");
488                 prom_halt();
489         }
490         if (unlikely(n > sizeof(prom_trans))) {
491                 prom_printf("prom_mappings: Size %Zd is too big.\n", n);
492                 prom_halt();
493         }
494
495         if ((n = prom_getproperty(node, "translations",
496                                   (char *)&prom_trans[0],
497                                   sizeof(prom_trans))) == -1) {
498                 prom_printf("prom_mappings: Couldn't get property.\n");
499                 prom_halt();
500         }
501
502         n = n / sizeof(struct linux_prom_translation);
503
504         ents = n;
505
506         sort(prom_trans, ents, sizeof(struct linux_prom_translation),
507              cmp_ptrans, NULL);
508
509         /* Now kick out all the non-OBP entries.  */
510         for (i = 0; i < ents; i++) {
511                 if (in_obp_range(prom_trans[i].virt))
512                         break;
513         }
514         first = i;
515         for (; i < ents; i++) {
516                 if (!in_obp_range(prom_trans[i].virt))
517                         break;
518         }
519         last = i;
520
521         for (i = 0; i < (last - first); i++) {
522                 struct linux_prom_translation *src = &prom_trans[i + first];
523                 struct linux_prom_translation *dest = &prom_trans[i];
524
525                 *dest = *src;
526         }
527         for (; i < ents; i++) {
528                 struct linux_prom_translation *dest = &prom_trans[i];
529                 dest->virt = dest->size = dest->data = 0x0UL;
530         }
531
532         prom_trans_ents = last - first;
533
534         if (tlb_type == spitfire) {
535                 /* Clear diag TTE bits. */
536                 for (i = 0; i < prom_trans_ents; i++)
537                         prom_trans[i].data &= ~0x0003fe0000000000UL;
538         }
539 }
540
541 static void __init hypervisor_tlb_lock(unsigned long vaddr,
542                                        unsigned long pte,
543                                        unsigned long mmu)
544 {
545         register unsigned long func asm("%o5");
546         register unsigned long arg0 asm("%o0");
547         register unsigned long arg1 asm("%o1");
548         register unsigned long arg2 asm("%o2");
549         register unsigned long arg3 asm("%o3");
550
551         func = HV_FAST_MMU_MAP_PERM_ADDR;
552         arg0 = vaddr;
553         arg1 = 0;
554         arg2 = pte;
555         arg3 = mmu;
556         __asm__ __volatile__("ta        0x80"
557                              : "=&r" (func), "=&r" (arg0),
558                                "=&r" (arg1), "=&r" (arg2),
559                                "=&r" (arg3)
560                              : "0" (func), "1" (arg0), "2" (arg1),
561                                "3" (arg2), "4" (arg3));
562         if (arg0 != 0) {
563                 prom_printf("hypervisor_tlb_lock[%lx:%lx:%lx:%lx]: "
564                             "errors with %lx\n", vaddr, 0, pte, mmu, arg0);
565                 prom_halt();
566         }
567 }
568
569 static unsigned long kern_large_tte(unsigned long paddr);
570
571 static void __init remap_kernel(void)
572 {
573         unsigned long phys_page, tte_vaddr, tte_data;
574         int tlb_ent = sparc64_highest_locked_tlbent();
575
576         tte_vaddr = (unsigned long) KERNBASE;
577         phys_page = (prom_boot_mapping_phys_low >> 22UL) << 22UL;
578         tte_data = kern_large_tte(phys_page);
579
580         kern_locked_tte_data = tte_data;
581
582         /* Now lock us into the TLBs via Hypervisor or OBP. */
583         if (tlb_type == hypervisor) {
584                 hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_DMMU);
585                 hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_IMMU);
586                 if (bigkernel) {
587                         tte_vaddr += 0x400000;
588                         tte_data += 0x400000;
589                         hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_DMMU);
590                         hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_IMMU);
591                 }
592         } else {
593                 prom_dtlb_load(tlb_ent, tte_data, tte_vaddr);
594                 prom_itlb_load(tlb_ent, tte_data, tte_vaddr);
595                 if (bigkernel) {
596                         tlb_ent -= 1;
597                         prom_dtlb_load(tlb_ent,
598                                        tte_data + 0x400000, 
599                                        tte_vaddr + 0x400000);
600                         prom_itlb_load(tlb_ent,
601                                        tte_data + 0x400000, 
602                                        tte_vaddr + 0x400000);
603                 }
604                 sparc64_highest_unlocked_tlb_ent = tlb_ent - 1;
605         }
606         if (tlb_type == cheetah_plus) {
607                 sparc64_kern_pri_context = (CTX_CHEETAH_PLUS_CTX0 |
608                                             CTX_CHEETAH_PLUS_NUC);
609                 sparc64_kern_pri_nuc_bits = CTX_CHEETAH_PLUS_NUC;
610                 sparc64_kern_sec_context = CTX_CHEETAH_PLUS_CTX0;
611         }
612 }
613
614
615 static void __init inherit_prom_mappings(void)
616 {
617         read_obp_translations();
618
619         /* Now fixup OBP's idea about where we really are mapped. */
620         prom_printf("Remapping the kernel... ");
621         remap_kernel();
622         prom_printf("done.\n");
623 }
624
625 void prom_world(int enter)
626 {
627         if (!enter)
628                 set_fs((mm_segment_t) { get_thread_current_ds() });
629
630         __asm__ __volatile__("flushw");
631 }
632
633 #ifdef DCACHE_ALIASING_POSSIBLE
634 void __flush_dcache_range(unsigned long start, unsigned long end)
635 {
636         unsigned long va;
637
638         if (tlb_type == spitfire) {
639                 int n = 0;
640
641                 for (va = start; va < end; va += 32) {
642                         spitfire_put_dcache_tag(va & 0x3fe0, 0x0);
643                         if (++n >= 512)
644                                 break;
645                 }
646         } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
647                 start = __pa(start);
648                 end = __pa(end);
649                 for (va = start; va < end; va += 32)
650                         __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
651                                              "membar #Sync"
652                                              : /* no outputs */
653                                              : "r" (va),
654                                                "i" (ASI_DCACHE_INVALIDATE));
655         }
656 }
657 #endif /* DCACHE_ALIASING_POSSIBLE */
658
659 /* Caller does TLB context flushing on local CPU if necessary.
660  * The caller also ensures that CTX_VALID(mm->context) is false.
661  *
662  * We must be careful about boundary cases so that we never
663  * let the user have CTX 0 (nucleus) or we ever use a CTX
664  * version of zero (and thus NO_CONTEXT would not be caught
665  * by version mis-match tests in mmu_context.h).
666  *
667  * Always invoked with interrupts disabled.
668  */
669 void get_new_mmu_context(struct mm_struct *mm)
670 {
671         unsigned long ctx, new_ctx;
672         unsigned long orig_pgsz_bits;
673         unsigned long flags;
674         int new_version;
675
676         spin_lock_irqsave(&ctx_alloc_lock, flags);
677         orig_pgsz_bits = (mm->context.sparc64_ctx_val & CTX_PGSZ_MASK);
678         ctx = (tlb_context_cache + 1) & CTX_NR_MASK;
679         new_ctx = find_next_zero_bit(mmu_context_bmap, 1 << CTX_NR_BITS, ctx);
680         new_version = 0;
681         if (new_ctx >= (1 << CTX_NR_BITS)) {
682                 new_ctx = find_next_zero_bit(mmu_context_bmap, ctx, 1);
683                 if (new_ctx >= ctx) {
684                         int i;
685                         new_ctx = (tlb_context_cache & CTX_VERSION_MASK) +
686                                 CTX_FIRST_VERSION;
687                         if (new_ctx == 1)
688                                 new_ctx = CTX_FIRST_VERSION;
689
690                         /* Don't call memset, for 16 entries that's just
691                          * plain silly...
692                          */
693                         mmu_context_bmap[0] = 3;
694                         mmu_context_bmap[1] = 0;
695                         mmu_context_bmap[2] = 0;
696                         mmu_context_bmap[3] = 0;
697                         for (i = 4; i < CTX_BMAP_SLOTS; i += 4) {
698                                 mmu_context_bmap[i + 0] = 0;
699                                 mmu_context_bmap[i + 1] = 0;
700                                 mmu_context_bmap[i + 2] = 0;
701                                 mmu_context_bmap[i + 3] = 0;
702                         }
703                         new_version = 1;
704                         goto out;
705                 }
706         }
707         mmu_context_bmap[new_ctx>>6] |= (1UL << (new_ctx & 63));
708         new_ctx |= (tlb_context_cache & CTX_VERSION_MASK);
709 out:
710         tlb_context_cache = new_ctx;
711         mm->context.sparc64_ctx_val = new_ctx | orig_pgsz_bits;
712         spin_unlock_irqrestore(&ctx_alloc_lock, flags);
713
714         if (unlikely(new_version))
715                 smp_new_mmu_context_version();
716 }
717
718 void sparc_ultra_dump_itlb(void)
719 {
720         int slot;
721
722         if (tlb_type == spitfire) {
723                 printk ("Contents of itlb: ");
724                 for (slot = 0; slot < 14; slot++) printk ("    ");
725                 printk ("%2x:%016lx,%016lx\n",
726                         0,
727                         spitfire_get_itlb_tag(0), spitfire_get_itlb_data(0));
728                 for (slot = 1; slot < 64; slot+=3) {
729                         printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx %2x:%016lx,%016lx\n", 
730                                 slot,
731                                 spitfire_get_itlb_tag(slot), spitfire_get_itlb_data(slot),
732                                 slot+1,
733                                 spitfire_get_itlb_tag(slot+1), spitfire_get_itlb_data(slot+1),
734                                 slot+2,
735                                 spitfire_get_itlb_tag(slot+2), spitfire_get_itlb_data(slot+2));
736                 }
737         } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
738                 printk ("Contents of itlb0:\n");
739                 for (slot = 0; slot < 16; slot+=2) {
740                         printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx\n",
741                                 slot,
742                                 cheetah_get_litlb_tag(slot), cheetah_get_litlb_data(slot),
743                                 slot+1,
744                                 cheetah_get_litlb_tag(slot+1), cheetah_get_litlb_data(slot+1));
745                 }
746                 printk ("Contents of itlb2:\n");
747                 for (slot = 0; slot < 128; slot+=2) {
748                         printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx\n",
749                                 slot,
750                                 cheetah_get_itlb_tag(slot), cheetah_get_itlb_data(slot),
751                                 slot+1,
752                                 cheetah_get_itlb_tag(slot+1), cheetah_get_itlb_data(slot+1));
753                 }
754         }
755 }
756
757 void sparc_ultra_dump_dtlb(void)
758 {
759         int slot;
760
761         if (tlb_type == spitfire) {
762                 printk ("Contents of dtlb: ");
763                 for (slot = 0; slot < 14; slot++) printk ("    ");
764                 printk ("%2x:%016lx,%016lx\n", 0,
765                         spitfire_get_dtlb_tag(0), spitfire_get_dtlb_data(0));
766                 for (slot = 1; slot < 64; slot+=3) {
767                         printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx %2x:%016lx,%016lx\n", 
768                                 slot,
769                                 spitfire_get_dtlb_tag(slot), spitfire_get_dtlb_data(slot),
770                                 slot+1,
771                                 spitfire_get_dtlb_tag(slot+1), spitfire_get_dtlb_data(slot+1),
772                                 slot+2,
773                                 spitfire_get_dtlb_tag(slot+2), spitfire_get_dtlb_data(slot+2));
774                 }
775         } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
776                 printk ("Contents of dtlb0:\n");
777                 for (slot = 0; slot < 16; slot+=2) {
778                         printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx\n",
779                                 slot,
780                                 cheetah_get_ldtlb_tag(slot), cheetah_get_ldtlb_data(slot),
781                                 slot+1,
782                                 cheetah_get_ldtlb_tag(slot+1), cheetah_get_ldtlb_data(slot+1));
783                 }
784                 printk ("Contents of dtlb2:\n");
785                 for (slot = 0; slot < 512; slot+=2) {
786                         printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx\n",
787                                 slot,
788                                 cheetah_get_dtlb_tag(slot, 2), cheetah_get_dtlb_data(slot, 2),
789                                 slot+1,
790                                 cheetah_get_dtlb_tag(slot+1, 2), cheetah_get_dtlb_data(slot+1, 2));
791                 }
792                 if (tlb_type == cheetah_plus) {
793                         printk ("Contents of dtlb3:\n");
794                         for (slot = 0; slot < 512; slot+=2) {
795                                 printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx\n",
796                                         slot,
797                                         cheetah_get_dtlb_tag(slot, 3), cheetah_get_dtlb_data(slot, 3),
798                                         slot+1,
799                                         cheetah_get_dtlb_tag(slot+1, 3), cheetah_get_dtlb_data(slot+1, 3));
800                         }
801                 }
802         }
803 }
804
805 extern unsigned long cmdline_memory_size;
806
807 /* Find a free area for the bootmem map, avoiding the kernel image
808  * and the initial ramdisk.
809  */
810 static unsigned long __init choose_bootmap_pfn(unsigned long start_pfn,
811                                                unsigned long end_pfn)
812 {
813         unsigned long avoid_start, avoid_end, bootmap_size;
814         int i;
815
816         bootmap_size = ((end_pfn - start_pfn) + 7) / 8;
817         bootmap_size = ALIGN(bootmap_size, sizeof(long));
818
819         avoid_start = avoid_end = 0;
820 #ifdef CONFIG_BLK_DEV_INITRD
821         avoid_start = initrd_start;
822         avoid_end = PAGE_ALIGN(initrd_end);
823 #endif
824
825 #ifdef CONFIG_DEBUG_BOOTMEM
826         prom_printf("choose_bootmap_pfn: kern[%lx:%lx] avoid[%lx:%lx]\n",
827                     kern_base, PAGE_ALIGN(kern_base + kern_size),
828                     avoid_start, avoid_end);
829 #endif
830         for (i = 0; i < pavail_ents; i++) {
831                 unsigned long start, end;
832
833                 start = pavail[i].phys_addr;
834                 end = start + pavail[i].reg_size;
835
836                 while (start < end) {
837                         if (start >= kern_base &&
838                             start < PAGE_ALIGN(kern_base + kern_size)) {
839                                 start = PAGE_ALIGN(kern_base + kern_size);
840                                 continue;
841                         }
842                         if (start >= avoid_start && start < avoid_end) {
843                                 start = avoid_end;
844                                 continue;
845                         }
846
847                         if ((end - start) < bootmap_size)
848                                 break;
849
850                         if (start < kern_base &&
851                             (start + bootmap_size) > kern_base) {
852                                 start = PAGE_ALIGN(kern_base + kern_size);
853                                 continue;
854                         }
855
856                         if (start < avoid_start &&
857                             (start + bootmap_size) > avoid_start) {
858                                 start = avoid_end;
859                                 continue;
860                         }
861
862                         /* OK, it doesn't overlap anything, use it.  */
863 #ifdef CONFIG_DEBUG_BOOTMEM
864                         prom_printf("choose_bootmap_pfn: Using %lx [%lx]\n",
865                                     start >> PAGE_SHIFT, start);
866 #endif
867                         return start >> PAGE_SHIFT;
868                 }
869         }
870
871         prom_printf("Cannot find free area for bootmap, aborting.\n");
872         prom_halt();
873 }
874
875 static unsigned long __init bootmem_init(unsigned long *pages_avail,
876                                          unsigned long phys_base)
877 {
878         unsigned long bootmap_size, end_pfn;
879         unsigned long end_of_phys_memory = 0UL;
880         unsigned long bootmap_pfn, bytes_avail, size;
881         int i;
882
883 #ifdef CONFIG_DEBUG_BOOTMEM
884         prom_printf("bootmem_init: Scan pavail, ");
885 #endif
886
887         bytes_avail = 0UL;
888         for (i = 0; i < pavail_ents; i++) {
889                 end_of_phys_memory = pavail[i].phys_addr +
890                         pavail[i].reg_size;
891                 bytes_avail += pavail[i].reg_size;
892                 if (cmdline_memory_size) {
893                         if (bytes_avail > cmdline_memory_size) {
894                                 unsigned long slack = bytes_avail - cmdline_memory_size;
895
896                                 bytes_avail -= slack;
897                                 end_of_phys_memory -= slack;
898
899                                 pavail[i].reg_size -= slack;
900                                 if ((long)pavail[i].reg_size <= 0L) {
901                                         pavail[i].phys_addr = 0xdeadbeefUL;
902                                         pavail[i].reg_size = 0UL;
903                                         pavail_ents = i;
904                                 } else {
905                                         pavail[i+1].reg_size = 0Ul;
906                                         pavail[i+1].phys_addr = 0xdeadbeefUL;
907                                         pavail_ents = i + 1;
908                                 }
909                                 break;
910                         }
911                 }
912         }
913
914         *pages_avail = bytes_avail >> PAGE_SHIFT;
915
916         end_pfn = end_of_phys_memory >> PAGE_SHIFT;
917
918 #ifdef CONFIG_BLK_DEV_INITRD
919         /* Now have to check initial ramdisk, so that bootmap does not overwrite it */
920         if (sparc_ramdisk_image || sparc_ramdisk_image64) {
921                 unsigned long ramdisk_image = sparc_ramdisk_image ?
922                         sparc_ramdisk_image : sparc_ramdisk_image64;
923                 if (ramdisk_image >= (unsigned long)_end - 2 * PAGE_SIZE)
924                         ramdisk_image -= KERNBASE;
925                 initrd_start = ramdisk_image + phys_base;
926                 initrd_end = initrd_start + sparc_ramdisk_size;
927                 if (initrd_end > end_of_phys_memory) {
928                         printk(KERN_CRIT "initrd extends beyond end of memory "
929                                          "(0x%016lx > 0x%016lx)\ndisabling initrd\n",
930                                initrd_end, end_of_phys_memory);
931                         initrd_start = 0;
932                         initrd_end = 0;
933                 }
934         }
935 #endif  
936         /* Initialize the boot-time allocator. */
937         max_pfn = max_low_pfn = end_pfn;
938         min_low_pfn = (phys_base >> PAGE_SHIFT);
939
940         bootmap_pfn = choose_bootmap_pfn(min_low_pfn, end_pfn);
941
942 #ifdef CONFIG_DEBUG_BOOTMEM
943         prom_printf("init_bootmem(min[%lx], bootmap[%lx], max[%lx])\n",
944                     min_low_pfn, bootmap_pfn, max_low_pfn);
945 #endif
946         bootmap_size = init_bootmem_node(NODE_DATA(0), bootmap_pfn,
947                                          min_low_pfn, end_pfn);
948
949         /* Now register the available physical memory with the
950          * allocator.
951          */
952         for (i = 0; i < pavail_ents; i++) {
953 #ifdef CONFIG_DEBUG_BOOTMEM
954                 prom_printf("free_bootmem(pavail:%d): base[%lx] size[%lx]\n",
955                             i, pavail[i].phys_addr, pavail[i].reg_size);
956 #endif
957                 free_bootmem(pavail[i].phys_addr, pavail[i].reg_size);
958         }
959
960 #ifdef CONFIG_BLK_DEV_INITRD
961         if (initrd_start) {
962                 size = initrd_end - initrd_start;
963
964                 /* Resert the initrd image area. */
965 #ifdef CONFIG_DEBUG_BOOTMEM
966                 prom_printf("reserve_bootmem(initrd): base[%llx] size[%lx]\n",
967                         initrd_start, initrd_end);
968 #endif
969                 reserve_bootmem(initrd_start, size);
970                 *pages_avail -= PAGE_ALIGN(size) >> PAGE_SHIFT;
971
972                 initrd_start += PAGE_OFFSET;
973                 initrd_end += PAGE_OFFSET;
974         }
975 #endif
976         /* Reserve the kernel text/data/bss. */
977 #ifdef CONFIG_DEBUG_BOOTMEM
978         prom_printf("reserve_bootmem(kernel): base[%lx] size[%lx]\n", kern_base, kern_size);
979 #endif
980         reserve_bootmem(kern_base, kern_size);
981         *pages_avail -= PAGE_ALIGN(kern_size) >> PAGE_SHIFT;
982
983         /* Reserve the bootmem map.   We do not account for it
984          * in pages_avail because we will release that memory
985          * in free_all_bootmem.
986          */
987         size = bootmap_size;
988 #ifdef CONFIG_DEBUG_BOOTMEM
989         prom_printf("reserve_bootmem(bootmap): base[%lx] size[%lx]\n",
990                     (bootmap_pfn << PAGE_SHIFT), size);
991 #endif
992         reserve_bootmem((bootmap_pfn << PAGE_SHIFT), size);
993         *pages_avail -= PAGE_ALIGN(size) >> PAGE_SHIFT;
994
995         for (i = 0; i < pavail_ents; i++) {
996                 unsigned long start_pfn, end_pfn;
997
998                 start_pfn = pavail[i].phys_addr >> PAGE_SHIFT;
999                 end_pfn = (start_pfn + (pavail[i].reg_size >> PAGE_SHIFT));
1000 #ifdef CONFIG_DEBUG_BOOTMEM
1001                 prom_printf("memory_present(0, %lx, %lx)\n",
1002                             start_pfn, end_pfn);
1003 #endif
1004                 memory_present(0, start_pfn, end_pfn);
1005         }
1006
1007         sparse_init();
1008
1009         return end_pfn;
1010 }
1011
1012 static struct linux_prom64_registers pall[MAX_BANKS] __initdata;
1013 static int pall_ents __initdata;
1014
1015 #ifdef CONFIG_DEBUG_PAGEALLOC
1016 static unsigned long kernel_map_range(unsigned long pstart, unsigned long pend, pgprot_t prot)
1017 {
1018         unsigned long vstart = PAGE_OFFSET + pstart;
1019         unsigned long vend = PAGE_OFFSET + pend;
1020         unsigned long alloc_bytes = 0UL;
1021
1022         if ((vstart & ~PAGE_MASK) || (vend & ~PAGE_MASK)) {
1023                 prom_printf("kernel_map: Unaligned physmem[%lx:%lx]\n",
1024                             vstart, vend);
1025                 prom_halt();
1026         }
1027
1028         while (vstart < vend) {
1029                 unsigned long this_end, paddr = __pa(vstart);
1030                 pgd_t *pgd = pgd_offset_k(vstart);
1031                 pud_t *pud;
1032                 pmd_t *pmd;
1033                 pte_t *pte;
1034
1035                 pud = pud_offset(pgd, vstart);
1036                 if (pud_none(*pud)) {
1037                         pmd_t *new;
1038
1039                         new = __alloc_bootmem(PAGE_SIZE, PAGE_SIZE, PAGE_SIZE);
1040                         alloc_bytes += PAGE_SIZE;
1041                         pud_populate(&init_mm, pud, new);
1042                 }
1043
1044                 pmd = pmd_offset(pud, vstart);
1045                 if (!pmd_present(*pmd)) {
1046                         pte_t *new;
1047
1048                         new = __alloc_bootmem(PAGE_SIZE, PAGE_SIZE, PAGE_SIZE);
1049                         alloc_bytes += PAGE_SIZE;
1050                         pmd_populate_kernel(&init_mm, pmd, new);
1051                 }
1052
1053                 pte = pte_offset_kernel(pmd, vstart);
1054                 this_end = (vstart + PMD_SIZE) & PMD_MASK;
1055                 if (this_end > vend)
1056                         this_end = vend;
1057
1058                 while (vstart < this_end) {
1059                         pte_val(*pte) = (paddr | pgprot_val(prot));
1060
1061                         vstart += PAGE_SIZE;
1062                         paddr += PAGE_SIZE;
1063                         pte++;
1064                 }
1065         }
1066
1067         return alloc_bytes;
1068 }
1069
1070 extern unsigned int kvmap_linear_patch[1];
1071 #endif /* CONFIG_DEBUG_PAGEALLOC */
1072
1073 static void __init mark_kpte_bitmap(unsigned long start, unsigned long end)
1074 {
1075         const unsigned long shift_256MB = 28;
1076         const unsigned long mask_256MB = ((1UL << shift_256MB) - 1UL);
1077         const unsigned long size_256MB = (1UL << shift_256MB);
1078
1079         while (start < end) {
1080                 long remains;
1081
1082                 remains = end - start;
1083                 if (remains < size_256MB)
1084                         break;
1085
1086                 if (start & mask_256MB) {
1087                         start = (start + size_256MB) & ~mask_256MB;
1088                         continue;
1089                 }
1090
1091                 while (remains >= size_256MB) {
1092                         unsigned long index = start >> shift_256MB;
1093
1094                         __set_bit(index, kpte_linear_bitmap);
1095
1096                         start += size_256MB;
1097                         remains -= size_256MB;
1098                 }
1099         }
1100 }
1101
1102 static void __init kernel_physical_mapping_init(void)
1103 {
1104         unsigned long i;
1105 #ifdef CONFIG_DEBUG_PAGEALLOC
1106         unsigned long mem_alloced = 0UL;
1107 #endif
1108
1109         read_obp_memory("reg", &pall[0], &pall_ents);
1110
1111         for (i = 0; i < pall_ents; i++) {
1112                 unsigned long phys_start, phys_end;
1113
1114                 phys_start = pall[i].phys_addr;
1115                 phys_end = phys_start + pall[i].reg_size;
1116
1117                 mark_kpte_bitmap(phys_start, phys_end);
1118
1119 #ifdef CONFIG_DEBUG_PAGEALLOC
1120                 mem_alloced += kernel_map_range(phys_start, phys_end,
1121                                                 PAGE_KERNEL);
1122 #endif
1123         }
1124
1125 #ifdef CONFIG_DEBUG_PAGEALLOC
1126         printk("Allocated %ld bytes for kernel page tables.\n",
1127                mem_alloced);
1128
1129         kvmap_linear_patch[0] = 0x01000000; /* nop */
1130         flushi(&kvmap_linear_patch[0]);
1131
1132         __flush_tlb_all();
1133 #endif
1134 }
1135
1136 #ifdef CONFIG_DEBUG_PAGEALLOC
1137 void kernel_map_pages(struct page *page, int numpages, int enable)
1138 {
1139         unsigned long phys_start = page_to_pfn(page) << PAGE_SHIFT;
1140         unsigned long phys_end = phys_start + (numpages * PAGE_SIZE);
1141
1142         kernel_map_range(phys_start, phys_end,
1143                          (enable ? PAGE_KERNEL : __pgprot(0)));
1144
1145         flush_tsb_kernel_range(PAGE_OFFSET + phys_start,
1146                                PAGE_OFFSET + phys_end);
1147
1148         /* we should perform an IPI and flush all tlbs,
1149          * but that can deadlock->flush only current cpu.
1150          */
1151         __flush_tlb_kernel_range(PAGE_OFFSET + phys_start,
1152                                  PAGE_OFFSET + phys_end);
1153 }
1154 #endif
1155
1156 unsigned long __init find_ecache_flush_span(unsigned long size)
1157 {
1158         int i;
1159
1160         for (i = 0; i < pavail_ents; i++) {
1161                 if (pavail[i].reg_size >= size)
1162                         return pavail[i].phys_addr;
1163         }
1164
1165         return ~0UL;
1166 }
1167
1168 static void __init tsb_phys_patch(void)
1169 {
1170         struct tsb_ldquad_phys_patch_entry *pquad;
1171         struct tsb_phys_patch_entry *p;
1172
1173         pquad = &__tsb_ldquad_phys_patch;
1174         while (pquad < &__tsb_ldquad_phys_patch_end) {
1175                 unsigned long addr = pquad->addr;
1176
1177                 if (tlb_type == hypervisor)
1178                         *(unsigned int *) addr = pquad->sun4v_insn;
1179                 else
1180                         *(unsigned int *) addr = pquad->sun4u_insn;
1181                 wmb();
1182                 __asm__ __volatile__("flush     %0"
1183                                      : /* no outputs */
1184                                      : "r" (addr));
1185
1186                 pquad++;
1187         }
1188
1189         p = &__tsb_phys_patch;
1190         while (p < &__tsb_phys_patch_end) {
1191                 unsigned long addr = p->addr;
1192
1193                 *(unsigned int *) addr = p->insn;
1194                 wmb();
1195                 __asm__ __volatile__("flush     %0"
1196                                      : /* no outputs */
1197                                      : "r" (addr));
1198
1199                 p++;
1200         }
1201 }
1202
1203 /* Don't mark as init, we give this to the Hypervisor.  */
1204 static struct hv_tsb_descr ktsb_descr[2];
1205 extern struct tsb swapper_tsb[KERNEL_TSB_NENTRIES];
1206
1207 static void __init sun4v_ktsb_init(void)
1208 {
1209         unsigned long ktsb_pa;
1210
1211         /* First KTSB for PAGE_SIZE mappings.  */
1212         ktsb_pa = kern_base + ((unsigned long)&swapper_tsb[0] - KERNBASE);
1213
1214         switch (PAGE_SIZE) {
1215         case 8 * 1024:
1216         default:
1217                 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_8K;
1218                 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_8K;
1219                 break;
1220
1221         case 64 * 1024:
1222                 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_64K;
1223                 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_64K;
1224                 break;
1225
1226         case 512 * 1024:
1227                 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_512K;
1228                 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_512K;
1229                 break;
1230
1231         case 4 * 1024 * 1024:
1232                 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_4MB;
1233                 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_4MB;
1234                 break;
1235         };
1236
1237         ktsb_descr[0].assoc = 1;
1238         ktsb_descr[0].num_ttes = KERNEL_TSB_NENTRIES;
1239         ktsb_descr[0].ctx_idx = 0;
1240         ktsb_descr[0].tsb_base = ktsb_pa;
1241         ktsb_descr[0].resv = 0;
1242
1243         /* Second KTSB for 4MB/256MB mappings.  */
1244         ktsb_pa = (kern_base +
1245                    ((unsigned long)&swapper_4m_tsb[0] - KERNBASE));
1246
1247         ktsb_descr[1].pgsz_idx = HV_PGSZ_IDX_4MB;
1248         ktsb_descr[1].pgsz_mask = (HV_PGSZ_MASK_4MB |
1249                                    HV_PGSZ_MASK_256MB);
1250         ktsb_descr[1].assoc = 1;
1251         ktsb_descr[1].num_ttes = KERNEL_TSB4M_NENTRIES;
1252         ktsb_descr[1].ctx_idx = 0;
1253         ktsb_descr[1].tsb_base = ktsb_pa;
1254         ktsb_descr[1].resv = 0;
1255 }
1256
1257 void __cpuinit sun4v_ktsb_register(void)
1258 {
1259         register unsigned long func asm("%o5");
1260         register unsigned long arg0 asm("%o0");
1261         register unsigned long arg1 asm("%o1");
1262         unsigned long pa;
1263
1264         pa = kern_base + ((unsigned long)&ktsb_descr[0] - KERNBASE);
1265
1266         func = HV_FAST_MMU_TSB_CTX0;
1267         arg0 = 2;
1268         arg1 = pa;
1269         __asm__ __volatile__("ta        %6"
1270                              : "=&r" (func), "=&r" (arg0), "=&r" (arg1)
1271                              : "0" (func), "1" (arg0), "2" (arg1),
1272                                "i" (HV_FAST_TRAP));
1273 }
1274
1275 /* paging_init() sets up the page tables */
1276
1277 extern void cheetah_ecache_flush_init(void);
1278 extern void sun4v_patch_tlb_handlers(void);
1279
1280 static unsigned long last_valid_pfn;
1281 pgd_t swapper_pg_dir[2048];
1282
1283 static void sun4u_pgprot_init(void);
1284 static void sun4v_pgprot_init(void);
1285
1286 void __init paging_init(void)
1287 {
1288         unsigned long end_pfn, pages_avail, shift, phys_base;
1289         unsigned long real_end, i;
1290
1291         kern_base = (prom_boot_mapping_phys_low >> 22UL) << 22UL;
1292         kern_size = (unsigned long)&_end - (unsigned long)KERNBASE;
1293
1294         /* Invalidate both kernel TSBs.  */
1295         memset(swapper_tsb, 0x40, sizeof(swapper_tsb));
1296         memset(swapper_4m_tsb, 0x40, sizeof(swapper_4m_tsb));
1297
1298         if (tlb_type == hypervisor)
1299                 sun4v_pgprot_init();
1300         else
1301                 sun4u_pgprot_init();
1302
1303         if (tlb_type == cheetah_plus ||
1304             tlb_type == hypervisor)
1305                 tsb_phys_patch();
1306
1307         if (tlb_type == hypervisor) {
1308                 sun4v_patch_tlb_handlers();
1309                 sun4v_ktsb_init();
1310         }
1311
1312         /* Find available physical memory... */
1313         read_obp_memory("available", &pavail[0], &pavail_ents);
1314
1315         phys_base = 0xffffffffffffffffUL;
1316         for (i = 0; i < pavail_ents; i++)
1317                 phys_base = min(phys_base, pavail[i].phys_addr);
1318
1319         set_bit(0, mmu_context_bmap);
1320
1321         shift = kern_base + PAGE_OFFSET - ((unsigned long)KERNBASE);
1322
1323         real_end = (unsigned long)_end;
1324         if ((real_end > ((unsigned long)KERNBASE + 0x400000)))
1325                 bigkernel = 1;
1326         if ((real_end > ((unsigned long)KERNBASE + 0x800000))) {
1327                 prom_printf("paging_init: Kernel > 8MB, too large.\n");
1328                 prom_halt();
1329         }
1330
1331         /* Set kernel pgd to upper alias so physical page computations
1332          * work.
1333          */
1334         init_mm.pgd += ((shift) / (sizeof(pgd_t)));
1335         
1336         memset(swapper_low_pmd_dir, 0, sizeof(swapper_low_pmd_dir));
1337
1338         /* Now can init the kernel/bad page tables. */
1339         pud_set(pud_offset(&swapper_pg_dir[0], 0),
1340                 swapper_low_pmd_dir + (shift / sizeof(pgd_t)));
1341         
1342         inherit_prom_mappings();
1343         
1344         /* Ok, we can use our TLB miss and window trap handlers safely.  */
1345         setup_tba();
1346
1347         __flush_tlb_all();
1348
1349         if (tlb_type == hypervisor)
1350                 sun4v_ktsb_register();
1351
1352         /* Setup bootmem... */
1353         pages_avail = 0;
1354         last_valid_pfn = end_pfn = bootmem_init(&pages_avail, phys_base);
1355
1356         max_mapnr = last_valid_pfn;
1357
1358         kernel_physical_mapping_init();
1359
1360         prom_build_devicetree();
1361
1362         {
1363                 unsigned long zones_size[MAX_NR_ZONES];
1364                 unsigned long zholes_size[MAX_NR_ZONES];
1365                 int znum;
1366
1367                 for (znum = 0; znum < MAX_NR_ZONES; znum++)
1368                         zones_size[znum] = zholes_size[znum] = 0;
1369
1370                 zones_size[ZONE_DMA] = end_pfn;
1371                 zholes_size[ZONE_DMA] = end_pfn - pages_avail;
1372
1373                 free_area_init_node(0, &contig_page_data, zones_size,
1374                                     __pa(PAGE_OFFSET) >> PAGE_SHIFT,
1375                                     zholes_size);
1376         }
1377
1378         device_scan();
1379 }
1380
1381 static void __init taint_real_pages(void)
1382 {
1383         int i;
1384
1385         read_obp_memory("available", &pavail_rescan[0], &pavail_rescan_ents);
1386
1387         /* Find changes discovered in the physmem available rescan and
1388          * reserve the lost portions in the bootmem maps.
1389          */
1390         for (i = 0; i < pavail_ents; i++) {
1391                 unsigned long old_start, old_end;
1392
1393                 old_start = pavail[i].phys_addr;
1394                 old_end = old_start +
1395                         pavail[i].reg_size;
1396                 while (old_start < old_end) {
1397                         int n;
1398
1399                         for (n = 0; n < pavail_rescan_ents; n++) {
1400                                 unsigned long new_start, new_end;
1401
1402                                 new_start = pavail_rescan[n].phys_addr;
1403                                 new_end = new_start +
1404                                         pavail_rescan[n].reg_size;
1405
1406                                 if (new_start <= old_start &&
1407                                     new_end >= (old_start + PAGE_SIZE)) {
1408                                         set_bit(old_start >> 22,
1409                                                 sparc64_valid_addr_bitmap);
1410                                         goto do_next_page;
1411                                 }
1412                         }
1413                         reserve_bootmem(old_start, PAGE_SIZE);
1414
1415                 do_next_page:
1416                         old_start += PAGE_SIZE;
1417                 }
1418         }
1419 }
1420
1421 int __init page_in_phys_avail(unsigned long paddr)
1422 {
1423         int i;
1424
1425         paddr &= PAGE_MASK;
1426
1427         for (i = 0; i < pavail_rescan_ents; i++) {
1428                 unsigned long start, end;
1429
1430                 start = pavail_rescan[i].phys_addr;
1431                 end = start + pavail_rescan[i].reg_size;
1432
1433                 if (paddr >= start && paddr < end)
1434                         return 1;
1435         }
1436         if (paddr >= kern_base && paddr < (kern_base + kern_size))
1437                 return 1;
1438 #ifdef CONFIG_BLK_DEV_INITRD
1439         if (paddr >= __pa(initrd_start) &&
1440             paddr < __pa(PAGE_ALIGN(initrd_end)))
1441                 return 1;
1442 #endif
1443
1444         return 0;
1445 }
1446
1447 void __init mem_init(void)
1448 {
1449         unsigned long codepages, datapages, initpages;
1450         unsigned long addr, last;
1451         int i;
1452
1453         i = last_valid_pfn >> ((22 - PAGE_SHIFT) + 6);
1454         i += 1;
1455         sparc64_valid_addr_bitmap = (unsigned long *) alloc_bootmem(i << 3);
1456         if (sparc64_valid_addr_bitmap == NULL) {
1457                 prom_printf("mem_init: Cannot alloc valid_addr_bitmap.\n");
1458                 prom_halt();
1459         }
1460         memset(sparc64_valid_addr_bitmap, 0, i << 3);
1461
1462         addr = PAGE_OFFSET + kern_base;
1463         last = PAGE_ALIGN(kern_size) + addr;
1464         while (addr < last) {
1465                 set_bit(__pa(addr) >> 22, sparc64_valid_addr_bitmap);
1466                 addr += PAGE_SIZE;
1467         }
1468
1469         taint_real_pages();
1470
1471         high_memory = __va(last_valid_pfn << PAGE_SHIFT);
1472
1473 #ifdef CONFIG_DEBUG_BOOTMEM
1474         prom_printf("mem_init: Calling free_all_bootmem().\n");
1475 #endif
1476         totalram_pages = num_physpages = free_all_bootmem() - 1;
1477
1478         /*
1479          * Set up the zero page, mark it reserved, so that page count
1480          * is not manipulated when freeing the page from user ptes.
1481          */
1482         mem_map_zero = alloc_pages(GFP_KERNEL|__GFP_ZERO, 0);
1483         if (mem_map_zero == NULL) {
1484                 prom_printf("paging_init: Cannot alloc zero page.\n");
1485                 prom_halt();
1486         }
1487         SetPageReserved(mem_map_zero);
1488
1489         codepages = (((unsigned long) _etext) - ((unsigned long) _start));
1490         codepages = PAGE_ALIGN(codepages) >> PAGE_SHIFT;
1491         datapages = (((unsigned long) _edata) - ((unsigned long) _etext));
1492         datapages = PAGE_ALIGN(datapages) >> PAGE_SHIFT;
1493         initpages = (((unsigned long) __init_end) - ((unsigned long) __init_begin));
1494         initpages = PAGE_ALIGN(initpages) >> PAGE_SHIFT;
1495
1496         printk("Memory: %uk available (%ldk kernel code, %ldk data, %ldk init) [%016lx,%016lx]\n",
1497                nr_free_pages() << (PAGE_SHIFT-10),
1498                codepages << (PAGE_SHIFT-10),
1499                datapages << (PAGE_SHIFT-10), 
1500                initpages << (PAGE_SHIFT-10), 
1501                PAGE_OFFSET, (last_valid_pfn << PAGE_SHIFT));
1502
1503         if (tlb_type == cheetah || tlb_type == cheetah_plus)
1504                 cheetah_ecache_flush_init();
1505 }
1506
1507 void free_initmem(void)
1508 {
1509         unsigned long addr, initend;
1510
1511         /*
1512          * The init section is aligned to 8k in vmlinux.lds. Page align for >8k pagesizes.
1513          */
1514         addr = PAGE_ALIGN((unsigned long)(__init_begin));
1515         initend = (unsigned long)(__init_end) & PAGE_MASK;
1516         for (; addr < initend; addr += PAGE_SIZE) {
1517                 unsigned long page;
1518                 struct page *p;
1519
1520                 page = (addr +
1521                         ((unsigned long) __va(kern_base)) -
1522                         ((unsigned long) KERNBASE));
1523                 memset((void *)addr, POISON_FREE_INITMEM, PAGE_SIZE);
1524                 p = virt_to_page(page);
1525
1526                 ClearPageReserved(p);
1527                 init_page_count(p);
1528                 __free_page(p);
1529                 num_physpages++;
1530                 totalram_pages++;
1531         }
1532 }
1533
1534 #ifdef CONFIG_BLK_DEV_INITRD
1535 void free_initrd_mem(unsigned long start, unsigned long end)
1536 {
1537         if (start < end)
1538                 printk ("Freeing initrd memory: %ldk freed\n", (end - start) >> 10);
1539         for (; start < end; start += PAGE_SIZE) {
1540                 struct page *p = virt_to_page(start);
1541
1542                 ClearPageReserved(p);
1543                 init_page_count(p);
1544                 __free_page(p);
1545                 num_physpages++;
1546                 totalram_pages++;
1547         }
1548 }
1549 #endif
1550
1551 #define _PAGE_CACHE_4U  (_PAGE_CP_4U | _PAGE_CV_4U)
1552 #define _PAGE_CACHE_4V  (_PAGE_CP_4V | _PAGE_CV_4V)
1553 #define __DIRTY_BITS_4U  (_PAGE_MODIFIED_4U | _PAGE_WRITE_4U | _PAGE_W_4U)
1554 #define __DIRTY_BITS_4V  (_PAGE_MODIFIED_4V | _PAGE_WRITE_4V | _PAGE_W_4V)
1555 #define __ACCESS_BITS_4U (_PAGE_ACCESSED_4U | _PAGE_READ_4U | _PAGE_R)
1556 #define __ACCESS_BITS_4V (_PAGE_ACCESSED_4V | _PAGE_READ_4V | _PAGE_R)
1557
1558 pgprot_t PAGE_KERNEL __read_mostly;
1559 EXPORT_SYMBOL(PAGE_KERNEL);
1560
1561 pgprot_t PAGE_KERNEL_LOCKED __read_mostly;
1562 pgprot_t PAGE_COPY __read_mostly;
1563
1564 pgprot_t PAGE_SHARED __read_mostly;
1565 EXPORT_SYMBOL(PAGE_SHARED);
1566
1567 pgprot_t PAGE_EXEC __read_mostly;
1568 unsigned long pg_iobits __read_mostly;
1569
1570 unsigned long _PAGE_IE __read_mostly;
1571 EXPORT_SYMBOL(_PAGE_IE);
1572
1573 unsigned long _PAGE_E __read_mostly;
1574 EXPORT_SYMBOL(_PAGE_E);
1575
1576 unsigned long _PAGE_CACHE __read_mostly;
1577 EXPORT_SYMBOL(_PAGE_CACHE);
1578
1579 static void prot_init_common(unsigned long page_none,
1580                              unsigned long page_shared,
1581                              unsigned long page_copy,
1582                              unsigned long page_readonly,
1583                              unsigned long page_exec_bit)
1584 {
1585         PAGE_COPY = __pgprot(page_copy);
1586         PAGE_SHARED = __pgprot(page_shared);
1587
1588         protection_map[0x0] = __pgprot(page_none);
1589         protection_map[0x1] = __pgprot(page_readonly & ~page_exec_bit);
1590         protection_map[0x2] = __pgprot(page_copy & ~page_exec_bit);
1591         protection_map[0x3] = __pgprot(page_copy & ~page_exec_bit);
1592         protection_map[0x4] = __pgprot(page_readonly);
1593         protection_map[0x5] = __pgprot(page_readonly);
1594         protection_map[0x6] = __pgprot(page_copy);
1595         protection_map[0x7] = __pgprot(page_copy);
1596         protection_map[0x8] = __pgprot(page_none);
1597         protection_map[0x9] = __pgprot(page_readonly & ~page_exec_bit);
1598         protection_map[0xa] = __pgprot(page_shared & ~page_exec_bit);
1599         protection_map[0xb] = __pgprot(page_shared & ~page_exec_bit);
1600         protection_map[0xc] = __pgprot(page_readonly);
1601         protection_map[0xd] = __pgprot(page_readonly);
1602         protection_map[0xe] = __pgprot(page_shared);
1603         protection_map[0xf] = __pgprot(page_shared);
1604 }
1605
1606 static void __init sun4u_pgprot_init(void)
1607 {
1608         unsigned long page_none, page_shared, page_copy, page_readonly;
1609         unsigned long page_exec_bit;
1610
1611         PAGE_KERNEL = __pgprot (_PAGE_PRESENT_4U | _PAGE_VALID |
1612                                 _PAGE_CACHE_4U | _PAGE_P_4U |
1613                                 __ACCESS_BITS_4U | __DIRTY_BITS_4U |
1614                                 _PAGE_EXEC_4U);
1615         PAGE_KERNEL_LOCKED = __pgprot (_PAGE_PRESENT_4U | _PAGE_VALID |
1616                                        _PAGE_CACHE_4U | _PAGE_P_4U |
1617                                        __ACCESS_BITS_4U | __DIRTY_BITS_4U |
1618                                        _PAGE_EXEC_4U | _PAGE_L_4U);
1619         PAGE_EXEC = __pgprot(_PAGE_EXEC_4U);
1620
1621         _PAGE_IE = _PAGE_IE_4U;
1622         _PAGE_E = _PAGE_E_4U;
1623         _PAGE_CACHE = _PAGE_CACHE_4U;
1624
1625         pg_iobits = (_PAGE_VALID | _PAGE_PRESENT_4U | __DIRTY_BITS_4U |
1626                      __ACCESS_BITS_4U | _PAGE_E_4U);
1627
1628         kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZ4MB_4U) ^
1629                 0xfffff80000000000;
1630         kern_linear_pte_xor[0] |= (_PAGE_CP_4U | _PAGE_CV_4U |
1631                                    _PAGE_P_4U | _PAGE_W_4U);
1632
1633         /* XXX Should use 256MB on Panther. XXX */
1634         kern_linear_pte_xor[1] = kern_linear_pte_xor[0];
1635
1636         _PAGE_SZBITS = _PAGE_SZBITS_4U;
1637         _PAGE_ALL_SZ_BITS =  (_PAGE_SZ4MB_4U | _PAGE_SZ512K_4U |
1638                               _PAGE_SZ64K_4U | _PAGE_SZ8K_4U |
1639                               _PAGE_SZ32MB_4U | _PAGE_SZ256MB_4U);
1640
1641
1642         page_none = _PAGE_PRESENT_4U | _PAGE_ACCESSED_4U | _PAGE_CACHE_4U;
1643         page_shared = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U |
1644                        __ACCESS_BITS_4U | _PAGE_WRITE_4U | _PAGE_EXEC_4U);
1645         page_copy   = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U |
1646                        __ACCESS_BITS_4U | _PAGE_EXEC_4U);
1647         page_readonly   = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U |
1648                            __ACCESS_BITS_4U | _PAGE_EXEC_4U);
1649
1650         page_exec_bit = _PAGE_EXEC_4U;
1651
1652         prot_init_common(page_none, page_shared, page_copy, page_readonly,
1653                          page_exec_bit);
1654 }
1655
1656 static void __init sun4v_pgprot_init(void)
1657 {
1658         unsigned long page_none, page_shared, page_copy, page_readonly;
1659         unsigned long page_exec_bit;
1660
1661         PAGE_KERNEL = __pgprot (_PAGE_PRESENT_4V | _PAGE_VALID |
1662                                 _PAGE_CACHE_4V | _PAGE_P_4V |
1663                                 __ACCESS_BITS_4V | __DIRTY_BITS_4V |
1664                                 _PAGE_EXEC_4V);
1665         PAGE_KERNEL_LOCKED = PAGE_KERNEL;
1666         PAGE_EXEC = __pgprot(_PAGE_EXEC_4V);
1667
1668         _PAGE_IE = _PAGE_IE_4V;
1669         _PAGE_E = _PAGE_E_4V;
1670         _PAGE_CACHE = _PAGE_CACHE_4V;
1671
1672         kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZ4MB_4V) ^
1673                 0xfffff80000000000;
1674         kern_linear_pte_xor[0] |= (_PAGE_CP_4V | _PAGE_CV_4V |
1675                                    _PAGE_P_4V | _PAGE_W_4V);
1676
1677         kern_linear_pte_xor[1] = (_PAGE_VALID | _PAGE_SZ256MB_4V) ^
1678                 0xfffff80000000000;
1679         kern_linear_pte_xor[1] |= (_PAGE_CP_4V | _PAGE_CV_4V |
1680                                    _PAGE_P_4V | _PAGE_W_4V);
1681
1682         pg_iobits = (_PAGE_VALID | _PAGE_PRESENT_4V | __DIRTY_BITS_4V |
1683                      __ACCESS_BITS_4V | _PAGE_E_4V);
1684
1685         _PAGE_SZBITS = _PAGE_SZBITS_4V;
1686         _PAGE_ALL_SZ_BITS = (_PAGE_SZ16GB_4V | _PAGE_SZ2GB_4V |
1687                              _PAGE_SZ256MB_4V | _PAGE_SZ32MB_4V |
1688                              _PAGE_SZ4MB_4V | _PAGE_SZ512K_4V |
1689                              _PAGE_SZ64K_4V | _PAGE_SZ8K_4V);
1690
1691         page_none = _PAGE_PRESENT_4V | _PAGE_ACCESSED_4V | _PAGE_CACHE_4V;
1692         page_shared = (_PAGE_VALID | _PAGE_PRESENT_4V | _PAGE_CACHE_4V |
1693                        __ACCESS_BITS_4V | _PAGE_WRITE_4V | _PAGE_EXEC_4V);
1694         page_copy   = (_PAGE_VALID | _PAGE_PRESENT_4V | _PAGE_CACHE_4V |
1695                        __ACCESS_BITS_4V | _PAGE_EXEC_4V);
1696         page_readonly = (_PAGE_VALID | _PAGE_PRESENT_4V | _PAGE_CACHE_4V |
1697                          __ACCESS_BITS_4V | _PAGE_EXEC_4V);
1698
1699         page_exec_bit = _PAGE_EXEC_4V;
1700
1701         prot_init_common(page_none, page_shared, page_copy, page_readonly,
1702                          page_exec_bit);
1703 }
1704
1705 unsigned long pte_sz_bits(unsigned long sz)
1706 {
1707         if (tlb_type == hypervisor) {
1708                 switch (sz) {
1709                 case 8 * 1024:
1710                 default:
1711                         return _PAGE_SZ8K_4V;
1712                 case 64 * 1024:
1713                         return _PAGE_SZ64K_4V;
1714                 case 512 * 1024:
1715                         return _PAGE_SZ512K_4V;
1716                 case 4 * 1024 * 1024:
1717                         return _PAGE_SZ4MB_4V;
1718                 };
1719         } else {
1720                 switch (sz) {
1721                 case 8 * 1024:
1722                 default:
1723                         return _PAGE_SZ8K_4U;
1724                 case 64 * 1024:
1725                         return _PAGE_SZ64K_4U;
1726                 case 512 * 1024:
1727                         return _PAGE_SZ512K_4U;
1728                 case 4 * 1024 * 1024:
1729                         return _PAGE_SZ4MB_4U;
1730                 };
1731         }
1732 }
1733
1734 pte_t mk_pte_io(unsigned long page, pgprot_t prot, int space, unsigned long page_size)
1735 {
1736         pte_t pte;
1737
1738         pte_val(pte)  = page | pgprot_val(pgprot_noncached(prot));
1739         pte_val(pte) |= (((unsigned long)space) << 32);
1740         pte_val(pte) |= pte_sz_bits(page_size);
1741
1742         return pte;
1743 }
1744
1745 static unsigned long kern_large_tte(unsigned long paddr)
1746 {
1747         unsigned long val;
1748
1749         val = (_PAGE_VALID | _PAGE_SZ4MB_4U |
1750                _PAGE_CP_4U | _PAGE_CV_4U | _PAGE_P_4U |
1751                _PAGE_EXEC_4U | _PAGE_L_4U | _PAGE_W_4U);
1752         if (tlb_type == hypervisor)
1753                 val = (_PAGE_VALID | _PAGE_SZ4MB_4V |
1754                        _PAGE_CP_4V | _PAGE_CV_4V | _PAGE_P_4V |
1755                        _PAGE_EXEC_4V | _PAGE_W_4V);
1756
1757         return val | paddr;
1758 }
1759
1760 /*
1761  * Translate PROM's mapping we capture at boot time into physical address.
1762  * The second parameter is only set from prom_callback() invocations.
1763  */
1764 unsigned long prom_virt_to_phys(unsigned long promva, int *error)
1765 {
1766         unsigned long mask;
1767         int i;
1768
1769         mask = _PAGE_PADDR_4U;
1770         if (tlb_type == hypervisor)
1771                 mask = _PAGE_PADDR_4V;
1772
1773         for (i = 0; i < prom_trans_ents; i++) {
1774                 struct linux_prom_translation *p = &prom_trans[i];
1775
1776                 if (promva >= p->virt &&
1777                     promva < (p->virt + p->size)) {
1778                         unsigned long base = p->data & mask;
1779
1780                         if (error)
1781                                 *error = 0;
1782                         return base + (promva & (8192 - 1));
1783                 }
1784         }
1785         if (error)
1786                 *error = 1;
1787         return 0UL;
1788 }
1789
1790 /* XXX We should kill off this ugly thing at so me point. XXX */
1791 unsigned long sun4u_get_pte(unsigned long addr)
1792 {
1793         pgd_t *pgdp;
1794         pud_t *pudp;
1795         pmd_t *pmdp;
1796         pte_t *ptep;
1797         unsigned long mask = _PAGE_PADDR_4U;
1798
1799         if (tlb_type == hypervisor)
1800                 mask = _PAGE_PADDR_4V;
1801
1802         if (addr >= PAGE_OFFSET)
1803                 return addr & mask;
1804
1805         if ((addr >= LOW_OBP_ADDRESS) && (addr < HI_OBP_ADDRESS))
1806                 return prom_virt_to_phys(addr, NULL);
1807
1808         pgdp = pgd_offset_k(addr);
1809         pudp = pud_offset(pgdp, addr);
1810         pmdp = pmd_offset(pudp, addr);
1811         ptep = pte_offset_kernel(pmdp, addr);
1812
1813         return pte_val(*ptep) & mask;
1814 }
1815
1816 /* If not locked, zap it. */
1817 void __flush_tlb_all(void)
1818 {
1819         unsigned long pstate;
1820         int i;
1821
1822         __asm__ __volatile__("flushw\n\t"
1823                              "rdpr      %%pstate, %0\n\t"
1824                              "wrpr      %0, %1, %%pstate"
1825                              : "=r" (pstate)
1826                              : "i" (PSTATE_IE));
1827         if (tlb_type == spitfire) {
1828                 for (i = 0; i < 64; i++) {
1829                         /* Spitfire Errata #32 workaround */
1830                         /* NOTE: Always runs on spitfire, so no
1831                          *       cheetah+ page size encodings.
1832                          */
1833                         __asm__ __volatile__("stxa      %0, [%1] %2\n\t"
1834                                              "flush     %%g6"
1835                                              : /* No outputs */
1836                                              : "r" (0),
1837                                              "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
1838
1839                         if (!(spitfire_get_dtlb_data(i) & _PAGE_L_4U)) {
1840                                 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
1841                                                      "membar #Sync"
1842                                                      : /* no outputs */
1843                                                      : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU));
1844                                 spitfire_put_dtlb_data(i, 0x0UL);
1845                         }
1846
1847                         /* Spitfire Errata #32 workaround */
1848                         /* NOTE: Always runs on spitfire, so no
1849                          *       cheetah+ page size encodings.
1850                          */
1851                         __asm__ __volatile__("stxa      %0, [%1] %2\n\t"
1852                                              "flush     %%g6"
1853                                              : /* No outputs */
1854                                              : "r" (0),
1855                                              "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
1856
1857                         if (!(spitfire_get_itlb_data(i) & _PAGE_L_4U)) {
1858                                 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
1859                                                      "membar #Sync"
1860                                                      : /* no outputs */
1861                                                      : "r" (TLB_TAG_ACCESS), "i" (ASI_IMMU));
1862                                 spitfire_put_itlb_data(i, 0x0UL);
1863                         }
1864                 }
1865         } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
1866                 cheetah_flush_dtlb_all();
1867                 cheetah_flush_itlb_all();
1868         }
1869         __asm__ __volatile__("wrpr      %0, 0, %%pstate"
1870                              : : "r" (pstate));
1871 }
1872
1873 #ifdef CONFIG_MEMORY_HOTPLUG
1874
1875 void online_page(struct page *page)
1876 {
1877         ClearPageReserved(page);
1878         init_page_count(page);
1879         __free_page(page);
1880         totalram_pages++;
1881         num_physpages++;
1882 }
1883
1884 int remove_memory(u64 start, u64 size)
1885 {
1886         return -EINVAL;
1887 }
1888
1889 #endif /* CONFIG_MEMORY_HOTPLUG */