arch/powerpc/mm/hash_utils_64.c

   1 /*
   2  * PowerPC64 port by Mike Corrigan and Dave Engebretsen
   3  *   {mikejc|engebret}@us.ibm.com
   4  *
   5  *    Copyright (c) 2000 Mike Corrigan <mikejc@us.ibm.com>
   6  *
   7  * SMP scalability work:
   8  *    Copyright (C) 2001 Anton Blanchard <anton@au.ibm.com>, IBM
   9  *
  10  *    Module name: htab.c
  11  *
  12  *    Description:
  13  *      PowerPC Hashed Page Table functions
  14  *
  15  * This program is free software; you can redistribute it and/or
  16  * modify it under the terms of the GNU General Public License
  17  * as published by the Free Software Foundation; either version
  18  * 2 of the License, or (at your option) any later version.
  19  */
  20
  21 #undef DEBUG
  22 #undef DEBUG_LOW
  23
  24 #include <linux/config.h>
  25 #include <linux/spinlock.h>
  26 #include <linux/errno.h>
  27 #include <linux/sched.h>
  28 #include <linux/proc_fs.h>
  29 #include <linux/stat.h>
  30 #include <linux/sysctl.h>
  31 #include <linux/ctype.h>
  32 #include <linux/cache.h>
  33 #include <linux/init.h>
  34 #include <linux/signal.h>
  35
  36 #include <asm/processor.h>
  37 #include <asm/pgtable.h>
  38 #include <asm/mmu.h>
  39 #include <asm/mmu_context.h>
  40 #include <asm/page.h>
  41 #include <asm/types.h>
  42 #include <asm/system.h>
  43 #include <asm/uaccess.h>
  44 #include <asm/machdep.h>
  45 #include <asm/lmb.h>
  46 #include <asm/abs_addr.h>
  47 #include <asm/tlbflush.h>
  48 #include <asm/io.h>
  49 #include <asm/eeh.h>
  50 #include <asm/tlb.h>
  51 #include <asm/cacheflush.h>
  52 #include <asm/cputable.h>
  53 #include <asm/abs_addr.h>
  54 #include <asm/sections.h>
  55
  56 #ifdef DEBUG
  57 #define DBG(fmt...) udbg_printf(fmt)
  58 #else
  59 #define DBG(fmt...)
  60 #endif
  61
  62 #ifdef DEBUG_LOW
  63 #define DBG_LOW(fmt...) udbg_printf(fmt)
  64 #else
  65 #define DBG_LOW(fmt...)
  66 #endif
  67
  68 #define KB (1024)
  69 #define MB (1024*KB)
  70
  71 /*
  72  * Note:  pte   --> Linux PTE
  73  *        HPTE  --> PowerPC Hashed Page Table Entry
  74  *
  75  * Execution context:
  76  *   htab_initialize is called with the MMU off (of course), but
  77  *   the kernel has been copied down to zero so it can directly
  78  *   reference global data.  At this point it is very difficult
  79  *   to print debug info.
  80  *
  81  */
  82
  83 #ifdef CONFIG_U3_DART
  84 extern unsigned long dart_tablebase;
  85 #endif /* CONFIG_U3_DART */
  86
  87 static unsigned long _SDR1;
  88 struct mmu_psize_def mmu_psize_defs[MMU_PAGE_COUNT];
  89
  90 hpte_t *htab_address;
  91 unsigned long htab_size_bytes;
  92 unsigned long htab_hash_mask;
  93 int mmu_linear_psize = MMU_PAGE_4K;
  94 int mmu_virtual_psize = MMU_PAGE_4K;
  95 int mmu_vmalloc_psize = MMU_PAGE_4K;
  96 int mmu_io_psize = MMU_PAGE_4K;
  97 #ifdef CONFIG_HUGETLB_PAGE
  98 int mmu_huge_psize = MMU_PAGE_16M;
  99 unsigned int HPAGE_SHIFT;
 100 #endif
 101 #ifdef CONFIG_PPC_64K_PAGES
 102 int mmu_ci_restrictions;
 103 #endif
 104
 105 /* There are definitions of page sizes arrays to be used when none
 106  * is provided by the firmware.
 107  */
 108
 109 /* Pre-POWER4 CPUs (4k pages only)
 110  */
 111 struct mmu_psize_def mmu_psize_defaults_old[] = {
 112         [MMU_PAGE_4K] = {
 113                 .shift  = 12,
 114                 .sllp   = 0,
 115                 .penc   = 0,
 116                 .avpnm  = 0,
 117                 .tlbiel = 0,
 118         },
 119 };
 120
 121 /* POWER4, GPUL, POWER5
 122  *
 123  * Support for 16Mb large pages
 124  */
 125 struct mmu_psize_def mmu_psize_defaults_gp[] = {
 126         [MMU_PAGE_4K] = {
 127                 .shift  = 12,
 128                 .sllp   = 0,
 129                 .penc   = 0,
 130                 .avpnm  = 0,
 131                 .tlbiel = 1,
 132         },
 133         [MMU_PAGE_16M] = {
 134                 .shift  = 24,
 135                 .sllp   = SLB_VSID_L,
 136                 .penc   = 0,
 137                 .avpnm  = 0x1UL,
 138                 .tlbiel = 0,
 139         },
 140 };
 141
 142
 143 int htab_bolt_mapping(unsigned long vstart, unsigned long vend,
 144                       unsigned long pstart, unsigned long mode, int psize)
 145 {
 146         unsigned long vaddr, paddr;
 147         unsigned int step, shift;
 148         unsigned long tmp_mode;
 149         int ret = 0;
 150
 151         shift = mmu_psize_defs[psize].shift;
 152         step = 1 << shift;
 153
 154         for (vaddr = vstart, paddr = pstart; vaddr < vend;
 155              vaddr += step, paddr += step) {
 156                 unsigned long vpn, hash, hpteg;
 157                 unsigned long vsid = get_kernel_vsid(vaddr);
 158                 unsigned long va = (vsid << 28) | (vaddr & 0x0fffffff);
 159
 160                 vpn = va >> shift;
 161                 tmp_mode = mode;
 162
 163                 /* Make non-kernel text non-executable */
 164                 if (!in_kernel_text(vaddr))
 165                         tmp_mode = mode | HPTE_R_N;
 166
 167                 hash = hpt_hash(va, shift);
 168                 hpteg = ((hash & htab_hash_mask) * HPTES_PER_GROUP);
 169
 170                 /* The crap below can be cleaned once ppd_md.probe() can
 171                  * set up the hash callbacks, thus we can just used the
 172                  * normal insert callback here.
 173                  */
 174 #ifdef CONFIG_PPC_ISERIES
 175                 if (machine_is(iseries))
 176                         ret = iSeries_hpte_insert(hpteg, va,
 177                                                   paddr,
 178                                                   tmp_mode,
 179                                                   HPTE_V_BOLTED,
 180                                                   psize);
 181                 else
 182 #endif
 183 #ifdef CONFIG_PPC_PSERIES
 184                 if (machine_is(pseries) && firmware_has_feature(FW_FEATURE_LPAR))
 185                         ret = pSeries_lpar_hpte_insert(hpteg, va,
 186                                                        paddr,
 187                                                        tmp_mode,
 188                                                        HPTE_V_BOLTED,
 189                                                        psize);
 190                 else
 191 #endif
 192 #ifdef CONFIG_PPC_MULTIPLATFORM
 193                         ret = native_hpte_insert(hpteg, va,
 194                                                  paddr,
 195                                                  tmp_mode, HPTE_V_BOLTED,
 196                                                  psize);
 197 #endif
 198                 if (ret < 0)
 199                         break;
 200         }
 201         return ret < 0 ? ret : 0;
 202 }
 203
 204 static int __init htab_dt_scan_page_sizes(unsigned long node,
 205                                           const char *uname, int depth,
 206                                           void *data)
 207 {
 208         char *type = of_get_flat_dt_prop(node, "device_type", NULL);
 209         u32 *prop;
 210         unsigned long size = 0;
 211
 212         /* We are scanning "cpu" nodes only */
 213         if (type == NULL || strcmp(type, "cpu") != 0)
 214                 return 0;
 215
 216         prop = (u32 *)of_get_flat_dt_prop(node,
 217                                           "ibm,segment-page-sizes", &size);
 218         if (prop != NULL) {
 219                 DBG("Page sizes from device-tree:\n");
 220                 size /= 4;
 221                 cur_cpu_spec->cpu_features &= ~(CPU_FTR_16M_PAGE);
 222                 while(size > 0) {
 223                         unsigned int shift = prop[0];
 224                         unsigned int slbenc = prop[1];
 225                         unsigned int lpnum = prop[2];
 226                         unsigned int lpenc = 0;
 227                         struct mmu_psize_def *def;
 228                         int idx = -1;
 229
 230                         size -= 3; prop += 3;
 231                         while(size > 0 && lpnum) {
 232                                 if (prop[0] == shift)
 233                                         lpenc = prop[1];
 234                                 prop += 2; size -= 2;
 235                                 lpnum--;
 236                         }
 237                         switch(shift) {
 238                         case 0xc:
 239                                 idx = MMU_PAGE_4K;
 240                                 break;
 241                         case 0x10:
 242                                 idx = MMU_PAGE_64K;
 243                                 break;
 244                         case 0x14:
 245                                 idx = MMU_PAGE_1M;
 246                                 break;
 247                         case 0x18:
 248                                 idx = MMU_PAGE_16M;
 249                                 cur_cpu_spec->cpu_features |= CPU_FTR_16M_PAGE;
 250                                 break;
 251                         case 0x22:
 252                                 idx = MMU_PAGE_16G;
 253                                 break;
 254                         }
 255                         if (idx < 0)
 256                                 continue;
 257                         def = &mmu_psize_defs[idx];
 258                         def->shift = shift;
 259                         if (shift <= 23)
 260                                 def->avpnm = 0;
 261                         else
 262                                 def->avpnm = (1 << (shift - 23)) - 1;
 263                         def->sllp = slbenc;
 264                         def->penc = lpenc;
 265                         /* We don't know for sure what's up with tlbiel, so
 266                          * for now we only set it for 4K and 64K pages
 267                          */
 268                         if (idx == MMU_PAGE_4K || idx == MMU_PAGE_64K)
 269                                 def->tlbiel = 1;
 270                         else
 271                                 def->tlbiel = 0;
 272
 273                         DBG(" %d: shift=%02x, sllp=%04x, avpnm=%08x, "
 274                             "tlbiel=%d, penc=%d\n",
 275                             idx, shift, def->sllp, def->avpnm, def->tlbiel,
 276                             def->penc);
 277                 }
 278                 return 1;
 279         }
 280         return 0;
 281 }
 282
 283
 284 static void __init htab_init_page_sizes(void)
 285 {
 286         int rc;
 287
 288         /* Default to 4K pages only */
 289         memcpy(mmu_psize_defs, mmu_psize_defaults_old,
 290                sizeof(mmu_psize_defaults_old));
 291
 292         /*
 293          * Try to find the available page sizes in the device-tree
 294          */
 295         rc = of_scan_flat_dt(htab_dt_scan_page_sizes, NULL);
 296         if (rc != 0)  /* Found */
 297                 goto found;
 298
 299         /*
 300          * Not in the device-tree, let's fallback on known size
 301          * list for 16M capable GP & GR
 302          */
 303         if (cpu_has_feature(CPU_FTR_16M_PAGE) && !machine_is(iseries))
 304                 memcpy(mmu_psize_defs, mmu_psize_defaults_gp,
 305                        sizeof(mmu_psize_defaults_gp));
 306  found:
 307         /*
 308          * Pick a size for the linear mapping. Currently, we only support
 309          * 16M, 1M and 4K which is the default
 310          */
 311         if (mmu_psize_defs[MMU_PAGE_16M].shift)
 312                 mmu_linear_psize = MMU_PAGE_16M;
 313         else if (mmu_psize_defs[MMU_PAGE_1M].shift)
 314                 mmu_linear_psize = MMU_PAGE_1M;
 315
 316 #ifdef CONFIG_PPC_64K_PAGES
 317         /*
 318          * Pick a size for the ordinary pages. Default is 4K, we support
 319          * 64K for user mappings and vmalloc if supported by the processor.
 320          * We only use 64k for ioremap if the processor
 321          * (and firmware) support cache-inhibited large pages.
 322          * If not, we use 4k and set mmu_ci_restrictions so that
 323          * hash_page knows to switch processes that use cache-inhibited
 324          * mappings to 4k pages.
 325          */
 326         if (mmu_psize_defs[MMU_PAGE_64K].shift) {
 327                 mmu_virtual_psize = MMU_PAGE_64K;
 328                 mmu_vmalloc_psize = MMU_PAGE_64K;
 329                 if (cpu_has_feature(CPU_FTR_CI_LARGE_PAGE))
 330                         mmu_io_psize = MMU_PAGE_64K;
 331                 else
 332                         mmu_ci_restrictions = 1;
 333         }
 334 #endif
 335
 336         printk(KERN_DEBUG "Page orders: linear mapping = %d, "
 337                "virtual = %d, io = %d\n",
 338                mmu_psize_defs[mmu_linear_psize].shift,
 339                mmu_psize_defs[mmu_virtual_psize].shift,
 340                mmu_psize_defs[mmu_io_psize].shift);
 341
 342 #ifdef CONFIG_HUGETLB_PAGE
 343         /* Init large page size. Currently, we pick 16M or 1M depending
 344          * on what is available
 345          */
 346         if (mmu_psize_defs[MMU_PAGE_16M].shift)
 347                 mmu_huge_psize = MMU_PAGE_16M;
 348         /* With 4k/4level pagetables, we can't (for now) cope with a
 349          * huge page size < PMD_SIZE */
 350         else if (mmu_psize_defs[MMU_PAGE_1M].shift)
 351                 mmu_huge_psize = MMU_PAGE_1M;
 352
 353         /* Calculate HPAGE_SHIFT and sanity check it */
 354         if (mmu_psize_defs[mmu_huge_psize].shift > MIN_HUGEPTE_SHIFT &&
 355             mmu_psize_defs[mmu_huge_psize].shift < SID_SHIFT)
 356                 HPAGE_SHIFT = mmu_psize_defs[mmu_huge_psize].shift;
 357         else
 358                 HPAGE_SHIFT = 0; /* No huge pages dude ! */
 359 #endif /* CONFIG_HUGETLB_PAGE */
 360 }
 361
 362 static int __init htab_dt_scan_pftsize(unsigned long node,
 363                                        const char *uname, int depth,
 364                                        void *data)
 365 {
 366         char *type = of_get_flat_dt_prop(node, "device_type", NULL);
 367         u32 *prop;
 368
 369         /* We are scanning "cpu" nodes only */
 370         if (type == NULL || strcmp(type, "cpu") != 0)
 371                 return 0;
 372
 373         prop = (u32 *)of_get_flat_dt_prop(node, "ibm,pft-size", NULL);
 374         if (prop != NULL) {
 375                 /* pft_size[0] is the NUMA CEC cookie */
 376                 ppc64_pft_size = prop[1];
 377                 return 1;
 378         }
 379         return 0;
 380 }
 381
 382 static unsigned long __init htab_get_table_size(void)
 383 {
 384         unsigned long mem_size, rnd_mem_size, pteg_count;
 385
 386         /* If hash size isn't already provided by the platform, we try to
 387          * retrieve it from the device-tree. If it's not there neither, we
 388          * calculate it now based on the total RAM size
 389          */
 390         if (ppc64_pft_size == 0)
 391                 of_scan_flat_dt(htab_dt_scan_pftsize, NULL);
 392         if (ppc64_pft_size)
 393                 return 1UL << ppc64_pft_size;
 394
 395         /* round mem_size up to next power of 2 */
 396         mem_size = lmb_phys_mem_size();
 397         rnd_mem_size = 1UL << __ilog2(mem_size);
 398         if (rnd_mem_size < mem_size)
 399                 rnd_mem_size <<= 1;
 400
 401         /* # pages / 2 */
 402         pteg_count = max(rnd_mem_size >> (12 + 1), 1UL << 11);
 403
 404         return pteg_count << 7;
 405 }
 406
 407 #ifdef CONFIG_MEMORY_HOTPLUG
 408 void create_section_mapping(unsigned long start, unsigned long end)
 409 {
 410                 BUG_ON(htab_bolt_mapping(start, end, __pa(start),
 411                         _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_COHERENT | PP_RWXX,
 412                         mmu_linear_psize));
 413 }
 414 #endif /* CONFIG_MEMORY_HOTPLUG */
 415
 416 static inline void make_bl(unsigned int *insn_addr, void *func)
 417 {
 418         unsigned long funcp = *((unsigned long *)func);
 419         int offset = funcp - (unsigned long)insn_addr;
 420
 421         *insn_addr = (unsigned int)(0x48000001 | (offset & 0x03fffffc));
 422         flush_icache_range((unsigned long)insn_addr, 4+
 423                            (unsigned long)insn_addr);
 424 }
 425
 426 static void __init htab_finish_init(void)
 427 {
 428         extern unsigned int *htab_call_hpte_insert1;
 429         extern unsigned int *htab_call_hpte_insert2;
 430         extern unsigned int *htab_call_hpte_remove;
 431         extern unsigned int *htab_call_hpte_updatepp;
 432
 433 #ifdef CONFIG_PPC_64K_PAGES
 434         extern unsigned int *ht64_call_hpte_insert1;
 435         extern unsigned int *ht64_call_hpte_insert2;
 436         extern unsigned int *ht64_call_hpte_remove;
 437         extern unsigned int *ht64_call_hpte_updatepp;
 438
 439         make_bl(ht64_call_hpte_insert1, ppc_md.hpte_insert);
 440         make_bl(ht64_call_hpte_insert2, ppc_md.hpte_insert);
 441         make_bl(ht64_call_hpte_remove, ppc_md.hpte_remove);
 442         make_bl(ht64_call_hpte_updatepp, ppc_md.hpte_updatepp);
 443 #endif /* CONFIG_PPC_64K_PAGES */
 444
 445         make_bl(htab_call_hpte_insert1, ppc_md.hpte_insert);
 446         make_bl(htab_call_hpte_insert2, ppc_md.hpte_insert);
 447         make_bl(htab_call_hpte_remove, ppc_md.hpte_remove);
 448         make_bl(htab_call_hpte_updatepp, ppc_md.hpte_updatepp);
 449 }
 450
 451 void __init htab_initialize(void)
 452 {
 453         unsigned long table;
 454         unsigned long pteg_count;
 455         unsigned long mode_rw;
 456         unsigned long base = 0, size = 0;
 457         int i;
 458
 459         extern unsigned long tce_alloc_start, tce_alloc_end;
 460
 461         DBG(" -> htab_initialize()\n");
 462
 463         /* Initialize page sizes */
 464         htab_init_page_sizes();
 465
 466         /*
 467          * Calculate the required size of the htab.  We want the number of
 468          * PTEGs to equal one half the number of real pages.
 469          */
 470         htab_size_bytes = htab_get_table_size();
 471         pteg_count = htab_size_bytes >> 7;
 472
 473         htab_hash_mask = pteg_count - 1;
 474
 475         if (firmware_has_feature(FW_FEATURE_LPAR)) {
 476                 /* Using a hypervisor which owns the htab */
 477                 htab_address = NULL;
 478                 _SDR1 = 0;
 479         } else {
 480                 /* Find storage for the HPT.  Must be contiguous in
 481                  * the absolute address space.
 482                  */
 483                 table = lmb_alloc(htab_size_bytes, htab_size_bytes);
 484
 485                 DBG("Hash table allocated at %lx, size: %lx\n", table,
 486                     htab_size_bytes);
 487
 488                 htab_address = abs_to_virt(table);
 489
 490                 /* htab absolute addr + encoded htabsize */
 491                 _SDR1 = table + __ilog2(pteg_count) - 11;
 492
 493                 /* Initialize the HPT with no entries */
 494                 memset((void *)table, 0, htab_size_bytes);
 495
 496                 /* Set SDR1 */
 497                 mtspr(SPRN_SDR1, _SDR1);
 498         }
 499
 500         mode_rw = _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_COHERENT | PP_RWXX;
 501
 502         /* On U3 based machines, we need to reserve the DART area and
 503          * _NOT_ map it to avoid cache paradoxes as it's remapped non
 504          * cacheable later on
 505          */
 506
 507         /* create bolted the linear mapping in the hash table */
 508         for (i=0; i < lmb.memory.cnt; i++) {
 509                 base = (unsigned long)__va(lmb.memory.region[i].base);
 510                 size = lmb.memory.region[i].size;
 511
 512                 DBG("creating mapping for region: %lx : %lx\n", base, size);
 513
 514 #ifdef CONFIG_U3_DART
 515                 /* Do not map the DART space. Fortunately, it will be aligned
 516                  * in such a way that it will not cross two lmb regions and
 517                  * will fit within a single 16Mb page.
 518                  * The DART space is assumed to be a full 16Mb region even if
 519                  * we only use 2Mb of that space. We will use more of it later
 520                  * for AGP GART. We have to use a full 16Mb large page.
 521                  */
 522                 DBG("DART base: %lx\n", dart_tablebase);
 523
 524                 if (dart_tablebase != 0 && dart_tablebase >= base
 525                     && dart_tablebase < (base + size)) {
 526                         unsigned long dart_table_end = dart_tablebase + 16 * MB;
 527                         if (base != dart_tablebase)
 528                                 BUG_ON(htab_bolt_mapping(base, dart_tablebase,
 529                                                         __pa(base), mode_rw,
 530                                                         mmu_linear_psize));
 531                         if ((base + size) > dart_table_end)
 532                                 BUG_ON(htab_bolt_mapping(dart_tablebase+16*MB,
 533                                                         base + size,
 534                                                         __pa(dart_table_end),
 535                                                          mode_rw,
 536                                                          mmu_linear_psize));
 537                         continue;
 538                 }
 539 #endif /* CONFIG_U3_DART */
 540                 BUG_ON(htab_bolt_mapping(base, base + size, __pa(base),
 541                                         mode_rw, mmu_linear_psize));
 542        }
 543
 544         /*
 545          * If we have a memory_limit and we've allocated TCEs then we need to
 546          * explicitly map the TCE area at the top of RAM. We also cope with the
 547          * case that the TCEs start below memory_limit.
 548          * tce_alloc_start/end are 16MB aligned so the mapping should work
 549          * for either 4K or 16MB pages.
 550          */
 551         if (tce_alloc_start) {
 552                 tce_alloc_start = (unsigned long)__va(tce_alloc_start);
 553                 tce_alloc_end = (unsigned long)__va(tce_alloc_end);
 554
 555                 if (base + size >= tce_alloc_start)
 556                         tce_alloc_start = base + size + 1;
 557
 558                 BUG_ON(htab_bolt_mapping(tce_alloc_start, tce_alloc_end,
 559                                          __pa(tce_alloc_start), mode_rw,
 560                                          mmu_linear_psize));
 561         }
 562
 563         htab_finish_init();
 564
 565         DBG(" <- htab_initialize()\n");
 566 }
 567 #undef KB
 568 #undef MB
 569
 570 void htab_initialize_secondary(void)
 571 {
 572         if (!firmware_has_feature(FW_FEATURE_LPAR))
 573                 mtspr(SPRN_SDR1, _SDR1);
 574 }
 575
 576 /*
 577  * Called by asm hashtable.S for doing lazy icache flush
 578  */
 579 unsigned int hash_page_do_lazy_icache(unsigned int pp, pte_t pte, int trap)
 580 {
 581         struct page *page;
 582
 583         if (!pfn_valid(pte_pfn(pte)))
 584                 return pp;
 585
 586         page = pte_page(pte);
 587
 588         /* page is dirty */
 589         if (!test_bit(PG_arch_1, &page->flags) && !PageReserved(page)) {
 590                 if (trap == 0x400) {
 591                         __flush_dcache_icache(page_address(page));
 592                         set_bit(PG_arch_1, &page->flags);
 593                 } else
 594                         pp |= HPTE_R_N;
 595         }
 596         return pp;
 597 }
 598
 599 /* Result code is:
 600  *  0 - handled
 601  *  1 - normal page fault
 602  * -1 - critical hash insertion error
 603  */
 604 int hash_page(unsigned long ea, unsigned long access, unsigned long trap)
 605 {
 606         void *pgdir;
 607         unsigned long vsid;
 608         struct mm_struct *mm;
 609         pte_t *ptep;
 610         cpumask_t tmp;
 611         int rc, user_region = 0, local = 0;
 612         int psize;
 613
 614         DBG_LOW("hash_page(ea=%016lx, access=%lx, trap=%lx\n",
 615                 ea, access, trap);
 616
 617         if ((ea & ~REGION_MASK) >= PGTABLE_RANGE) {
 618                 DBG_LOW(" out of pgtable range !\n");
 619                 return 1;
 620         }
 621
 622         /* Get region & vsid */
 623         switch (REGION_ID(ea)) {
 624         case USER_REGION_ID:
 625                 user_region = 1;
 626                 mm = current->mm;
 627                 if (! mm) {
 628                         DBG_LOW(" user region with no mm !\n");
 629                         return 1;
 630                 }
 631                 vsid = get_vsid(mm->context.id, ea);
 632                 psize = mm->context.user_psize;
 633                 break;
 634         case VMALLOC_REGION_ID:
 635                 mm = &init_mm;
 636                 vsid = get_kernel_vsid(ea);
 637                 if (ea < VMALLOC_END)
 638                         psize = mmu_vmalloc_psize;
 639                 else
 640                         psize = mmu_io_psize;
 641                 break;
 642         default:
 643                 /* Not a valid range
 644                  * Send the problem up to do_page_fault
 645                  */
 646                 return 1;
 647         }
 648         DBG_LOW(" mm=%p, mm->pgdir=%p, vsid=%016lx\n", mm, mm->pgd, vsid);
 649
 650         /* Get pgdir */
 651         pgdir = mm->pgd;
 652         if (pgdir == NULL)
 653                 return 1;
 654
 655         /* Check CPU locality */
 656         tmp = cpumask_of_cpu(smp_processor_id());
 657         if (user_region && cpus_equal(mm->cpu_vm_mask, tmp))
 658                 local = 1;
 659
 660         /* Handle hugepage regions */
 661         if (unlikely(in_hugepage_area(mm->context, ea))) {
 662                 DBG_LOW(" -> huge page !\n");
 663                 return hash_huge_page(mm, access, ea, vsid, local, trap);
 664         }
 665
 666         /* Get PTE and page size from page tables */
 667         ptep = find_linux_pte(pgdir, ea);
 668         if (ptep == NULL || !pte_present(*ptep)) {
 669                 DBG_LOW(" no PTE !\n");
 670                 return 1;
 671         }
 672
 673 #ifndef CONFIG_PPC_64K_PAGES
 674         DBG_LOW(" i-pte: %016lx\n", pte_val(*ptep));
 675 #else
 676         DBG_LOW(" i-pte: %016lx %016lx\n", pte_val(*ptep),
 677                 pte_val(*(ptep + PTRS_PER_PTE)));
 678 #endif
 679         /* Pre-check access permissions (will be re-checked atomically
 680          * in __hash_page_XX but this pre-check is a fast path
 681          */
 682         if (access & ~pte_val(*ptep)) {
 683                 DBG_LOW(" no access !\n");
 684                 return 1;
 685         }
 686
 687         /* Do actual hashing */
 688 #ifndef CONFIG_PPC_64K_PAGES
 689         rc = __hash_page_4K(ea, access, vsid, ptep, trap, local);
 690 #else
 691         if (mmu_ci_restrictions) {
 692                 /* If this PTE is non-cacheable, switch to 4k */
 693                 if (psize == MMU_PAGE_64K &&
 694                     (pte_val(*ptep) & _PAGE_NO_CACHE)) {
 695                         if (user_region) {
 696                                 psize = MMU_PAGE_4K;
 697                                 mm->context.user_psize = MMU_PAGE_4K;
 698                                 mm->context.sllp = SLB_VSID_USER |
 699                                         mmu_psize_defs[MMU_PAGE_4K].sllp;
 700                         } else if (ea < VMALLOC_END) {
 701                                 /*
 702                                  * some driver did a non-cacheable mapping
 703                                  * in vmalloc space, so switch vmalloc
 704                                  * to 4k pages
 705                                  */
 706                                 printk(KERN_ALERT "Reducing vmalloc segment "
 707                                        "to 4kB pages because of "
 708                                        "non-cacheable mapping\n");
 709                                 psize = mmu_vmalloc_psize = MMU_PAGE_4K;
 710                         }
 711                 }
 712                 if (user_region) {
 713                         if (psize != get_paca()->context.user_psize) {
 714                                 get_paca()->context = mm->context;
 715                                 slb_flush_and_rebolt();
 716                         }
 717                 } else if (get_paca()->vmalloc_sllp !=
 718                            mmu_psize_defs[mmu_vmalloc_psize].sllp) {
 719                         get_paca()->vmalloc_sllp =
 720                                 mmu_psize_defs[mmu_vmalloc_psize].sllp;
 721                         slb_flush_and_rebolt();
 722                 }
 723         }
 724         if (psize == MMU_PAGE_64K)
 725                 rc = __hash_page_64K(ea, access, vsid, ptep, trap, local);
 726         else
 727                 rc = __hash_page_4K(ea, access, vsid, ptep, trap, local);
 728 #endif /* CONFIG_PPC_64K_PAGES */
 729
 730 #ifndef CONFIG_PPC_64K_PAGES
 731         DBG_LOW(" o-pte: %016lx\n", pte_val(*ptep));
 732 #else
 733         DBG_LOW(" o-pte: %016lx %016lx\n", pte_val(*ptep),
 734                 pte_val(*(ptep + PTRS_PER_PTE)));
 735 #endif
 736         DBG_LOW(" -> rc=%d\n", rc);
 737         return rc;
 738 }
 739 EXPORT_SYMBOL_GPL(hash_page);
 740
 741 void hash_preload(struct mm_struct *mm, unsigned long ea,
 742                   unsigned long access, unsigned long trap)
 743 {
 744         unsigned long vsid;
 745         void *pgdir;
 746         pte_t *ptep;
 747         cpumask_t mask;
 748         unsigned long flags;
 749         int local = 0;
 750
 751         /* We don't want huge pages prefaulted for now
 752          */
 753         if (unlikely(in_hugepage_area(mm->context, ea)))
 754                 return;
 755
 756         DBG_LOW("hash_preload(mm=%p, mm->pgdir=%p, ea=%016lx, access=%lx,"
 757                 " trap=%lx\n", mm, mm->pgd, ea, access, trap);
 758
 759         /* Get PTE, VSID, access mask */
 760         pgdir = mm->pgd;
 761         if (pgdir == NULL)
 762                 return;
 763         ptep = find_linux_pte(pgdir, ea);
 764         if (!ptep)
 765                 return;
 766         vsid = get_vsid(mm->context.id, ea);
 767
 768         /* Hash it in */
 769         local_irq_save(flags);
 770         mask = cpumask_of_cpu(smp_processor_id());
 771         if (cpus_equal(mm->cpu_vm_mask, mask))
 772                 local = 1;
 773 #ifndef CONFIG_PPC_64K_PAGES
 774         __hash_page_4K(ea, access, vsid, ptep, trap, local);
 775 #else
 776         if (mmu_ci_restrictions) {
 777                 /* If this PTE is non-cacheable, switch to 4k */
 778                 if (mm->context.user_psize == MMU_PAGE_64K &&
 779                     (pte_val(*ptep) & _PAGE_NO_CACHE)) {
 780                         mm->context.user_psize = MMU_PAGE_4K;
 781                         mm->context.sllp = SLB_VSID_USER |
 782                                 mmu_psize_defs[MMU_PAGE_4K].sllp;
 783                         get_paca()->context = mm->context;
 784                         slb_flush_and_rebolt();
 785                 }
 786         }
 787         if (mm->context.user_psize == MMU_PAGE_64K)
 788                 __hash_page_64K(ea, access, vsid, ptep, trap, local);
 789         else
 790                 __hash_page_4K(ea, access, vsid, ptep, trap, local);
 791 #endif /* CONFIG_PPC_64K_PAGES */
 792         local_irq_restore(flags);
 793 }
 794
 795 void flush_hash_page(unsigned long va, real_pte_t pte, int psize, int local)
 796 {
 797         unsigned long hash, index, shift, hidx, slot;
 798
 799         DBG_LOW("flush_hash_page(va=%016x)\n", va);
 800         pte_iterate_hashed_subpages(pte, psize, va, index, shift) {
 801                 hash = hpt_hash(va, shift);
 802                 hidx = __rpte_to_hidx(pte, index);
 803                 if (hidx & _PTEIDX_SECONDARY)
 804                         hash = ~hash;
 805                 slot = (hash & htab_hash_mask) * HPTES_PER_GROUP;
 806                 slot += hidx & _PTEIDX_GROUP_IX;
 807                 DBG_LOW(" sub %d: hash=%x, hidx=%x\n", index, slot, hidx);
 808                 ppc_md.hpte_invalidate(slot, va, psize, local);
 809         } pte_iterate_hashed_end();
 810 }
 811
 812 void flush_hash_range(unsigned long number, int local)
 813 {
 814         if (ppc_md.flush_hash_range)
 815                 ppc_md.flush_hash_range(number, local);
 816         else {
 817                 int i;
 818                 struct ppc64_tlb_batch *batch =
 819                         &__get_cpu_var(ppc64_tlb_batch);
 820
 821                 for (i = 0; i < number; i++)
 822                         flush_hash_page(batch->vaddr[i], batch->pte[i],
 823                                         batch->psize, local);
 824         }
 825 }
 826
 827 /*
 828  * low_hash_fault is called when we the low level hash code failed
 829  * to instert a PTE due to an hypervisor error
 830  */
 831 void low_hash_fault(struct pt_regs *regs, unsigned long address)
 832 {
 833         if (user_mode(regs)) {
 834                 siginfo_t info;
 835
 836                 info.si_signo = SIGBUS;
 837                 info.si_errno = 0;
 838                 info.si_code = BUS_ADRERR;
 839                 info.si_addr = (void __user *)address;
 840                 force_sig_info(SIGBUS, &info, current);
 841                 return;
 842         }
 843         bad_page_fault(regs, address, SIGBUS);
 844 }