Merge branch 'for-linus' of git://one.firstfloor.org/home/andi/git/linux-2.6
[linux-3.10.git] / arch / i386 / kernel / io_apic.c
1 /*
2  *      Intel IO-APIC support for multi-Pentium hosts.
3  *
4  *      Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
5  *
6  *      Many thanks to Stig Venaas for trying out countless experimental
7  *      patches and reporting/debugging problems patiently!
8  *
9  *      (c) 1999, Multiple IO-APIC support, developed by
10  *      Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11  *      Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12  *      further tested and cleaned up by Zach Brown <zab@redhat.com>
13  *      and Ingo Molnar <mingo@redhat.com>
14  *
15  *      Fixes
16  *      Maciej W. Rozycki       :       Bits for genuine 82489DX APICs;
17  *                                      thanks to Eric Gilmore
18  *                                      and Rolf G. Tews
19  *                                      for testing these extensively
20  *      Paul Diefenbaugh        :       Added full ACPI support
21  */
22
23 #include <linux/mm.h>
24 #include <linux/interrupt.h>
25 #include <linux/init.h>
26 #include <linux/delay.h>
27 #include <linux/sched.h>
28 #include <linux/smp_lock.h>
29 #include <linux/mc146818rtc.h>
30 #include <linux/compiler.h>
31 #include <linux/acpi.h>
32 #include <linux/module.h>
33 #include <linux/sysdev.h>
34 #include <linux/pci.h>
35 #include <linux/msi.h>
36 #include <linux/htirq.h>
37 #include <linux/freezer.h>
38 #include <linux/kthread.h>
39
40 #include <asm/io.h>
41 #include <asm/smp.h>
42 #include <asm/desc.h>
43 #include <asm/timer.h>
44 #include <asm/i8259.h>
45 #include <asm/nmi.h>
46 #include <asm/msidef.h>
47 #include <asm/hypertransport.h>
48
49 #include <mach_apic.h>
50 #include <mach_apicdef.h>
51
52 #include "io_ports.h"
53
54 int (*ioapic_renumber_irq)(int ioapic, int irq);
55 atomic_t irq_mis_count;
56
57 /* Where if anywhere is the i8259 connect in external int mode */
58 static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
59
60 static DEFINE_SPINLOCK(ioapic_lock);
61 static DEFINE_SPINLOCK(vector_lock);
62
63 int timer_over_8254 __initdata = 1;
64
65 /*
66  *      Is the SiS APIC rmw bug present ?
67  *      -1 = don't know, 0 = no, 1 = yes
68  */
69 int sis_apic_bug = -1;
70
71 /*
72  * # of IRQ routing registers
73  */
74 int nr_ioapic_registers[MAX_IO_APICS];
75
76 static int disable_timer_pin_1 __initdata;
77
78 /*
79  * Rough estimation of how many shared IRQs there are, can
80  * be changed anytime.
81  */
82 #define MAX_PLUS_SHARED_IRQS NR_IRQS
83 #define PIN_MAP_SIZE (MAX_PLUS_SHARED_IRQS + NR_IRQS)
84
85 /*
86  * This is performance-critical, we want to do it O(1)
87  *
88  * the indexing order of this array favors 1:1 mappings
89  * between pins and IRQs.
90  */
91
92 static struct irq_pin_list {
93         int apic, pin, next;
94 } irq_2_pin[PIN_MAP_SIZE];
95
96 struct io_apic {
97         unsigned int index;
98         unsigned int unused[3];
99         unsigned int data;
100 };
101
102 static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx)
103 {
104         return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx)
105                 + (mp_ioapics[idx].mpc_apicaddr & ~PAGE_MASK);
106 }
107
108 static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg)
109 {
110         struct io_apic __iomem *io_apic = io_apic_base(apic);
111         writel(reg, &io_apic->index);
112         return readl(&io_apic->data);
113 }
114
115 static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value)
116 {
117         struct io_apic __iomem *io_apic = io_apic_base(apic);
118         writel(reg, &io_apic->index);
119         writel(value, &io_apic->data);
120 }
121
122 /*
123  * Re-write a value: to be used for read-modify-write
124  * cycles where the read already set up the index register.
125  *
126  * Older SiS APIC requires we rewrite the index register
127  */
128 static inline void io_apic_modify(unsigned int apic, unsigned int reg, unsigned int value)
129 {
130         volatile struct io_apic __iomem *io_apic = io_apic_base(apic);
131         if (sis_apic_bug)
132                 writel(reg, &io_apic->index);
133         writel(value, &io_apic->data);
134 }
135
136 union entry_union {
137         struct { u32 w1, w2; };
138         struct IO_APIC_route_entry entry;
139 };
140
141 static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin)
142 {
143         union entry_union eu;
144         unsigned long flags;
145         spin_lock_irqsave(&ioapic_lock, flags);
146         eu.w1 = io_apic_read(apic, 0x10 + 2 * pin);
147         eu.w2 = io_apic_read(apic, 0x11 + 2 * pin);
148         spin_unlock_irqrestore(&ioapic_lock, flags);
149         return eu.entry;
150 }
151
152 /*
153  * When we write a new IO APIC routing entry, we need to write the high
154  * word first! If the mask bit in the low word is clear, we will enable
155  * the interrupt, and we need to make sure the entry is fully populated
156  * before that happens.
157  */
158 static void
159 __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
160 {
161         union entry_union eu;
162         eu.entry = e;
163         io_apic_write(apic, 0x11 + 2*pin, eu.w2);
164         io_apic_write(apic, 0x10 + 2*pin, eu.w1);
165 }
166
167 static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
168 {
169         unsigned long flags;
170         spin_lock_irqsave(&ioapic_lock, flags);
171         __ioapic_write_entry(apic, pin, e);
172         spin_unlock_irqrestore(&ioapic_lock, flags);
173 }
174
175 /*
176  * When we mask an IO APIC routing entry, we need to write the low
177  * word first, in order to set the mask bit before we change the
178  * high bits!
179  */
180 static void ioapic_mask_entry(int apic, int pin)
181 {
182         unsigned long flags;
183         union entry_union eu = { .entry.mask = 1 };
184
185         spin_lock_irqsave(&ioapic_lock, flags);
186         io_apic_write(apic, 0x10 + 2*pin, eu.w1);
187         io_apic_write(apic, 0x11 + 2*pin, eu.w2);
188         spin_unlock_irqrestore(&ioapic_lock, flags);
189 }
190
191 /*
192  * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
193  * shared ISA-space IRQs, so we have to support them. We are super
194  * fast in the common case, and fast for shared ISA-space IRQs.
195  */
196 static void add_pin_to_irq(unsigned int irq, int apic, int pin)
197 {
198         static int first_free_entry = NR_IRQS;
199         struct irq_pin_list *entry = irq_2_pin + irq;
200
201         while (entry->next)
202                 entry = irq_2_pin + entry->next;
203
204         if (entry->pin != -1) {
205                 entry->next = first_free_entry;
206                 entry = irq_2_pin + entry->next;
207                 if (++first_free_entry >= PIN_MAP_SIZE)
208                         panic("io_apic.c: whoops");
209         }
210         entry->apic = apic;
211         entry->pin = pin;
212 }
213
214 /*
215  * Reroute an IRQ to a different pin.
216  */
217 static void __init replace_pin_at_irq(unsigned int irq,
218                                       int oldapic, int oldpin,
219                                       int newapic, int newpin)
220 {
221         struct irq_pin_list *entry = irq_2_pin + irq;
222
223         while (1) {
224                 if (entry->apic == oldapic && entry->pin == oldpin) {
225                         entry->apic = newapic;
226                         entry->pin = newpin;
227                 }
228                 if (!entry->next)
229                         break;
230                 entry = irq_2_pin + entry->next;
231         }
232 }
233
234 static void __modify_IO_APIC_irq (unsigned int irq, unsigned long enable, unsigned long disable)
235 {
236         struct irq_pin_list *entry = irq_2_pin + irq;
237         unsigned int pin, reg;
238
239         for (;;) {
240                 pin = entry->pin;
241                 if (pin == -1)
242                         break;
243                 reg = io_apic_read(entry->apic, 0x10 + pin*2);
244                 reg &= ~disable;
245                 reg |= enable;
246                 io_apic_modify(entry->apic, 0x10 + pin*2, reg);
247                 if (!entry->next)
248                         break;
249                 entry = irq_2_pin + entry->next;
250         }
251 }
252
253 /* mask = 1 */
254 static void __mask_IO_APIC_irq (unsigned int irq)
255 {
256         __modify_IO_APIC_irq(irq, 0x00010000, 0);
257 }
258
259 /* mask = 0 */
260 static void __unmask_IO_APIC_irq (unsigned int irq)
261 {
262         __modify_IO_APIC_irq(irq, 0, 0x00010000);
263 }
264
265 /* mask = 1, trigger = 0 */
266 static void __mask_and_edge_IO_APIC_irq (unsigned int irq)
267 {
268         __modify_IO_APIC_irq(irq, 0x00010000, 0x00008000);
269 }
270
271 /* mask = 0, trigger = 1 */
272 static void __unmask_and_level_IO_APIC_irq (unsigned int irq)
273 {
274         __modify_IO_APIC_irq(irq, 0x00008000, 0x00010000);
275 }
276
277 static void mask_IO_APIC_irq (unsigned int irq)
278 {
279         unsigned long flags;
280
281         spin_lock_irqsave(&ioapic_lock, flags);
282         __mask_IO_APIC_irq(irq);
283         spin_unlock_irqrestore(&ioapic_lock, flags);
284 }
285
286 static void unmask_IO_APIC_irq (unsigned int irq)
287 {
288         unsigned long flags;
289
290         spin_lock_irqsave(&ioapic_lock, flags);
291         __unmask_IO_APIC_irq(irq);
292         spin_unlock_irqrestore(&ioapic_lock, flags);
293 }
294
295 static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
296 {
297         struct IO_APIC_route_entry entry;
298         
299         /* Check delivery_mode to be sure we're not clearing an SMI pin */
300         entry = ioapic_read_entry(apic, pin);
301         if (entry.delivery_mode == dest_SMI)
302                 return;
303
304         /*
305          * Disable it in the IO-APIC irq-routing table:
306          */
307         ioapic_mask_entry(apic, pin);
308 }
309
310 static void clear_IO_APIC (void)
311 {
312         int apic, pin;
313
314         for (apic = 0; apic < nr_ioapics; apic++)
315                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
316                         clear_IO_APIC_pin(apic, pin);
317 }
318
319 #ifdef CONFIG_SMP
320 static void set_ioapic_affinity_irq(unsigned int irq, cpumask_t cpumask)
321 {
322         unsigned long flags;
323         int pin;
324         struct irq_pin_list *entry = irq_2_pin + irq;
325         unsigned int apicid_value;
326         cpumask_t tmp;
327         
328         cpus_and(tmp, cpumask, cpu_online_map);
329         if (cpus_empty(tmp))
330                 tmp = TARGET_CPUS;
331
332         cpus_and(cpumask, tmp, CPU_MASK_ALL);
333
334         apicid_value = cpu_mask_to_apicid(cpumask);
335         /* Prepare to do the io_apic_write */
336         apicid_value = apicid_value << 24;
337         spin_lock_irqsave(&ioapic_lock, flags);
338         for (;;) {
339                 pin = entry->pin;
340                 if (pin == -1)
341                         break;
342                 io_apic_write(entry->apic, 0x10 + 1 + pin*2, apicid_value);
343                 if (!entry->next)
344                         break;
345                 entry = irq_2_pin + entry->next;
346         }
347         irq_desc[irq].affinity = cpumask;
348         spin_unlock_irqrestore(&ioapic_lock, flags);
349 }
350
351 #if defined(CONFIG_IRQBALANCE)
352 # include <asm/processor.h>     /* kernel_thread() */
353 # include <linux/kernel_stat.h> /* kstat */
354 # include <linux/slab.h>                /* kmalloc() */
355 # include <linux/timer.h>       /* time_after() */
356  
357 #ifdef CONFIG_BALANCED_IRQ_DEBUG
358 #  define TDprintk(x...) do { printk("<%ld:%s:%d>: ", jiffies, __FILE__, __LINE__); printk(x); } while (0)
359 #  define Dprintk(x...) do { TDprintk(x); } while (0)
360 # else
361 #  define TDprintk(x...) 
362 #  define Dprintk(x...) 
363 # endif
364
365 #define IRQBALANCE_CHECK_ARCH -999
366 #define MAX_BALANCED_IRQ_INTERVAL       (5*HZ)
367 #define MIN_BALANCED_IRQ_INTERVAL       (HZ/2)
368 #define BALANCED_IRQ_MORE_DELTA         (HZ/10)
369 #define BALANCED_IRQ_LESS_DELTA         (HZ)
370
371 static int irqbalance_disabled __read_mostly = IRQBALANCE_CHECK_ARCH;
372 static int physical_balance __read_mostly;
373 static long balanced_irq_interval __read_mostly = MAX_BALANCED_IRQ_INTERVAL;
374
375 static struct irq_cpu_info {
376         unsigned long * last_irq;
377         unsigned long * irq_delta;
378         unsigned long irq;
379 } irq_cpu_data[NR_CPUS];
380
381 #define CPU_IRQ(cpu)            (irq_cpu_data[cpu].irq)
382 #define LAST_CPU_IRQ(cpu,irq)   (irq_cpu_data[cpu].last_irq[irq])
383 #define IRQ_DELTA(cpu,irq)      (irq_cpu_data[cpu].irq_delta[irq])
384
385 #define IDLE_ENOUGH(cpu,now) \
386         (idle_cpu(cpu) && ((now) - per_cpu(irq_stat, (cpu)).idle_timestamp > 1))
387
388 #define IRQ_ALLOWED(cpu, allowed_mask)  cpu_isset(cpu, allowed_mask)
389
390 #define CPU_TO_PACKAGEINDEX(i) (first_cpu(cpu_sibling_map[i]))
391
392 static cpumask_t balance_irq_affinity[NR_IRQS] = {
393         [0 ... NR_IRQS-1] = CPU_MASK_ALL
394 };
395
396 void set_balance_irq_affinity(unsigned int irq, cpumask_t mask)
397 {
398         balance_irq_affinity[irq] = mask;
399 }
400
401 static unsigned long move(int curr_cpu, cpumask_t allowed_mask,
402                         unsigned long now, int direction)
403 {
404         int search_idle = 1;
405         int cpu = curr_cpu;
406
407         goto inside;
408
409         do {
410                 if (unlikely(cpu == curr_cpu))
411                         search_idle = 0;
412 inside:
413                 if (direction == 1) {
414                         cpu++;
415                         if (cpu >= NR_CPUS)
416                                 cpu = 0;
417                 } else {
418                         cpu--;
419                         if (cpu == -1)
420                                 cpu = NR_CPUS-1;
421                 }
422         } while (!cpu_online(cpu) || !IRQ_ALLOWED(cpu,allowed_mask) ||
423                         (search_idle && !IDLE_ENOUGH(cpu,now)));
424
425         return cpu;
426 }
427
428 static inline void balance_irq(int cpu, int irq)
429 {
430         unsigned long now = jiffies;
431         cpumask_t allowed_mask;
432         unsigned int new_cpu;
433                 
434         if (irqbalance_disabled)
435                 return; 
436
437         cpus_and(allowed_mask, cpu_online_map, balance_irq_affinity[irq]);
438         new_cpu = move(cpu, allowed_mask, now, 1);
439         if (cpu != new_cpu) {
440                 set_pending_irq(irq, cpumask_of_cpu(new_cpu));
441         }
442 }
443
444 static inline void rotate_irqs_among_cpus(unsigned long useful_load_threshold)
445 {
446         int i, j;
447         Dprintk("Rotating IRQs among CPUs.\n");
448         for_each_online_cpu(i) {
449                 for (j = 0; j < NR_IRQS; j++) {
450                         if (!irq_desc[j].action)
451                                 continue;
452                         /* Is it a significant load ?  */
453                         if (IRQ_DELTA(CPU_TO_PACKAGEINDEX(i),j) <
454                                                 useful_load_threshold)
455                                 continue;
456                         balance_irq(i, j);
457                 }
458         }
459         balanced_irq_interval = max((long)MIN_BALANCED_IRQ_INTERVAL,
460                 balanced_irq_interval - BALANCED_IRQ_LESS_DELTA);       
461         return;
462 }
463
464 static void do_irq_balance(void)
465 {
466         int i, j;
467         unsigned long max_cpu_irq = 0, min_cpu_irq = (~0);
468         unsigned long move_this_load = 0;
469         int max_loaded = 0, min_loaded = 0;
470         int load;
471         unsigned long useful_load_threshold = balanced_irq_interval + 10;
472         int selected_irq;
473         int tmp_loaded, first_attempt = 1;
474         unsigned long tmp_cpu_irq;
475         unsigned long imbalance = 0;
476         cpumask_t allowed_mask, target_cpu_mask, tmp;
477
478         for_each_possible_cpu(i) {
479                 int package_index;
480                 CPU_IRQ(i) = 0;
481                 if (!cpu_online(i))
482                         continue;
483                 package_index = CPU_TO_PACKAGEINDEX(i);
484                 for (j = 0; j < NR_IRQS; j++) {
485                         unsigned long value_now, delta;
486                         /* Is this an active IRQ or balancing disabled ? */
487                         if (!irq_desc[j].action || irq_balancing_disabled(j))
488                                 continue;
489                         if ( package_index == i )
490                                 IRQ_DELTA(package_index,j) = 0;
491                         /* Determine the total count per processor per IRQ */
492                         value_now = (unsigned long) kstat_cpu(i).irqs[j];
493
494                         /* Determine the activity per processor per IRQ */
495                         delta = value_now - LAST_CPU_IRQ(i,j);
496
497                         /* Update last_cpu_irq[][] for the next time */
498                         LAST_CPU_IRQ(i,j) = value_now;
499
500                         /* Ignore IRQs whose rate is less than the clock */
501                         if (delta < useful_load_threshold)
502                                 continue;
503                         /* update the load for the processor or package total */
504                         IRQ_DELTA(package_index,j) += delta;
505
506                         /* Keep track of the higher numbered sibling as well */
507                         if (i != package_index)
508                                 CPU_IRQ(i) += delta;
509                         /*
510                          * We have sibling A and sibling B in the package
511                          *
512                          * cpu_irq[A] = load for cpu A + load for cpu B
513                          * cpu_irq[B] = load for cpu B
514                          */
515                         CPU_IRQ(package_index) += delta;
516                 }
517         }
518         /* Find the least loaded processor package */
519         for_each_online_cpu(i) {
520                 if (i != CPU_TO_PACKAGEINDEX(i))
521                         continue;
522                 if (min_cpu_irq > CPU_IRQ(i)) {
523                         min_cpu_irq = CPU_IRQ(i);
524                         min_loaded = i;
525                 }
526         }
527         max_cpu_irq = ULONG_MAX;
528
529 tryanothercpu:
530         /* Look for heaviest loaded processor.
531          * We may come back to get the next heaviest loaded processor.
532          * Skip processors with trivial loads.
533          */
534         tmp_cpu_irq = 0;
535         tmp_loaded = -1;
536         for_each_online_cpu(i) {
537                 if (i != CPU_TO_PACKAGEINDEX(i))
538                         continue;
539                 if (max_cpu_irq <= CPU_IRQ(i)) 
540                         continue;
541                 if (tmp_cpu_irq < CPU_IRQ(i)) {
542                         tmp_cpu_irq = CPU_IRQ(i);
543                         tmp_loaded = i;
544                 }
545         }
546
547         if (tmp_loaded == -1) {
548          /* In the case of small number of heavy interrupt sources, 
549           * loading some of the cpus too much. We use Ingo's original 
550           * approach to rotate them around.
551           */
552                 if (!first_attempt && imbalance >= useful_load_threshold) {
553                         rotate_irqs_among_cpus(useful_load_threshold);
554                         return;
555                 }
556                 goto not_worth_the_effort;
557         }
558         
559         first_attempt = 0;              /* heaviest search */
560         max_cpu_irq = tmp_cpu_irq;      /* load */
561         max_loaded = tmp_loaded;        /* processor */
562         imbalance = (max_cpu_irq - min_cpu_irq) / 2;
563         
564         Dprintk("max_loaded cpu = %d\n", max_loaded);
565         Dprintk("min_loaded cpu = %d\n", min_loaded);
566         Dprintk("max_cpu_irq load = %ld\n", max_cpu_irq);
567         Dprintk("min_cpu_irq load = %ld\n", min_cpu_irq);
568         Dprintk("load imbalance = %lu\n", imbalance);
569
570         /* if imbalance is less than approx 10% of max load, then
571          * observe diminishing returns action. - quit
572          */
573         if (imbalance < (max_cpu_irq >> 3)) {
574                 Dprintk("Imbalance too trivial\n");
575                 goto not_worth_the_effort;
576         }
577
578 tryanotherirq:
579         /* if we select an IRQ to move that can't go where we want, then
580          * see if there is another one to try.
581          */
582         move_this_load = 0;
583         selected_irq = -1;
584         for (j = 0; j < NR_IRQS; j++) {
585                 /* Is this an active IRQ? */
586                 if (!irq_desc[j].action)
587                         continue;
588                 if (imbalance <= IRQ_DELTA(max_loaded,j))
589                         continue;
590                 /* Try to find the IRQ that is closest to the imbalance
591                  * without going over.
592                  */
593                 if (move_this_load < IRQ_DELTA(max_loaded,j)) {
594                         move_this_load = IRQ_DELTA(max_loaded,j);
595                         selected_irq = j;
596                 }
597         }
598         if (selected_irq == -1) {
599                 goto tryanothercpu;
600         }
601
602         imbalance = move_this_load;
603         
604         /* For physical_balance case, we accumlated both load
605          * values in the one of the siblings cpu_irq[],
606          * to use the same code for physical and logical processors
607          * as much as possible. 
608          *
609          * NOTE: the cpu_irq[] array holds the sum of the load for
610          * sibling A and sibling B in the slot for the lowest numbered
611          * sibling (A), _AND_ the load for sibling B in the slot for
612          * the higher numbered sibling.
613          *
614          * We seek the least loaded sibling by making the comparison
615          * (A+B)/2 vs B
616          */
617         load = CPU_IRQ(min_loaded) >> 1;
618         for_each_cpu_mask(j, cpu_sibling_map[min_loaded]) {
619                 if (load > CPU_IRQ(j)) {
620                         /* This won't change cpu_sibling_map[min_loaded] */
621                         load = CPU_IRQ(j);
622                         min_loaded = j;
623                 }
624         }
625
626         cpus_and(allowed_mask,
627                 cpu_online_map,
628                 balance_irq_affinity[selected_irq]);
629         target_cpu_mask = cpumask_of_cpu(min_loaded);
630         cpus_and(tmp, target_cpu_mask, allowed_mask);
631
632         if (!cpus_empty(tmp)) {
633
634                 Dprintk("irq = %d moved to cpu = %d\n",
635                                 selected_irq, min_loaded);
636                 /* mark for change destination */
637                 set_pending_irq(selected_irq, cpumask_of_cpu(min_loaded));
638
639                 /* Since we made a change, come back sooner to 
640                  * check for more variation.
641                  */
642                 balanced_irq_interval = max((long)MIN_BALANCED_IRQ_INTERVAL,
643                         balanced_irq_interval - BALANCED_IRQ_LESS_DELTA);       
644                 return;
645         }
646         goto tryanotherirq;
647
648 not_worth_the_effort:
649         /*
650          * if we did not find an IRQ to move, then adjust the time interval
651          * upward
652          */
653         balanced_irq_interval = min((long)MAX_BALANCED_IRQ_INTERVAL,
654                 balanced_irq_interval + BALANCED_IRQ_MORE_DELTA);       
655         Dprintk("IRQ worth rotating not found\n");
656         return;
657 }
658
659 static int balanced_irq(void *unused)
660 {
661         int i;
662         unsigned long prev_balance_time = jiffies;
663         long time_remaining = balanced_irq_interval;
664
665         /* push everything to CPU 0 to give us a starting point.  */
666         for (i = 0 ; i < NR_IRQS ; i++) {
667                 irq_desc[i].pending_mask = cpumask_of_cpu(0);
668                 set_pending_irq(i, cpumask_of_cpu(0));
669         }
670
671         for ( ; ; ) {
672                 time_remaining = schedule_timeout_interruptible(time_remaining);
673                 try_to_freeze();
674                 if (time_after(jiffies,
675                                 prev_balance_time+balanced_irq_interval)) {
676                         preempt_disable();
677                         do_irq_balance();
678                         prev_balance_time = jiffies;
679                         time_remaining = balanced_irq_interval;
680                         preempt_enable();
681                 }
682         }
683         return 0;
684 }
685
686 static int __init balanced_irq_init(void)
687 {
688         int i;
689         struct cpuinfo_x86 *c;
690         cpumask_t tmp;
691
692         cpus_shift_right(tmp, cpu_online_map, 2);
693         c = &boot_cpu_data;
694         /* When not overwritten by the command line ask subarchitecture. */
695         if (irqbalance_disabled == IRQBALANCE_CHECK_ARCH)
696                 irqbalance_disabled = NO_BALANCE_IRQ;
697         if (irqbalance_disabled)
698                 return 0;
699         
700          /* disable irqbalance completely if there is only one processor online */
701         if (num_online_cpus() < 2) {
702                 irqbalance_disabled = 1;
703                 return 0;
704         }
705         /*
706          * Enable physical balance only if more than 1 physical processor
707          * is present
708          */
709         if (smp_num_siblings > 1 && !cpus_empty(tmp))
710                 physical_balance = 1;
711
712         for_each_online_cpu(i) {
713                 irq_cpu_data[i].irq_delta = kmalloc(sizeof(unsigned long) * NR_IRQS, GFP_KERNEL);
714                 irq_cpu_data[i].last_irq = kmalloc(sizeof(unsigned long) * NR_IRQS, GFP_KERNEL);
715                 if (irq_cpu_data[i].irq_delta == NULL || irq_cpu_data[i].last_irq == NULL) {
716                         printk(KERN_ERR "balanced_irq_init: out of memory");
717                         goto failed;
718                 }
719                 memset(irq_cpu_data[i].irq_delta,0,sizeof(unsigned long) * NR_IRQS);
720                 memset(irq_cpu_data[i].last_irq,0,sizeof(unsigned long) * NR_IRQS);
721         }
722         
723         printk(KERN_INFO "Starting balanced_irq\n");
724         if (!IS_ERR(kthread_run(balanced_irq, NULL, "kirqd")))
725                 return 0;
726         printk(KERN_ERR "balanced_irq_init: failed to spawn balanced_irq");
727 failed:
728         for_each_possible_cpu(i) {
729                 kfree(irq_cpu_data[i].irq_delta);
730                 irq_cpu_data[i].irq_delta = NULL;
731                 kfree(irq_cpu_data[i].last_irq);
732                 irq_cpu_data[i].last_irq = NULL;
733         }
734         return 0;
735 }
736
737 int __devinit irqbalance_disable(char *str)
738 {
739         irqbalance_disabled = 1;
740         return 1;
741 }
742
743 __setup("noirqbalance", irqbalance_disable);
744
745 late_initcall(balanced_irq_init);
746 #endif /* CONFIG_IRQBALANCE */
747 #endif /* CONFIG_SMP */
748
749 #ifndef CONFIG_SMP
750 void fastcall send_IPI_self(int vector)
751 {
752         unsigned int cfg;
753
754         /*
755          * Wait for idle.
756          */
757         apic_wait_icr_idle();
758         cfg = APIC_DM_FIXED | APIC_DEST_SELF | vector | APIC_DEST_LOGICAL;
759         /*
760          * Send the IPI. The write to APIC_ICR fires this off.
761          */
762         apic_write_around(APIC_ICR, cfg);
763 }
764 #endif /* !CONFIG_SMP */
765
766
767 /*
768  * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
769  * specific CPU-side IRQs.
770  */
771
772 #define MAX_PIRQS 8
773 static int pirq_entries [MAX_PIRQS];
774 static int pirqs_enabled;
775 int skip_ioapic_setup;
776
777 static int __init ioapic_setup(char *str)
778 {
779         skip_ioapic_setup = 1;
780         return 1;
781 }
782
783 __setup("noapic", ioapic_setup);
784
785 static int __init ioapic_pirq_setup(char *str)
786 {
787         int i, max;
788         int ints[MAX_PIRQS+1];
789
790         get_options(str, ARRAY_SIZE(ints), ints);
791
792         for (i = 0; i < MAX_PIRQS; i++)
793                 pirq_entries[i] = -1;
794
795         pirqs_enabled = 1;
796         apic_printk(APIC_VERBOSE, KERN_INFO
797                         "PIRQ redirection, working around broken MP-BIOS.\n");
798         max = MAX_PIRQS;
799         if (ints[0] < MAX_PIRQS)
800                 max = ints[0];
801
802         for (i = 0; i < max; i++) {
803                 apic_printk(APIC_VERBOSE, KERN_DEBUG
804                                 "... PIRQ%d -> IRQ %d\n", i, ints[i+1]);
805                 /*
806                  * PIRQs are mapped upside down, usually.
807                  */
808                 pirq_entries[MAX_PIRQS-i-1] = ints[i+1];
809         }
810         return 1;
811 }
812
813 __setup("pirq=", ioapic_pirq_setup);
814
815 /*
816  * Find the IRQ entry number of a certain pin.
817  */
818 static int find_irq_entry(int apic, int pin, int type)
819 {
820         int i;
821
822         for (i = 0; i < mp_irq_entries; i++)
823                 if (mp_irqs[i].mpc_irqtype == type &&
824                     (mp_irqs[i].mpc_dstapic == mp_ioapics[apic].mpc_apicid ||
825                      mp_irqs[i].mpc_dstapic == MP_APIC_ALL) &&
826                     mp_irqs[i].mpc_dstirq == pin)
827                         return i;
828
829         return -1;
830 }
831
832 /*
833  * Find the pin to which IRQ[irq] (ISA) is connected
834  */
835 static int __init find_isa_irq_pin(int irq, int type)
836 {
837         int i;
838
839         for (i = 0; i < mp_irq_entries; i++) {
840                 int lbus = mp_irqs[i].mpc_srcbus;
841
842                 if ((mp_bus_id_to_type[lbus] == MP_BUS_ISA ||
843                      mp_bus_id_to_type[lbus] == MP_BUS_EISA ||
844                      mp_bus_id_to_type[lbus] == MP_BUS_MCA
845                     ) &&
846                     (mp_irqs[i].mpc_irqtype == type) &&
847                     (mp_irqs[i].mpc_srcbusirq == irq))
848
849                         return mp_irqs[i].mpc_dstirq;
850         }
851         return -1;
852 }
853
854 static int __init find_isa_irq_apic(int irq, int type)
855 {
856         int i;
857
858         for (i = 0; i < mp_irq_entries; i++) {
859                 int lbus = mp_irqs[i].mpc_srcbus;
860
861                 if ((mp_bus_id_to_type[lbus] == MP_BUS_ISA ||
862                      mp_bus_id_to_type[lbus] == MP_BUS_EISA ||
863                      mp_bus_id_to_type[lbus] == MP_BUS_MCA
864                     ) &&
865                     (mp_irqs[i].mpc_irqtype == type) &&
866                     (mp_irqs[i].mpc_srcbusirq == irq))
867                         break;
868         }
869         if (i < mp_irq_entries) {
870                 int apic;
871                 for(apic = 0; apic < nr_ioapics; apic++) {
872                         if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic)
873                                 return apic;
874                 }
875         }
876
877         return -1;
878 }
879
880 /*
881  * Find a specific PCI IRQ entry.
882  * Not an __init, possibly needed by modules
883  */
884 static int pin_2_irq(int idx, int apic, int pin);
885
886 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
887 {
888         int apic, i, best_guess = -1;
889
890         apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, "
891                 "slot:%d, pin:%d.\n", bus, slot, pin);
892         if (mp_bus_id_to_pci_bus[bus] == -1) {
893                 printk(KERN_WARNING "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
894                 return -1;
895         }
896         for (i = 0; i < mp_irq_entries; i++) {
897                 int lbus = mp_irqs[i].mpc_srcbus;
898
899                 for (apic = 0; apic < nr_ioapics; apic++)
900                         if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic ||
901                             mp_irqs[i].mpc_dstapic == MP_APIC_ALL)
902                                 break;
903
904                 if ((mp_bus_id_to_type[lbus] == MP_BUS_PCI) &&
905                     !mp_irqs[i].mpc_irqtype &&
906                     (bus == lbus) &&
907                     (slot == ((mp_irqs[i].mpc_srcbusirq >> 2) & 0x1f))) {
908                         int irq = pin_2_irq(i,apic,mp_irqs[i].mpc_dstirq);
909
910                         if (!(apic || IO_APIC_IRQ(irq)))
911                                 continue;
912
913                         if (pin == (mp_irqs[i].mpc_srcbusirq & 3))
914                                 return irq;
915                         /*
916                          * Use the first all-but-pin matching entry as a
917                          * best-guess fuzzy result for broken mptables.
918                          */
919                         if (best_guess < 0)
920                                 best_guess = irq;
921                 }
922         }
923         return best_guess;
924 }
925 EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector);
926
927 /*
928  * This function currently is only a helper for the i386 smp boot process where 
929  * we need to reprogram the ioredtbls to cater for the cpus which have come online
930  * so mask in all cases should simply be TARGET_CPUS
931  */
932 #ifdef CONFIG_SMP
933 void __init setup_ioapic_dest(void)
934 {
935         int pin, ioapic, irq, irq_entry;
936
937         if (skip_ioapic_setup == 1)
938                 return;
939
940         for (ioapic = 0; ioapic < nr_ioapics; ioapic++) {
941                 for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
942                         irq_entry = find_irq_entry(ioapic, pin, mp_INT);
943                         if (irq_entry == -1)
944                                 continue;
945                         irq = pin_2_irq(irq_entry, ioapic, pin);
946                         set_ioapic_affinity_irq(irq, TARGET_CPUS);
947                 }
948
949         }
950 }
951 #endif
952
953 /*
954  * EISA Edge/Level control register, ELCR
955  */
956 static int EISA_ELCR(unsigned int irq)
957 {
958         if (irq < 16) {
959                 unsigned int port = 0x4d0 + (irq >> 3);
960                 return (inb(port) >> (irq & 7)) & 1;
961         }
962         apic_printk(APIC_VERBOSE, KERN_INFO
963                         "Broken MPtable reports ISA irq %d\n", irq);
964         return 0;
965 }
966
967 /* EISA interrupts are always polarity zero and can be edge or level
968  * trigger depending on the ELCR value.  If an interrupt is listed as
969  * EISA conforming in the MP table, that means its trigger type must
970  * be read in from the ELCR */
971
972 #define default_EISA_trigger(idx)       (EISA_ELCR(mp_irqs[idx].mpc_srcbusirq))
973 #define default_EISA_polarity(idx)      (0)
974
975 /* ISA interrupts are always polarity zero edge triggered,
976  * when listed as conforming in the MP table. */
977
978 #define default_ISA_trigger(idx)        (0)
979 #define default_ISA_polarity(idx)       (0)
980
981 /* PCI interrupts are always polarity one level triggered,
982  * when listed as conforming in the MP table. */
983
984 #define default_PCI_trigger(idx)        (1)
985 #define default_PCI_polarity(idx)       (1)
986
987 /* MCA interrupts are always polarity zero level triggered,
988  * when listed as conforming in the MP table. */
989
990 #define default_MCA_trigger(idx)        (1)
991 #define default_MCA_polarity(idx)       (0)
992
993 static int __init MPBIOS_polarity(int idx)
994 {
995         int bus = mp_irqs[idx].mpc_srcbus;
996         int polarity;
997
998         /*
999          * Determine IRQ line polarity (high active or low active):
1000          */
1001         switch (mp_irqs[idx].mpc_irqflag & 3)
1002         {
1003                 case 0: /* conforms, ie. bus-type dependent polarity */
1004                 {
1005                         switch (mp_bus_id_to_type[bus])
1006                         {
1007                                 case MP_BUS_ISA: /* ISA pin */
1008                                 {
1009                                         polarity = default_ISA_polarity(idx);
1010                                         break;
1011                                 }
1012                                 case MP_BUS_EISA: /* EISA pin */
1013                                 {
1014                                         polarity = default_EISA_polarity(idx);
1015                                         break;
1016                                 }
1017                                 case MP_BUS_PCI: /* PCI pin */
1018                                 {
1019                                         polarity = default_PCI_polarity(idx);
1020                                         break;
1021                                 }
1022                                 case MP_BUS_MCA: /* MCA pin */
1023                                 {
1024                                         polarity = default_MCA_polarity(idx);
1025                                         break;
1026                                 }
1027                                 default:
1028                                 {
1029                                         printk(KERN_WARNING "broken BIOS!!\n");
1030                                         polarity = 1;
1031                                         break;
1032                                 }
1033                         }
1034                         break;
1035                 }
1036                 case 1: /* high active */
1037                 {
1038                         polarity = 0;
1039                         break;
1040                 }
1041                 case 2: /* reserved */
1042                 {
1043                         printk(KERN_WARNING "broken BIOS!!\n");
1044                         polarity = 1;
1045                         break;
1046                 }
1047                 case 3: /* low active */
1048                 {
1049                         polarity = 1;
1050                         break;
1051                 }
1052                 default: /* invalid */
1053                 {
1054                         printk(KERN_WARNING "broken BIOS!!\n");
1055                         polarity = 1;
1056                         break;
1057                 }
1058         }
1059         return polarity;
1060 }
1061
1062 static int MPBIOS_trigger(int idx)
1063 {
1064         int bus = mp_irqs[idx].mpc_srcbus;
1065         int trigger;
1066
1067         /*
1068          * Determine IRQ trigger mode (edge or level sensitive):
1069          */
1070         switch ((mp_irqs[idx].mpc_irqflag>>2) & 3)
1071         {
1072                 case 0: /* conforms, ie. bus-type dependent */
1073                 {
1074                         switch (mp_bus_id_to_type[bus])
1075                         {
1076                                 case MP_BUS_ISA: /* ISA pin */
1077                                 {
1078                                         trigger = default_ISA_trigger(idx);
1079                                         break;
1080                                 }
1081                                 case MP_BUS_EISA: /* EISA pin */
1082                                 {
1083                                         trigger = default_EISA_trigger(idx);
1084                                         break;
1085                                 }
1086                                 case MP_BUS_PCI: /* PCI pin */
1087                                 {
1088                                         trigger = default_PCI_trigger(idx);
1089                                         break;
1090                                 }
1091                                 case MP_BUS_MCA: /* MCA pin */
1092                                 {
1093                                         trigger = default_MCA_trigger(idx);
1094                                         break;
1095                                 }
1096                                 default:
1097                                 {
1098                                         printk(KERN_WARNING "broken BIOS!!\n");
1099                                         trigger = 1;
1100                                         break;
1101                                 }
1102                         }
1103                         break;
1104                 }
1105                 case 1: /* edge */
1106                 {
1107                         trigger = 0;
1108                         break;
1109                 }
1110                 case 2: /* reserved */
1111                 {
1112                         printk(KERN_WARNING "broken BIOS!!\n");
1113                         trigger = 1;
1114                         break;
1115                 }
1116                 case 3: /* level */
1117                 {
1118                         trigger = 1;
1119                         break;
1120                 }
1121                 default: /* invalid */
1122                 {
1123                         printk(KERN_WARNING "broken BIOS!!\n");
1124                         trigger = 0;
1125                         break;
1126                 }
1127         }
1128         return trigger;
1129 }
1130
1131 static inline int irq_polarity(int idx)
1132 {
1133         return MPBIOS_polarity(idx);
1134 }
1135
1136 static inline int irq_trigger(int idx)
1137 {
1138         return MPBIOS_trigger(idx);
1139 }
1140
1141 static int pin_2_irq(int idx, int apic, int pin)
1142 {
1143         int irq, i;
1144         int bus = mp_irqs[idx].mpc_srcbus;
1145
1146         /*
1147          * Debugging check, we are in big trouble if this message pops up!
1148          */
1149         if (mp_irqs[idx].mpc_dstirq != pin)
1150                 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
1151
1152         switch (mp_bus_id_to_type[bus])
1153         {
1154                 case MP_BUS_ISA: /* ISA pin */
1155                 case MP_BUS_EISA:
1156                 case MP_BUS_MCA:
1157                 {
1158                         irq = mp_irqs[idx].mpc_srcbusirq;
1159                         break;
1160                 }
1161                 case MP_BUS_PCI: /* PCI pin */
1162                 {
1163                         /*
1164                          * PCI IRQs are mapped in order
1165                          */
1166                         i = irq = 0;
1167                         while (i < apic)
1168                                 irq += nr_ioapic_registers[i++];
1169                         irq += pin;
1170
1171                         /*
1172                          * For MPS mode, so far only needed by ES7000 platform
1173                          */
1174                         if (ioapic_renumber_irq)
1175                                 irq = ioapic_renumber_irq(apic, irq);
1176
1177                         break;
1178                 }
1179                 default:
1180                 {
1181                         printk(KERN_ERR "unknown bus type %d.\n",bus); 
1182                         irq = 0;
1183                         break;
1184                 }
1185         }
1186
1187         /*
1188          * PCI IRQ command line redirection. Yes, limits are hardcoded.
1189          */
1190         if ((pin >= 16) && (pin <= 23)) {
1191                 if (pirq_entries[pin-16] != -1) {
1192                         if (!pirq_entries[pin-16]) {
1193                                 apic_printk(APIC_VERBOSE, KERN_DEBUG
1194                                                 "disabling PIRQ%d\n", pin-16);
1195                         } else {
1196                                 irq = pirq_entries[pin-16];
1197                                 apic_printk(APIC_VERBOSE, KERN_DEBUG
1198                                                 "using PIRQ%d -> IRQ %d\n",
1199                                                 pin-16, irq);
1200                         }
1201                 }
1202         }
1203         return irq;
1204 }
1205
1206 static inline int IO_APIC_irq_trigger(int irq)
1207 {
1208         int apic, idx, pin;
1209
1210         for (apic = 0; apic < nr_ioapics; apic++) {
1211                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1212                         idx = find_irq_entry(apic,pin,mp_INT);
1213                         if ((idx != -1) && (irq == pin_2_irq(idx,apic,pin)))
1214                                 return irq_trigger(idx);
1215                 }
1216         }
1217         /*
1218          * nonexistent IRQs are edge default
1219          */
1220         return 0;
1221 }
1222
1223 /* irq_vectors is indexed by the sum of all RTEs in all I/O APICs. */
1224 static u8 irq_vector[NR_IRQ_VECTORS] __read_mostly = { FIRST_DEVICE_VECTOR , 0 };
1225
1226 static int __assign_irq_vector(int irq)
1227 {
1228         static int current_vector = FIRST_DEVICE_VECTOR, current_offset = 0;
1229         int vector, offset, i;
1230
1231         BUG_ON((unsigned)irq >= NR_IRQ_VECTORS);
1232
1233         if (irq_vector[irq] > 0)
1234                 return irq_vector[irq];
1235
1236         vector = current_vector;
1237         offset = current_offset;
1238 next:
1239         vector += 8;
1240         if (vector >= FIRST_SYSTEM_VECTOR) {
1241                 offset = (offset + 1) % 8;
1242                 vector = FIRST_DEVICE_VECTOR + offset;
1243         }
1244         if (vector == current_vector)
1245                 return -ENOSPC;
1246         if (vector == SYSCALL_VECTOR)
1247                 goto next;
1248         for (i = 0; i < NR_IRQ_VECTORS; i++)
1249                 if (irq_vector[i] == vector)
1250                         goto next;
1251
1252         current_vector = vector;
1253         current_offset = offset;
1254         irq_vector[irq] = vector;
1255
1256         return vector;
1257 }
1258
1259 static int assign_irq_vector(int irq)
1260 {
1261         unsigned long flags;
1262         int vector;
1263
1264         spin_lock_irqsave(&vector_lock, flags);
1265         vector = __assign_irq_vector(irq);
1266         spin_unlock_irqrestore(&vector_lock, flags);
1267
1268         return vector;
1269 }
1270 static struct irq_chip ioapic_chip;
1271
1272 #define IOAPIC_AUTO     -1
1273 #define IOAPIC_EDGE     0
1274 #define IOAPIC_LEVEL    1
1275
1276 static void ioapic_register_intr(int irq, int vector, unsigned long trigger)
1277 {
1278         if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1279                         trigger == IOAPIC_LEVEL)
1280                 set_irq_chip_and_handler_name(irq, &ioapic_chip,
1281                                          handle_fasteoi_irq, "fasteoi");
1282         else
1283                 set_irq_chip_and_handler_name(irq, &ioapic_chip,
1284                                          handle_edge_irq, "edge");
1285         set_intr_gate(vector, interrupt[irq]);
1286 }
1287
1288 static void __init setup_IO_APIC_irqs(void)
1289 {
1290         struct IO_APIC_route_entry entry;
1291         int apic, pin, idx, irq, first_notcon = 1, vector;
1292         unsigned long flags;
1293
1294         apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
1295
1296         for (apic = 0; apic < nr_ioapics; apic++) {
1297         for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1298
1299                 /*
1300                  * add it to the IO-APIC irq-routing table:
1301                  */
1302                 memset(&entry,0,sizeof(entry));
1303
1304                 entry.delivery_mode = INT_DELIVERY_MODE;
1305                 entry.dest_mode = INT_DEST_MODE;
1306                 entry.mask = 0;                         /* enable IRQ */
1307                 entry.dest.logical.logical_dest = 
1308                                         cpu_mask_to_apicid(TARGET_CPUS);
1309
1310                 idx = find_irq_entry(apic,pin,mp_INT);
1311                 if (idx == -1) {
1312                         if (first_notcon) {
1313                                 apic_printk(APIC_VERBOSE, KERN_DEBUG
1314                                                 " IO-APIC (apicid-pin) %d-%d",
1315                                                 mp_ioapics[apic].mpc_apicid,
1316                                                 pin);
1317                                 first_notcon = 0;
1318                         } else
1319                                 apic_printk(APIC_VERBOSE, ", %d-%d",
1320                                         mp_ioapics[apic].mpc_apicid, pin);
1321                         continue;
1322                 }
1323
1324                 entry.trigger = irq_trigger(idx);
1325                 entry.polarity = irq_polarity(idx);
1326
1327                 if (irq_trigger(idx)) {
1328                         entry.trigger = 1;
1329                         entry.mask = 1;
1330                 }
1331
1332                 irq = pin_2_irq(idx, apic, pin);
1333                 /*
1334                  * skip adding the timer int on secondary nodes, which causes
1335                  * a small but painful rift in the time-space continuum
1336                  */
1337                 if (multi_timer_check(apic, irq))
1338                         continue;
1339                 else
1340                         add_pin_to_irq(irq, apic, pin);
1341
1342                 if (!apic && !IO_APIC_IRQ(irq))
1343                         continue;
1344
1345                 if (IO_APIC_IRQ(irq)) {
1346                         vector = assign_irq_vector(irq);
1347                         entry.vector = vector;
1348                         ioapic_register_intr(irq, vector, IOAPIC_AUTO);
1349                 
1350                         if (!apic && (irq < 16))
1351                                 disable_8259A_irq(irq);
1352                 }
1353                 spin_lock_irqsave(&ioapic_lock, flags);
1354                 __ioapic_write_entry(apic, pin, entry);
1355                 spin_unlock_irqrestore(&ioapic_lock, flags);
1356         }
1357         }
1358
1359         if (!first_notcon)
1360                 apic_printk(APIC_VERBOSE, " not connected.\n");
1361 }
1362
1363 /*
1364  * Set up the 8259A-master output pin:
1365  */
1366 static void __init setup_ExtINT_IRQ0_pin(unsigned int apic, unsigned int pin, int vector)
1367 {
1368         struct IO_APIC_route_entry entry;
1369
1370         memset(&entry,0,sizeof(entry));
1371
1372         disable_8259A_irq(0);
1373
1374         /* mask LVT0 */
1375         apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
1376
1377         /*
1378          * We use logical delivery to get the timer IRQ
1379          * to the first CPU.
1380          */
1381         entry.dest_mode = INT_DEST_MODE;
1382         entry.mask = 0;                                 /* unmask IRQ now */
1383         entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
1384         entry.delivery_mode = INT_DELIVERY_MODE;
1385         entry.polarity = 0;
1386         entry.trigger = 0;
1387         entry.vector = vector;
1388
1389         /*
1390          * The timer IRQ doesn't have to know that behind the
1391          * scene we have a 8259A-master in AEOI mode ...
1392          */
1393         irq_desc[0].chip = &ioapic_chip;
1394         set_irq_handler(0, handle_edge_irq);
1395
1396         /*
1397          * Add it to the IO-APIC irq-routing table:
1398          */
1399         ioapic_write_entry(apic, pin, entry);
1400
1401         enable_8259A_irq(0);
1402 }
1403
1404 void __init print_IO_APIC(void)
1405 {
1406         int apic, i;
1407         union IO_APIC_reg_00 reg_00;
1408         union IO_APIC_reg_01 reg_01;
1409         union IO_APIC_reg_02 reg_02;
1410         union IO_APIC_reg_03 reg_03;
1411         unsigned long flags;
1412
1413         if (apic_verbosity == APIC_QUIET)
1414                 return;
1415
1416         printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
1417         for (i = 0; i < nr_ioapics; i++)
1418                 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
1419                        mp_ioapics[i].mpc_apicid, nr_ioapic_registers[i]);
1420
1421         /*
1422          * We are a bit conservative about what we expect.  We have to
1423          * know about every hardware change ASAP.
1424          */
1425         printk(KERN_INFO "testing the IO APIC.......................\n");
1426
1427         for (apic = 0; apic < nr_ioapics; apic++) {
1428
1429         spin_lock_irqsave(&ioapic_lock, flags);
1430         reg_00.raw = io_apic_read(apic, 0);
1431         reg_01.raw = io_apic_read(apic, 1);
1432         if (reg_01.bits.version >= 0x10)
1433                 reg_02.raw = io_apic_read(apic, 2);
1434         if (reg_01.bits.version >= 0x20)
1435                 reg_03.raw = io_apic_read(apic, 3);
1436         spin_unlock_irqrestore(&ioapic_lock, flags);
1437
1438         printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mpc_apicid);
1439         printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
1440         printk(KERN_DEBUG ".......    : physical APIC id: %02X\n", reg_00.bits.ID);
1441         printk(KERN_DEBUG ".......    : Delivery Type: %X\n", reg_00.bits.delivery_type);
1442         printk(KERN_DEBUG ".......    : LTS          : %X\n", reg_00.bits.LTS);
1443
1444         printk(KERN_DEBUG ".... register #01: %08X\n", reg_01.raw);
1445         printk(KERN_DEBUG ".......     : max redirection entries: %04X\n", reg_01.bits.entries);
1446
1447         printk(KERN_DEBUG ".......     : PRQ implemented: %X\n", reg_01.bits.PRQ);
1448         printk(KERN_DEBUG ".......     : IO APIC version: %04X\n", reg_01.bits.version);
1449
1450         /*
1451          * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
1452          * but the value of reg_02 is read as the previous read register
1453          * value, so ignore it if reg_02 == reg_01.
1454          */
1455         if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) {
1456                 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
1457                 printk(KERN_DEBUG ".......     : arbitration: %02X\n", reg_02.bits.arbitration);
1458         }
1459
1460         /*
1461          * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
1462          * or reg_03, but the value of reg_0[23] is read as the previous read
1463          * register value, so ignore it if reg_03 == reg_0[12].
1464          */
1465         if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw &&
1466             reg_03.raw != reg_01.raw) {
1467                 printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw);
1468                 printk(KERN_DEBUG ".......     : Boot DT    : %X\n", reg_03.bits.boot_DT);
1469         }
1470
1471         printk(KERN_DEBUG ".... IRQ redirection table:\n");
1472
1473         printk(KERN_DEBUG " NR Log Phy Mask Trig IRR Pol"
1474                           " Stat Dest Deli Vect:   \n");
1475
1476         for (i = 0; i <= reg_01.bits.entries; i++) {
1477                 struct IO_APIC_route_entry entry;
1478
1479                 entry = ioapic_read_entry(apic, i);
1480
1481                 printk(KERN_DEBUG " %02x %03X %02X  ",
1482                         i,
1483                         entry.dest.logical.logical_dest,
1484                         entry.dest.physical.physical_dest
1485                 );
1486
1487                 printk("%1d    %1d    %1d   %1d   %1d    %1d    %1d    %02X\n",
1488                         entry.mask,
1489                         entry.trigger,
1490                         entry.irr,
1491                         entry.polarity,
1492                         entry.delivery_status,
1493                         entry.dest_mode,
1494                         entry.delivery_mode,
1495                         entry.vector
1496                 );
1497         }
1498         }
1499         printk(KERN_DEBUG "IRQ to pin mappings:\n");
1500         for (i = 0; i < NR_IRQS; i++) {
1501                 struct irq_pin_list *entry = irq_2_pin + i;
1502                 if (entry->pin < 0)
1503                         continue;
1504                 printk(KERN_DEBUG "IRQ%d ", i);
1505                 for (;;) {
1506                         printk("-> %d:%d", entry->apic, entry->pin);
1507                         if (!entry->next)
1508                                 break;
1509                         entry = irq_2_pin + entry->next;
1510                 }
1511                 printk("\n");
1512         }
1513
1514         printk(KERN_INFO ".................................... done.\n");
1515
1516         return;
1517 }
1518
1519 #if 0
1520
1521 static void print_APIC_bitfield (int base)
1522 {
1523         unsigned int v;
1524         int i, j;
1525
1526         if (apic_verbosity == APIC_QUIET)
1527                 return;
1528
1529         printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG);
1530         for (i = 0; i < 8; i++) {
1531                 v = apic_read(base + i*0x10);
1532                 for (j = 0; j < 32; j++) {
1533                         if (v & (1<<j))
1534                                 printk("1");
1535                         else
1536                                 printk("0");
1537                 }
1538                 printk("\n");
1539         }
1540 }
1541
1542 void /*__init*/ print_local_APIC(void * dummy)
1543 {
1544         unsigned int v, ver, maxlvt;
1545
1546         if (apic_verbosity == APIC_QUIET)
1547                 return;
1548
1549         printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
1550                 smp_processor_id(), hard_smp_processor_id());
1551         v = apic_read(APIC_ID);
1552         printk(KERN_INFO "... APIC ID:      %08x (%01x)\n", v, GET_APIC_ID(v));
1553         v = apic_read(APIC_LVR);
1554         printk(KERN_INFO "... APIC VERSION: %08x\n", v);
1555         ver = GET_APIC_VERSION(v);
1556         maxlvt = lapic_get_maxlvt();
1557
1558         v = apic_read(APIC_TASKPRI);
1559         printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1560
1561         if (APIC_INTEGRATED(ver)) {                     /* !82489DX */
1562                 v = apic_read(APIC_ARBPRI);
1563                 printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
1564                         v & APIC_ARBPRI_MASK);
1565                 v = apic_read(APIC_PROCPRI);
1566                 printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
1567         }
1568
1569         v = apic_read(APIC_EOI);
1570         printk(KERN_DEBUG "... APIC EOI: %08x\n", v);
1571         v = apic_read(APIC_RRR);
1572         printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1573         v = apic_read(APIC_LDR);
1574         printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
1575         v = apic_read(APIC_DFR);
1576         printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1577         v = apic_read(APIC_SPIV);
1578         printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1579
1580         printk(KERN_DEBUG "... APIC ISR field:\n");
1581         print_APIC_bitfield(APIC_ISR);
1582         printk(KERN_DEBUG "... APIC TMR field:\n");
1583         print_APIC_bitfield(APIC_TMR);
1584         printk(KERN_DEBUG "... APIC IRR field:\n");
1585         print_APIC_bitfield(APIC_IRR);
1586
1587         if (APIC_INTEGRATED(ver)) {             /* !82489DX */
1588                 if (maxlvt > 3)         /* Due to the Pentium erratum 3AP. */
1589                         apic_write(APIC_ESR, 0);
1590                 v = apic_read(APIC_ESR);
1591                 printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1592         }
1593
1594         v = apic_read(APIC_ICR);
1595         printk(KERN_DEBUG "... APIC ICR: %08x\n", v);
1596         v = apic_read(APIC_ICR2);
1597         printk(KERN_DEBUG "... APIC ICR2: %08x\n", v);
1598
1599         v = apic_read(APIC_LVTT);
1600         printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1601
1602         if (maxlvt > 3) {                       /* PC is LVT#4. */
1603                 v = apic_read(APIC_LVTPC);
1604                 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1605         }
1606         v = apic_read(APIC_LVT0);
1607         printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1608         v = apic_read(APIC_LVT1);
1609         printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1610
1611         if (maxlvt > 2) {                       /* ERR is LVT#3. */
1612                 v = apic_read(APIC_LVTERR);
1613                 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1614         }
1615
1616         v = apic_read(APIC_TMICT);
1617         printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1618         v = apic_read(APIC_TMCCT);
1619         printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1620         v = apic_read(APIC_TDCR);
1621         printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1622         printk("\n");
1623 }
1624
1625 void print_all_local_APICs (void)
1626 {
1627         on_each_cpu(print_local_APIC, NULL, 1, 1);
1628 }
1629
1630 void /*__init*/ print_PIC(void)
1631 {
1632         unsigned int v;
1633         unsigned long flags;
1634
1635         if (apic_verbosity == APIC_QUIET)
1636                 return;
1637
1638         printk(KERN_DEBUG "\nprinting PIC contents\n");
1639
1640         spin_lock_irqsave(&i8259A_lock, flags);
1641
1642         v = inb(0xa1) << 8 | inb(0x21);
1643         printk(KERN_DEBUG "... PIC  IMR: %04x\n", v);
1644
1645         v = inb(0xa0) << 8 | inb(0x20);
1646         printk(KERN_DEBUG "... PIC  IRR: %04x\n", v);
1647
1648         outb(0x0b,0xa0);
1649         outb(0x0b,0x20);
1650         v = inb(0xa0) << 8 | inb(0x20);
1651         outb(0x0a,0xa0);
1652         outb(0x0a,0x20);
1653
1654         spin_unlock_irqrestore(&i8259A_lock, flags);
1655
1656         printk(KERN_DEBUG "... PIC  ISR: %04x\n", v);
1657
1658         v = inb(0x4d1) << 8 | inb(0x4d0);
1659         printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1660 }
1661
1662 #endif  /*  0  */
1663
1664 static void __init enable_IO_APIC(void)
1665 {
1666         union IO_APIC_reg_01 reg_01;
1667         int i8259_apic, i8259_pin;
1668         int i, apic;
1669         unsigned long flags;
1670
1671         for (i = 0; i < PIN_MAP_SIZE; i++) {
1672                 irq_2_pin[i].pin = -1;
1673                 irq_2_pin[i].next = 0;
1674         }
1675         if (!pirqs_enabled)
1676                 for (i = 0; i < MAX_PIRQS; i++)
1677                         pirq_entries[i] = -1;
1678
1679         /*
1680          * The number of IO-APIC IRQ registers (== #pins):
1681          */
1682         for (apic = 0; apic < nr_ioapics; apic++) {
1683                 spin_lock_irqsave(&ioapic_lock, flags);
1684                 reg_01.raw = io_apic_read(apic, 1);
1685                 spin_unlock_irqrestore(&ioapic_lock, flags);
1686                 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
1687         }
1688         for(apic = 0; apic < nr_ioapics; apic++) {
1689                 int pin;
1690                 /* See if any of the pins is in ExtINT mode */
1691                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1692                         struct IO_APIC_route_entry entry;
1693                         entry = ioapic_read_entry(apic, pin);
1694
1695
1696                         /* If the interrupt line is enabled and in ExtInt mode
1697                          * I have found the pin where the i8259 is connected.
1698                          */
1699                         if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
1700                                 ioapic_i8259.apic = apic;
1701                                 ioapic_i8259.pin  = pin;
1702                                 goto found_i8259;
1703                         }
1704                 }
1705         }
1706  found_i8259:
1707         /* Look to see what if the MP table has reported the ExtINT */
1708         /* If we could not find the appropriate pin by looking at the ioapic
1709          * the i8259 probably is not connected the ioapic but give the
1710          * mptable a chance anyway.
1711          */
1712         i8259_pin  = find_isa_irq_pin(0, mp_ExtINT);
1713         i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
1714         /* Trust the MP table if nothing is setup in the hardware */
1715         if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
1716                 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
1717                 ioapic_i8259.pin  = i8259_pin;
1718                 ioapic_i8259.apic = i8259_apic;
1719         }
1720         /* Complain if the MP table and the hardware disagree */
1721         if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
1722                 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
1723         {
1724                 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
1725         }
1726
1727         /*
1728          * Do not trust the IO-APIC being empty at bootup
1729          */
1730         clear_IO_APIC();
1731 }
1732
1733 /*
1734  * Not an __init, needed by the reboot code
1735  */
1736 void disable_IO_APIC(void)
1737 {
1738         /*
1739          * Clear the IO-APIC before rebooting:
1740          */
1741         clear_IO_APIC();
1742
1743         /*
1744          * If the i8259 is routed through an IOAPIC
1745          * Put that IOAPIC in virtual wire mode
1746          * so legacy interrupts can be delivered.
1747          */
1748         if (ioapic_i8259.pin != -1) {
1749                 struct IO_APIC_route_entry entry;
1750
1751                 memset(&entry, 0, sizeof(entry));
1752                 entry.mask            = 0; /* Enabled */
1753                 entry.trigger         = 0; /* Edge */
1754                 entry.irr             = 0;
1755                 entry.polarity        = 0; /* High */
1756                 entry.delivery_status = 0;
1757                 entry.dest_mode       = 0; /* Physical */
1758                 entry.delivery_mode   = dest_ExtINT; /* ExtInt */
1759                 entry.vector          = 0;
1760                 entry.dest.physical.physical_dest =
1761                                         GET_APIC_ID(apic_read(APIC_ID));
1762
1763                 /*
1764                  * Add it to the IO-APIC irq-routing table:
1765                  */
1766                 ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry);
1767         }
1768         disconnect_bsp_APIC(ioapic_i8259.pin != -1);
1769 }
1770
1771 /*
1772  * function to set the IO-APIC physical IDs based on the
1773  * values stored in the MPC table.
1774  *
1775  * by Matt Domsch <Matt_Domsch@dell.com>  Tue Dec 21 12:25:05 CST 1999
1776  */
1777
1778 #ifndef CONFIG_X86_NUMAQ
1779 static void __init setup_ioapic_ids_from_mpc(void)
1780 {
1781         union IO_APIC_reg_00 reg_00;
1782         physid_mask_t phys_id_present_map;
1783         int apic;
1784         int i;
1785         unsigned char old_id;
1786         unsigned long flags;
1787
1788         /*
1789          * Don't check I/O APIC IDs for xAPIC systems.  They have
1790          * no meaning without the serial APIC bus.
1791          */
1792         if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
1793                 || APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
1794                 return;
1795         /*
1796          * This is broken; anything with a real cpu count has to
1797          * circumvent this idiocy regardless.
1798          */
1799         phys_id_present_map = ioapic_phys_id_map(phys_cpu_present_map);
1800
1801         /*
1802          * Set the IOAPIC ID to the value stored in the MPC table.
1803          */
1804         for (apic = 0; apic < nr_ioapics; apic++) {
1805
1806                 /* Read the register 0 value */
1807                 spin_lock_irqsave(&ioapic_lock, flags);
1808                 reg_00.raw = io_apic_read(apic, 0);
1809                 spin_unlock_irqrestore(&ioapic_lock, flags);
1810                 
1811                 old_id = mp_ioapics[apic].mpc_apicid;
1812
1813                 if (mp_ioapics[apic].mpc_apicid >= get_physical_broadcast()) {
1814                         printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
1815                                 apic, mp_ioapics[apic].mpc_apicid);
1816                         printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1817                                 reg_00.bits.ID);
1818                         mp_ioapics[apic].mpc_apicid = reg_00.bits.ID;
1819                 }
1820
1821                 /*
1822                  * Sanity check, is the ID really free? Every APIC in a
1823                  * system must have a unique ID or we get lots of nice
1824                  * 'stuck on smp_invalidate_needed IPI wait' messages.
1825                  */
1826                 if (check_apicid_used(phys_id_present_map,
1827                                         mp_ioapics[apic].mpc_apicid)) {
1828                         printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n",
1829                                 apic, mp_ioapics[apic].mpc_apicid);
1830                         for (i = 0; i < get_physical_broadcast(); i++)
1831                                 if (!physid_isset(i, phys_id_present_map))
1832                                         break;
1833                         if (i >= get_physical_broadcast())
1834                                 panic("Max APIC ID exceeded!\n");
1835                         printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1836                                 i);
1837                         physid_set(i, phys_id_present_map);
1838                         mp_ioapics[apic].mpc_apicid = i;
1839                 } else {
1840                         physid_mask_t tmp;
1841                         tmp = apicid_to_cpu_present(mp_ioapics[apic].mpc_apicid);
1842                         apic_printk(APIC_VERBOSE, "Setting %d in the "
1843                                         "phys_id_present_map\n",
1844                                         mp_ioapics[apic].mpc_apicid);
1845                         physids_or(phys_id_present_map, phys_id_present_map, tmp);
1846                 }
1847
1848
1849                 /*
1850                  * We need to adjust the IRQ routing table
1851                  * if the ID changed.
1852                  */
1853                 if (old_id != mp_ioapics[apic].mpc_apicid)
1854                         for (i = 0; i < mp_irq_entries; i++)
1855                                 if (mp_irqs[i].mpc_dstapic == old_id)
1856                                         mp_irqs[i].mpc_dstapic
1857                                                 = mp_ioapics[apic].mpc_apicid;
1858
1859                 /*
1860                  * Read the right value from the MPC table and
1861                  * write it into the ID register.
1862                  */
1863                 apic_printk(APIC_VERBOSE, KERN_INFO
1864                         "...changing IO-APIC physical APIC ID to %d ...",
1865                         mp_ioapics[apic].mpc_apicid);
1866
1867                 reg_00.bits.ID = mp_ioapics[apic].mpc_apicid;
1868                 spin_lock_irqsave(&ioapic_lock, flags);
1869                 io_apic_write(apic, 0, reg_00.raw);
1870                 spin_unlock_irqrestore(&ioapic_lock, flags);
1871
1872                 /*
1873                  * Sanity check
1874                  */
1875                 spin_lock_irqsave(&ioapic_lock, flags);
1876                 reg_00.raw = io_apic_read(apic, 0);
1877                 spin_unlock_irqrestore(&ioapic_lock, flags);
1878                 if (reg_00.bits.ID != mp_ioapics[apic].mpc_apicid)
1879                         printk("could not set ID!\n");
1880                 else
1881                         apic_printk(APIC_VERBOSE, " ok.\n");
1882         }
1883 }
1884 #else
1885 static void __init setup_ioapic_ids_from_mpc(void) { }
1886 #endif
1887
1888 int no_timer_check __initdata;
1889
1890 static int __init notimercheck(char *s)
1891 {
1892         no_timer_check = 1;
1893         return 1;
1894 }
1895 __setup("no_timer_check", notimercheck);
1896
1897 /*
1898  * There is a nasty bug in some older SMP boards, their mptable lies
1899  * about the timer IRQ. We do the following to work around the situation:
1900  *
1901  *      - timer IRQ defaults to IO-APIC IRQ
1902  *      - if this function detects that timer IRQs are defunct, then we fall
1903  *        back to ISA timer IRQs
1904  */
1905 int __init timer_irq_works(void)
1906 {
1907         unsigned long t1 = jiffies;
1908
1909         if (no_timer_check)
1910                 return 1;
1911
1912         local_irq_enable();
1913         /* Let ten ticks pass... */
1914         mdelay((10 * 1000) / HZ);
1915
1916         /*
1917          * Expect a few ticks at least, to be sure some possible
1918          * glue logic does not lock up after one or two first
1919          * ticks in a non-ExtINT mode.  Also the local APIC
1920          * might have cached one ExtINT interrupt.  Finally, at
1921          * least one tick may be lost due to delays.
1922          */
1923         if (jiffies - t1 > 4)
1924                 return 1;
1925
1926         return 0;
1927 }
1928
1929 /*
1930  * In the SMP+IOAPIC case it might happen that there are an unspecified
1931  * number of pending IRQ events unhandled. These cases are very rare,
1932  * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1933  * better to do it this way as thus we do not have to be aware of
1934  * 'pending' interrupts in the IRQ path, except at this point.
1935  */
1936 /*
1937  * Edge triggered needs to resend any interrupt
1938  * that was delayed but this is now handled in the device
1939  * independent code.
1940  */
1941
1942 /*
1943  * Startup quirk:
1944  *
1945  * Starting up a edge-triggered IO-APIC interrupt is
1946  * nasty - we need to make sure that we get the edge.
1947  * If it is already asserted for some reason, we need
1948  * return 1 to indicate that is was pending.
1949  *
1950  * This is not complete - we should be able to fake
1951  * an edge even if it isn't on the 8259A...
1952  *
1953  * (We do this for level-triggered IRQs too - it cannot hurt.)
1954  */
1955 static unsigned int startup_ioapic_irq(unsigned int irq)
1956 {
1957         int was_pending = 0;
1958         unsigned long flags;
1959
1960         spin_lock_irqsave(&ioapic_lock, flags);
1961         if (irq < 16) {
1962                 disable_8259A_irq(irq);
1963                 if (i8259A_irq_pending(irq))
1964                         was_pending = 1;
1965         }
1966         __unmask_IO_APIC_irq(irq);
1967         spin_unlock_irqrestore(&ioapic_lock, flags);
1968
1969         return was_pending;
1970 }
1971
1972 static void ack_ioapic_irq(unsigned int irq)
1973 {
1974         move_native_irq(irq);
1975         ack_APIC_irq();
1976 }
1977
1978 static void ack_ioapic_quirk_irq(unsigned int irq)
1979 {
1980         unsigned long v;
1981         int i;
1982
1983         move_native_irq(irq);
1984 /*
1985  * It appears there is an erratum which affects at least version 0x11
1986  * of I/O APIC (that's the 82093AA and cores integrated into various
1987  * chipsets).  Under certain conditions a level-triggered interrupt is
1988  * erroneously delivered as edge-triggered one but the respective IRR
1989  * bit gets set nevertheless.  As a result the I/O unit expects an EOI
1990  * message but it will never arrive and further interrupts are blocked
1991  * from the source.  The exact reason is so far unknown, but the
1992  * phenomenon was observed when two consecutive interrupt requests
1993  * from a given source get delivered to the same CPU and the source is
1994  * temporarily disabled in between.
1995  *
1996  * A workaround is to simulate an EOI message manually.  We achieve it
1997  * by setting the trigger mode to edge and then to level when the edge
1998  * trigger mode gets detected in the TMR of a local APIC for a
1999  * level-triggered interrupt.  We mask the source for the time of the
2000  * operation to prevent an edge-triggered interrupt escaping meanwhile.
2001  * The idea is from Manfred Spraul.  --macro
2002  */
2003         i = irq_vector[irq];
2004
2005         v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1));
2006
2007         ack_APIC_irq();
2008
2009         if (!(v & (1 << (i & 0x1f)))) {
2010                 atomic_inc(&irq_mis_count);
2011                 spin_lock(&ioapic_lock);
2012                 __mask_and_edge_IO_APIC_irq(irq);
2013                 __unmask_and_level_IO_APIC_irq(irq);
2014                 spin_unlock(&ioapic_lock);
2015         }
2016 }
2017
2018 static int ioapic_retrigger_irq(unsigned int irq)
2019 {
2020         send_IPI_self(irq_vector[irq]);
2021
2022         return 1;
2023 }
2024
2025 static struct irq_chip ioapic_chip __read_mostly = {
2026         .name           = "IO-APIC",
2027         .startup        = startup_ioapic_irq,
2028         .mask           = mask_IO_APIC_irq,
2029         .unmask         = unmask_IO_APIC_irq,
2030         .ack            = ack_ioapic_irq,
2031         .eoi            = ack_ioapic_quirk_irq,
2032 #ifdef CONFIG_SMP
2033         .set_affinity   = set_ioapic_affinity_irq,
2034 #endif
2035         .retrigger      = ioapic_retrigger_irq,
2036 };
2037
2038
2039 static inline void init_IO_APIC_traps(void)
2040 {
2041         int irq;
2042
2043         /*
2044          * NOTE! The local APIC isn't very good at handling
2045          * multiple interrupts at the same interrupt level.
2046          * As the interrupt level is determined by taking the
2047          * vector number and shifting that right by 4, we
2048          * want to spread these out a bit so that they don't
2049          * all fall in the same interrupt level.
2050          *
2051          * Also, we've got to be careful not to trash gate
2052          * 0x80, because int 0x80 is hm, kind of importantish. ;)
2053          */
2054         for (irq = 0; irq < NR_IRQS ; irq++) {
2055                 int tmp = irq;
2056                 if (IO_APIC_IRQ(tmp) && !irq_vector[tmp]) {
2057                         /*
2058                          * Hmm.. We don't have an entry for this,
2059                          * so default to an old-fashioned 8259
2060                          * interrupt if we can..
2061                          */
2062                         if (irq < 16)
2063                                 make_8259A_irq(irq);
2064                         else
2065                                 /* Strange. Oh, well.. */
2066                                 irq_desc[irq].chip = &no_irq_chip;
2067                 }
2068         }
2069 }
2070
2071 /*
2072  * The local APIC irq-chip implementation:
2073  */
2074
2075 static void ack_apic(unsigned int irq)
2076 {
2077         ack_APIC_irq();
2078 }
2079
2080 static void mask_lapic_irq (unsigned int irq)
2081 {
2082         unsigned long v;
2083
2084         v = apic_read(APIC_LVT0);
2085         apic_write_around(APIC_LVT0, v | APIC_LVT_MASKED);
2086 }
2087
2088 static void unmask_lapic_irq (unsigned int irq)
2089 {
2090         unsigned long v;
2091
2092         v = apic_read(APIC_LVT0);
2093         apic_write_around(APIC_LVT0, v & ~APIC_LVT_MASKED);
2094 }
2095
2096 static struct irq_chip lapic_chip __read_mostly = {
2097         .name           = "local-APIC-edge",
2098         .mask           = mask_lapic_irq,
2099         .unmask         = unmask_lapic_irq,
2100         .eoi            = ack_apic,
2101 };
2102
2103 static void setup_nmi (void)
2104 {
2105         /*
2106          * Dirty trick to enable the NMI watchdog ...
2107          * We put the 8259A master into AEOI mode and
2108          * unmask on all local APICs LVT0 as NMI.
2109          *
2110          * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
2111          * is from Maciej W. Rozycki - so we do not have to EOI from
2112          * the NMI handler or the timer interrupt.
2113          */ 
2114         apic_printk(APIC_VERBOSE, KERN_INFO "activating NMI Watchdog ...");
2115
2116         on_each_cpu(enable_NMI_through_LVT0, NULL, 1, 1);
2117
2118         apic_printk(APIC_VERBOSE, " done.\n");
2119 }
2120
2121 /*
2122  * This looks a bit hackish but it's about the only one way of sending
2123  * a few INTA cycles to 8259As and any associated glue logic.  ICR does
2124  * not support the ExtINT mode, unfortunately.  We need to send these
2125  * cycles as some i82489DX-based boards have glue logic that keeps the
2126  * 8259A interrupt line asserted until INTA.  --macro
2127  */
2128 static inline void unlock_ExtINT_logic(void)
2129 {
2130         int apic, pin, i;
2131         struct IO_APIC_route_entry entry0, entry1;
2132         unsigned char save_control, save_freq_select;
2133
2134         pin  = find_isa_irq_pin(8, mp_INT);
2135         if (pin == -1) {
2136                 WARN_ON_ONCE(1);
2137                 return;
2138         }
2139         apic = find_isa_irq_apic(8, mp_INT);
2140         if (apic == -1) {
2141                 WARN_ON_ONCE(1);
2142                 return;
2143         }
2144
2145         entry0 = ioapic_read_entry(apic, pin);
2146         clear_IO_APIC_pin(apic, pin);
2147
2148         memset(&entry1, 0, sizeof(entry1));
2149
2150         entry1.dest_mode = 0;                   /* physical delivery */
2151         entry1.mask = 0;                        /* unmask IRQ now */
2152         entry1.dest.physical.physical_dest = hard_smp_processor_id();
2153         entry1.delivery_mode = dest_ExtINT;
2154         entry1.polarity = entry0.polarity;
2155         entry1.trigger = 0;
2156         entry1.vector = 0;
2157
2158         ioapic_write_entry(apic, pin, entry1);
2159
2160         save_control = CMOS_READ(RTC_CONTROL);
2161         save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
2162         CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
2163                    RTC_FREQ_SELECT);
2164         CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
2165
2166         i = 100;
2167         while (i-- > 0) {
2168                 mdelay(10);
2169                 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
2170                         i -= 10;
2171         }
2172
2173         CMOS_WRITE(save_control, RTC_CONTROL);
2174         CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
2175         clear_IO_APIC_pin(apic, pin);
2176
2177         ioapic_write_entry(apic, pin, entry0);
2178 }
2179
2180 int timer_uses_ioapic_pin_0;
2181
2182 /*
2183  * This code may look a bit paranoid, but it's supposed to cooperate with
2184  * a wide range of boards and BIOS bugs.  Fortunately only the timer IRQ
2185  * is so screwy.  Thanks to Brian Perkins for testing/hacking this beast
2186  * fanatically on his truly buggy board.
2187  */
2188 static inline void __init check_timer(void)
2189 {
2190         int apic1, pin1, apic2, pin2;
2191         int vector;
2192
2193         /*
2194          * get/set the timer IRQ vector:
2195          */
2196         disable_8259A_irq(0);
2197         vector = assign_irq_vector(0);
2198         set_intr_gate(vector, interrupt[0]);
2199
2200         /*
2201          * Subtle, code in do_timer_interrupt() expects an AEOI
2202          * mode for the 8259A whenever interrupts are routed
2203          * through I/O APICs.  Also IRQ0 has to be enabled in
2204          * the 8259A which implies the virtual wire has to be
2205          * disabled in the local APIC.
2206          */
2207         apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
2208         init_8259A(1);
2209         timer_ack = 1;
2210         if (timer_over_8254 > 0)
2211                 enable_8259A_irq(0);
2212
2213         pin1  = find_isa_irq_pin(0, mp_INT);
2214         apic1 = find_isa_irq_apic(0, mp_INT);
2215         pin2  = ioapic_i8259.pin;
2216         apic2 = ioapic_i8259.apic;
2217
2218         if (pin1 == 0)
2219                 timer_uses_ioapic_pin_0 = 1;
2220
2221         printk(KERN_INFO "..TIMER: vector=0x%02X apic1=%d pin1=%d apic2=%d pin2=%d\n",
2222                 vector, apic1, pin1, apic2, pin2);
2223
2224         if (pin1 != -1) {
2225                 /*
2226                  * Ok, does IRQ0 through the IOAPIC work?
2227                  */
2228                 unmask_IO_APIC_irq(0);
2229                 if (timer_irq_works()) {
2230                         if (nmi_watchdog == NMI_IO_APIC) {
2231                                 disable_8259A_irq(0);
2232                                 setup_nmi();
2233                                 enable_8259A_irq(0);
2234                         }
2235                         if (disable_timer_pin_1 > 0)
2236                                 clear_IO_APIC_pin(0, pin1);
2237                         return;
2238                 }
2239                 clear_IO_APIC_pin(apic1, pin1);
2240                 printk(KERN_ERR "..MP-BIOS bug: 8254 timer not connected to "
2241                                 "IO-APIC\n");
2242         }
2243
2244         printk(KERN_INFO "...trying to set up timer (IRQ0) through the 8259A ... ");
2245         if (pin2 != -1) {
2246                 printk("\n..... (found pin %d) ...", pin2);
2247                 /*
2248                  * legacy devices should be connected to IO APIC #0
2249                  */
2250                 setup_ExtINT_IRQ0_pin(apic2, pin2, vector);
2251                 if (timer_irq_works()) {
2252                         printk("works.\n");
2253                         if (pin1 != -1)
2254                                 replace_pin_at_irq(0, apic1, pin1, apic2, pin2);
2255                         else
2256                                 add_pin_to_irq(0, apic2, pin2);
2257                         if (nmi_watchdog == NMI_IO_APIC) {
2258                                 setup_nmi();
2259                         }
2260                         return;
2261                 }
2262                 /*
2263                  * Cleanup, just in case ...
2264                  */
2265                 clear_IO_APIC_pin(apic2, pin2);
2266         }
2267         printk(" failed.\n");
2268
2269         if (nmi_watchdog == NMI_IO_APIC) {
2270                 printk(KERN_WARNING "timer doesn't work through the IO-APIC - disabling NMI Watchdog!\n");
2271                 nmi_watchdog = 0;
2272         }
2273
2274         printk(KERN_INFO "...trying to set up timer as Virtual Wire IRQ...");
2275
2276         disable_8259A_irq(0);
2277         set_irq_chip_and_handler_name(0, &lapic_chip, handle_fasteoi_irq,
2278                                       "fasteoi");
2279         apic_write_around(APIC_LVT0, APIC_DM_FIXED | vector);   /* Fixed mode */
2280         enable_8259A_irq(0);
2281
2282         if (timer_irq_works()) {
2283                 printk(" works.\n");
2284                 return;
2285         }
2286         apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | vector);
2287         printk(" failed.\n");
2288
2289         printk(KERN_INFO "...trying to set up timer as ExtINT IRQ...");
2290
2291         timer_ack = 0;
2292         init_8259A(0);
2293         make_8259A_irq(0);
2294         apic_write_around(APIC_LVT0, APIC_DM_EXTINT);
2295
2296         unlock_ExtINT_logic();
2297
2298         if (timer_irq_works()) {
2299                 printk(" works.\n");
2300                 return;
2301         }
2302         printk(" failed :(.\n");
2303         panic("IO-APIC + timer doesn't work!  Boot with apic=debug and send a "
2304                 "report.  Then try booting with the 'noapic' option");
2305 }
2306
2307 /*
2308  *
2309  * IRQ's that are handled by the PIC in the MPS IOAPIC case.
2310  * - IRQ2 is the cascade IRQ, and cannot be a io-apic IRQ.
2311  *   Linux doesn't really care, as it's not actually used
2312  *   for any interrupt handling anyway.
2313  */
2314 #define PIC_IRQS        (1 << PIC_CASCADE_IR)
2315
2316 void __init setup_IO_APIC(void)
2317 {
2318         enable_IO_APIC();
2319
2320         if (acpi_ioapic)
2321                 io_apic_irqs = ~0;      /* all IRQs go through IOAPIC */
2322         else
2323                 io_apic_irqs = ~PIC_IRQS;
2324
2325         printk("ENABLING IO-APIC IRQs\n");
2326
2327         /*
2328          * Set up IO-APIC IRQ routing.
2329          */
2330         if (!acpi_ioapic)
2331                 setup_ioapic_ids_from_mpc();
2332         sync_Arb_IDs();
2333         setup_IO_APIC_irqs();
2334         init_IO_APIC_traps();
2335         check_timer();
2336         if (!acpi_ioapic)
2337                 print_IO_APIC();
2338 }
2339
2340 static int __init setup_disable_8254_timer(char *s)
2341 {
2342         timer_over_8254 = -1;
2343         return 1;
2344 }
2345 static int __init setup_enable_8254_timer(char *s)
2346 {
2347         timer_over_8254 = 2;
2348         return 1;
2349 }
2350
2351 __setup("disable_8254_timer", setup_disable_8254_timer);
2352 __setup("enable_8254_timer", setup_enable_8254_timer);
2353
2354 /*
2355  *      Called after all the initialization is done. If we didnt find any
2356  *      APIC bugs then we can allow the modify fast path
2357  */
2358  
2359 static int __init io_apic_bug_finalize(void)
2360 {
2361         if(sis_apic_bug == -1)
2362                 sis_apic_bug = 0;
2363         return 0;
2364 }
2365
2366 late_initcall(io_apic_bug_finalize);
2367
2368 struct sysfs_ioapic_data {
2369         struct sys_device dev;
2370         struct IO_APIC_route_entry entry[0];
2371 };
2372 static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS];
2373
2374 static int ioapic_suspend(struct sys_device *dev, pm_message_t state)
2375 {
2376         struct IO_APIC_route_entry *entry;
2377         struct sysfs_ioapic_data *data;
2378         int i;
2379         
2380         data = container_of(dev, struct sysfs_ioapic_data, dev);
2381         entry = data->entry;
2382         for (i = 0; i < nr_ioapic_registers[dev->id]; i ++)
2383                 entry[i] = ioapic_read_entry(dev->id, i);
2384
2385         return 0;
2386 }
2387
2388 static int ioapic_resume(struct sys_device *dev)
2389 {
2390         struct IO_APIC_route_entry *entry;
2391         struct sysfs_ioapic_data *data;
2392         unsigned long flags;
2393         union IO_APIC_reg_00 reg_00;
2394         int i;
2395         
2396         data = container_of(dev, struct sysfs_ioapic_data, dev);
2397         entry = data->entry;
2398
2399         spin_lock_irqsave(&ioapic_lock, flags);
2400         reg_00.raw = io_apic_read(dev->id, 0);
2401         if (reg_00.bits.ID != mp_ioapics[dev->id].mpc_apicid) {
2402                 reg_00.bits.ID = mp_ioapics[dev->id].mpc_apicid;
2403                 io_apic_write(dev->id, 0, reg_00.raw);
2404         }
2405         spin_unlock_irqrestore(&ioapic_lock, flags);
2406         for (i = 0; i < nr_ioapic_registers[dev->id]; i ++)
2407                 ioapic_write_entry(dev->id, i, entry[i]);
2408
2409         return 0;
2410 }
2411
2412 static struct sysdev_class ioapic_sysdev_class = {
2413         set_kset_name("ioapic"),
2414         .suspend = ioapic_suspend,
2415         .resume = ioapic_resume,
2416 };
2417
2418 static int __init ioapic_init_sysfs(void)
2419 {
2420         struct sys_device * dev;
2421         int i, size, error = 0;
2422
2423         error = sysdev_class_register(&ioapic_sysdev_class);
2424         if (error)
2425                 return error;
2426
2427         for (i = 0; i < nr_ioapics; i++ ) {
2428                 size = sizeof(struct sys_device) + nr_ioapic_registers[i] 
2429                         * sizeof(struct IO_APIC_route_entry);
2430                 mp_ioapic_data[i] = kmalloc(size, GFP_KERNEL);
2431                 if (!mp_ioapic_data[i]) {
2432                         printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
2433                         continue;
2434                 }
2435                 memset(mp_ioapic_data[i], 0, size);
2436                 dev = &mp_ioapic_data[i]->dev;
2437                 dev->id = i; 
2438                 dev->cls = &ioapic_sysdev_class;
2439                 error = sysdev_register(dev);
2440                 if (error) {
2441                         kfree(mp_ioapic_data[i]);
2442                         mp_ioapic_data[i] = NULL;
2443                         printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
2444                         continue;
2445                 }
2446         }
2447
2448         return 0;
2449 }
2450
2451 device_initcall(ioapic_init_sysfs);
2452
2453 /*
2454  * Dynamic irq allocate and deallocation
2455  */
2456 int create_irq(void)
2457 {
2458         /* Allocate an unused irq */
2459         int irq, new, vector = 0;
2460         unsigned long flags;
2461
2462         irq = -ENOSPC;
2463         spin_lock_irqsave(&vector_lock, flags);
2464         for (new = (NR_IRQS - 1); new >= 0; new--) {
2465                 if (platform_legacy_irq(new))
2466                         continue;
2467                 if (irq_vector[new] != 0)
2468                         continue;
2469                 vector = __assign_irq_vector(new);
2470                 if (likely(vector > 0))
2471                         irq = new;
2472                 break;
2473         }
2474         spin_unlock_irqrestore(&vector_lock, flags);
2475
2476         if (irq >= 0) {
2477                 set_intr_gate(vector, interrupt[irq]);
2478                 dynamic_irq_init(irq);
2479         }
2480         return irq;
2481 }
2482
2483 void destroy_irq(unsigned int irq)
2484 {
2485         unsigned long flags;
2486
2487         dynamic_irq_cleanup(irq);
2488
2489         spin_lock_irqsave(&vector_lock, flags);
2490         irq_vector[irq] = 0;
2491         spin_unlock_irqrestore(&vector_lock, flags);
2492 }
2493
2494 /*
2495  * MSI mesage composition
2496  */
2497 #ifdef CONFIG_PCI_MSI
2498 static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, struct msi_msg *msg)
2499 {
2500         int vector;
2501         unsigned dest;
2502
2503         vector = assign_irq_vector(irq);
2504         if (vector >= 0) {
2505                 dest = cpu_mask_to_apicid(TARGET_CPUS);
2506
2507                 msg->address_hi = MSI_ADDR_BASE_HI;
2508                 msg->address_lo =
2509                         MSI_ADDR_BASE_LO |
2510                         ((INT_DEST_MODE == 0) ?
2511                                 MSI_ADDR_DEST_MODE_PHYSICAL:
2512                                 MSI_ADDR_DEST_MODE_LOGICAL) |
2513                         ((INT_DELIVERY_MODE != dest_LowestPrio) ?
2514                                 MSI_ADDR_REDIRECTION_CPU:
2515                                 MSI_ADDR_REDIRECTION_LOWPRI) |
2516                         MSI_ADDR_DEST_ID(dest);
2517
2518                 msg->data =
2519                         MSI_DATA_TRIGGER_EDGE |
2520                         MSI_DATA_LEVEL_ASSERT |
2521                         ((INT_DELIVERY_MODE != dest_LowestPrio) ?
2522                                 MSI_DATA_DELIVERY_FIXED:
2523                                 MSI_DATA_DELIVERY_LOWPRI) |
2524                         MSI_DATA_VECTOR(vector);
2525         }
2526         return vector;
2527 }
2528
2529 #ifdef CONFIG_SMP
2530 static void set_msi_irq_affinity(unsigned int irq, cpumask_t mask)
2531 {
2532         struct msi_msg msg;
2533         unsigned int dest;
2534         cpumask_t tmp;
2535         int vector;
2536
2537         cpus_and(tmp, mask, cpu_online_map);
2538         if (cpus_empty(tmp))
2539                 tmp = TARGET_CPUS;
2540
2541         vector = assign_irq_vector(irq);
2542         if (vector < 0)
2543                 return;
2544
2545         dest = cpu_mask_to_apicid(mask);
2546
2547         read_msi_msg(irq, &msg);
2548
2549         msg.data &= ~MSI_DATA_VECTOR_MASK;
2550         msg.data |= MSI_DATA_VECTOR(vector);
2551         msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
2552         msg.address_lo |= MSI_ADDR_DEST_ID(dest);
2553
2554         write_msi_msg(irq, &msg);
2555         irq_desc[irq].affinity = mask;
2556 }
2557 #endif /* CONFIG_SMP */
2558
2559 /*
2560  * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
2561  * which implement the MSI or MSI-X Capability Structure.
2562  */
2563 static struct irq_chip msi_chip = {
2564         .name           = "PCI-MSI",
2565         .unmask         = unmask_msi_irq,
2566         .mask           = mask_msi_irq,
2567         .ack            = ack_ioapic_irq,
2568 #ifdef CONFIG_SMP
2569         .set_affinity   = set_msi_irq_affinity,
2570 #endif
2571         .retrigger      = ioapic_retrigger_irq,
2572 };
2573
2574 int arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc)
2575 {
2576         struct msi_msg msg;
2577         int irq, ret;
2578         irq = create_irq();
2579         if (irq < 0)
2580                 return irq;
2581
2582         ret = msi_compose_msg(dev, irq, &msg);
2583         if (ret < 0) {
2584                 destroy_irq(irq);
2585                 return ret;
2586         }
2587
2588         set_irq_msi(irq, desc);
2589         write_msi_msg(irq, &msg);
2590
2591         set_irq_chip_and_handler_name(irq, &msi_chip, handle_edge_irq,
2592                                       "edge");
2593
2594         return 0;
2595 }
2596
2597 void arch_teardown_msi_irq(unsigned int irq)
2598 {
2599         destroy_irq(irq);
2600 }
2601
2602 #endif /* CONFIG_PCI_MSI */
2603
2604 /*
2605  * Hypertransport interrupt support
2606  */
2607 #ifdef CONFIG_HT_IRQ
2608
2609 #ifdef CONFIG_SMP
2610
2611 static void target_ht_irq(unsigned int irq, unsigned int dest)
2612 {
2613         struct ht_irq_msg msg;
2614         fetch_ht_irq_msg(irq, &msg);
2615
2616         msg.address_lo &= ~(HT_IRQ_LOW_DEST_ID_MASK);
2617         msg.address_hi &= ~(HT_IRQ_HIGH_DEST_ID_MASK);
2618
2619         msg.address_lo |= HT_IRQ_LOW_DEST_ID(dest);
2620         msg.address_hi |= HT_IRQ_HIGH_DEST_ID(dest);
2621
2622         write_ht_irq_msg(irq, &msg);
2623 }
2624
2625 static void set_ht_irq_affinity(unsigned int irq, cpumask_t mask)
2626 {
2627         unsigned int dest;
2628         cpumask_t tmp;
2629
2630         cpus_and(tmp, mask, cpu_online_map);
2631         if (cpus_empty(tmp))
2632                 tmp = TARGET_CPUS;
2633
2634         cpus_and(mask, tmp, CPU_MASK_ALL);
2635
2636         dest = cpu_mask_to_apicid(mask);
2637
2638         target_ht_irq(irq, dest);
2639         irq_desc[irq].affinity = mask;
2640 }
2641 #endif
2642
2643 static struct irq_chip ht_irq_chip = {
2644         .name           = "PCI-HT",
2645         .mask           = mask_ht_irq,
2646         .unmask         = unmask_ht_irq,
2647         .ack            = ack_ioapic_irq,
2648 #ifdef CONFIG_SMP
2649         .set_affinity   = set_ht_irq_affinity,
2650 #endif
2651         .retrigger      = ioapic_retrigger_irq,
2652 };
2653
2654 int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev)
2655 {
2656         int vector;
2657
2658         vector = assign_irq_vector(irq);
2659         if (vector >= 0) {
2660                 struct ht_irq_msg msg;
2661                 unsigned dest;
2662                 cpumask_t tmp;
2663
2664                 cpus_clear(tmp);
2665                 cpu_set(vector >> 8, tmp);
2666                 dest = cpu_mask_to_apicid(tmp);
2667
2668                 msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest);
2669
2670                 msg.address_lo =
2671                         HT_IRQ_LOW_BASE |
2672                         HT_IRQ_LOW_DEST_ID(dest) |
2673                         HT_IRQ_LOW_VECTOR(vector) |
2674                         ((INT_DEST_MODE == 0) ?
2675                                 HT_IRQ_LOW_DM_PHYSICAL :
2676                                 HT_IRQ_LOW_DM_LOGICAL) |
2677                         HT_IRQ_LOW_RQEOI_EDGE |
2678                         ((INT_DELIVERY_MODE != dest_LowestPrio) ?
2679                                 HT_IRQ_LOW_MT_FIXED :
2680                                 HT_IRQ_LOW_MT_ARBITRATED) |
2681                         HT_IRQ_LOW_IRQ_MASKED;
2682
2683                 write_ht_irq_msg(irq, &msg);
2684
2685                 set_irq_chip_and_handler_name(irq, &ht_irq_chip,
2686                                               handle_edge_irq, "edge");
2687         }
2688         return vector;
2689 }
2690 #endif /* CONFIG_HT_IRQ */
2691
2692 /* --------------------------------------------------------------------------
2693                           ACPI-based IOAPIC Configuration
2694    -------------------------------------------------------------------------- */
2695
2696 #ifdef CONFIG_ACPI
2697
2698 int __init io_apic_get_unique_id (int ioapic, int apic_id)
2699 {
2700         union IO_APIC_reg_00 reg_00;
2701         static physid_mask_t apic_id_map = PHYSID_MASK_NONE;
2702         physid_mask_t tmp;
2703         unsigned long flags;
2704         int i = 0;
2705
2706         /*
2707          * The P4 platform supports up to 256 APIC IDs on two separate APIC 
2708          * buses (one for LAPICs, one for IOAPICs), where predecessors only 
2709          * supports up to 16 on one shared APIC bus.
2710          * 
2711          * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
2712          *      advantage of new APIC bus architecture.
2713          */
2714
2715         if (physids_empty(apic_id_map))
2716                 apic_id_map = ioapic_phys_id_map(phys_cpu_present_map);
2717
2718         spin_lock_irqsave(&ioapic_lock, flags);
2719         reg_00.raw = io_apic_read(ioapic, 0);
2720         spin_unlock_irqrestore(&ioapic_lock, flags);
2721
2722         if (apic_id >= get_physical_broadcast()) {
2723                 printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying "
2724                         "%d\n", ioapic, apic_id, reg_00.bits.ID);
2725                 apic_id = reg_00.bits.ID;
2726         }
2727
2728         /*
2729          * Every APIC in a system must have a unique ID or we get lots of nice 
2730          * 'stuck on smp_invalidate_needed IPI wait' messages.
2731          */
2732         if (check_apicid_used(apic_id_map, apic_id)) {
2733
2734                 for (i = 0; i < get_physical_broadcast(); i++) {
2735                         if (!check_apicid_used(apic_id_map, i))
2736                                 break;
2737                 }
2738
2739                 if (i == get_physical_broadcast())
2740                         panic("Max apic_id exceeded!\n");
2741
2742                 printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, "
2743                         "trying %d\n", ioapic, apic_id, i);
2744
2745                 apic_id = i;
2746         } 
2747
2748         tmp = apicid_to_cpu_present(apic_id);
2749         physids_or(apic_id_map, apic_id_map, tmp);
2750
2751         if (reg_00.bits.ID != apic_id) {
2752                 reg_00.bits.ID = apic_id;
2753
2754                 spin_lock_irqsave(&ioapic_lock, flags);
2755                 io_apic_write(ioapic, 0, reg_00.raw);
2756                 reg_00.raw = io_apic_read(ioapic, 0);
2757                 spin_unlock_irqrestore(&ioapic_lock, flags);
2758
2759                 /* Sanity check */
2760                 if (reg_00.bits.ID != apic_id) {
2761                         printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic);
2762                         return -1;
2763                 }
2764         }
2765
2766         apic_printk(APIC_VERBOSE, KERN_INFO
2767                         "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id);
2768
2769         return apic_id;
2770 }
2771
2772
2773 int __init io_apic_get_version (int ioapic)
2774 {
2775         union IO_APIC_reg_01    reg_01;
2776         unsigned long flags;
2777
2778         spin_lock_irqsave(&ioapic_lock, flags);
2779         reg_01.raw = io_apic_read(ioapic, 1);
2780         spin_unlock_irqrestore(&ioapic_lock, flags);
2781
2782         return reg_01.bits.version;
2783 }
2784
2785
2786 int __init io_apic_get_redir_entries (int ioapic)
2787 {
2788         union IO_APIC_reg_01    reg_01;
2789         unsigned long flags;
2790
2791         spin_lock_irqsave(&ioapic_lock, flags);
2792         reg_01.raw = io_apic_read(ioapic, 1);
2793         spin_unlock_irqrestore(&ioapic_lock, flags);
2794
2795         return reg_01.bits.entries;
2796 }
2797
2798
2799 int io_apic_set_pci_routing (int ioapic, int pin, int irq, int edge_level, int active_high_low)
2800 {
2801         struct IO_APIC_route_entry entry;
2802         unsigned long flags;
2803
2804         if (!IO_APIC_IRQ(irq)) {
2805                 printk(KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
2806                         ioapic);
2807                 return -EINVAL;
2808         }
2809
2810         /*
2811          * Generate a PCI IRQ routing entry and program the IOAPIC accordingly.
2812          * Note that we mask (disable) IRQs now -- these get enabled when the
2813          * corresponding device driver registers for this IRQ.
2814          */
2815
2816         memset(&entry,0,sizeof(entry));
2817
2818         entry.delivery_mode = INT_DELIVERY_MODE;
2819         entry.dest_mode = INT_DEST_MODE;
2820         entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
2821         entry.trigger = edge_level;
2822         entry.polarity = active_high_low;
2823         entry.mask  = 1;
2824
2825         /*
2826          * IRQs < 16 are already in the irq_2_pin[] map
2827          */
2828         if (irq >= 16)
2829                 add_pin_to_irq(irq, ioapic, pin);
2830
2831         entry.vector = assign_irq_vector(irq);
2832
2833         apic_printk(APIC_DEBUG, KERN_DEBUG "IOAPIC[%d]: Set PCI routing entry "
2834                 "(%d-%d -> 0x%x -> IRQ %d Mode:%i Active:%i)\n", ioapic,
2835                 mp_ioapics[ioapic].mpc_apicid, pin, entry.vector, irq,
2836                 edge_level, active_high_low);
2837
2838         ioapic_register_intr(irq, entry.vector, edge_level);
2839
2840         if (!ioapic && (irq < 16))
2841                 disable_8259A_irq(irq);
2842
2843         spin_lock_irqsave(&ioapic_lock, flags);
2844         __ioapic_write_entry(ioapic, pin, entry);
2845         spin_unlock_irqrestore(&ioapic_lock, flags);
2846
2847         return 0;
2848 }
2849
2850 #endif /* CONFIG_ACPI */
2851
2852 static int __init parse_disable_timer_pin_1(char *arg)
2853 {
2854         disable_timer_pin_1 = 1;
2855         return 0;
2856 }
2857 early_param("disable_timer_pin_1", parse_disable_timer_pin_1);
2858
2859 static int __init parse_enable_timer_pin_1(char *arg)
2860 {
2861         disable_timer_pin_1 = -1;
2862         return 0;
2863 }
2864 early_param("enable_timer_pin_1", parse_enable_timer_pin_1);
2865
2866 static int __init parse_noapic(char *arg)
2867 {
2868         /* disable IO-APIC */
2869         disable_ioapic_setup();
2870         return 0;
2871 }
2872 early_param("noapic", parse_noapic);