include cleanup: Update gfp.h and slab.h includes to prepare for breaking implicit...
[linux-3.10.git] / arch / frv / kernel / irq.c
1 /* irq.c: FRV IRQ handling
2  *
3  * Copyright (C) 2003, 2004, 2006 Red Hat, Inc. All Rights Reserved.
4  * Written by David Howells (dhowells@redhat.com)
5  *
6  * This program is free software; you can redistribute it and/or
7  * modify it under the terms of the GNU General Public License
8  * as published by the Free Software Foundation; either version
9  * 2 of the License, or (at your option) any later version.
10  */
11
12 #include <linux/ptrace.h>
13 #include <linux/errno.h>
14 #include <linux/signal.h>
15 #include <linux/sched.h>
16 #include <linux/ioport.h>
17 #include <linux/interrupt.h>
18 #include <linux/timex.h>
19 #include <linux/random.h>
20 #include <linux/init.h>
21 #include <linux/kernel_stat.h>
22 #include <linux/irq.h>
23 #include <linux/proc_fs.h>
24 #include <linux/seq_file.h>
25 #include <linux/module.h>
26 #include <linux/bitops.h>
27
28 #include <asm/atomic.h>
29 #include <asm/io.h>
30 #include <asm/smp.h>
31 #include <asm/system.h>
32 #include <asm/uaccess.h>
33 #include <asm/pgalloc.h>
34 #include <asm/delay.h>
35 #include <asm/irq.h>
36 #include <asm/irc-regs.h>
37 #include <asm/gdb-stub.h>
38
39 #define set_IRR(N,A,B,C,D) __set_IRR(N, (A << 28) | (B << 24) | (C << 20) | (D << 16))
40
41 extern void __init fpga_init(void);
42 #ifdef CONFIG_FUJITSU_MB93493
43 extern void __init mb93493_init(void);
44 #endif
45
46 #define __reg16(ADDR) (*(volatile unsigned short *)(ADDR))
47
48 atomic_t irq_err_count;
49
50 /*
51  * Generic, controller-independent functions:
52  */
53 int show_interrupts(struct seq_file *p, void *v)
54 {
55         int i = *(loff_t *) v, cpu;
56         struct irqaction * action;
57         unsigned long flags;
58
59         if (i == 0) {
60                 char cpuname[12];
61
62                 seq_printf(p, "    ");
63                 for_each_present_cpu(cpu) {
64                         sprintf(cpuname, "CPU%d", cpu);
65                         seq_printf(p, " %10s", cpuname);
66                 }
67                 seq_putc(p, '\n');
68         }
69
70         if (i < NR_IRQS) {
71                 raw_spin_lock_irqsave(&irq_desc[i].lock, flags);
72                 action = irq_desc[i].action;
73                 if (action) {
74                         seq_printf(p, "%3d: ", i);
75                         for_each_present_cpu(cpu)
76                                 seq_printf(p, "%10u ", kstat_irqs_cpu(i, cpu));
77                         seq_printf(p, " %10s", irq_desc[i].chip->name ? : "-");
78                         seq_printf(p, "  %s", action->name);
79                         for (action = action->next;
80                              action;
81                              action = action->next)
82                                 seq_printf(p, ", %s", action->name);
83
84                         seq_putc(p, '\n');
85                 }
86
87                 raw_spin_unlock_irqrestore(&irq_desc[i].lock, flags);
88         } else if (i == NR_IRQS) {
89                 seq_printf(p, "Err: %10u\n", atomic_read(&irq_err_count));
90         }
91
92         return 0;
93 }
94
95 /*
96  * on-CPU PIC operations
97  */
98 static void frv_cpupic_ack(unsigned int irqlevel)
99 {
100         __clr_RC(irqlevel);
101         __clr_IRL();
102 }
103
104 static void frv_cpupic_mask(unsigned int irqlevel)
105 {
106         __set_MASK(irqlevel);
107 }
108
109 static void frv_cpupic_mask_ack(unsigned int irqlevel)
110 {
111         __set_MASK(irqlevel);
112         __clr_RC(irqlevel);
113         __clr_IRL();
114 }
115
116 static void frv_cpupic_unmask(unsigned int irqlevel)
117 {
118         __clr_MASK(irqlevel);
119 }
120
121 static void frv_cpupic_end(unsigned int irqlevel)
122 {
123         __clr_MASK(irqlevel);
124 }
125
126 static struct irq_chip frv_cpu_pic = {
127         .name           = "cpu",
128         .ack            = frv_cpupic_ack,
129         .mask           = frv_cpupic_mask,
130         .mask_ack       = frv_cpupic_mask_ack,
131         .unmask         = frv_cpupic_unmask,
132         .end            = frv_cpupic_end,
133 };
134
135 /*
136  * handles all normal device IRQs
137  * - registers are referred to by the __frame variable (GR28)
138  * - IRQ distribution is complicated in this arch because of the many PICs, the
139  *   way they work and the way they cascade
140  */
141 asmlinkage void do_IRQ(void)
142 {
143         irq_enter();
144         generic_handle_irq(__get_IRL());
145         irq_exit();
146 }
147
148 /*
149  * handles all NMIs when not co-opted by the debugger
150  * - registers are referred to by the __frame variable (GR28)
151  */
152 asmlinkage void do_NMI(void)
153 {
154 }
155
156 /*
157  * initialise the interrupt system
158  */
159 void __init init_IRQ(void)
160 {
161         int level;
162
163         for (level = 1; level <= 14; level++)
164                 set_irq_chip_and_handler(level, &frv_cpu_pic,
165                                          handle_level_irq);
166
167         set_irq_handler(IRQ_CPU_TIMER0, handle_edge_irq);
168
169         /* set the trigger levels for internal interrupt sources
170          * - timers all falling-edge
171          * - ERR0 is rising-edge
172          * - all others are high-level
173          */
174         __set_IITMR(0, 0x003f0000);     /* DMA0-3, TIMER0-2 */
175         __set_IITMR(1, 0x20000000);     /* ERR0-1, UART0-1, DMA4-7 */
176
177         /* route internal interrupts */
178         set_IRR(4, IRQ_DMA3_LEVEL, IRQ_DMA2_LEVEL, IRQ_DMA1_LEVEL,
179                 IRQ_DMA0_LEVEL);
180         set_IRR(5, 0, IRQ_TIMER2_LEVEL, IRQ_TIMER1_LEVEL, IRQ_TIMER0_LEVEL);
181         set_IRR(6, IRQ_GDBSTUB_LEVEL, IRQ_GDBSTUB_LEVEL,
182                 IRQ_UART1_LEVEL, IRQ_UART0_LEVEL);
183         set_IRR(7, IRQ_DMA7_LEVEL, IRQ_DMA6_LEVEL, IRQ_DMA5_LEVEL,
184                 IRQ_DMA4_LEVEL);
185
186         /* route external interrupts */
187         set_IRR(2, IRQ_XIRQ7_LEVEL, IRQ_XIRQ6_LEVEL, IRQ_XIRQ5_LEVEL,
188                 IRQ_XIRQ4_LEVEL);
189         set_IRR(3, IRQ_XIRQ3_LEVEL, IRQ_XIRQ2_LEVEL, IRQ_XIRQ1_LEVEL,
190                 IRQ_XIRQ0_LEVEL);
191
192 #if defined(CONFIG_MB93091_VDK)
193         __set_TM1(0x55550000);          /* XIRQ7-0 all active low */
194 #elif defined(CONFIG_MB93093_PDK)
195         __set_TM1(0x15550000);          /* XIRQ7 active high, 6-0 all active low */
196 #else
197 #error dont know external IRQ trigger levels for this setup
198 #endif
199
200         fpga_init();
201 #ifdef CONFIG_FUJITSU_MB93493
202         mb93493_init();
203 #endif
204 }