ARM: tegra12: set CPU rate to 2.2GHz for sku 0x87
[linux-3.10.git] / arch / frv / kernel / head-uc-fr401.S
1 /* head-uc-fr401.S: FR401/3/5 uc-linux specific bits of initialisation
2  *
3  * Copyright (C) 2004 Red Hat, Inc. All Rights Reserved.
4  * Written by David Howells (dhowells@redhat.com)
5  *
6  * This program is free software; you can redistribute it and/or
7  * modify it under the terms of the GNU General Public License
8  * as published by the Free Software Foundation; either version
9  * 2 of the License, or (at your option) any later version.
10  */
11
12 #include <linux/init.h>
13 #include <linux/threads.h>
14 #include <linux/linkage.h>
15 #include <asm/ptrace.h>
16 #include <asm/page.h>
17 #include <asm/spr-regs.h>
18 #include <asm/mb86943a.h>
19 #include "head.inc"
20
21
22 #define __400_DBR0      0xfe000e00
23 #define __400_DBR1      0xfe000e08
24 #define __400_DBR2      0xfe000e10      /* not on FR401 */
25 #define __400_DBR3      0xfe000e18      /* not on FR401 */
26 #define __400_DAM0      0xfe000f00
27 #define __400_DAM1      0xfe000f08
28 #define __400_DAM2      0xfe000f10      /* not on FR401 */
29 #define __400_DAM3      0xfe000f18      /* not on FR401 */
30 #define __400_LGCR      0xfe000010
31 #define __400_LCR       0xfe000100
32 #define __400_LSBR      0xfe000c00
33
34         __INIT
35         .balign         4
36
37 ###############################################################################
38 #
39 # describe the position and layout of the SDRAM controller registers
40 #
41 #       ENTRY:                  EXIT:
42 # GR5   -                       cacheline size
43 # GR11  -                       displacement of 2nd SDRAM addr reg from GR14
44 # GR12  -                       displacement of 3rd SDRAM addr reg from GR14
45 # GR13  -                       displacement of 4th SDRAM addr reg from GR14
46 # GR14  -                       address of 1st SDRAM addr reg
47 # GR15  -                       amount to shift address by to match SDRAM addr reg
48 # GR26  &__head_reference       [saved]
49 # GR30  LED address             [saved]
50 # CC0   -                       T if DBR0 is present
51 # CC1   -                       T if DBR1 is present
52 # CC2   -                       T if DBR2 is present (not FR401/FR401A)
53 # CC3   -                       T if DBR3 is present (not FR401/FR401A)
54 #
55 ###############################################################################
56         .globl          __head_fr401_describe_sdram
57 __head_fr401_describe_sdram:
58         sethi.p         %hi(__400_DBR0),gr14
59         setlo           %lo(__400_DBR0),gr14
60         setlos.p        #__400_DBR1-__400_DBR0,gr11
61         setlos          #__400_DBR2-__400_DBR0,gr12
62         setlos.p        #__400_DBR3-__400_DBR0,gr13
63         setlos          #32,gr5                 ; cacheline size
64         setlos.p        #0,gr15                 ; amount to shift addr reg by
65
66         # specify which DBR regs are present
67         setlos          #0x00ff,gr4
68         movgs           gr4,cccr
69         movsg           psr,gr3                 ; check for FR401/FR401A
70         srli            gr3,#25,gr3
71         subicc          gr3,#0x20>>1,gr0,icc0
72         bnelr           icc0,#1
73         setlos          #0x000f,gr4
74         movgs           gr4,cccr
75         bralr
76
77 ###############################################################################
78 #
79 # rearrange the bus controller registers
80 #
81 #       ENTRY:                  EXIT:
82 # GR26  &__head_reference       [saved]
83 # GR30  LED address             revised LED address
84 #
85 ###############################################################################
86         .globl          __head_fr401_set_busctl
87 __head_fr401_set_busctl:
88         sethi.p         %hi(__400_LGCR),gr4
89         setlo           %lo(__400_LGCR),gr4
90         sethi.p         %hi(__400_LSBR),gr10
91         setlo           %lo(__400_LSBR),gr10
92         sethi.p         %hi(__400_LCR),gr11
93         setlo           %lo(__400_LCR),gr11
94
95         # set the bus controller
96         ldi             @(gr4,#0),gr5
97         ori             gr5,#0xff,gr5           ; make sure all chip-selects are enabled
98         sti             gr5,@(gr4,#0)
99
100         sethi.p         %hi(__region_CS1),gr4
101         setlo           %lo(__region_CS1),gr4
102         sethi.p         %hi(__region_CS1_M),gr5
103         setlo           %lo(__region_CS1_M),gr5
104         sethi.p         %hi(__region_CS1_C),gr6
105         setlo           %lo(__region_CS1_C),gr6
106         sti             gr4,@(gr10,#1*0x08)
107         sti             gr5,@(gr10,#1*0x08+0x100)
108         sti             gr6,@(gr11,#1*0x08)
109         sethi.p         %hi(__region_CS2),gr4
110         setlo           %lo(__region_CS2),gr4
111         sethi.p         %hi(__region_CS2_M),gr5
112         setlo           %lo(__region_CS2_M),gr5
113         sethi.p         %hi(__region_CS2_C),gr6
114         setlo           %lo(__region_CS2_C),gr6
115         sti             gr4,@(gr10,#2*0x08)
116         sti             gr5,@(gr10,#2*0x08+0x100)
117         sti             gr6,@(gr11,#2*0x08)
118         sethi.p         %hi(__region_CS3),gr4
119         setlo           %lo(__region_CS3),gr4
120         sethi.p         %hi(__region_CS3_M),gr5
121         setlo           %lo(__region_CS3_M),gr5
122         sethi.p         %hi(__region_CS3_C),gr6
123         setlo           %lo(__region_CS3_C),gr6
124         sti             gr4,@(gr10,#3*0x08)
125         sti             gr5,@(gr10,#3*0x08+0x100)
126         sti             gr6,@(gr11,#3*0x08)
127         sethi.p         %hi(__region_CS4),gr4
128         setlo           %lo(__region_CS4),gr4
129         sethi.p         %hi(__region_CS4_M),gr5
130         setlo           %lo(__region_CS4_M),gr5
131         sethi.p         %hi(__region_CS4_C),gr6
132         setlo           %lo(__region_CS4_C),gr6
133         sti             gr4,@(gr10,#4*0x08)
134         sti             gr5,@(gr10,#4*0x08+0x100)
135         sti             gr6,@(gr11,#4*0x08)
136         sethi.p         %hi(__region_CS5),gr4
137         setlo           %lo(__region_CS5),gr4
138         sethi.p         %hi(__region_CS5_M),gr5
139         setlo           %lo(__region_CS5_M),gr5
140         sethi.p         %hi(__region_CS5_C),gr6
141         setlo           %lo(__region_CS5_C),gr6
142         sti             gr4,@(gr10,#5*0x08)
143         sti             gr5,@(gr10,#5*0x08+0x100)
144         sti             gr6,@(gr11,#5*0x08)
145         sethi.p         %hi(__region_CS6),gr4
146         setlo           %lo(__region_CS6),gr4
147         sethi.p         %hi(__region_CS6_M),gr5
148         setlo           %lo(__region_CS6_M),gr5
149         sethi.p         %hi(__region_CS6_C),gr6
150         setlo           %lo(__region_CS6_C),gr6
151         sti             gr4,@(gr10,#6*0x08)
152         sti             gr5,@(gr10,#6*0x08+0x100)
153         sti             gr6,@(gr11,#6*0x08)
154         sethi.p         %hi(__region_CS7),gr4
155         setlo           %lo(__region_CS7),gr4
156         sethi.p         %hi(__region_CS7_M),gr5
157         setlo           %lo(__region_CS7_M),gr5
158         sethi.p         %hi(__region_CS7_C),gr6
159         setlo           %lo(__region_CS7_C),gr6
160         sti             gr4,@(gr10,#7*0x08)
161         sti             gr5,@(gr10,#7*0x08+0x100)
162         sti             gr6,@(gr11,#7*0x08)
163         membar
164         bar
165
166         # adjust LED bank address
167         sethi.p         %hi(LED_ADDR - 0x20000000 +__region_CS2),gr30
168         setlo           %lo(LED_ADDR - 0x20000000 +__region_CS2),gr30
169         bralr
170
171 ###############################################################################
172 #
173 # determine the total SDRAM size
174 #
175 #       ENTRY:                  EXIT:
176 # GR25  -                       SDRAM size
177 # GR26  &__head_reference       [saved]
178 # GR30  LED address             [saved]
179 #
180 ###############################################################################
181         .globl          __head_fr401_survey_sdram
182 __head_fr401_survey_sdram:
183         sethi.p         %hi(__400_DAM0),gr11
184         setlo           %lo(__400_DAM0),gr11
185         sethi.p         %hi(__400_DBR0),gr12
186         setlo           %lo(__400_DBR0),gr12
187
188         sethi.p         %hi(0xfe000000),gr17            ; unused SDRAM DBR value
189         setlo           %lo(0xfe000000),gr17
190         setlos          #0,gr25
191
192         ldi             @(gr12,#0x00),gr4               ; DAR0
193         subcc           gr4,gr17,gr0,icc0
194         beq             icc0,#0,__head_no_DCS0
195         ldi             @(gr11,#0x00),gr6               ; DAM0: bits 31:20 match addr 31:20
196         add             gr25,gr6,gr25
197         addi            gr25,#1,gr25
198 __head_no_DCS0:
199
200         ldi             @(gr12,#0x08),gr4               ; DAR1
201         subcc           gr4,gr17,gr0,icc0
202         beq             icc0,#0,__head_no_DCS1
203         ldi             @(gr11,#0x08),gr6               ; DAM1: bits 31:20 match addr 31:20
204         add             gr25,gr6,gr25
205         addi            gr25,#1,gr25
206 __head_no_DCS1:
207
208         # FR401/FR401A does not have DCS2/3
209         movsg           psr,gr3
210         srli            gr3,#25,gr3
211         subicc          gr3,#0x20>>1,gr0,icc0
212         beq             icc0,#0,__head_no_DCS3
213
214         ldi             @(gr12,#0x10),gr4               ; DAR2
215         subcc           gr4,gr17,gr0,icc0
216         beq             icc0,#0,__head_no_DCS2
217         ldi             @(gr11,#0x10),gr6               ; DAM2: bits 31:20 match addr 31:20
218         add             gr25,gr6,gr25
219         addi            gr25,#1,gr25
220 __head_no_DCS2:
221
222         ldi             @(gr12,#0x18),gr4               ; DAR3
223         subcc           gr4,gr17,gr0,icc0
224         beq             icc0,#0,__head_no_DCS3
225         ldi             @(gr11,#0x18),gr6               ; DAM3: bits 31:20 match addr 31:20
226         add             gr25,gr6,gr25
227         addi            gr25,#1,gr25
228 __head_no_DCS3:
229         bralr
230
231 ###############################################################################
232 #
233 # set the protection map with the I/DAMPR registers
234 #
235 #       ENTRY:                  EXIT:
236 # GR25  SDRAM size              [saved]
237 # GR26  &__head_reference       [saved]
238 # GR30  LED address             [saved]
239 #
240 ###############################################################################
241         .globl          __head_fr401_set_protection
242 __head_fr401_set_protection:
243         movsg           lr,gr27
244
245         # set the I/O region protection registers for FR401/3/5
246         sethi.p         %hi(__region_IO),gr5
247         setlo           %lo(__region_IO),gr5
248         ori             gr5,#xAMPRx_SS_512Mb|xAMPRx_S_KERNEL|xAMPRx_C|xAMPRx_V,gr5
249         movgs           gr0,iampr7
250         movgs           gr5,dampr7                      ; General I/O tile
251
252         # need to tile the remaining IAMPR/DAMPR registers to cover as much of the RAM as possible
253         # - start with the highest numbered registers
254         sethi.p         %hi(__kernel_image_end),gr8
255         setlo           %lo(__kernel_image_end),gr8
256         sethi.p         %hi(32768),gr4                  ; allow for a maximal allocator bitmap
257         setlo           %lo(32768),gr4
258         add             gr8,gr4,gr8
259         sethi.p         %hi(1024*2048-1),gr4            ; round up to nearest 2MiB
260         setlo           %lo(1024*2048-1),gr4
261         add.p           gr8,gr4,gr8
262         not             gr4,gr4
263         and             gr8,gr4,gr8
264
265         sethi.p         %hi(__page_offset),gr9
266         setlo           %lo(__page_offset),gr9
267         add             gr9,gr25,gr9
268
269         # GR8 = base of uncovered RAM
270         # GR9 = top of uncovered RAM
271
272 #ifdef CONFIG_MB93093_PDK
273         sethi.p         %hi(__region_CS2),gr4
274         setlo           %lo(__region_CS2),gr4
275         ori             gr4,#xAMPRx_SS_1Mb|xAMPRx_S_KERNEL|xAMPRx_C|xAMPRx_V,gr4
276         movgs           gr4,dampr6
277         movgs           gr0,iampr6
278 #else
279         call            __head_split_region
280         movgs           gr4,iampr6
281         movgs           gr5,dampr6
282 #endif
283         call            __head_split_region
284         movgs           gr4,iampr5
285         movgs           gr5,dampr5
286         call            __head_split_region
287         movgs           gr4,iampr4
288         movgs           gr5,dampr4
289         call            __head_split_region
290         movgs           gr4,iampr3
291         movgs           gr5,dampr3
292         call            __head_split_region
293         movgs           gr4,iampr2
294         movgs           gr5,dampr2
295         call            __head_split_region
296         movgs           gr4,iampr1
297         movgs           gr5,dampr1
298
299         # cover kernel core image with kernel-only segment
300         sethi.p         %hi(__page_offset),gr8
301         setlo           %lo(__page_offset),gr8
302         call            __head_split_region
303
304 #ifdef CONFIG_PROTECT_KERNEL
305         ori.p           gr4,#xAMPRx_S_KERNEL,gr4
306         ori             gr5,#xAMPRx_S_KERNEL,gr5
307 #endif
308
309         movgs           gr4,iampr0
310         movgs           gr5,dampr0
311         jmpl            @(gr27,gr0)