Blackfin: SMP: work around anomaly 05000491
[linux-3.10.git] / arch / blackfin / mach-common / smp.c
1 /*
2  * IPI management based on arch/arm/kernel/smp.c (Copyright 2002 ARM Limited)
3  *
4  * Copyright 2007-2009 Analog Devices Inc.
5  *                         Philippe Gerum <rpm@xenomai.org>
6  *
7  * Licensed under the GPL-2.
8  */
9
10 #include <linux/module.h>
11 #include <linux/delay.h>
12 #include <linux/init.h>
13 #include <linux/spinlock.h>
14 #include <linux/sched.h>
15 #include <linux/interrupt.h>
16 #include <linux/cache.h>
17 #include <linux/profile.h>
18 #include <linux/errno.h>
19 #include <linux/mm.h>
20 #include <linux/cpu.h>
21 #include <linux/smp.h>
22 #include <linux/cpumask.h>
23 #include <linux/seq_file.h>
24 #include <linux/irq.h>
25 #include <linux/slab.h>
26 #include <asm/atomic.h>
27 #include <asm/cacheflush.h>
28 #include <asm/mmu_context.h>
29 #include <asm/pgtable.h>
30 #include <asm/pgalloc.h>
31 #include <asm/processor.h>
32 #include <asm/ptrace.h>
33 #include <asm/cpu.h>
34 #include <asm/time.h>
35 #include <linux/err.h>
36
37 /*
38  * Anomaly notes:
39  * 05000120 - we always define corelock as 32-bit integer in L2
40  */
41 struct corelock_slot corelock __attribute__ ((__section__(".l2.bss")));
42
43 #ifdef CONFIG_ICACHE_FLUSH_L1
44 unsigned long blackfin_iflush_l1_entry[NR_CPUS];
45 #endif
46
47 void __cpuinitdata *init_retx_coreb, *init_saved_retx_coreb,
48         *init_saved_seqstat_coreb, *init_saved_icplb_fault_addr_coreb,
49         *init_saved_dcplb_fault_addr_coreb;
50
51 #define BFIN_IPI_RESCHEDULE   0
52 #define BFIN_IPI_CALL_FUNC    1
53 #define BFIN_IPI_CPU_STOP     2
54
55 struct blackfin_flush_data {
56         unsigned long start;
57         unsigned long end;
58 };
59
60 void *secondary_stack;
61
62
63 struct smp_call_struct {
64         void (*func)(void *info);
65         void *info;
66         int wait;
67         cpumask_t *waitmask;
68 };
69
70 static struct blackfin_flush_data smp_flush_data;
71
72 static DEFINE_SPINLOCK(stop_lock);
73
74 struct ipi_message {
75         unsigned long type;
76         struct smp_call_struct call_struct;
77 };
78
79 /* A magic number - stress test shows this is safe for common cases */
80 #define BFIN_IPI_MSGQ_LEN 5
81
82 /* Simple FIFO buffer, overflow leads to panic */
83 struct ipi_message_queue {
84         spinlock_t lock;
85         unsigned long count;
86         unsigned long head; /* head of the queue */
87         struct ipi_message ipi_message[BFIN_IPI_MSGQ_LEN];
88 };
89
90 static DEFINE_PER_CPU(struct ipi_message_queue, ipi_msg_queue);
91
92 static void ipi_cpu_stop(unsigned int cpu)
93 {
94         spin_lock(&stop_lock);
95         printk(KERN_CRIT "CPU%u: stopping\n", cpu);
96         dump_stack();
97         spin_unlock(&stop_lock);
98
99         cpu_clear(cpu, cpu_online_map);
100
101         local_irq_disable();
102
103         while (1)
104                 SSYNC();
105 }
106
107 static void ipi_flush_icache(void *info)
108 {
109         struct blackfin_flush_data *fdata = info;
110
111         /* Invalidate the memory holding the bounds of the flushed region. */
112         invalidate_dcache_range((unsigned long)fdata,
113                 (unsigned long)fdata + sizeof(*fdata));
114
115         flush_icache_range(fdata->start, fdata->end);
116 }
117
118 static void ipi_call_function(unsigned int cpu, struct ipi_message *msg)
119 {
120         int wait;
121         void (*func)(void *info);
122         void *info;
123         func = msg->call_struct.func;
124         info = msg->call_struct.info;
125         wait = msg->call_struct.wait;
126         func(info);
127         if (wait) {
128 #ifdef __ARCH_SYNC_CORE_DCACHE
129                 /*
130                  * 'wait' usually means synchronization between CPUs.
131                  * Invalidate D cache in case shared data was changed
132                  * by func() to ensure cache coherence.
133                  */
134                 resync_core_dcache();
135 #endif
136                 cpu_clear(cpu, *msg->call_struct.waitmask);
137         }
138 }
139
140 /* Use IRQ_SUPPLE_0 to request reschedule.
141  * When returning from interrupt to user space,
142  * there is chance to reschedule */
143 static irqreturn_t ipi_handler_int0(int irq, void *dev_instance)
144 {
145         unsigned int cpu = smp_processor_id();
146
147         platform_clear_ipi(cpu, IRQ_SUPPLE_0);
148         return IRQ_HANDLED;
149 }
150
151 static irqreturn_t ipi_handler_int1(int irq, void *dev_instance)
152 {
153         struct ipi_message *msg;
154         struct ipi_message_queue *msg_queue;
155         unsigned int cpu = smp_processor_id();
156         unsigned long flags;
157
158         platform_clear_ipi(cpu, IRQ_SUPPLE_1);
159
160         msg_queue = &__get_cpu_var(ipi_msg_queue);
161
162         spin_lock_irqsave(&msg_queue->lock, flags);
163
164         while (msg_queue->count) {
165                 msg = &msg_queue->ipi_message[msg_queue->head];
166                 switch (msg->type) {
167                 case BFIN_IPI_CALL_FUNC:
168                         spin_unlock_irqrestore(&msg_queue->lock, flags);
169                         ipi_call_function(cpu, msg);
170                         spin_lock_irqsave(&msg_queue->lock, flags);
171                         break;
172                 case BFIN_IPI_CPU_STOP:
173                         spin_unlock_irqrestore(&msg_queue->lock, flags);
174                         ipi_cpu_stop(cpu);
175                         spin_lock_irqsave(&msg_queue->lock, flags);
176                         break;
177                 default:
178                         printk(KERN_CRIT "CPU%u: Unknown IPI message 0x%lx\n",
179                                cpu, msg->type);
180                         break;
181                 }
182                 msg_queue->head++;
183                 msg_queue->head %= BFIN_IPI_MSGQ_LEN;
184                 msg_queue->count--;
185         }
186         spin_unlock_irqrestore(&msg_queue->lock, flags);
187         return IRQ_HANDLED;
188 }
189
190 static void ipi_queue_init(void)
191 {
192         unsigned int cpu;
193         struct ipi_message_queue *msg_queue;
194         for_each_possible_cpu(cpu) {
195                 msg_queue = &per_cpu(ipi_msg_queue, cpu);
196                 spin_lock_init(&msg_queue->lock);
197                 msg_queue->count = 0;
198                 msg_queue->head = 0;
199         }
200 }
201
202 static inline void smp_send_message(cpumask_t callmap, unsigned long type,
203                                         void (*func) (void *info), void *info, int wait)
204 {
205         unsigned int cpu;
206         struct ipi_message_queue *msg_queue;
207         struct ipi_message *msg;
208         unsigned long flags, next_msg;
209         cpumask_t waitmask = callmap; /* waitmask is shared by all cpus */
210
211         for_each_cpu_mask(cpu, callmap) {
212                 msg_queue = &per_cpu(ipi_msg_queue, cpu);
213                 spin_lock_irqsave(&msg_queue->lock, flags);
214                 if (msg_queue->count < BFIN_IPI_MSGQ_LEN) {
215                         next_msg = (msg_queue->head + msg_queue->count)
216                                         % BFIN_IPI_MSGQ_LEN;
217                         msg = &msg_queue->ipi_message[next_msg];
218                         msg->type = type;
219                         if (type == BFIN_IPI_CALL_FUNC) {
220                                 msg->call_struct.func = func;
221                                 msg->call_struct.info = info;
222                                 msg->call_struct.wait = wait;
223                                 msg->call_struct.waitmask = &waitmask;
224                         }
225                         msg_queue->count++;
226                 } else
227                         panic("IPI message queue overflow\n");
228                 spin_unlock_irqrestore(&msg_queue->lock, flags);
229                 platform_send_ipi_cpu(cpu, IRQ_SUPPLE_1);
230         }
231
232         if (wait) {
233                 while (!cpus_empty(waitmask))
234                         blackfin_dcache_invalidate_range(
235                                 (unsigned long)(&waitmask),
236                                 (unsigned long)(&waitmask));
237 #ifdef __ARCH_SYNC_CORE_DCACHE
238                 /*
239                  * Invalidate D cache in case shared data was changed by
240                  * other processors to ensure cache coherence.
241                  */
242                 resync_core_dcache();
243 #endif
244         }
245 }
246
247 int smp_call_function(void (*func)(void *info), void *info, int wait)
248 {
249         cpumask_t callmap;
250
251         preempt_disable();
252         callmap = cpu_online_map;
253         cpu_clear(smp_processor_id(), callmap);
254         if (!cpus_empty(callmap))
255                 smp_send_message(callmap, BFIN_IPI_CALL_FUNC, func, info, wait);
256
257         preempt_enable();
258
259         return 0;
260 }
261 EXPORT_SYMBOL_GPL(smp_call_function);
262
263 int smp_call_function_single(int cpuid, void (*func) (void *info), void *info,
264                                 int wait)
265 {
266         unsigned int cpu = cpuid;
267         cpumask_t callmap;
268
269         if (cpu_is_offline(cpu))
270                 return 0;
271         cpus_clear(callmap);
272         cpu_set(cpu, callmap);
273
274         smp_send_message(callmap, BFIN_IPI_CALL_FUNC, func, info, wait);
275
276         return 0;
277 }
278 EXPORT_SYMBOL_GPL(smp_call_function_single);
279
280 void smp_send_reschedule(int cpu)
281 {
282         /* simply trigger an ipi */
283         if (cpu_is_offline(cpu))
284                 return;
285         platform_send_ipi_cpu(cpu, IRQ_SUPPLE_0);
286
287         return;
288 }
289
290 void smp_send_stop(void)
291 {
292         cpumask_t callmap;
293
294         preempt_disable();
295         callmap = cpu_online_map;
296         cpu_clear(smp_processor_id(), callmap);
297         if (!cpus_empty(callmap))
298                 smp_send_message(callmap, BFIN_IPI_CPU_STOP, NULL, NULL, 0);
299
300         preempt_enable();
301
302         return;
303 }
304
305 int __cpuinit __cpu_up(unsigned int cpu)
306 {
307         int ret;
308         static struct task_struct *idle;
309
310         if (idle)
311                 free_task(idle);
312
313         idle = fork_idle(cpu);
314         if (IS_ERR(idle)) {
315                 printk(KERN_ERR "CPU%u: fork() failed\n", cpu);
316                 return PTR_ERR(idle);
317         }
318
319         secondary_stack = task_stack_page(idle) + THREAD_SIZE;
320
321         ret = platform_boot_secondary(cpu, idle);
322
323         secondary_stack = NULL;
324
325         return ret;
326 }
327
328 static void __cpuinit setup_secondary(unsigned int cpu)
329 {
330         unsigned long ilat;
331
332         bfin_write_IMASK(0);
333         CSYNC();
334         ilat = bfin_read_ILAT();
335         CSYNC();
336         bfin_write_ILAT(ilat);
337         CSYNC();
338
339         /* Enable interrupt levels IVG7-15. IARs have been already
340          * programmed by the boot CPU.  */
341         bfin_irq_flags |= IMASK_IVG15 |
342             IMASK_IVG14 | IMASK_IVG13 | IMASK_IVG12 | IMASK_IVG11 |
343             IMASK_IVG10 | IMASK_IVG9 | IMASK_IVG8 | IMASK_IVG7 | IMASK_IVGHW;
344 }
345
346 void __cpuinit secondary_start_kernel(void)
347 {
348         unsigned int cpu = smp_processor_id();
349         struct mm_struct *mm = &init_mm;
350
351         if (_bfin_swrst & SWRST_DBL_FAULT_B) {
352                 printk(KERN_EMERG "CoreB Recovering from DOUBLE FAULT event\n");
353 #ifdef CONFIG_DEBUG_DOUBLEFAULT
354                 printk(KERN_EMERG " While handling exception (EXCAUSE = 0x%x) at %pF\n",
355                         (int)init_saved_seqstat_coreb & SEQSTAT_EXCAUSE, init_saved_retx_coreb);
356                 printk(KERN_NOTICE "   DCPLB_FAULT_ADDR: %pF\n", init_saved_dcplb_fault_addr_coreb);
357                 printk(KERN_NOTICE "   ICPLB_FAULT_ADDR: %pF\n", init_saved_icplb_fault_addr_coreb);
358 #endif
359                 printk(KERN_NOTICE " The instruction at %pF caused a double exception\n",
360                         init_retx_coreb);
361         }
362
363         /*
364          * We want the D-cache to be enabled early, in case the atomic
365          * support code emulates cache coherence (see
366          * __ARCH_SYNC_CORE_DCACHE).
367          */
368         init_exception_vectors();
369
370         local_irq_disable();
371
372         /* Attach the new idle task to the global mm. */
373         atomic_inc(&mm->mm_users);
374         atomic_inc(&mm->mm_count);
375         current->active_mm = mm;
376
377         preempt_disable();
378
379         setup_secondary(cpu);
380
381         platform_secondary_init(cpu);
382
383         /* setup local core timer */
384         bfin_local_timer_setup();
385
386         local_irq_enable();
387
388         bfin_setup_caches(cpu);
389
390         /*
391          * Calibrate loops per jiffy value.
392          * IRQs need to be enabled here - D-cache can be invalidated
393          * in timer irq handler, so core B can read correct jiffies.
394          */
395         calibrate_delay();
396
397         cpu_idle();
398 }
399
400 void __init smp_prepare_boot_cpu(void)
401 {
402 }
403
404 void __init smp_prepare_cpus(unsigned int max_cpus)
405 {
406         platform_prepare_cpus(max_cpus);
407         ipi_queue_init();
408         platform_request_ipi(IRQ_SUPPLE_0, ipi_handler_int0);
409         platform_request_ipi(IRQ_SUPPLE_1, ipi_handler_int1);
410 }
411
412 void __init smp_cpus_done(unsigned int max_cpus)
413 {
414         unsigned long bogosum = 0;
415         unsigned int cpu;
416
417         for_each_online_cpu(cpu)
418                 bogosum += loops_per_jiffy;
419
420         printk(KERN_INFO "SMP: Total of %d processors activated "
421                "(%lu.%02lu BogoMIPS).\n",
422                num_online_cpus(),
423                bogosum / (500000/HZ),
424                (bogosum / (5000/HZ)) % 100);
425 }
426
427 void smp_icache_flush_range_others(unsigned long start, unsigned long end)
428 {
429         smp_flush_data.start = start;
430         smp_flush_data.end = end;
431
432         if (smp_call_function(&ipi_flush_icache, &smp_flush_data, 0))
433                 printk(KERN_WARNING "SMP: failed to run I-cache flush request on other CPUs\n");
434 }
435 EXPORT_SYMBOL_GPL(smp_icache_flush_range_others);
436
437 #ifdef __ARCH_SYNC_CORE_ICACHE
438 unsigned long icache_invld_count[NR_CPUS];
439 void resync_core_icache(void)
440 {
441         unsigned int cpu = get_cpu();
442         blackfin_invalidate_entire_icache();
443         icache_invld_count[cpu]++;
444         put_cpu();
445 }
446 EXPORT_SYMBOL(resync_core_icache);
447 #endif
448
449 #ifdef __ARCH_SYNC_CORE_DCACHE
450 unsigned long dcache_invld_count[NR_CPUS];
451 unsigned long barrier_mask __attribute__ ((__section__(".l2.bss")));
452
453 void resync_core_dcache(void)
454 {
455         unsigned int cpu = get_cpu();
456         blackfin_invalidate_entire_dcache();
457         dcache_invld_count[cpu]++;
458         put_cpu();
459 }
460 EXPORT_SYMBOL(resync_core_dcache);
461 #endif
462
463 #ifdef CONFIG_HOTPLUG_CPU
464 int __cpuexit __cpu_disable(void)
465 {
466         unsigned int cpu = smp_processor_id();
467
468         if (cpu == 0)
469                 return -EPERM;
470
471         set_cpu_online(cpu, false);
472         return 0;
473 }
474
475 static DECLARE_COMPLETION(cpu_killed);
476
477 int __cpuexit __cpu_die(unsigned int cpu)
478 {
479         return wait_for_completion_timeout(&cpu_killed, 5000);
480 }
481
482 void cpu_die(void)
483 {
484         complete(&cpu_killed);
485
486         atomic_dec(&init_mm.mm_users);
487         atomic_dec(&init_mm.mm_count);
488
489         local_irq_disable();
490         platform_cpu_die();
491 }
492 #endif