sched: Provide scheduler_ipi() callback in response to smp_send_reschedule()
[linux-3.10.git] / arch / blackfin / mach-common / smp.c
1 /*
2  * IPI management based on arch/arm/kernel/smp.c (Copyright 2002 ARM Limited)
3  *
4  * Copyright 2007-2009 Analog Devices Inc.
5  *                         Philippe Gerum <rpm@xenomai.org>
6  *
7  * Licensed under the GPL-2.
8  */
9
10 #include <linux/module.h>
11 #include <linux/delay.h>
12 #include <linux/init.h>
13 #include <linux/spinlock.h>
14 #include <linux/sched.h>
15 #include <linux/interrupt.h>
16 #include <linux/cache.h>
17 #include <linux/profile.h>
18 #include <linux/errno.h>
19 #include <linux/mm.h>
20 #include <linux/cpu.h>
21 #include <linux/smp.h>
22 #include <linux/cpumask.h>
23 #include <linux/seq_file.h>
24 #include <linux/irq.h>
25 #include <linux/slab.h>
26 #include <asm/atomic.h>
27 #include <asm/cacheflush.h>
28 #include <asm/mmu_context.h>
29 #include <asm/pgtable.h>
30 #include <asm/pgalloc.h>
31 #include <asm/processor.h>
32 #include <asm/ptrace.h>
33 #include <asm/cpu.h>
34 #include <asm/time.h>
35 #include <linux/err.h>
36
37 /*
38  * Anomaly notes:
39  * 05000120 - we always define corelock as 32-bit integer in L2
40  */
41 struct corelock_slot corelock __attribute__ ((__section__(".l2.bss")));
42
43 #ifdef CONFIG_ICACHE_FLUSH_L1
44 unsigned long blackfin_iflush_l1_entry[NR_CPUS];
45 #endif
46
47 void __cpuinitdata *init_retx_coreb, *init_saved_retx_coreb,
48         *init_saved_seqstat_coreb, *init_saved_icplb_fault_addr_coreb,
49         *init_saved_dcplb_fault_addr_coreb;
50
51 #define BFIN_IPI_RESCHEDULE   0
52 #define BFIN_IPI_CALL_FUNC    1
53 #define BFIN_IPI_CPU_STOP     2
54
55 struct blackfin_flush_data {
56         unsigned long start;
57         unsigned long end;
58 };
59
60 void *secondary_stack;
61
62
63 struct smp_call_struct {
64         void (*func)(void *info);
65         void *info;
66         int wait;
67         cpumask_t *waitmask;
68 };
69
70 static struct blackfin_flush_data smp_flush_data;
71
72 static DEFINE_SPINLOCK(stop_lock);
73
74 struct ipi_message {
75         unsigned long type;
76         struct smp_call_struct call_struct;
77 };
78
79 /* A magic number - stress test shows this is safe for common cases */
80 #define BFIN_IPI_MSGQ_LEN 5
81
82 /* Simple FIFO buffer, overflow leads to panic */
83 struct ipi_message_queue {
84         spinlock_t lock;
85         unsigned long count;
86         unsigned long head; /* head of the queue */
87         struct ipi_message ipi_message[BFIN_IPI_MSGQ_LEN];
88 };
89
90 static DEFINE_PER_CPU(struct ipi_message_queue, ipi_msg_queue);
91
92 static void ipi_cpu_stop(unsigned int cpu)
93 {
94         spin_lock(&stop_lock);
95         printk(KERN_CRIT "CPU%u: stopping\n", cpu);
96         dump_stack();
97         spin_unlock(&stop_lock);
98
99         cpu_clear(cpu, cpu_online_map);
100
101         local_irq_disable();
102
103         while (1)
104                 SSYNC();
105 }
106
107 static void ipi_flush_icache(void *info)
108 {
109         struct blackfin_flush_data *fdata = info;
110
111         /* Invalidate the memory holding the bounds of the flushed region. */
112         invalidate_dcache_range((unsigned long)fdata,
113                 (unsigned long)fdata + sizeof(*fdata));
114
115         flush_icache_range(fdata->start, fdata->end);
116 }
117
118 static void ipi_call_function(unsigned int cpu, struct ipi_message *msg)
119 {
120         int wait;
121         void (*func)(void *info);
122         void *info;
123         func = msg->call_struct.func;
124         info = msg->call_struct.info;
125         wait = msg->call_struct.wait;
126         func(info);
127         if (wait) {
128 #ifdef __ARCH_SYNC_CORE_DCACHE
129                 /*
130                  * 'wait' usually means synchronization between CPUs.
131                  * Invalidate D cache in case shared data was changed
132                  * by func() to ensure cache coherence.
133                  */
134                 resync_core_dcache();
135 #endif
136                 cpu_clear(cpu, *msg->call_struct.waitmask);
137         }
138 }
139
140 /* Use IRQ_SUPPLE_0 to request reschedule.
141  * When returning from interrupt to user space,
142  * there is chance to reschedule */
143 static irqreturn_t ipi_handler_int0(int irq, void *dev_instance)
144 {
145         unsigned int cpu = smp_processor_id();
146
147         platform_clear_ipi(cpu, IRQ_SUPPLE_0);
148         return IRQ_HANDLED;
149 }
150
151 static irqreturn_t ipi_handler_int1(int irq, void *dev_instance)
152 {
153         struct ipi_message *msg;
154         struct ipi_message_queue *msg_queue;
155         unsigned int cpu = smp_processor_id();
156         unsigned long flags;
157
158         platform_clear_ipi(cpu, IRQ_SUPPLE_1);
159
160         msg_queue = &__get_cpu_var(ipi_msg_queue);
161
162         spin_lock_irqsave(&msg_queue->lock, flags);
163
164         while (msg_queue->count) {
165                 msg = &msg_queue->ipi_message[msg_queue->head];
166                 switch (msg->type) {
167                 case BFIN_IPI_RESCHEDULE:
168                         scheduler_ipi();
169                         break;
170                 case BFIN_IPI_CALL_FUNC:
171                         spin_unlock_irqrestore(&msg_queue->lock, flags);
172                         ipi_call_function(cpu, msg);
173                         spin_lock_irqsave(&msg_queue->lock, flags);
174                         break;
175                 case BFIN_IPI_CPU_STOP:
176                         spin_unlock_irqrestore(&msg_queue->lock, flags);
177                         ipi_cpu_stop(cpu);
178                         spin_lock_irqsave(&msg_queue->lock, flags);
179                         break;
180                 default:
181                         printk(KERN_CRIT "CPU%u: Unknown IPI message 0x%lx\n",
182                                cpu, msg->type);
183                         break;
184                 }
185                 msg_queue->head++;
186                 msg_queue->head %= BFIN_IPI_MSGQ_LEN;
187                 msg_queue->count--;
188         }
189         spin_unlock_irqrestore(&msg_queue->lock, flags);
190         return IRQ_HANDLED;
191 }
192
193 static void ipi_queue_init(void)
194 {
195         unsigned int cpu;
196         struct ipi_message_queue *msg_queue;
197         for_each_possible_cpu(cpu) {
198                 msg_queue = &per_cpu(ipi_msg_queue, cpu);
199                 spin_lock_init(&msg_queue->lock);
200                 msg_queue->count = 0;
201                 msg_queue->head = 0;
202         }
203 }
204
205 static inline void smp_send_message(cpumask_t callmap, unsigned long type,
206                                         void (*func) (void *info), void *info, int wait)
207 {
208         unsigned int cpu;
209         struct ipi_message_queue *msg_queue;
210         struct ipi_message *msg;
211         unsigned long flags, next_msg;
212         cpumask_t waitmask = callmap; /* waitmask is shared by all cpus */
213
214         for_each_cpu_mask(cpu, callmap) {
215                 msg_queue = &per_cpu(ipi_msg_queue, cpu);
216                 spin_lock_irqsave(&msg_queue->lock, flags);
217                 if (msg_queue->count < BFIN_IPI_MSGQ_LEN) {
218                         next_msg = (msg_queue->head + msg_queue->count)
219                                         % BFIN_IPI_MSGQ_LEN;
220                         msg = &msg_queue->ipi_message[next_msg];
221                         msg->type = type;
222                         if (type == BFIN_IPI_CALL_FUNC) {
223                                 msg->call_struct.func = func;
224                                 msg->call_struct.info = info;
225                                 msg->call_struct.wait = wait;
226                                 msg->call_struct.waitmask = &waitmask;
227                         }
228                         msg_queue->count++;
229                 } else
230                         panic("IPI message queue overflow\n");
231                 spin_unlock_irqrestore(&msg_queue->lock, flags);
232                 platform_send_ipi_cpu(cpu, IRQ_SUPPLE_1);
233         }
234
235         if (wait) {
236                 while (!cpus_empty(waitmask))
237                         blackfin_dcache_invalidate_range(
238                                 (unsigned long)(&waitmask),
239                                 (unsigned long)(&waitmask));
240 #ifdef __ARCH_SYNC_CORE_DCACHE
241                 /*
242                  * Invalidate D cache in case shared data was changed by
243                  * other processors to ensure cache coherence.
244                  */
245                 resync_core_dcache();
246 #endif
247         }
248 }
249
250 int smp_call_function(void (*func)(void *info), void *info, int wait)
251 {
252         cpumask_t callmap;
253
254         preempt_disable();
255         callmap = cpu_online_map;
256         cpu_clear(smp_processor_id(), callmap);
257         if (!cpus_empty(callmap))
258                 smp_send_message(callmap, BFIN_IPI_CALL_FUNC, func, info, wait);
259
260         preempt_enable();
261
262         return 0;
263 }
264 EXPORT_SYMBOL_GPL(smp_call_function);
265
266 int smp_call_function_single(int cpuid, void (*func) (void *info), void *info,
267                                 int wait)
268 {
269         unsigned int cpu = cpuid;
270         cpumask_t callmap;
271
272         if (cpu_is_offline(cpu))
273                 return 0;
274         cpus_clear(callmap);
275         cpu_set(cpu, callmap);
276
277         smp_send_message(callmap, BFIN_IPI_CALL_FUNC, func, info, wait);
278
279         return 0;
280 }
281 EXPORT_SYMBOL_GPL(smp_call_function_single);
282
283 void smp_send_reschedule(int cpu)
284 {
285         /* simply trigger an ipi */
286         if (cpu_is_offline(cpu))
287                 return;
288         platform_send_ipi_cpu(cpu, IRQ_SUPPLE_0);
289
290         return;
291 }
292
293 void smp_send_stop(void)
294 {
295         cpumask_t callmap;
296
297         preempt_disable();
298         callmap = cpu_online_map;
299         cpu_clear(smp_processor_id(), callmap);
300         if (!cpus_empty(callmap))
301                 smp_send_message(callmap, BFIN_IPI_CPU_STOP, NULL, NULL, 0);
302
303         preempt_enable();
304
305         return;
306 }
307
308 int __cpuinit __cpu_up(unsigned int cpu)
309 {
310         int ret;
311         static struct task_struct *idle;
312
313         if (idle)
314                 free_task(idle);
315
316         idle = fork_idle(cpu);
317         if (IS_ERR(idle)) {
318                 printk(KERN_ERR "CPU%u: fork() failed\n", cpu);
319                 return PTR_ERR(idle);
320         }
321
322         secondary_stack = task_stack_page(idle) + THREAD_SIZE;
323
324         ret = platform_boot_secondary(cpu, idle);
325
326         secondary_stack = NULL;
327
328         return ret;
329 }
330
331 static void __cpuinit setup_secondary(unsigned int cpu)
332 {
333         unsigned long ilat;
334
335         bfin_write_IMASK(0);
336         CSYNC();
337         ilat = bfin_read_ILAT();
338         CSYNC();
339         bfin_write_ILAT(ilat);
340         CSYNC();
341
342         /* Enable interrupt levels IVG7-15. IARs have been already
343          * programmed by the boot CPU.  */
344         bfin_irq_flags |= IMASK_IVG15 |
345             IMASK_IVG14 | IMASK_IVG13 | IMASK_IVG12 | IMASK_IVG11 |
346             IMASK_IVG10 | IMASK_IVG9 | IMASK_IVG8 | IMASK_IVG7 | IMASK_IVGHW;
347 }
348
349 void __cpuinit secondary_start_kernel(void)
350 {
351         unsigned int cpu = smp_processor_id();
352         struct mm_struct *mm = &init_mm;
353
354         if (_bfin_swrst & SWRST_DBL_FAULT_B) {
355                 printk(KERN_EMERG "CoreB Recovering from DOUBLE FAULT event\n");
356 #ifdef CONFIG_DEBUG_DOUBLEFAULT
357                 printk(KERN_EMERG " While handling exception (EXCAUSE = 0x%x) at %pF\n",
358                         (int)init_saved_seqstat_coreb & SEQSTAT_EXCAUSE, init_saved_retx_coreb);
359                 printk(KERN_NOTICE "   DCPLB_FAULT_ADDR: %pF\n", init_saved_dcplb_fault_addr_coreb);
360                 printk(KERN_NOTICE "   ICPLB_FAULT_ADDR: %pF\n", init_saved_icplb_fault_addr_coreb);
361 #endif
362                 printk(KERN_NOTICE " The instruction at %pF caused a double exception\n",
363                         init_retx_coreb);
364         }
365
366         /*
367          * We want the D-cache to be enabled early, in case the atomic
368          * support code emulates cache coherence (see
369          * __ARCH_SYNC_CORE_DCACHE).
370          */
371         init_exception_vectors();
372
373         local_irq_disable();
374
375         /* Attach the new idle task to the global mm. */
376         atomic_inc(&mm->mm_users);
377         atomic_inc(&mm->mm_count);
378         current->active_mm = mm;
379
380         preempt_disable();
381
382         setup_secondary(cpu);
383
384         platform_secondary_init(cpu);
385
386         /* setup local core timer */
387         bfin_local_timer_setup();
388
389         local_irq_enable();
390
391         bfin_setup_caches(cpu);
392
393         /*
394          * Calibrate loops per jiffy value.
395          * IRQs need to be enabled here - D-cache can be invalidated
396          * in timer irq handler, so core B can read correct jiffies.
397          */
398         calibrate_delay();
399
400         cpu_idle();
401 }
402
403 void __init smp_prepare_boot_cpu(void)
404 {
405 }
406
407 void __init smp_prepare_cpus(unsigned int max_cpus)
408 {
409         platform_prepare_cpus(max_cpus);
410         ipi_queue_init();
411         platform_request_ipi(IRQ_SUPPLE_0, ipi_handler_int0);
412         platform_request_ipi(IRQ_SUPPLE_1, ipi_handler_int1);
413 }
414
415 void __init smp_cpus_done(unsigned int max_cpus)
416 {
417         unsigned long bogosum = 0;
418         unsigned int cpu;
419
420         for_each_online_cpu(cpu)
421                 bogosum += loops_per_jiffy;
422
423         printk(KERN_INFO "SMP: Total of %d processors activated "
424                "(%lu.%02lu BogoMIPS).\n",
425                num_online_cpus(),
426                bogosum / (500000/HZ),
427                (bogosum / (5000/HZ)) % 100);
428 }
429
430 void smp_icache_flush_range_others(unsigned long start, unsigned long end)
431 {
432         smp_flush_data.start = start;
433         smp_flush_data.end = end;
434
435         if (smp_call_function(&ipi_flush_icache, &smp_flush_data, 0))
436                 printk(KERN_WARNING "SMP: failed to run I-cache flush request on other CPUs\n");
437 }
438 EXPORT_SYMBOL_GPL(smp_icache_flush_range_others);
439
440 #ifdef __ARCH_SYNC_CORE_ICACHE
441 unsigned long icache_invld_count[NR_CPUS];
442 void resync_core_icache(void)
443 {
444         unsigned int cpu = get_cpu();
445         blackfin_invalidate_entire_icache();
446         icache_invld_count[cpu]++;
447         put_cpu();
448 }
449 EXPORT_SYMBOL(resync_core_icache);
450 #endif
451
452 #ifdef __ARCH_SYNC_CORE_DCACHE
453 unsigned long dcache_invld_count[NR_CPUS];
454 unsigned long barrier_mask __attribute__ ((__section__(".l2.bss")));
455
456 void resync_core_dcache(void)
457 {
458         unsigned int cpu = get_cpu();
459         blackfin_invalidate_entire_dcache();
460         dcache_invld_count[cpu]++;
461         put_cpu();
462 }
463 EXPORT_SYMBOL(resync_core_dcache);
464 #endif
465
466 #ifdef CONFIG_HOTPLUG_CPU
467 int __cpuexit __cpu_disable(void)
468 {
469         unsigned int cpu = smp_processor_id();
470
471         if (cpu == 0)
472                 return -EPERM;
473
474         set_cpu_online(cpu, false);
475         return 0;
476 }
477
478 static DECLARE_COMPLETION(cpu_killed);
479
480 int __cpuexit __cpu_die(unsigned int cpu)
481 {
482         return wait_for_completion_timeout(&cpu_killed, 5000);
483 }
484
485 void cpu_die(void)
486 {
487         complete(&cpu_killed);
488
489         atomic_dec(&init_mm.mm_users);
490         atomic_dec(&init_mm.mm_count);
491
492         local_irq_disable();
493         platform_cpu_die();
494 }
495 #endif