Blackfin: bf54x: drop unused pm gpio handling
[linux-3.10.git] / arch / blackfin / mach-common / smp.c
1 /*
2  * IPI management based on arch/arm/kernel/smp.c (Copyright 2002 ARM Limited)
3  *
4  * Copyright 2007-2009 Analog Devices Inc.
5  *                         Philippe Gerum <rpm@xenomai.org>
6  *
7  * Licensed under the GPL-2.
8  */
9
10 #include <linux/module.h>
11 #include <linux/delay.h>
12 #include <linux/init.h>
13 #include <linux/spinlock.h>
14 #include <linux/sched.h>
15 #include <linux/interrupt.h>
16 #include <linux/cache.h>
17 #include <linux/profile.h>
18 #include <linux/errno.h>
19 #include <linux/mm.h>
20 #include <linux/cpu.h>
21 #include <linux/smp.h>
22 #include <linux/cpumask.h>
23 #include <linux/seq_file.h>
24 #include <linux/irq.h>
25 #include <linux/slab.h>
26 #include <asm/atomic.h>
27 #include <asm/cacheflush.h>
28 #include <asm/irq_handler.h>
29 #include <asm/mmu_context.h>
30 #include <asm/pgtable.h>
31 #include <asm/pgalloc.h>
32 #include <asm/processor.h>
33 #include <asm/ptrace.h>
34 #include <asm/cpu.h>
35 #include <asm/time.h>
36 #include <linux/err.h>
37
38 /*
39  * Anomaly notes:
40  * 05000120 - we always define corelock as 32-bit integer in L2
41  */
42 struct corelock_slot corelock __attribute__ ((__section__(".l2.bss")));
43
44 #ifdef CONFIG_ICACHE_FLUSH_L1
45 unsigned long blackfin_iflush_l1_entry[NR_CPUS];
46 #endif
47
48 void __cpuinitdata *init_retx_coreb, *init_saved_retx_coreb,
49         *init_saved_seqstat_coreb, *init_saved_icplb_fault_addr_coreb,
50         *init_saved_dcplb_fault_addr_coreb;
51
52 #define BFIN_IPI_RESCHEDULE   0
53 #define BFIN_IPI_CALL_FUNC    1
54 #define BFIN_IPI_CPU_STOP     2
55
56 struct blackfin_flush_data {
57         unsigned long start;
58         unsigned long end;
59 };
60
61 void *secondary_stack;
62
63
64 struct smp_call_struct {
65         void (*func)(void *info);
66         void *info;
67         int wait;
68         cpumask_t *waitmask;
69 };
70
71 static struct blackfin_flush_data smp_flush_data;
72
73 static DEFINE_SPINLOCK(stop_lock);
74
75 struct ipi_message {
76         unsigned long type;
77         struct smp_call_struct call_struct;
78 };
79
80 /* A magic number - stress test shows this is safe for common cases */
81 #define BFIN_IPI_MSGQ_LEN 5
82
83 /* Simple FIFO buffer, overflow leads to panic */
84 struct ipi_message_queue {
85         spinlock_t lock;
86         unsigned long count;
87         unsigned long head; /* head of the queue */
88         struct ipi_message ipi_message[BFIN_IPI_MSGQ_LEN];
89 };
90
91 static DEFINE_PER_CPU(struct ipi_message_queue, ipi_msg_queue);
92
93 static void ipi_cpu_stop(unsigned int cpu)
94 {
95         spin_lock(&stop_lock);
96         printk(KERN_CRIT "CPU%u: stopping\n", cpu);
97         dump_stack();
98         spin_unlock(&stop_lock);
99
100         cpu_clear(cpu, cpu_online_map);
101
102         local_irq_disable();
103
104         while (1)
105                 SSYNC();
106 }
107
108 static void ipi_flush_icache(void *info)
109 {
110         struct blackfin_flush_data *fdata = info;
111
112         /* Invalidate the memory holding the bounds of the flushed region. */
113         blackfin_dcache_invalidate_range((unsigned long)fdata,
114                                          (unsigned long)fdata + sizeof(*fdata));
115
116         /* Make sure all write buffers in the data side of the core
117          * are flushed before trying to invalidate the icache.  This
118          * needs to be after the data flush and before the icache
119          * flush so that the SSYNC does the right thing in preventing
120          * the instruction prefetcher from hitting things in cached
121          * memory at the wrong time -- it runs much further ahead than
122          * the pipeline.
123          */
124         SSYNC();
125
126         /* ipi_flaush_icache is invoked by generic flush_icache_range,
127          * so call blackfin arch icache flush directly here.
128          */
129         blackfin_icache_flush_range(fdata->start, fdata->end);
130 }
131
132 static void ipi_call_function(unsigned int cpu, struct ipi_message *msg)
133 {
134         int wait;
135         void (*func)(void *info);
136         void *info;
137         func = msg->call_struct.func;
138         info = msg->call_struct.info;
139         wait = msg->call_struct.wait;
140         func(info);
141         if (wait) {
142 #ifdef __ARCH_SYNC_CORE_DCACHE
143                 /*
144                  * 'wait' usually means synchronization between CPUs.
145                  * Invalidate D cache in case shared data was changed
146                  * by func() to ensure cache coherence.
147                  */
148                 resync_core_dcache();
149 #endif
150                 cpu_clear(cpu, *msg->call_struct.waitmask);
151         }
152 }
153
154 /* Use IRQ_SUPPLE_0 to request reschedule.
155  * When returning from interrupt to user space,
156  * there is chance to reschedule */
157 static irqreturn_t ipi_handler_int0(int irq, void *dev_instance)
158 {
159         unsigned int cpu = smp_processor_id();
160
161         platform_clear_ipi(cpu, IRQ_SUPPLE_0);
162         return IRQ_HANDLED;
163 }
164
165 static irqreturn_t ipi_handler_int1(int irq, void *dev_instance)
166 {
167         struct ipi_message *msg;
168         struct ipi_message_queue *msg_queue;
169         unsigned int cpu = smp_processor_id();
170         unsigned long flags;
171
172         platform_clear_ipi(cpu, IRQ_SUPPLE_1);
173
174         msg_queue = &__get_cpu_var(ipi_msg_queue);
175
176         spin_lock_irqsave(&msg_queue->lock, flags);
177
178         while (msg_queue->count) {
179                 msg = &msg_queue->ipi_message[msg_queue->head];
180                 switch (msg->type) {
181                 case BFIN_IPI_RESCHEDULE:
182                         scheduler_ipi();
183                         break;
184                 case BFIN_IPI_CALL_FUNC:
185                         spin_unlock_irqrestore(&msg_queue->lock, flags);
186                         ipi_call_function(cpu, msg);
187                         spin_lock_irqsave(&msg_queue->lock, flags);
188                         break;
189                 case BFIN_IPI_CPU_STOP:
190                         spin_unlock_irqrestore(&msg_queue->lock, flags);
191                         ipi_cpu_stop(cpu);
192                         spin_lock_irqsave(&msg_queue->lock, flags);
193                         break;
194                 default:
195                         printk(KERN_CRIT "CPU%u: Unknown IPI message 0x%lx\n",
196                                cpu, msg->type);
197                         break;
198                 }
199                 msg_queue->head++;
200                 msg_queue->head %= BFIN_IPI_MSGQ_LEN;
201                 msg_queue->count--;
202         }
203         spin_unlock_irqrestore(&msg_queue->lock, flags);
204         return IRQ_HANDLED;
205 }
206
207 static void ipi_queue_init(void)
208 {
209         unsigned int cpu;
210         struct ipi_message_queue *msg_queue;
211         for_each_possible_cpu(cpu) {
212                 msg_queue = &per_cpu(ipi_msg_queue, cpu);
213                 spin_lock_init(&msg_queue->lock);
214                 msg_queue->count = 0;
215                 msg_queue->head = 0;
216         }
217 }
218
219 static inline void smp_send_message(cpumask_t callmap, unsigned long type,
220                                         void (*func) (void *info), void *info, int wait)
221 {
222         unsigned int cpu;
223         struct ipi_message_queue *msg_queue;
224         struct ipi_message *msg;
225         unsigned long flags, next_msg;
226         cpumask_t waitmask = callmap; /* waitmask is shared by all cpus */
227
228         for_each_cpu_mask(cpu, callmap) {
229                 msg_queue = &per_cpu(ipi_msg_queue, cpu);
230                 spin_lock_irqsave(&msg_queue->lock, flags);
231                 if (msg_queue->count < BFIN_IPI_MSGQ_LEN) {
232                         next_msg = (msg_queue->head + msg_queue->count)
233                                         % BFIN_IPI_MSGQ_LEN;
234                         msg = &msg_queue->ipi_message[next_msg];
235                         msg->type = type;
236                         if (type == BFIN_IPI_CALL_FUNC) {
237                                 msg->call_struct.func = func;
238                                 msg->call_struct.info = info;
239                                 msg->call_struct.wait = wait;
240                                 msg->call_struct.waitmask = &waitmask;
241                         }
242                         msg_queue->count++;
243                 } else
244                         panic("IPI message queue overflow\n");
245                 spin_unlock_irqrestore(&msg_queue->lock, flags);
246                 platform_send_ipi_cpu(cpu, IRQ_SUPPLE_1);
247         }
248
249         if (wait) {
250                 while (!cpus_empty(waitmask))
251                         blackfin_dcache_invalidate_range(
252                                 (unsigned long)(&waitmask),
253                                 (unsigned long)(&waitmask));
254 #ifdef __ARCH_SYNC_CORE_DCACHE
255                 /*
256                  * Invalidate D cache in case shared data was changed by
257                  * other processors to ensure cache coherence.
258                  */
259                 resync_core_dcache();
260 #endif
261         }
262 }
263
264 int smp_call_function(void (*func)(void *info), void *info, int wait)
265 {
266         cpumask_t callmap;
267
268         preempt_disable();
269         callmap = cpu_online_map;
270         cpu_clear(smp_processor_id(), callmap);
271         if (!cpus_empty(callmap))
272                 smp_send_message(callmap, BFIN_IPI_CALL_FUNC, func, info, wait);
273
274         preempt_enable();
275
276         return 0;
277 }
278 EXPORT_SYMBOL_GPL(smp_call_function);
279
280 int smp_call_function_single(int cpuid, void (*func) (void *info), void *info,
281                                 int wait)
282 {
283         unsigned int cpu = cpuid;
284         cpumask_t callmap;
285
286         if (cpu_is_offline(cpu))
287                 return 0;
288         cpus_clear(callmap);
289         cpu_set(cpu, callmap);
290
291         smp_send_message(callmap, BFIN_IPI_CALL_FUNC, func, info, wait);
292
293         return 0;
294 }
295 EXPORT_SYMBOL_GPL(smp_call_function_single);
296
297 void smp_send_reschedule(int cpu)
298 {
299         /* simply trigger an ipi */
300         if (cpu_is_offline(cpu))
301                 return;
302         platform_send_ipi_cpu(cpu, IRQ_SUPPLE_0);
303
304         return;
305 }
306
307 void smp_send_stop(void)
308 {
309         cpumask_t callmap;
310
311         preempt_disable();
312         callmap = cpu_online_map;
313         cpu_clear(smp_processor_id(), callmap);
314         if (!cpus_empty(callmap))
315                 smp_send_message(callmap, BFIN_IPI_CPU_STOP, NULL, NULL, 0);
316
317         preempt_enable();
318
319         return;
320 }
321
322 int __cpuinit __cpu_up(unsigned int cpu)
323 {
324         int ret;
325         static struct task_struct *idle;
326
327         if (idle)
328                 free_task(idle);
329
330         idle = fork_idle(cpu);
331         if (IS_ERR(idle)) {
332                 printk(KERN_ERR "CPU%u: fork() failed\n", cpu);
333                 return PTR_ERR(idle);
334         }
335
336         secondary_stack = task_stack_page(idle) + THREAD_SIZE;
337
338         ret = platform_boot_secondary(cpu, idle);
339
340         secondary_stack = NULL;
341
342         return ret;
343 }
344
345 static void __cpuinit setup_secondary(unsigned int cpu)
346 {
347         unsigned long ilat;
348
349         bfin_write_IMASK(0);
350         CSYNC();
351         ilat = bfin_read_ILAT();
352         CSYNC();
353         bfin_write_ILAT(ilat);
354         CSYNC();
355
356         /* Enable interrupt levels IVG7-15. IARs have been already
357          * programmed by the boot CPU.  */
358         bfin_irq_flags |= IMASK_IVG15 |
359             IMASK_IVG14 | IMASK_IVG13 | IMASK_IVG12 | IMASK_IVG11 |
360             IMASK_IVG10 | IMASK_IVG9 | IMASK_IVG8 | IMASK_IVG7 | IMASK_IVGHW;
361 }
362
363 void __cpuinit secondary_start_kernel(void)
364 {
365         unsigned int cpu = smp_processor_id();
366         struct mm_struct *mm = &init_mm;
367
368         if (_bfin_swrst & SWRST_DBL_FAULT_B) {
369                 printk(KERN_EMERG "CoreB Recovering from DOUBLE FAULT event\n");
370 #ifdef CONFIG_DEBUG_DOUBLEFAULT
371                 printk(KERN_EMERG " While handling exception (EXCAUSE = 0x%x) at %pF\n",
372                         (int)init_saved_seqstat_coreb & SEQSTAT_EXCAUSE, init_saved_retx_coreb);
373                 printk(KERN_NOTICE "   DCPLB_FAULT_ADDR: %pF\n", init_saved_dcplb_fault_addr_coreb);
374                 printk(KERN_NOTICE "   ICPLB_FAULT_ADDR: %pF\n", init_saved_icplb_fault_addr_coreb);
375 #endif
376                 printk(KERN_NOTICE " The instruction at %pF caused a double exception\n",
377                         init_retx_coreb);
378         }
379
380         /*
381          * We want the D-cache to be enabled early, in case the atomic
382          * support code emulates cache coherence (see
383          * __ARCH_SYNC_CORE_DCACHE).
384          */
385         init_exception_vectors();
386
387         local_irq_disable();
388
389         /* Attach the new idle task to the global mm. */
390         atomic_inc(&mm->mm_users);
391         atomic_inc(&mm->mm_count);
392         current->active_mm = mm;
393
394         preempt_disable();
395
396         setup_secondary(cpu);
397
398         platform_secondary_init(cpu);
399
400         /* setup local core timer */
401         bfin_local_timer_setup();
402
403         local_irq_enable();
404
405         bfin_setup_caches(cpu);
406
407         /*
408          * Calibrate loops per jiffy value.
409          * IRQs need to be enabled here - D-cache can be invalidated
410          * in timer irq handler, so core B can read correct jiffies.
411          */
412         calibrate_delay();
413
414         cpu_idle();
415 }
416
417 void __init smp_prepare_boot_cpu(void)
418 {
419 }
420
421 void __init smp_prepare_cpus(unsigned int max_cpus)
422 {
423         platform_prepare_cpus(max_cpus);
424         ipi_queue_init();
425         platform_request_ipi(IRQ_SUPPLE_0, ipi_handler_int0);
426         platform_request_ipi(IRQ_SUPPLE_1, ipi_handler_int1);
427 }
428
429 void __init smp_cpus_done(unsigned int max_cpus)
430 {
431         unsigned long bogosum = 0;
432         unsigned int cpu;
433
434         for_each_online_cpu(cpu)
435                 bogosum += loops_per_jiffy;
436
437         printk(KERN_INFO "SMP: Total of %d processors activated "
438                "(%lu.%02lu BogoMIPS).\n",
439                num_online_cpus(),
440                bogosum / (500000/HZ),
441                (bogosum / (5000/HZ)) % 100);
442 }
443
444 void smp_icache_flush_range_others(unsigned long start, unsigned long end)
445 {
446         smp_flush_data.start = start;
447         smp_flush_data.end = end;
448
449         if (smp_call_function(&ipi_flush_icache, &smp_flush_data, 0))
450                 printk(KERN_WARNING "SMP: failed to run I-cache flush request on other CPUs\n");
451 }
452 EXPORT_SYMBOL_GPL(smp_icache_flush_range_others);
453
454 #ifdef __ARCH_SYNC_CORE_ICACHE
455 unsigned long icache_invld_count[NR_CPUS];
456 void resync_core_icache(void)
457 {
458         unsigned int cpu = get_cpu();
459         blackfin_invalidate_entire_icache();
460         icache_invld_count[cpu]++;
461         put_cpu();
462 }
463 EXPORT_SYMBOL(resync_core_icache);
464 #endif
465
466 #ifdef __ARCH_SYNC_CORE_DCACHE
467 unsigned long dcache_invld_count[NR_CPUS];
468 unsigned long barrier_mask __attribute__ ((__section__(".l2.bss")));
469
470 void resync_core_dcache(void)
471 {
472         unsigned int cpu = get_cpu();
473         blackfin_invalidate_entire_dcache();
474         dcache_invld_count[cpu]++;
475         put_cpu();
476 }
477 EXPORT_SYMBOL(resync_core_dcache);
478 #endif
479
480 #ifdef CONFIG_HOTPLUG_CPU
481 int __cpuexit __cpu_disable(void)
482 {
483         unsigned int cpu = smp_processor_id();
484
485         if (cpu == 0)
486                 return -EPERM;
487
488         set_cpu_online(cpu, false);
489         return 0;
490 }
491
492 static DECLARE_COMPLETION(cpu_killed);
493
494 int __cpuexit __cpu_die(unsigned int cpu)
495 {
496         return wait_for_completion_timeout(&cpu_killed, 5000);
497 }
498
499 void cpu_die(void)
500 {
501         complete(&cpu_killed);
502
503         atomic_dec(&init_mm.mm_users);
504         atomic_dec(&init_mm.mm_count);
505
506         local_irq_disable();
507         platform_cpu_die();
508 }
509 #endif