Blackfin arch: BF538/9 Linux kernel Support
[linux-3.10.git] / arch / blackfin / mach-bf538 / include / mach / blackfin.h
1 /*
2  * File:         include/asm-blackfin/mach-bf538/blackfin.h
3  * Based on:
4  * Author:
5  *
6  * Created:
7  * Description:
8  *
9  * Rev:
10  *
11  * Modified:
12  *
13  *
14  * Bugs:         Enter bugs at http://blackfin.uclinux.org/
15  *
16  * This program is free software; you can redistribute it and/or modify
17  * it under the terms of the GNU General Public License as published by
18  * the Free Software Foundation; either version 2, or (at your option)
19  * any later version.
20  *
21  * This program is distributed in the hope that it will be useful,
22  * but WITHOUT ANY WARRANTY; without even the implied warranty of
23  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
24  * GNU General Public License for more details.
25  *
26  * You should have received a copy of the GNU General Public License
27  * along with this program; see the file COPYING.
28  * If not, write to the Free Software Foundation,
29  * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
30  */
31
32 #ifndef _MACH_BLACKFIN_H_
33 #define _MACH_BLACKFIN_H_
34
35 #define BF538_FAMILY
36
37 #include "bf538.h"
38 #include "mem_map.h"
39 #include "defBF539.h"
40 #include "anomaly.h"
41
42
43 #if !defined(__ASSEMBLY__)
44 #include "cdefBF538.h"
45
46 #if defined(CONFIG_BF539)
47 #include "cdefBF539.h"
48 #endif
49 #endif
50
51 /* UART_IIR Register */
52 #define STATUS(x)       ((x << 1) & 0x06)
53 #define STATUS_P1       0x02
54 #define STATUS_P0       0x01
55
56 #define BFIN_UART_NR_PORTS      3
57
58 #define OFFSET_THR              0x00    /* Transmit Holding register            */
59 #define OFFSET_RBR              0x00    /* Receive Buffer register              */
60 #define OFFSET_DLL              0x00    /* Divisor Latch (Low-Byte)             */
61 #define OFFSET_IER              0x04    /* Interrupt Enable Register            */
62 #define OFFSET_DLH              0x04    /* Divisor Latch (High-Byte)            */
63 #define OFFSET_IIR              0x08    /* Interrupt Identification Register    */
64 #define OFFSET_LCR              0x0C    /* Line Control Register                */
65 #define OFFSET_MCR              0x10    /* Modem Control Register               */
66 #define OFFSET_LSR              0x14    /* Line Status Register                 */
67 #define OFFSET_MSR              0x18    /* Modem Status Register                */
68 #define OFFSET_SCR              0x1C    /* SCR Scratch Register                 */
69 #define OFFSET_GCTL             0x24    /* Global Control Register              */
70
71
72 #define bfin_write_MDMA_D0_IRQ_STATUS   bfin_write_MDMA0_D0_IRQ_STATUS
73 #define bfin_write_MDMA_D0_START_ADDR   bfin_write_MDMA0_D0_START_ADDR
74 #define bfin_write_MDMA_S0_START_ADDR   bfin_write_MDMA0_S0_START_ADDR
75 #define bfin_write_MDMA_D0_X_COUNT      bfin_write_MDMA0_D0_X_COUNT
76 #define bfin_write_MDMA_S0_X_COUNT      bfin_write_MDMA0_S0_X_COUNT
77 #define bfin_write_MDMA_D0_Y_COUNT      bfin_write_MDMA0_D0_Y_COUNT
78 #define bfin_write_MDMA_S0_Y_COUNT      bfin_write_MDMA0_S0_Y_COUNT
79 #define bfin_write_MDMA_D0_X_MODIFY     bfin_write_MDMA0_D0_X_MODIFY
80 #define bfin_write_MDMA_S0_X_MODIFY     bfin_write_MDMA0_S0_X_MODIFY
81 #define bfin_write_MDMA_D0_Y_MODIFY     bfin_write_MDMA0_D0_Y_MODIFY
82 #define bfin_write_MDMA_S0_Y_MODIFY     bfin_write_MDMA0_S0_Y_MODIFY
83 #define bfin_write_MDMA_S0_CONFIG       bfin_write_MDMA0_S0_CONFIG
84 #define bfin_write_MDMA_D0_CONFIG       bfin_write_MDMA0_D0_CONFIG
85 #define bfin_read_MDMA_D0_IRQ_STATUS    bfin_read_MDMA0_D0_IRQ_STATUS
86 #define bfin_write_MDMA_S0_IRQ_STATUS   bfin_write_MDMA0_S0_IRQ_STATUS
87
88
89 /* DPMC*/
90 #define bfin_read_STOPCK_OFF() bfin_read_STOPCK()
91 #define bfin_write_STOPCK_OFF(val) bfin_write_STOPCK(val)
92 #define STOPCK_OFF STOPCK
93
94 /* PLL_DIV Masks                                                                                                        */
95 #define CCLK_DIV1 CSEL_DIV1     /*          CCLK = VCO / 1                                  */
96 #define CCLK_DIV2 CSEL_DIV2     /*          CCLK = VCO / 2                                  */
97 #define CCLK_DIV4 CSEL_DIV4     /*          CCLK = VCO / 4                                  */
98 #define CCLK_DIV8 CSEL_DIV8     /*          CCLK = VCO / 8                                  */
99
100 #endif