include cleanup: Update gfp.h and slab.h includes to prepare for breaking implicit...
[linux-3.10.git] / arch / avr32 / mach-at32ap / at32ap700x.c
1 /*
2  * Copyright (C) 2005-2006 Atmel Corporation
3  *
4  * This program is free software; you can redistribute it and/or modify
5  * it under the terms of the GNU General Public License version 2 as
6  * published by the Free Software Foundation.
7  */
8 #include <linux/clk.h>
9 #include <linux/delay.h>
10 #include <linux/dw_dmac.h>
11 #include <linux/fb.h>
12 #include <linux/init.h>
13 #include <linux/platform_device.h>
14 #include <linux/dma-mapping.h>
15 #include <linux/slab.h>
16 #include <linux/gpio.h>
17 #include <linux/spi/spi.h>
18 #include <linux/usb/atmel_usba_udc.h>
19
20 #include <mach/atmel-mci.h>
21 #include <linux/atmel-mci.h>
22
23 #include <asm/io.h>
24 #include <asm/irq.h>
25
26 #include <mach/at32ap700x.h>
27 #include <mach/board.h>
28 #include <mach/hmatrix.h>
29 #include <mach/portmux.h>
30 #include <mach/sram.h>
31
32 #include <sound/atmel-abdac.h>
33 #include <sound/atmel-ac97c.h>
34
35 #include <video/atmel_lcdc.h>
36
37 #include "clock.h"
38 #include "pio.h"
39 #include "pm.h"
40
41
42 #define PBMEM(base)                                     \
43         {                                               \
44                 .start          = base,                 \
45                 .end            = base + 0x3ff,         \
46                 .flags          = IORESOURCE_MEM,       \
47         }
48 #define IRQ(num)                                        \
49         {                                               \
50                 .start          = num,                  \
51                 .end            = num,                  \
52                 .flags          = IORESOURCE_IRQ,       \
53         }
54 #define NAMED_IRQ(num, _name)                           \
55         {                                               \
56                 .start          = num,                  \
57                 .end            = num,                  \
58                 .name           = _name,                \
59                 .flags          = IORESOURCE_IRQ,       \
60         }
61
62 /* REVISIT these assume *every* device supports DMA, but several
63  * don't ... tc, smc, pio, rtc, watchdog, pwm, ps2, and more.
64  */
65 #define DEFINE_DEV(_name, _id)                                  \
66 static u64 _name##_id##_dma_mask = DMA_BIT_MASK(32);            \
67 static struct platform_device _name##_id##_device = {           \
68         .name           = #_name,                               \
69         .id             = _id,                                  \
70         .dev            = {                                     \
71                 .dma_mask = &_name##_id##_dma_mask,             \
72                 .coherent_dma_mask = DMA_BIT_MASK(32),          \
73         },                                                      \
74         .resource       = _name##_id##_resource,                \
75         .num_resources  = ARRAY_SIZE(_name##_id##_resource),    \
76 }
77 #define DEFINE_DEV_DATA(_name, _id)                             \
78 static u64 _name##_id##_dma_mask = DMA_BIT_MASK(32);            \
79 static struct platform_device _name##_id##_device = {           \
80         .name           = #_name,                               \
81         .id             = _id,                                  \
82         .dev            = {                                     \
83                 .dma_mask = &_name##_id##_dma_mask,             \
84                 .platform_data  = &_name##_id##_data,           \
85                 .coherent_dma_mask = DMA_BIT_MASK(32),          \
86         },                                                      \
87         .resource       = _name##_id##_resource,                \
88         .num_resources  = ARRAY_SIZE(_name##_id##_resource),    \
89 }
90
91 #define select_peripheral(port, pin_mask, periph, flags)        \
92         at32_select_periph(GPIO_##port##_BASE, pin_mask,        \
93                            GPIO_##periph, flags)
94
95 #define DEV_CLK(_name, devname, bus, _index)                    \
96 static struct clk devname##_##_name = {                         \
97         .name           = #_name,                               \
98         .dev            = &devname##_device.dev,                \
99         .parent         = &bus##_clk,                           \
100         .mode           = bus##_clk_mode,                       \
101         .get_rate       = bus##_clk_get_rate,                   \
102         .index          = _index,                               \
103 }
104
105 static DEFINE_SPINLOCK(pm_lock);
106
107 static struct clk osc0;
108 static struct clk osc1;
109
110 static unsigned long osc_get_rate(struct clk *clk)
111 {
112         return at32_board_osc_rates[clk->index];
113 }
114
115 static unsigned long pll_get_rate(struct clk *clk, unsigned long control)
116 {
117         unsigned long div, mul, rate;
118
119         div = PM_BFEXT(PLLDIV, control) + 1;
120         mul = PM_BFEXT(PLLMUL, control) + 1;
121
122         rate = clk->parent->get_rate(clk->parent);
123         rate = (rate + div / 2) / div;
124         rate *= mul;
125
126         return rate;
127 }
128
129 static long pll_set_rate(struct clk *clk, unsigned long rate,
130                          u32 *pll_ctrl)
131 {
132         unsigned long mul;
133         unsigned long mul_best_fit = 0;
134         unsigned long div;
135         unsigned long div_min;
136         unsigned long div_max;
137         unsigned long div_best_fit = 0;
138         unsigned long base;
139         unsigned long pll_in;
140         unsigned long actual = 0;
141         unsigned long rate_error;
142         unsigned long rate_error_prev = ~0UL;
143         u32 ctrl;
144
145         /* Rate must be between 80 MHz and 200 Mhz. */
146         if (rate < 80000000UL || rate > 200000000UL)
147                 return -EINVAL;
148
149         ctrl = PM_BF(PLLOPT, 4);
150         base = clk->parent->get_rate(clk->parent);
151
152         /* PLL input frequency must be between 6 MHz and 32 MHz. */
153         div_min = DIV_ROUND_UP(base, 32000000UL);
154         div_max = base / 6000000UL;
155
156         if (div_max < div_min)
157                 return -EINVAL;
158
159         for (div = div_min; div <= div_max; div++) {
160                 pll_in = (base + div / 2) / div;
161                 mul = (rate + pll_in / 2) / pll_in;
162
163                 if (mul == 0)
164                         continue;
165
166                 actual = pll_in * mul;
167                 rate_error = abs(actual - rate);
168
169                 if (rate_error < rate_error_prev) {
170                         mul_best_fit = mul;
171                         div_best_fit = div;
172                         rate_error_prev = rate_error;
173                 }
174
175                 if (rate_error == 0)
176                         break;
177         }
178
179         if (div_best_fit == 0)
180                 return -EINVAL;
181
182         ctrl |= PM_BF(PLLMUL, mul_best_fit - 1);
183         ctrl |= PM_BF(PLLDIV, div_best_fit - 1);
184         ctrl |= PM_BF(PLLCOUNT, 16);
185
186         if (clk->parent == &osc1)
187                 ctrl |= PM_BIT(PLLOSC);
188
189         *pll_ctrl = ctrl;
190
191         return actual;
192 }
193
194 static unsigned long pll0_get_rate(struct clk *clk)
195 {
196         u32 control;
197
198         control = pm_readl(PLL0);
199
200         return pll_get_rate(clk, control);
201 }
202
203 static void pll1_mode(struct clk *clk, int enabled)
204 {
205         unsigned long timeout;
206         u32 status;
207         u32 ctrl;
208
209         ctrl = pm_readl(PLL1);
210
211         if (enabled) {
212                 if (!PM_BFEXT(PLLMUL, ctrl) && !PM_BFEXT(PLLDIV, ctrl)) {
213                         pr_debug("clk %s: failed to enable, rate not set\n",
214                                         clk->name);
215                         return;
216                 }
217
218                 ctrl |= PM_BIT(PLLEN);
219                 pm_writel(PLL1, ctrl);
220
221                 /* Wait for PLL lock. */
222                 for (timeout = 10000; timeout; timeout--) {
223                         status = pm_readl(ISR);
224                         if (status & PM_BIT(LOCK1))
225                                 break;
226                         udelay(10);
227                 }
228
229                 if (!(status & PM_BIT(LOCK1)))
230                         printk(KERN_ERR "clk %s: timeout waiting for lock\n",
231                                         clk->name);
232         } else {
233                 ctrl &= ~PM_BIT(PLLEN);
234                 pm_writel(PLL1, ctrl);
235         }
236 }
237
238 static unsigned long pll1_get_rate(struct clk *clk)
239 {
240         u32 control;
241
242         control = pm_readl(PLL1);
243
244         return pll_get_rate(clk, control);
245 }
246
247 static long pll1_set_rate(struct clk *clk, unsigned long rate, int apply)
248 {
249         u32 ctrl = 0;
250         unsigned long actual_rate;
251
252         actual_rate = pll_set_rate(clk, rate, &ctrl);
253
254         if (apply) {
255                 if (actual_rate != rate)
256                         return -EINVAL;
257                 if (clk->users > 0)
258                         return -EBUSY;
259                 pr_debug(KERN_INFO "clk %s: new rate %lu (actual rate %lu)\n",
260                                 clk->name, rate, actual_rate);
261                 pm_writel(PLL1, ctrl);
262         }
263
264         return actual_rate;
265 }
266
267 static int pll1_set_parent(struct clk *clk, struct clk *parent)
268 {
269         u32 ctrl;
270
271         if (clk->users > 0)
272                 return -EBUSY;
273
274         ctrl = pm_readl(PLL1);
275         WARN_ON(ctrl & PM_BIT(PLLEN));
276
277         if (parent == &osc0)
278                 ctrl &= ~PM_BIT(PLLOSC);
279         else if (parent == &osc1)
280                 ctrl |= PM_BIT(PLLOSC);
281         else
282                 return -EINVAL;
283
284         pm_writel(PLL1, ctrl);
285         clk->parent = parent;
286
287         return 0;
288 }
289
290 /*
291  * The AT32AP7000 has five primary clock sources: One 32kHz
292  * oscillator, two crystal oscillators and two PLLs.
293  */
294 static struct clk osc32k = {
295         .name           = "osc32k",
296         .get_rate       = osc_get_rate,
297         .users          = 1,
298         .index          = 0,
299 };
300 static struct clk osc0 = {
301         .name           = "osc0",
302         .get_rate       = osc_get_rate,
303         .users          = 1,
304         .index          = 1,
305 };
306 static struct clk osc1 = {
307         .name           = "osc1",
308         .get_rate       = osc_get_rate,
309         .index          = 2,
310 };
311 static struct clk pll0 = {
312         .name           = "pll0",
313         .get_rate       = pll0_get_rate,
314         .parent         = &osc0,
315 };
316 static struct clk pll1 = {
317         .name           = "pll1",
318         .mode           = pll1_mode,
319         .get_rate       = pll1_get_rate,
320         .set_rate       = pll1_set_rate,
321         .set_parent     = pll1_set_parent,
322         .parent         = &osc0,
323 };
324
325 /*
326  * The main clock can be either osc0 or pll0.  The boot loader may
327  * have chosen one for us, so we don't really know which one until we
328  * have a look at the SM.
329  */
330 static struct clk *main_clock;
331
332 /*
333  * Synchronous clocks are generated from the main clock. The clocks
334  * must satisfy the constraint
335  *   fCPU >= fHSB >= fPB
336  * i.e. each clock must not be faster than its parent.
337  */
338 static unsigned long bus_clk_get_rate(struct clk *clk, unsigned int shift)
339 {
340         return main_clock->get_rate(main_clock) >> shift;
341 };
342
343 static void cpu_clk_mode(struct clk *clk, int enabled)
344 {
345         unsigned long flags;
346         u32 mask;
347
348         spin_lock_irqsave(&pm_lock, flags);
349         mask = pm_readl(CPU_MASK);
350         if (enabled)
351                 mask |= 1 << clk->index;
352         else
353                 mask &= ~(1 << clk->index);
354         pm_writel(CPU_MASK, mask);
355         spin_unlock_irqrestore(&pm_lock, flags);
356 }
357
358 static unsigned long cpu_clk_get_rate(struct clk *clk)
359 {
360         unsigned long cksel, shift = 0;
361
362         cksel = pm_readl(CKSEL);
363         if (cksel & PM_BIT(CPUDIV))
364                 shift = PM_BFEXT(CPUSEL, cksel) + 1;
365
366         return bus_clk_get_rate(clk, shift);
367 }
368
369 static long cpu_clk_set_rate(struct clk *clk, unsigned long rate, int apply)
370 {
371         u32 control;
372         unsigned long parent_rate, child_div, actual_rate, div;
373
374         parent_rate = clk->parent->get_rate(clk->parent);
375         control = pm_readl(CKSEL);
376
377         if (control & PM_BIT(HSBDIV))
378                 child_div = 1 << (PM_BFEXT(HSBSEL, control) + 1);
379         else
380                 child_div = 1;
381
382         if (rate > 3 * (parent_rate / 4) || child_div == 1) {
383                 actual_rate = parent_rate;
384                 control &= ~PM_BIT(CPUDIV);
385         } else {
386                 unsigned int cpusel;
387                 div = (parent_rate + rate / 2) / rate;
388                 if (div > child_div)
389                         div = child_div;
390                 cpusel = (div > 1) ? (fls(div) - 2) : 0;
391                 control = PM_BIT(CPUDIV) | PM_BFINS(CPUSEL, cpusel, control);
392                 actual_rate = parent_rate / (1 << (cpusel + 1));
393         }
394
395         pr_debug("clk %s: new rate %lu (actual rate %lu)\n",
396                         clk->name, rate, actual_rate);
397
398         if (apply)
399                 pm_writel(CKSEL, control);
400
401         return actual_rate;
402 }
403
404 static void hsb_clk_mode(struct clk *clk, int enabled)
405 {
406         unsigned long flags;
407         u32 mask;
408
409         spin_lock_irqsave(&pm_lock, flags);
410         mask = pm_readl(HSB_MASK);
411         if (enabled)
412                 mask |= 1 << clk->index;
413         else
414                 mask &= ~(1 << clk->index);
415         pm_writel(HSB_MASK, mask);
416         spin_unlock_irqrestore(&pm_lock, flags);
417 }
418
419 static unsigned long hsb_clk_get_rate(struct clk *clk)
420 {
421         unsigned long cksel, shift = 0;
422
423         cksel = pm_readl(CKSEL);
424         if (cksel & PM_BIT(HSBDIV))
425                 shift = PM_BFEXT(HSBSEL, cksel) + 1;
426
427         return bus_clk_get_rate(clk, shift);
428 }
429
430 void pba_clk_mode(struct clk *clk, int enabled)
431 {
432         unsigned long flags;
433         u32 mask;
434
435         spin_lock_irqsave(&pm_lock, flags);
436         mask = pm_readl(PBA_MASK);
437         if (enabled)
438                 mask |= 1 << clk->index;
439         else
440                 mask &= ~(1 << clk->index);
441         pm_writel(PBA_MASK, mask);
442         spin_unlock_irqrestore(&pm_lock, flags);
443 }
444
445 unsigned long pba_clk_get_rate(struct clk *clk)
446 {
447         unsigned long cksel, shift = 0;
448
449         cksel = pm_readl(CKSEL);
450         if (cksel & PM_BIT(PBADIV))
451                 shift = PM_BFEXT(PBASEL, cksel) + 1;
452
453         return bus_clk_get_rate(clk, shift);
454 }
455
456 static void pbb_clk_mode(struct clk *clk, int enabled)
457 {
458         unsigned long flags;
459         u32 mask;
460
461         spin_lock_irqsave(&pm_lock, flags);
462         mask = pm_readl(PBB_MASK);
463         if (enabled)
464                 mask |= 1 << clk->index;
465         else
466                 mask &= ~(1 << clk->index);
467         pm_writel(PBB_MASK, mask);
468         spin_unlock_irqrestore(&pm_lock, flags);
469 }
470
471 static unsigned long pbb_clk_get_rate(struct clk *clk)
472 {
473         unsigned long cksel, shift = 0;
474
475         cksel = pm_readl(CKSEL);
476         if (cksel & PM_BIT(PBBDIV))
477                 shift = PM_BFEXT(PBBSEL, cksel) + 1;
478
479         return bus_clk_get_rate(clk, shift);
480 }
481
482 static struct clk cpu_clk = {
483         .name           = "cpu",
484         .get_rate       = cpu_clk_get_rate,
485         .set_rate       = cpu_clk_set_rate,
486         .users          = 1,
487 };
488 static struct clk hsb_clk = {
489         .name           = "hsb",
490         .parent         = &cpu_clk,
491         .get_rate       = hsb_clk_get_rate,
492 };
493 static struct clk pba_clk = {
494         .name           = "pba",
495         .parent         = &hsb_clk,
496         .mode           = hsb_clk_mode,
497         .get_rate       = pba_clk_get_rate,
498         .index          = 1,
499 };
500 static struct clk pbb_clk = {
501         .name           = "pbb",
502         .parent         = &hsb_clk,
503         .mode           = hsb_clk_mode,
504         .get_rate       = pbb_clk_get_rate,
505         .users          = 1,
506         .index          = 2,
507 };
508
509 /* --------------------------------------------------------------------
510  *  Generic Clock operations
511  * -------------------------------------------------------------------- */
512
513 static void genclk_mode(struct clk *clk, int enabled)
514 {
515         u32 control;
516
517         control = pm_readl(GCCTRL(clk->index));
518         if (enabled)
519                 control |= PM_BIT(CEN);
520         else
521                 control &= ~PM_BIT(CEN);
522         pm_writel(GCCTRL(clk->index), control);
523 }
524
525 static unsigned long genclk_get_rate(struct clk *clk)
526 {
527         u32 control;
528         unsigned long div = 1;
529
530         control = pm_readl(GCCTRL(clk->index));
531         if (control & PM_BIT(DIVEN))
532                 div = 2 * (PM_BFEXT(DIV, control) + 1);
533
534         return clk->parent->get_rate(clk->parent) / div;
535 }
536
537 static long genclk_set_rate(struct clk *clk, unsigned long rate, int apply)
538 {
539         u32 control;
540         unsigned long parent_rate, actual_rate, div;
541
542         parent_rate = clk->parent->get_rate(clk->parent);
543         control = pm_readl(GCCTRL(clk->index));
544
545         if (rate > 3 * parent_rate / 4) {
546                 actual_rate = parent_rate;
547                 control &= ~PM_BIT(DIVEN);
548         } else {
549                 div = (parent_rate + rate) / (2 * rate) - 1;
550                 control = PM_BFINS(DIV, div, control) | PM_BIT(DIVEN);
551                 actual_rate = parent_rate / (2 * (div + 1));
552         }
553
554         dev_dbg(clk->dev, "clk %s: new rate %lu (actual rate %lu)\n",
555                 clk->name, rate, actual_rate);
556
557         if (apply)
558                 pm_writel(GCCTRL(clk->index), control);
559
560         return actual_rate;
561 }
562
563 int genclk_set_parent(struct clk *clk, struct clk *parent)
564 {
565         u32 control;
566
567         dev_dbg(clk->dev, "clk %s: new parent %s (was %s)\n",
568                 clk->name, parent->name, clk->parent->name);
569
570         control = pm_readl(GCCTRL(clk->index));
571
572         if (parent == &osc1 || parent == &pll1)
573                 control |= PM_BIT(OSCSEL);
574         else if (parent == &osc0 || parent == &pll0)
575                 control &= ~PM_BIT(OSCSEL);
576         else
577                 return -EINVAL;
578
579         if (parent == &pll0 || parent == &pll1)
580                 control |= PM_BIT(PLLSEL);
581         else
582                 control &= ~PM_BIT(PLLSEL);
583
584         pm_writel(GCCTRL(clk->index), control);
585         clk->parent = parent;
586
587         return 0;
588 }
589
590 static void __init genclk_init_parent(struct clk *clk)
591 {
592         u32 control;
593         struct clk *parent;
594
595         BUG_ON(clk->index > 7);
596
597         control = pm_readl(GCCTRL(clk->index));
598         if (control & PM_BIT(OSCSEL))
599                 parent = (control & PM_BIT(PLLSEL)) ? &pll1 : &osc1;
600         else
601                 parent = (control & PM_BIT(PLLSEL)) ? &pll0 : &osc0;
602
603         clk->parent = parent;
604 }
605
606 static struct dw_dma_platform_data dw_dmac0_data = {
607         .nr_channels    = 3,
608 };
609
610 static struct resource dw_dmac0_resource[] = {
611         PBMEM(0xff200000),
612         IRQ(2),
613 };
614 DEFINE_DEV_DATA(dw_dmac, 0);
615 DEV_CLK(hclk, dw_dmac0, hsb, 10);
616
617 /* --------------------------------------------------------------------
618  *  System peripherals
619  * -------------------------------------------------------------------- */
620 static struct resource at32_pm0_resource[] = {
621         {
622                 .start  = 0xfff00000,
623                 .end    = 0xfff0007f,
624                 .flags  = IORESOURCE_MEM,
625         },
626         IRQ(20),
627 };
628
629 static struct resource at32ap700x_rtc0_resource[] = {
630         {
631                 .start  = 0xfff00080,
632                 .end    = 0xfff000af,
633                 .flags  = IORESOURCE_MEM,
634         },
635         IRQ(21),
636 };
637
638 static struct resource at32_wdt0_resource[] = {
639         {
640                 .start  = 0xfff000b0,
641                 .end    = 0xfff000cf,
642                 .flags  = IORESOURCE_MEM,
643         },
644 };
645
646 static struct resource at32_eic0_resource[] = {
647         {
648                 .start  = 0xfff00100,
649                 .end    = 0xfff0013f,
650                 .flags  = IORESOURCE_MEM,
651         },
652         IRQ(19),
653 };
654
655 DEFINE_DEV(at32_pm, 0);
656 DEFINE_DEV(at32ap700x_rtc, 0);
657 DEFINE_DEV(at32_wdt, 0);
658 DEFINE_DEV(at32_eic, 0);
659
660 /*
661  * Peripheral clock for PM, RTC, WDT and EIC. PM will ensure that this
662  * is always running.
663  */
664 static struct clk at32_pm_pclk = {
665         .name           = "pclk",
666         .dev            = &at32_pm0_device.dev,
667         .parent         = &pbb_clk,
668         .mode           = pbb_clk_mode,
669         .get_rate       = pbb_clk_get_rate,
670         .users          = 1,
671         .index          = 0,
672 };
673
674 static struct resource intc0_resource[] = {
675         PBMEM(0xfff00400),
676 };
677 struct platform_device at32_intc0_device = {
678         .name           = "intc",
679         .id             = 0,
680         .resource       = intc0_resource,
681         .num_resources  = ARRAY_SIZE(intc0_resource),
682 };
683 DEV_CLK(pclk, at32_intc0, pbb, 1);
684
685 static struct clk ebi_clk = {
686         .name           = "ebi",
687         .parent         = &hsb_clk,
688         .mode           = hsb_clk_mode,
689         .get_rate       = hsb_clk_get_rate,
690         .users          = 1,
691 };
692 static struct clk hramc_clk = {
693         .name           = "hramc",
694         .parent         = &hsb_clk,
695         .mode           = hsb_clk_mode,
696         .get_rate       = hsb_clk_get_rate,
697         .users          = 1,
698         .index          = 3,
699 };
700 static struct clk sdramc_clk = {
701         .name           = "sdramc_clk",
702         .parent         = &pbb_clk,
703         .mode           = pbb_clk_mode,
704         .get_rate       = pbb_clk_get_rate,
705         .users          = 1,
706         .index          = 14,
707 };
708
709 static struct resource smc0_resource[] = {
710         PBMEM(0xfff03400),
711 };
712 DEFINE_DEV(smc, 0);
713 DEV_CLK(pclk, smc0, pbb, 13);
714 DEV_CLK(mck, smc0, hsb, 0);
715
716 static struct platform_device pdc_device = {
717         .name           = "pdc",
718         .id             = 0,
719 };
720 DEV_CLK(hclk, pdc, hsb, 4);
721 DEV_CLK(pclk, pdc, pba, 16);
722
723 static struct clk pico_clk = {
724         .name           = "pico",
725         .parent         = &cpu_clk,
726         .mode           = cpu_clk_mode,
727         .get_rate       = cpu_clk_get_rate,
728         .users          = 1,
729 };
730
731 /* --------------------------------------------------------------------
732  * HMATRIX
733  * -------------------------------------------------------------------- */
734
735 struct clk at32_hmatrix_clk = {
736         .name           = "hmatrix_clk",
737         .parent         = &pbb_clk,
738         .mode           = pbb_clk_mode,
739         .get_rate       = pbb_clk_get_rate,
740         .index          = 2,
741         .users          = 1,
742 };
743
744 /*
745  * Set bits in the HMATRIX Special Function Register (SFR) used by the
746  * External Bus Interface (EBI). This can be used to enable special
747  * features like CompactFlash support, NAND Flash support, etc. on
748  * certain chipselects.
749  */
750 static inline void set_ebi_sfr_bits(u32 mask)
751 {
752         hmatrix_sfr_set_bits(HMATRIX_SLAVE_EBI, mask);
753 }
754
755 /* --------------------------------------------------------------------
756  *  Timer/Counter (TC)
757  * -------------------------------------------------------------------- */
758
759 static struct resource at32_tcb0_resource[] = {
760         PBMEM(0xfff00c00),
761         IRQ(22),
762 };
763 static struct platform_device at32_tcb0_device = {
764         .name           = "atmel_tcb",
765         .id             = 0,
766         .resource       = at32_tcb0_resource,
767         .num_resources  = ARRAY_SIZE(at32_tcb0_resource),
768 };
769 DEV_CLK(t0_clk, at32_tcb0, pbb, 3);
770
771 static struct resource at32_tcb1_resource[] = {
772         PBMEM(0xfff01000),
773         IRQ(23),
774 };
775 static struct platform_device at32_tcb1_device = {
776         .name           = "atmel_tcb",
777         .id             = 1,
778         .resource       = at32_tcb1_resource,
779         .num_resources  = ARRAY_SIZE(at32_tcb1_resource),
780 };
781 DEV_CLK(t0_clk, at32_tcb1, pbb, 4);
782
783 /* --------------------------------------------------------------------
784  *  PIO
785  * -------------------------------------------------------------------- */
786
787 static struct resource pio0_resource[] = {
788         PBMEM(0xffe02800),
789         IRQ(13),
790 };
791 DEFINE_DEV(pio, 0);
792 DEV_CLK(mck, pio0, pba, 10);
793
794 static struct resource pio1_resource[] = {
795         PBMEM(0xffe02c00),
796         IRQ(14),
797 };
798 DEFINE_DEV(pio, 1);
799 DEV_CLK(mck, pio1, pba, 11);
800
801 static struct resource pio2_resource[] = {
802         PBMEM(0xffe03000),
803         IRQ(15),
804 };
805 DEFINE_DEV(pio, 2);
806 DEV_CLK(mck, pio2, pba, 12);
807
808 static struct resource pio3_resource[] = {
809         PBMEM(0xffe03400),
810         IRQ(16),
811 };
812 DEFINE_DEV(pio, 3);
813 DEV_CLK(mck, pio3, pba, 13);
814
815 static struct resource pio4_resource[] = {
816         PBMEM(0xffe03800),
817         IRQ(17),
818 };
819 DEFINE_DEV(pio, 4);
820 DEV_CLK(mck, pio4, pba, 14);
821
822 static int __init system_device_init(void)
823 {
824         platform_device_register(&at32_pm0_device);
825         platform_device_register(&at32_intc0_device);
826         platform_device_register(&at32ap700x_rtc0_device);
827         platform_device_register(&at32_wdt0_device);
828         platform_device_register(&at32_eic0_device);
829         platform_device_register(&smc0_device);
830         platform_device_register(&pdc_device);
831         platform_device_register(&dw_dmac0_device);
832
833         platform_device_register(&at32_tcb0_device);
834         platform_device_register(&at32_tcb1_device);
835
836         platform_device_register(&pio0_device);
837         platform_device_register(&pio1_device);
838         platform_device_register(&pio2_device);
839         platform_device_register(&pio3_device);
840         platform_device_register(&pio4_device);
841
842         return 0;
843 }
844 core_initcall(system_device_init);
845
846 /* --------------------------------------------------------------------
847  *  PSIF
848  * -------------------------------------------------------------------- */
849 static struct resource atmel_psif0_resource[] __initdata = {
850         {
851                 .start  = 0xffe03c00,
852                 .end    = 0xffe03cff,
853                 .flags  = IORESOURCE_MEM,
854         },
855         IRQ(18),
856 };
857 static struct clk atmel_psif0_pclk = {
858         .name           = "pclk",
859         .parent         = &pba_clk,
860         .mode           = pba_clk_mode,
861         .get_rate       = pba_clk_get_rate,
862         .index          = 15,
863 };
864
865 static struct resource atmel_psif1_resource[] __initdata = {
866         {
867                 .start  = 0xffe03d00,
868                 .end    = 0xffe03dff,
869                 .flags  = IORESOURCE_MEM,
870         },
871         IRQ(18),
872 };
873 static struct clk atmel_psif1_pclk = {
874         .name           = "pclk",
875         .parent         = &pba_clk,
876         .mode           = pba_clk_mode,
877         .get_rate       = pba_clk_get_rate,
878         .index          = 15,
879 };
880
881 struct platform_device *__init at32_add_device_psif(unsigned int id)
882 {
883         struct platform_device *pdev;
884         u32 pin_mask;
885
886         if (!(id == 0 || id == 1))
887                 return NULL;
888
889         pdev = platform_device_alloc("atmel_psif", id);
890         if (!pdev)
891                 return NULL;
892
893         switch (id) {
894         case 0:
895                 pin_mask  = (1 << 8) | (1 << 9); /* CLOCK & DATA */
896
897                 if (platform_device_add_resources(pdev, atmel_psif0_resource,
898                                         ARRAY_SIZE(atmel_psif0_resource)))
899                         goto err_add_resources;
900                 atmel_psif0_pclk.dev = &pdev->dev;
901                 select_peripheral(PIOA, pin_mask, PERIPH_A, 0);
902                 break;
903         case 1:
904                 pin_mask  = (1 << 11) | (1 << 12); /* CLOCK & DATA */
905
906                 if (platform_device_add_resources(pdev, atmel_psif1_resource,
907                                         ARRAY_SIZE(atmel_psif1_resource)))
908                         goto err_add_resources;
909                 atmel_psif1_pclk.dev = &pdev->dev;
910                 select_peripheral(PIOB, pin_mask, PERIPH_A, 0);
911                 break;
912         default:
913                 return NULL;
914         }
915
916         platform_device_add(pdev);
917         return pdev;
918
919 err_add_resources:
920         platform_device_put(pdev);
921         return NULL;
922 }
923
924 /* --------------------------------------------------------------------
925  *  USART
926  * -------------------------------------------------------------------- */
927
928 static struct atmel_uart_data atmel_usart0_data = {
929         .use_dma_tx     = 1,
930         .use_dma_rx     = 1,
931 };
932 static struct resource atmel_usart0_resource[] = {
933         PBMEM(0xffe00c00),
934         IRQ(6),
935 };
936 DEFINE_DEV_DATA(atmel_usart, 0);
937 DEV_CLK(usart, atmel_usart0, pba, 3);
938
939 static struct atmel_uart_data atmel_usart1_data = {
940         .use_dma_tx     = 1,
941         .use_dma_rx     = 1,
942 };
943 static struct resource atmel_usart1_resource[] = {
944         PBMEM(0xffe01000),
945         IRQ(7),
946 };
947 DEFINE_DEV_DATA(atmel_usart, 1);
948 DEV_CLK(usart, atmel_usart1, pba, 4);
949
950 static struct atmel_uart_data atmel_usart2_data = {
951         .use_dma_tx     = 1,
952         .use_dma_rx     = 1,
953 };
954 static struct resource atmel_usart2_resource[] = {
955         PBMEM(0xffe01400),
956         IRQ(8),
957 };
958 DEFINE_DEV_DATA(atmel_usart, 2);
959 DEV_CLK(usart, atmel_usart2, pba, 5);
960
961 static struct atmel_uart_data atmel_usart3_data = {
962         .use_dma_tx     = 1,
963         .use_dma_rx     = 1,
964 };
965 static struct resource atmel_usart3_resource[] = {
966         PBMEM(0xffe01800),
967         IRQ(9),
968 };
969 DEFINE_DEV_DATA(atmel_usart, 3);
970 DEV_CLK(usart, atmel_usart3, pba, 6);
971
972 static inline void configure_usart0_pins(int flags)
973 {
974         u32 pin_mask = (1 << 8) | (1 << 9); /* RXD & TXD */
975         if (flags & ATMEL_USART_RTS)    pin_mask |= (1 << 6);
976         if (flags & ATMEL_USART_CTS)    pin_mask |= (1 << 7);
977         if (flags & ATMEL_USART_CLK)    pin_mask |= (1 << 10);
978
979         select_peripheral(PIOA, pin_mask, PERIPH_B, AT32_GPIOF_PULLUP);
980 }
981
982 static inline void configure_usart1_pins(int flags)
983 {
984         u32 pin_mask = (1 << 17) | (1 << 18); /* RXD & TXD */
985         if (flags & ATMEL_USART_RTS)    pin_mask |= (1 << 19);
986         if (flags & ATMEL_USART_CTS)    pin_mask |= (1 << 20);
987         if (flags & ATMEL_USART_CLK)    pin_mask |= (1 << 16);
988
989         select_peripheral(PIOA, pin_mask, PERIPH_A, AT32_GPIOF_PULLUP);
990 }
991
992 static inline void configure_usart2_pins(int flags)
993 {
994         u32 pin_mask = (1 << 26) | (1 << 27); /* RXD & TXD */
995         if (flags & ATMEL_USART_RTS)    pin_mask |= (1 << 30);
996         if (flags & ATMEL_USART_CTS)    pin_mask |= (1 << 29);
997         if (flags & ATMEL_USART_CLK)    pin_mask |= (1 << 28);
998
999         select_peripheral(PIOB, pin_mask, PERIPH_B, AT32_GPIOF_PULLUP);
1000 }
1001
1002 static inline void configure_usart3_pins(int flags)
1003 {
1004         u32 pin_mask = (1 << 18) | (1 << 17); /* RXD & TXD */
1005         if (flags & ATMEL_USART_RTS)    pin_mask |= (1 << 16);
1006         if (flags & ATMEL_USART_CTS)    pin_mask |= (1 << 15);
1007         if (flags & ATMEL_USART_CLK)    pin_mask |= (1 << 19);
1008
1009         select_peripheral(PIOB, pin_mask, PERIPH_B, AT32_GPIOF_PULLUP);
1010 }
1011
1012 static struct platform_device *__initdata at32_usarts[4];
1013
1014 void __init at32_map_usart(unsigned int hw_id, unsigned int line, int flags)
1015 {
1016         struct platform_device *pdev;
1017
1018         switch (hw_id) {
1019         case 0:
1020                 pdev = &atmel_usart0_device;
1021                 configure_usart0_pins(flags);
1022                 break;
1023         case 1:
1024                 pdev = &atmel_usart1_device;
1025                 configure_usart1_pins(flags);
1026                 break;
1027         case 2:
1028                 pdev = &atmel_usart2_device;
1029                 configure_usart2_pins(flags);
1030                 break;
1031         case 3:
1032                 pdev = &atmel_usart3_device;
1033                 configure_usart3_pins(flags);
1034                 break;
1035         default:
1036                 return;
1037         }
1038
1039         if (PXSEG(pdev->resource[0].start) == P4SEG) {
1040                 /* Addresses in the P4 segment are permanently mapped 1:1 */
1041                 struct atmel_uart_data *data = pdev->dev.platform_data;
1042                 data->regs = (void __iomem *)pdev->resource[0].start;
1043         }
1044
1045         pdev->id = line;
1046         at32_usarts[line] = pdev;
1047 }
1048
1049 struct platform_device *__init at32_add_device_usart(unsigned int id)
1050 {
1051         platform_device_register(at32_usarts[id]);
1052         return at32_usarts[id];
1053 }
1054
1055 struct platform_device *atmel_default_console_device;
1056
1057 void __init at32_setup_serial_console(unsigned int usart_id)
1058 {
1059         atmel_default_console_device = at32_usarts[usart_id];
1060 }
1061
1062 /* --------------------------------------------------------------------
1063  *  Ethernet
1064  * -------------------------------------------------------------------- */
1065
1066 #ifdef CONFIG_CPU_AT32AP7000
1067 static struct eth_platform_data macb0_data;
1068 static struct resource macb0_resource[] = {
1069         PBMEM(0xfff01800),
1070         IRQ(25),
1071 };
1072 DEFINE_DEV_DATA(macb, 0);
1073 DEV_CLK(hclk, macb0, hsb, 8);
1074 DEV_CLK(pclk, macb0, pbb, 6);
1075
1076 static struct eth_platform_data macb1_data;
1077 static struct resource macb1_resource[] = {
1078         PBMEM(0xfff01c00),
1079         IRQ(26),
1080 };
1081 DEFINE_DEV_DATA(macb, 1);
1082 DEV_CLK(hclk, macb1, hsb, 9);
1083 DEV_CLK(pclk, macb1, pbb, 7);
1084
1085 struct platform_device *__init
1086 at32_add_device_eth(unsigned int id, struct eth_platform_data *data)
1087 {
1088         struct platform_device *pdev;
1089         u32 pin_mask;
1090
1091         switch (id) {
1092         case 0:
1093                 pdev = &macb0_device;
1094
1095                 pin_mask  = (1 << 3);   /* TXD0 */
1096                 pin_mask |= (1 << 4);   /* TXD1 */
1097                 pin_mask |= (1 << 7);   /* TXEN */
1098                 pin_mask |= (1 << 8);   /* TXCK */
1099                 pin_mask |= (1 << 9);   /* RXD0 */
1100                 pin_mask |= (1 << 10);  /* RXD1 */
1101                 pin_mask |= (1 << 13);  /* RXER */
1102                 pin_mask |= (1 << 15);  /* RXDV */
1103                 pin_mask |= (1 << 16);  /* MDC  */
1104                 pin_mask |= (1 << 17);  /* MDIO */
1105
1106                 if (!data->is_rmii) {
1107                         pin_mask |= (1 << 0);   /* COL  */
1108                         pin_mask |= (1 << 1);   /* CRS  */
1109                         pin_mask |= (1 << 2);   /* TXER */
1110                         pin_mask |= (1 << 5);   /* TXD2 */
1111                         pin_mask |= (1 << 6);   /* TXD3 */
1112                         pin_mask |= (1 << 11);  /* RXD2 */
1113                         pin_mask |= (1 << 12);  /* RXD3 */
1114                         pin_mask |= (1 << 14);  /* RXCK */
1115 #ifndef CONFIG_BOARD_MIMC200
1116                         pin_mask |= (1 << 18);  /* SPD  */
1117 #endif
1118                 }
1119
1120                 select_peripheral(PIOC, pin_mask, PERIPH_A, 0);
1121
1122                 break;
1123
1124         case 1:
1125                 pdev = &macb1_device;
1126
1127                 pin_mask  = (1 << 13);  /* TXD0 */
1128                 pin_mask |= (1 << 14);  /* TXD1 */
1129                 pin_mask |= (1 << 11);  /* TXEN */
1130                 pin_mask |= (1 << 12);  /* TXCK */
1131                 pin_mask |= (1 << 10);  /* RXD0 */
1132                 pin_mask |= (1 << 6);   /* RXD1 */
1133                 pin_mask |= (1 << 5);   /* RXER */
1134                 pin_mask |= (1 << 4);   /* RXDV */
1135                 pin_mask |= (1 << 3);   /* MDC  */
1136                 pin_mask |= (1 << 2);   /* MDIO */
1137
1138 #ifndef CONFIG_BOARD_MIMC200
1139                 if (!data->is_rmii)
1140                         pin_mask |= (1 << 15);  /* SPD  */
1141 #endif
1142
1143                 select_peripheral(PIOD, pin_mask, PERIPH_B, 0);
1144
1145                 if (!data->is_rmii) {
1146                         pin_mask  = (1 << 19);  /* COL  */
1147                         pin_mask |= (1 << 23);  /* CRS  */
1148                         pin_mask |= (1 << 26);  /* TXER */
1149                         pin_mask |= (1 << 27);  /* TXD2 */
1150                         pin_mask |= (1 << 28);  /* TXD3 */
1151                         pin_mask |= (1 << 29);  /* RXD2 */
1152                         pin_mask |= (1 << 30);  /* RXD3 */
1153                         pin_mask |= (1 << 24);  /* RXCK */
1154
1155                         select_peripheral(PIOC, pin_mask, PERIPH_B, 0);
1156                 }
1157                 break;
1158
1159         default:
1160                 return NULL;
1161         }
1162
1163         memcpy(pdev->dev.platform_data, data, sizeof(struct eth_platform_data));
1164         platform_device_register(pdev);
1165
1166         return pdev;
1167 }
1168 #endif
1169
1170 /* --------------------------------------------------------------------
1171  *  SPI
1172  * -------------------------------------------------------------------- */
1173 static struct resource atmel_spi0_resource[] = {
1174         PBMEM(0xffe00000),
1175         IRQ(3),
1176 };
1177 DEFINE_DEV(atmel_spi, 0);
1178 DEV_CLK(spi_clk, atmel_spi0, pba, 0);
1179
1180 static struct resource atmel_spi1_resource[] = {
1181         PBMEM(0xffe00400),
1182         IRQ(4),
1183 };
1184 DEFINE_DEV(atmel_spi, 1);
1185 DEV_CLK(spi_clk, atmel_spi1, pba, 1);
1186
1187 void __init
1188 at32_spi_setup_slaves(unsigned int bus_num, struct spi_board_info *b, unsigned int n)
1189 {
1190         /*
1191          * Manage the chipselects as GPIOs, normally using the same pins
1192          * the SPI controller expects; but boards can use other pins.
1193          */
1194         static u8 __initdata spi_pins[][4] = {
1195                 { GPIO_PIN_PA(3), GPIO_PIN_PA(4),
1196                   GPIO_PIN_PA(5), GPIO_PIN_PA(20) },
1197                 { GPIO_PIN_PB(2), GPIO_PIN_PB(3),
1198                   GPIO_PIN_PB(4), GPIO_PIN_PA(27) },
1199         };
1200         unsigned int pin, mode;
1201
1202         /* There are only 2 SPI controllers */
1203         if (bus_num > 1)
1204                 return;
1205
1206         for (; n; n--, b++) {
1207                 b->bus_num = bus_num;
1208                 if (b->chip_select >= 4)
1209                         continue;
1210                 pin = (unsigned)b->controller_data;
1211                 if (!pin) {
1212                         pin = spi_pins[bus_num][b->chip_select];
1213                         b->controller_data = (void *)pin;
1214                 }
1215                 mode = AT32_GPIOF_OUTPUT;
1216                 if (!(b->mode & SPI_CS_HIGH))
1217                         mode |= AT32_GPIOF_HIGH;
1218                 at32_select_gpio(pin, mode);
1219         }
1220 }
1221
1222 struct platform_device *__init
1223 at32_add_device_spi(unsigned int id, struct spi_board_info *b, unsigned int n)
1224 {
1225         struct platform_device *pdev;
1226         u32 pin_mask;
1227
1228         switch (id) {
1229         case 0:
1230                 pdev = &atmel_spi0_device;
1231                 pin_mask  = (1 << 1) | (1 << 2);        /* MOSI & SCK */
1232
1233                 /* pullup MISO so a level is always defined */
1234                 select_peripheral(PIOA, (1 << 0), PERIPH_A, AT32_GPIOF_PULLUP);
1235                 select_peripheral(PIOA, pin_mask, PERIPH_A, 0);
1236
1237                 at32_spi_setup_slaves(0, b, n);
1238                 break;
1239
1240         case 1:
1241                 pdev = &atmel_spi1_device;
1242                 pin_mask  = (1 << 1) | (1 << 5);        /* MOSI */
1243
1244                 /* pullup MISO so a level is always defined */
1245                 select_peripheral(PIOB, (1 << 0), PERIPH_B, AT32_GPIOF_PULLUP);
1246                 select_peripheral(PIOB, pin_mask, PERIPH_B, 0);
1247
1248                 at32_spi_setup_slaves(1, b, n);
1249                 break;
1250
1251         default:
1252                 return NULL;
1253         }
1254
1255         spi_register_board_info(b, n);
1256         platform_device_register(pdev);
1257         return pdev;
1258 }
1259
1260 /* --------------------------------------------------------------------
1261  *  TWI
1262  * -------------------------------------------------------------------- */
1263 static struct resource atmel_twi0_resource[] __initdata = {
1264         PBMEM(0xffe00800),
1265         IRQ(5),
1266 };
1267 static struct clk atmel_twi0_pclk = {
1268         .name           = "twi_pclk",
1269         .parent         = &pba_clk,
1270         .mode           = pba_clk_mode,
1271         .get_rate       = pba_clk_get_rate,
1272         .index          = 2,
1273 };
1274
1275 struct platform_device *__init at32_add_device_twi(unsigned int id,
1276                                                     struct i2c_board_info *b,
1277                                                     unsigned int n)
1278 {
1279         struct platform_device *pdev;
1280         u32 pin_mask;
1281
1282         if (id != 0)
1283                 return NULL;
1284
1285         pdev = platform_device_alloc("atmel_twi", id);
1286         if (!pdev)
1287                 return NULL;
1288
1289         if (platform_device_add_resources(pdev, atmel_twi0_resource,
1290                                 ARRAY_SIZE(atmel_twi0_resource)))
1291                 goto err_add_resources;
1292
1293         pin_mask  = (1 << 6) | (1 << 7);        /* SDA & SDL */
1294
1295         select_peripheral(PIOA, pin_mask, PERIPH_A, 0);
1296
1297         atmel_twi0_pclk.dev = &pdev->dev;
1298
1299         if (b)
1300                 i2c_register_board_info(id, b, n);
1301
1302         platform_device_add(pdev);
1303         return pdev;
1304
1305 err_add_resources:
1306         platform_device_put(pdev);
1307         return NULL;
1308 }
1309
1310 /* --------------------------------------------------------------------
1311  * MMC
1312  * -------------------------------------------------------------------- */
1313 static struct resource atmel_mci0_resource[] __initdata = {
1314         PBMEM(0xfff02400),
1315         IRQ(28),
1316 };
1317 static struct clk atmel_mci0_pclk = {
1318         .name           = "mci_clk",
1319         .parent         = &pbb_clk,
1320         .mode           = pbb_clk_mode,
1321         .get_rate       = pbb_clk_get_rate,
1322         .index          = 9,
1323 };
1324
1325 struct platform_device *__init
1326 at32_add_device_mci(unsigned int id, struct mci_platform_data *data)
1327 {
1328         struct platform_device          *pdev;
1329         struct mci_dma_data             *slave;
1330         u32                             pioa_mask;
1331         u32                             piob_mask;
1332
1333         if (id != 0 || !data)
1334                 return NULL;
1335
1336         /* Must have at least one usable slot */
1337         if (!data->slot[0].bus_width && !data->slot[1].bus_width)
1338                 return NULL;
1339
1340         pdev = platform_device_alloc("atmel_mci", id);
1341         if (!pdev)
1342                 goto fail;
1343
1344         if (platform_device_add_resources(pdev, atmel_mci0_resource,
1345                                 ARRAY_SIZE(atmel_mci0_resource)))
1346                 goto fail;
1347
1348         slave = kzalloc(sizeof(struct mci_dma_data), GFP_KERNEL);
1349         if (!slave)
1350                 goto fail;
1351
1352         slave->sdata.dma_dev = &dw_dmac0_device.dev;
1353         slave->sdata.reg_width = DW_DMA_SLAVE_WIDTH_32BIT;
1354         slave->sdata.cfg_hi = (DWC_CFGH_SRC_PER(0)
1355                                 | DWC_CFGH_DST_PER(1));
1356         slave->sdata.cfg_lo &= ~(DWC_CFGL_HS_DST_POL
1357                                 | DWC_CFGL_HS_SRC_POL);
1358
1359         data->dma_slave = slave;
1360
1361         if (platform_device_add_data(pdev, data,
1362                                 sizeof(struct mci_platform_data)))
1363                 goto fail_free;
1364
1365         /* CLK line is common to both slots */
1366         pioa_mask = 1 << 10;
1367
1368         switch (data->slot[0].bus_width) {
1369         case 4:
1370                 pioa_mask |= 1 << 13;           /* DATA1 */
1371                 pioa_mask |= 1 << 14;           /* DATA2 */
1372                 pioa_mask |= 1 << 15;           /* DATA3 */
1373                 /* fall through */
1374         case 1:
1375                 pioa_mask |= 1 << 11;           /* CMD   */
1376                 pioa_mask |= 1 << 12;           /* DATA0 */
1377
1378                 if (gpio_is_valid(data->slot[0].detect_pin))
1379                         at32_select_gpio(data->slot[0].detect_pin, 0);
1380                 if (gpio_is_valid(data->slot[0].wp_pin))
1381                         at32_select_gpio(data->slot[0].wp_pin, 0);
1382                 break;
1383         case 0:
1384                 /* Slot is unused */
1385                 break;
1386         default:
1387                 goto fail_free;
1388         }
1389
1390         select_peripheral(PIOA, pioa_mask, PERIPH_A, 0);
1391         piob_mask = 0;
1392
1393         switch (data->slot[1].bus_width) {
1394         case 4:
1395                 piob_mask |= 1 <<  8;           /* DATA1 */
1396                 piob_mask |= 1 <<  9;           /* DATA2 */
1397                 piob_mask |= 1 << 10;           /* DATA3 */
1398                 /* fall through */
1399         case 1:
1400                 piob_mask |= 1 <<  6;           /* CMD   */
1401                 piob_mask |= 1 <<  7;           /* DATA0 */
1402                 select_peripheral(PIOB, piob_mask, PERIPH_B, 0);
1403
1404                 if (gpio_is_valid(data->slot[1].detect_pin))
1405                         at32_select_gpio(data->slot[1].detect_pin, 0);
1406                 if (gpio_is_valid(data->slot[1].wp_pin))
1407                         at32_select_gpio(data->slot[1].wp_pin, 0);
1408                 break;
1409         case 0:
1410                 /* Slot is unused */
1411                 break;
1412         default:
1413                 if (!data->slot[0].bus_width)
1414                         goto fail_free;
1415
1416                 data->slot[1].bus_width = 0;
1417                 break;
1418         }
1419
1420         atmel_mci0_pclk.dev = &pdev->dev;
1421
1422         platform_device_add(pdev);
1423         return pdev;
1424
1425 fail_free:
1426         kfree(slave);
1427 fail:
1428         data->dma_slave = NULL;
1429         platform_device_put(pdev);
1430         return NULL;
1431 }
1432
1433 /* --------------------------------------------------------------------
1434  *  LCDC
1435  * -------------------------------------------------------------------- */
1436 #if defined(CONFIG_CPU_AT32AP7000) || defined(CONFIG_CPU_AT32AP7002)
1437 static struct atmel_lcdfb_info atmel_lcdfb0_data;
1438 static struct resource atmel_lcdfb0_resource[] = {
1439         {
1440                 .start          = 0xff000000,
1441                 .end            = 0xff000fff,
1442                 .flags          = IORESOURCE_MEM,
1443         },
1444         IRQ(1),
1445         {
1446                 /* Placeholder for pre-allocated fb memory */
1447                 .start          = 0x00000000,
1448                 .end            = 0x00000000,
1449                 .flags          = 0,
1450         },
1451 };
1452 DEFINE_DEV_DATA(atmel_lcdfb, 0);
1453 DEV_CLK(hck1, atmel_lcdfb0, hsb, 7);
1454 static struct clk atmel_lcdfb0_pixclk = {
1455         .name           = "lcdc_clk",
1456         .dev            = &atmel_lcdfb0_device.dev,
1457         .mode           = genclk_mode,
1458         .get_rate       = genclk_get_rate,
1459         .set_rate       = genclk_set_rate,
1460         .set_parent     = genclk_set_parent,
1461         .index          = 7,
1462 };
1463
1464 struct platform_device *__init
1465 at32_add_device_lcdc(unsigned int id, struct atmel_lcdfb_info *data,
1466                      unsigned long fbmem_start, unsigned long fbmem_len,
1467                      u64 pin_mask)
1468 {
1469         struct platform_device *pdev;
1470         struct atmel_lcdfb_info *info;
1471         struct fb_monspecs *monspecs;
1472         struct fb_videomode *modedb;
1473         unsigned int modedb_size;
1474         u32 portc_mask, portd_mask, porte_mask;
1475
1476         /*
1477          * Do a deep copy of the fb data, monspecs and modedb. Make
1478          * sure all allocations are done before setting up the
1479          * portmux.
1480          */
1481         monspecs = kmemdup(data->default_monspecs,
1482                            sizeof(struct fb_monspecs), GFP_KERNEL);
1483         if (!monspecs)
1484                 return NULL;
1485
1486         modedb_size = sizeof(struct fb_videomode) * monspecs->modedb_len;
1487         modedb = kmemdup(monspecs->modedb, modedb_size, GFP_KERNEL);
1488         if (!modedb)
1489                 goto err_dup_modedb;
1490         monspecs->modedb = modedb;
1491
1492         switch (id) {
1493         case 0:
1494                 pdev = &atmel_lcdfb0_device;
1495
1496                 if (pin_mask == 0ULL)
1497                         /* Default to "full" lcdc control signals and 24bit */
1498                         pin_mask = ATMEL_LCDC_PRI_24BIT | ATMEL_LCDC_PRI_CONTROL;
1499
1500                 /* LCDC on port C */
1501                 portc_mask = pin_mask & 0xfff80000;
1502                 select_peripheral(PIOC, portc_mask, PERIPH_A, 0);
1503
1504                 /* LCDC on port D */
1505                 portd_mask = pin_mask & 0x0003ffff;
1506                 select_peripheral(PIOD, portd_mask, PERIPH_A, 0);
1507
1508                 /* LCDC on port E */
1509                 porte_mask = (pin_mask >> 32) & 0x0007ffff;
1510                 select_peripheral(PIOE, porte_mask, PERIPH_B, 0);
1511
1512                 clk_set_parent(&atmel_lcdfb0_pixclk, &pll0);
1513                 clk_set_rate(&atmel_lcdfb0_pixclk, clk_get_rate(&pll0));
1514                 break;
1515
1516         default:
1517                 goto err_invalid_id;
1518         }
1519
1520         if (fbmem_len) {
1521                 pdev->resource[2].start = fbmem_start;
1522                 pdev->resource[2].end = fbmem_start + fbmem_len - 1;
1523                 pdev->resource[2].flags = IORESOURCE_MEM;
1524         }
1525
1526         info = pdev->dev.platform_data;
1527         memcpy(info, data, sizeof(struct atmel_lcdfb_info));
1528         info->default_monspecs = monspecs;
1529
1530         platform_device_register(pdev);
1531         return pdev;
1532
1533 err_invalid_id:
1534         kfree(modedb);
1535 err_dup_modedb:
1536         kfree(monspecs);
1537         return NULL;
1538 }
1539 #endif
1540
1541 /* --------------------------------------------------------------------
1542  *  PWM
1543  * -------------------------------------------------------------------- */
1544 static struct resource atmel_pwm0_resource[] __initdata = {
1545         PBMEM(0xfff01400),
1546         IRQ(24),
1547 };
1548 static struct clk atmel_pwm0_mck = {
1549         .name           = "pwm_clk",
1550         .parent         = &pbb_clk,
1551         .mode           = pbb_clk_mode,
1552         .get_rate       = pbb_clk_get_rate,
1553         .index          = 5,
1554 };
1555
1556 struct platform_device *__init at32_add_device_pwm(u32 mask)
1557 {
1558         struct platform_device *pdev;
1559         u32 pin_mask;
1560
1561         if (!mask)
1562                 return NULL;
1563
1564         pdev = platform_device_alloc("atmel_pwm", 0);
1565         if (!pdev)
1566                 return NULL;
1567
1568         if (platform_device_add_resources(pdev, atmel_pwm0_resource,
1569                                 ARRAY_SIZE(atmel_pwm0_resource)))
1570                 goto out_free_pdev;
1571
1572         if (platform_device_add_data(pdev, &mask, sizeof(mask)))
1573                 goto out_free_pdev;
1574
1575         pin_mask = 0;
1576         if (mask & (1 << 0))
1577                 pin_mask |= (1 << 28);
1578         if (mask & (1 << 1))
1579                 pin_mask |= (1 << 29);
1580         if (pin_mask > 0)
1581                 select_peripheral(PIOA, pin_mask, PERIPH_A, 0);
1582
1583         pin_mask = 0;
1584         if (mask & (1 << 2))
1585                 pin_mask |= (1 << 21);
1586         if (mask & (1 << 3))
1587                 pin_mask |= (1 << 22);
1588         if (pin_mask > 0)
1589                 select_peripheral(PIOA, pin_mask, PERIPH_B, 0);
1590
1591         atmel_pwm0_mck.dev = &pdev->dev;
1592
1593         platform_device_add(pdev);
1594
1595         return pdev;
1596
1597 out_free_pdev:
1598         platform_device_put(pdev);
1599         return NULL;
1600 }
1601
1602 /* --------------------------------------------------------------------
1603  *  SSC
1604  * -------------------------------------------------------------------- */
1605 static struct resource ssc0_resource[] = {
1606         PBMEM(0xffe01c00),
1607         IRQ(10),
1608 };
1609 DEFINE_DEV(ssc, 0);
1610 DEV_CLK(pclk, ssc0, pba, 7);
1611
1612 static struct resource ssc1_resource[] = {
1613         PBMEM(0xffe02000),
1614         IRQ(11),
1615 };
1616 DEFINE_DEV(ssc, 1);
1617 DEV_CLK(pclk, ssc1, pba, 8);
1618
1619 static struct resource ssc2_resource[] = {
1620         PBMEM(0xffe02400),
1621         IRQ(12),
1622 };
1623 DEFINE_DEV(ssc, 2);
1624 DEV_CLK(pclk, ssc2, pba, 9);
1625
1626 struct platform_device *__init
1627 at32_add_device_ssc(unsigned int id, unsigned int flags)
1628 {
1629         struct platform_device *pdev;
1630         u32 pin_mask = 0;
1631
1632         switch (id) {
1633         case 0:
1634                 pdev = &ssc0_device;
1635                 if (flags & ATMEL_SSC_RF)
1636                         pin_mask |= (1 << 21);  /* RF */
1637                 if (flags & ATMEL_SSC_RK)
1638                         pin_mask |= (1 << 22);  /* RK */
1639                 if (flags & ATMEL_SSC_TK)
1640                         pin_mask |= (1 << 23);  /* TK */
1641                 if (flags & ATMEL_SSC_TF)
1642                         pin_mask |= (1 << 24);  /* TF */
1643                 if (flags & ATMEL_SSC_TD)
1644                         pin_mask |= (1 << 25);  /* TD */
1645                 if (flags & ATMEL_SSC_RD)
1646                         pin_mask |= (1 << 26);  /* RD */
1647
1648                 if (pin_mask > 0)
1649                         select_peripheral(PIOA, pin_mask, PERIPH_A, 0);
1650
1651                 break;
1652         case 1:
1653                 pdev = &ssc1_device;
1654                 if (flags & ATMEL_SSC_RF)
1655                         pin_mask |= (1 << 0);   /* RF */
1656                 if (flags & ATMEL_SSC_RK)
1657                         pin_mask |= (1 << 1);   /* RK */
1658                 if (flags & ATMEL_SSC_TK)
1659                         pin_mask |= (1 << 2);   /* TK */
1660                 if (flags & ATMEL_SSC_TF)
1661                         pin_mask |= (1 << 3);   /* TF */
1662                 if (flags & ATMEL_SSC_TD)
1663                         pin_mask |= (1 << 4);   /* TD */
1664                 if (flags & ATMEL_SSC_RD)
1665                         pin_mask |= (1 << 5);   /* RD */
1666
1667                 if (pin_mask > 0)
1668                         select_peripheral(PIOA, pin_mask, PERIPH_B, 0);
1669
1670                 break;
1671         case 2:
1672                 pdev = &ssc2_device;
1673                 if (flags & ATMEL_SSC_TD)
1674                         pin_mask |= (1 << 13);  /* TD */
1675                 if (flags & ATMEL_SSC_RD)
1676                         pin_mask |= (1 << 14);  /* RD */
1677                 if (flags & ATMEL_SSC_TK)
1678                         pin_mask |= (1 << 15);  /* TK */
1679                 if (flags & ATMEL_SSC_TF)
1680                         pin_mask |= (1 << 16);  /* TF */
1681                 if (flags & ATMEL_SSC_RF)
1682                         pin_mask |= (1 << 17);  /* RF */
1683                 if (flags & ATMEL_SSC_RK)
1684                         pin_mask |= (1 << 18);  /* RK */
1685
1686                 if (pin_mask > 0)
1687                         select_peripheral(PIOB, pin_mask, PERIPH_A, 0);
1688
1689                 break;
1690         default:
1691                 return NULL;
1692         }
1693
1694         platform_device_register(pdev);
1695         return pdev;
1696 }
1697
1698 /* --------------------------------------------------------------------
1699  *  USB Device Controller
1700  * -------------------------------------------------------------------- */
1701 static struct resource usba0_resource[] __initdata = {
1702         {
1703                 .start          = 0xff300000,
1704                 .end            = 0xff3fffff,
1705                 .flags          = IORESOURCE_MEM,
1706         }, {
1707                 .start          = 0xfff03000,
1708                 .end            = 0xfff033ff,
1709                 .flags          = IORESOURCE_MEM,
1710         },
1711         IRQ(31),
1712 };
1713 static struct clk usba0_pclk = {
1714         .name           = "pclk",
1715         .parent         = &pbb_clk,
1716         .mode           = pbb_clk_mode,
1717         .get_rate       = pbb_clk_get_rate,
1718         .index          = 12,
1719 };
1720 static struct clk usba0_hclk = {
1721         .name           = "hclk",
1722         .parent         = &hsb_clk,
1723         .mode           = hsb_clk_mode,
1724         .get_rate       = hsb_clk_get_rate,
1725         .index          = 6,
1726 };
1727
1728 #define EP(nam, idx, maxpkt, maxbk, dma, isoc)                  \
1729         [idx] = {                                               \
1730                 .name           = nam,                          \
1731                 .index          = idx,                          \
1732                 .fifo_size      = maxpkt,                       \
1733                 .nr_banks       = maxbk,                        \
1734                 .can_dma        = dma,                          \
1735                 .can_isoc       = isoc,                         \
1736         }
1737
1738 static struct usba_ep_data at32_usba_ep[] __initdata = {
1739         EP("ep0",     0,   64, 1, 0, 0),
1740         EP("ep1",     1,  512, 2, 1, 1),
1741         EP("ep2",     2,  512, 2, 1, 1),
1742         EP("ep3-int", 3,   64, 3, 1, 0),
1743         EP("ep4-int", 4,   64, 3, 1, 0),
1744         EP("ep5",     5, 1024, 3, 1, 1),
1745         EP("ep6",     6, 1024, 3, 1, 1),
1746 };
1747
1748 #undef EP
1749
1750 struct platform_device *__init
1751 at32_add_device_usba(unsigned int id, struct usba_platform_data *data)
1752 {
1753         /*
1754          * pdata doesn't have room for any endpoints, so we need to
1755          * append room for the ones we need right after it.
1756          */
1757         struct {
1758                 struct usba_platform_data pdata;
1759                 struct usba_ep_data ep[7];
1760         } usba_data;
1761         struct platform_device *pdev;
1762
1763         if (id != 0)
1764                 return NULL;
1765
1766         pdev = platform_device_alloc("atmel_usba_udc", 0);
1767         if (!pdev)
1768                 return NULL;
1769
1770         if (platform_device_add_resources(pdev, usba0_resource,
1771                                           ARRAY_SIZE(usba0_resource)))
1772                 goto out_free_pdev;
1773
1774         if (data) {
1775                 usba_data.pdata.vbus_pin = data->vbus_pin;
1776                 usba_data.pdata.vbus_pin_inverted = data->vbus_pin_inverted;
1777         } else {
1778                 usba_data.pdata.vbus_pin = -EINVAL;
1779                 usba_data.pdata.vbus_pin_inverted = -EINVAL;
1780         }
1781
1782         data = &usba_data.pdata;
1783         data->num_ep = ARRAY_SIZE(at32_usba_ep);
1784         memcpy(data->ep, at32_usba_ep, sizeof(at32_usba_ep));
1785
1786         if (platform_device_add_data(pdev, data, sizeof(usba_data)))
1787                 goto out_free_pdev;
1788
1789         if (gpio_is_valid(data->vbus_pin))
1790                 at32_select_gpio(data->vbus_pin, 0);
1791
1792         usba0_pclk.dev = &pdev->dev;
1793         usba0_hclk.dev = &pdev->dev;
1794
1795         platform_device_add(pdev);
1796
1797         return pdev;
1798
1799 out_free_pdev:
1800         platform_device_put(pdev);
1801         return NULL;
1802 }
1803
1804 /* --------------------------------------------------------------------
1805  * IDE / CompactFlash
1806  * -------------------------------------------------------------------- */
1807 #if defined(CONFIG_CPU_AT32AP7000) || defined(CONFIG_CPU_AT32AP7001)
1808 static struct resource at32_smc_cs4_resource[] __initdata = {
1809         {
1810                 .start  = 0x04000000,
1811                 .end    = 0x07ffffff,
1812                 .flags  = IORESOURCE_MEM,
1813         },
1814         IRQ(~0UL), /* Magic IRQ will be overridden */
1815 };
1816 static struct resource at32_smc_cs5_resource[] __initdata = {
1817         {
1818                 .start  = 0x20000000,
1819                 .end    = 0x23ffffff,
1820                 .flags  = IORESOURCE_MEM,
1821         },
1822         IRQ(~0UL), /* Magic IRQ will be overridden */
1823 };
1824
1825 static int __init at32_init_ide_or_cf(struct platform_device *pdev,
1826                 unsigned int cs, unsigned int extint)
1827 {
1828         static unsigned int extint_pin_map[4] __initdata = {
1829                 (1 << 25),
1830                 (1 << 26),
1831                 (1 << 27),
1832                 (1 << 28),
1833         };
1834         static bool common_pins_initialized __initdata = false;
1835         unsigned int extint_pin;
1836         int ret;
1837         u32 pin_mask;
1838
1839         if (extint >= ARRAY_SIZE(extint_pin_map))
1840                 return -EINVAL;
1841         extint_pin = extint_pin_map[extint];
1842
1843         switch (cs) {
1844         case 4:
1845                 ret = platform_device_add_resources(pdev,
1846                                 at32_smc_cs4_resource,
1847                                 ARRAY_SIZE(at32_smc_cs4_resource));
1848                 if (ret)
1849                         return ret;
1850
1851                 /* NCS4   -> OE_N  */
1852                 select_peripheral(PIOE, (1 << 21), PERIPH_A, 0);
1853                 hmatrix_sfr_set_bits(HMATRIX_SLAVE_EBI, HMATRIX_EBI_CF0_ENABLE);
1854                 break;
1855         case 5:
1856                 ret = platform_device_add_resources(pdev,
1857                                 at32_smc_cs5_resource,
1858                                 ARRAY_SIZE(at32_smc_cs5_resource));
1859                 if (ret)
1860                         return ret;
1861
1862                 /* NCS5   -> OE_N  */
1863                 select_peripheral(PIOE, (1 << 22), PERIPH_A, 0);
1864                 hmatrix_sfr_set_bits(HMATRIX_SLAVE_EBI, HMATRIX_EBI_CF1_ENABLE);
1865                 break;
1866         default:
1867                 return -EINVAL;
1868         }
1869
1870         if (!common_pins_initialized) {
1871                 pin_mask  = (1 << 19);  /* CFCE1  -> CS0_N */
1872                 pin_mask |= (1 << 20);  /* CFCE2  -> CS1_N */
1873                 pin_mask |= (1 << 23);  /* CFRNW  -> DIR   */
1874                 pin_mask |= (1 << 24);  /* NWAIT  <- IORDY */
1875
1876                 select_peripheral(PIOE, pin_mask, PERIPH_A, 0);
1877
1878                 common_pins_initialized = true;
1879         }
1880
1881         select_peripheral(PIOB, extint_pin, PERIPH_A, AT32_GPIOF_DEGLITCH);
1882
1883         pdev->resource[1].start = EIM_IRQ_BASE + extint;
1884         pdev->resource[1].end = pdev->resource[1].start;
1885
1886         return 0;
1887 }
1888
1889 struct platform_device *__init
1890 at32_add_device_ide(unsigned int id, unsigned int extint,
1891                     struct ide_platform_data *data)
1892 {
1893         struct platform_device *pdev;
1894
1895         pdev = platform_device_alloc("at32_ide", id);
1896         if (!pdev)
1897                 goto fail;
1898
1899         if (platform_device_add_data(pdev, data,
1900                                 sizeof(struct ide_platform_data)))
1901                 goto fail;
1902
1903         if (at32_init_ide_or_cf(pdev, data->cs, extint))
1904                 goto fail;
1905
1906         platform_device_add(pdev);
1907         return pdev;
1908
1909 fail:
1910         platform_device_put(pdev);
1911         return NULL;
1912 }
1913
1914 struct platform_device *__init
1915 at32_add_device_cf(unsigned int id, unsigned int extint,
1916                     struct cf_platform_data *data)
1917 {
1918         struct platform_device *pdev;
1919
1920         pdev = platform_device_alloc("at32_cf", id);
1921         if (!pdev)
1922                 goto fail;
1923
1924         if (platform_device_add_data(pdev, data,
1925                                 sizeof(struct cf_platform_data)))
1926                 goto fail;
1927
1928         if (at32_init_ide_or_cf(pdev, data->cs, extint))
1929                 goto fail;
1930
1931         if (gpio_is_valid(data->detect_pin))
1932                 at32_select_gpio(data->detect_pin, AT32_GPIOF_DEGLITCH);
1933         if (gpio_is_valid(data->reset_pin))
1934                 at32_select_gpio(data->reset_pin, 0);
1935         if (gpio_is_valid(data->vcc_pin))
1936                 at32_select_gpio(data->vcc_pin, 0);
1937         /* READY is used as extint, so we can't select it as gpio */
1938
1939         platform_device_add(pdev);
1940         return pdev;
1941
1942 fail:
1943         platform_device_put(pdev);
1944         return NULL;
1945 }
1946 #endif
1947
1948 /* --------------------------------------------------------------------
1949  * NAND Flash / SmartMedia
1950  * -------------------------------------------------------------------- */
1951 static struct resource smc_cs3_resource[] __initdata = {
1952         {
1953                 .start  = 0x0c000000,
1954                 .end    = 0x0fffffff,
1955                 .flags  = IORESOURCE_MEM,
1956         }, {
1957                 .start  = 0xfff03c00,
1958                 .end    = 0xfff03fff,
1959                 .flags  = IORESOURCE_MEM,
1960         },
1961 };
1962
1963 struct platform_device *__init
1964 at32_add_device_nand(unsigned int id, struct atmel_nand_data *data)
1965 {
1966         struct platform_device *pdev;
1967
1968         if (id != 0 || !data)
1969                 return NULL;
1970
1971         pdev = platform_device_alloc("atmel_nand", id);
1972         if (!pdev)
1973                 goto fail;
1974
1975         if (platform_device_add_resources(pdev, smc_cs3_resource,
1976                                 ARRAY_SIZE(smc_cs3_resource)))
1977                 goto fail;
1978
1979         if (platform_device_add_data(pdev, data,
1980                                 sizeof(struct atmel_nand_data)))
1981                 goto fail;
1982
1983         hmatrix_sfr_set_bits(HMATRIX_SLAVE_EBI, HMATRIX_EBI_NAND_ENABLE);
1984         if (data->enable_pin)
1985                 at32_select_gpio(data->enable_pin,
1986                                 AT32_GPIOF_OUTPUT | AT32_GPIOF_HIGH);
1987         if (data->rdy_pin)
1988                 at32_select_gpio(data->rdy_pin, 0);
1989         if (data->det_pin)
1990                 at32_select_gpio(data->det_pin, 0);
1991
1992         platform_device_add(pdev);
1993         return pdev;
1994
1995 fail:
1996         platform_device_put(pdev);
1997         return NULL;
1998 }
1999
2000 /* --------------------------------------------------------------------
2001  * AC97C
2002  * -------------------------------------------------------------------- */
2003 static struct resource atmel_ac97c0_resource[] __initdata = {
2004         PBMEM(0xfff02800),
2005         IRQ(29),
2006 };
2007 static struct clk atmel_ac97c0_pclk = {
2008         .name           = "pclk",
2009         .parent         = &pbb_clk,
2010         .mode           = pbb_clk_mode,
2011         .get_rate       = pbb_clk_get_rate,
2012         .index          = 10,
2013 };
2014
2015 struct platform_device *__init
2016 at32_add_device_ac97c(unsigned int id, struct ac97c_platform_data *data,
2017                       unsigned int flags)
2018 {
2019         struct platform_device          *pdev;
2020         struct dw_dma_slave             *rx_dws;
2021         struct dw_dma_slave             *tx_dws;
2022         struct ac97c_platform_data      _data;
2023         u32                             pin_mask;
2024
2025         if (id != 0)
2026                 return NULL;
2027
2028         pdev = platform_device_alloc("atmel_ac97c", id);
2029         if (!pdev)
2030                 return NULL;
2031
2032         if (platform_device_add_resources(pdev, atmel_ac97c0_resource,
2033                                 ARRAY_SIZE(atmel_ac97c0_resource)))
2034                 goto out_free_resources;
2035
2036         if (!data) {
2037                 data = &_data;
2038                 memset(data, 0, sizeof(struct ac97c_platform_data));
2039                 data->reset_pin = -ENODEV;
2040         }
2041
2042         rx_dws = &data->rx_dws;
2043         tx_dws = &data->tx_dws;
2044
2045         /* Check if DMA slave interface for capture should be configured. */
2046         if (flags & AC97C_CAPTURE) {
2047                 rx_dws->dma_dev = &dw_dmac0_device.dev;
2048                 rx_dws->reg_width = DW_DMA_SLAVE_WIDTH_16BIT;
2049                 rx_dws->cfg_hi = DWC_CFGH_SRC_PER(3);
2050                 rx_dws->cfg_lo &= ~(DWC_CFGL_HS_DST_POL | DWC_CFGL_HS_SRC_POL);
2051         }
2052
2053         /* Check if DMA slave interface for playback should be configured. */
2054         if (flags & AC97C_PLAYBACK) {
2055                 tx_dws->dma_dev = &dw_dmac0_device.dev;
2056                 tx_dws->reg_width = DW_DMA_SLAVE_WIDTH_16BIT;
2057                 tx_dws->cfg_hi = DWC_CFGH_DST_PER(4);
2058                 tx_dws->cfg_lo &= ~(DWC_CFGL_HS_DST_POL | DWC_CFGL_HS_SRC_POL);
2059         }
2060
2061         if (platform_device_add_data(pdev, data,
2062                                 sizeof(struct ac97c_platform_data)))
2063                 goto out_free_resources;
2064
2065         /* SDO | SYNC | SCLK | SDI */
2066         pin_mask = (1 << 20) | (1 << 21) | (1 << 22) | (1 << 23);
2067
2068         select_peripheral(PIOB, pin_mask, PERIPH_B, 0);
2069
2070         if (gpio_is_valid(data->reset_pin))
2071                 at32_select_gpio(data->reset_pin, AT32_GPIOF_OUTPUT
2072                                 | AT32_GPIOF_HIGH);
2073
2074         atmel_ac97c0_pclk.dev = &pdev->dev;
2075
2076         platform_device_add(pdev);
2077         return pdev;
2078
2079 out_free_resources:
2080         platform_device_put(pdev);
2081         return NULL;
2082 }
2083
2084 /* --------------------------------------------------------------------
2085  * ABDAC
2086  * -------------------------------------------------------------------- */
2087 static struct resource abdac0_resource[] __initdata = {
2088         PBMEM(0xfff02000),
2089         IRQ(27),
2090 };
2091 static struct clk abdac0_pclk = {
2092         .name           = "pclk",
2093         .parent         = &pbb_clk,
2094         .mode           = pbb_clk_mode,
2095         .get_rate       = pbb_clk_get_rate,
2096         .index          = 8,
2097 };
2098 static struct clk abdac0_sample_clk = {
2099         .name           = "sample_clk",
2100         .mode           = genclk_mode,
2101         .get_rate       = genclk_get_rate,
2102         .set_rate       = genclk_set_rate,
2103         .set_parent     = genclk_set_parent,
2104         .index          = 6,
2105 };
2106
2107 struct platform_device *__init
2108 at32_add_device_abdac(unsigned int id, struct atmel_abdac_pdata *data)
2109 {
2110         struct platform_device  *pdev;
2111         struct dw_dma_slave     *dws;
2112         u32                     pin_mask;
2113
2114         if (id != 0 || !data)
2115                 return NULL;
2116
2117         pdev = platform_device_alloc("atmel_abdac", id);
2118         if (!pdev)
2119                 return NULL;
2120
2121         if (platform_device_add_resources(pdev, abdac0_resource,
2122                                 ARRAY_SIZE(abdac0_resource)))
2123                 goto out_free_resources;
2124
2125         dws = &data->dws;
2126
2127         dws->dma_dev = &dw_dmac0_device.dev;
2128         dws->reg_width = DW_DMA_SLAVE_WIDTH_32BIT;
2129         dws->cfg_hi = DWC_CFGH_DST_PER(2);
2130         dws->cfg_lo &= ~(DWC_CFGL_HS_DST_POL | DWC_CFGL_HS_SRC_POL);
2131
2132         if (platform_device_add_data(pdev, data,
2133                                 sizeof(struct atmel_abdac_pdata)))
2134                 goto out_free_resources;
2135
2136         pin_mask  = (1 << 20) | (1 << 22);      /* DATA1 & DATAN1 */
2137         pin_mask |= (1 << 21) | (1 << 23);      /* DATA0 & DATAN0 */
2138
2139         select_peripheral(PIOB, pin_mask, PERIPH_A, 0);
2140
2141         abdac0_pclk.dev = &pdev->dev;
2142         abdac0_sample_clk.dev = &pdev->dev;
2143
2144         platform_device_add(pdev);
2145         return pdev;
2146
2147 out_free_resources:
2148         platform_device_put(pdev);
2149         return NULL;
2150 }
2151
2152 /* --------------------------------------------------------------------
2153  *  GCLK
2154  * -------------------------------------------------------------------- */
2155 static struct clk gclk0 = {
2156         .name           = "gclk0",
2157         .mode           = genclk_mode,
2158         .get_rate       = genclk_get_rate,
2159         .set_rate       = genclk_set_rate,
2160         .set_parent     = genclk_set_parent,
2161         .index          = 0,
2162 };
2163 static struct clk gclk1 = {
2164         .name           = "gclk1",
2165         .mode           = genclk_mode,
2166         .get_rate       = genclk_get_rate,
2167         .set_rate       = genclk_set_rate,
2168         .set_parent     = genclk_set_parent,
2169         .index          = 1,
2170 };
2171 static struct clk gclk2 = {
2172         .name           = "gclk2",
2173         .mode           = genclk_mode,
2174         .get_rate       = genclk_get_rate,
2175         .set_rate       = genclk_set_rate,
2176         .set_parent     = genclk_set_parent,
2177         .index          = 2,
2178 };
2179 static struct clk gclk3 = {
2180         .name           = "gclk3",
2181         .mode           = genclk_mode,
2182         .get_rate       = genclk_get_rate,
2183         .set_rate       = genclk_set_rate,
2184         .set_parent     = genclk_set_parent,
2185         .index          = 3,
2186 };
2187 static struct clk gclk4 = {
2188         .name           = "gclk4",
2189         .mode           = genclk_mode,
2190         .get_rate       = genclk_get_rate,
2191         .set_rate       = genclk_set_rate,
2192         .set_parent     = genclk_set_parent,
2193         .index          = 4,
2194 };
2195
2196 static __initdata struct clk *init_clocks[] = {
2197         &osc32k,
2198         &osc0,
2199         &osc1,
2200         &pll0,
2201         &pll1,
2202         &cpu_clk,
2203         &hsb_clk,
2204         &pba_clk,
2205         &pbb_clk,
2206         &at32_pm_pclk,
2207         &at32_intc0_pclk,
2208         &at32_hmatrix_clk,
2209         &ebi_clk,
2210         &hramc_clk,
2211         &sdramc_clk,
2212         &smc0_pclk,
2213         &smc0_mck,
2214         &pdc_hclk,
2215         &pdc_pclk,
2216         &dw_dmac0_hclk,
2217         &pico_clk,
2218         &pio0_mck,
2219         &pio1_mck,
2220         &pio2_mck,
2221         &pio3_mck,
2222         &pio4_mck,
2223         &at32_tcb0_t0_clk,
2224         &at32_tcb1_t0_clk,
2225         &atmel_psif0_pclk,
2226         &atmel_psif1_pclk,
2227         &atmel_usart0_usart,
2228         &atmel_usart1_usart,
2229         &atmel_usart2_usart,
2230         &atmel_usart3_usart,
2231         &atmel_pwm0_mck,
2232 #if defined(CONFIG_CPU_AT32AP7000)
2233         &macb0_hclk,
2234         &macb0_pclk,
2235         &macb1_hclk,
2236         &macb1_pclk,
2237 #endif
2238         &atmel_spi0_spi_clk,
2239         &atmel_spi1_spi_clk,
2240         &atmel_twi0_pclk,
2241         &atmel_mci0_pclk,
2242 #if defined(CONFIG_CPU_AT32AP7000) || defined(CONFIG_CPU_AT32AP7002)
2243         &atmel_lcdfb0_hck1,
2244         &atmel_lcdfb0_pixclk,
2245 #endif
2246         &ssc0_pclk,
2247         &ssc1_pclk,
2248         &ssc2_pclk,
2249         &usba0_hclk,
2250         &usba0_pclk,
2251         &atmel_ac97c0_pclk,
2252         &abdac0_pclk,
2253         &abdac0_sample_clk,
2254         &gclk0,
2255         &gclk1,
2256         &gclk2,
2257         &gclk3,
2258         &gclk4,
2259 };
2260
2261 void __init setup_platform(void)
2262 {
2263         u32 cpu_mask = 0, hsb_mask = 0, pba_mask = 0, pbb_mask = 0;
2264         int i;
2265
2266         if (pm_readl(MCCTRL) & PM_BIT(PLLSEL)) {
2267                 main_clock = &pll0;
2268                 cpu_clk.parent = &pll0;
2269         } else {
2270                 main_clock = &osc0;
2271                 cpu_clk.parent = &osc0;
2272         }
2273
2274         if (pm_readl(PLL0) & PM_BIT(PLLOSC))
2275                 pll0.parent = &osc1;
2276         if (pm_readl(PLL1) & PM_BIT(PLLOSC))
2277                 pll1.parent = &osc1;
2278
2279         genclk_init_parent(&gclk0);
2280         genclk_init_parent(&gclk1);
2281         genclk_init_parent(&gclk2);
2282         genclk_init_parent(&gclk3);
2283         genclk_init_parent(&gclk4);
2284 #if defined(CONFIG_CPU_AT32AP7000) || defined(CONFIG_CPU_AT32AP7002)
2285         genclk_init_parent(&atmel_lcdfb0_pixclk);
2286 #endif
2287         genclk_init_parent(&abdac0_sample_clk);
2288
2289         /*
2290          * Build initial dynamic clock list by registering all clocks
2291          * from the array.
2292          * At the same time, turn on all clocks that have at least one
2293          * user already, and turn off everything else. We only do this
2294          * for module clocks, and even though it isn't particularly
2295          * pretty to  check the address of the mode function, it should
2296          * do the trick...
2297          */
2298         for (i = 0; i < ARRAY_SIZE(init_clocks); i++) {
2299                 struct clk *clk = init_clocks[i];
2300
2301                 /* first, register clock */
2302                 at32_clk_register(clk);
2303
2304                 if (clk->users == 0)
2305                         continue;
2306
2307                 if (clk->mode == &cpu_clk_mode)
2308                         cpu_mask |= 1 << clk->index;
2309                 else if (clk->mode == &hsb_clk_mode)
2310                         hsb_mask |= 1 << clk->index;
2311                 else if (clk->mode == &pba_clk_mode)
2312                         pba_mask |= 1 << clk->index;
2313                 else if (clk->mode == &pbb_clk_mode)
2314                         pbb_mask |= 1 << clk->index;
2315         }
2316
2317         pm_writel(CPU_MASK, cpu_mask);
2318         pm_writel(HSB_MASK, hsb_mask);
2319         pm_writel(PBA_MASK, pba_mask);
2320         pm_writel(PBB_MASK, pbb_mask);
2321
2322         /* Initialize the port muxes */
2323         at32_init_pio(&pio0_device);
2324         at32_init_pio(&pio1_device);
2325         at32_init_pio(&pio2_device);
2326         at32_init_pio(&pio3_device);
2327         at32_init_pio(&pio4_device);
2328 }
2329
2330 struct gen_pool *sram_pool;
2331
2332 static int __init sram_init(void)
2333 {
2334         struct gen_pool *pool;
2335
2336         /* 1KiB granularity */
2337         pool = gen_pool_create(10, -1);
2338         if (!pool)
2339                 goto fail;
2340
2341         if (gen_pool_add(pool, 0x24000000, 0x8000, -1))
2342                 goto err_pool_add;
2343
2344         sram_pool = pool;
2345         return 0;
2346
2347 err_pool_add:
2348         gen_pool_destroy(pool);
2349 fail:
2350         pr_err("Failed to create SRAM pool\n");
2351         return -ENOMEM;
2352 }
2353 core_initcall(sram_init);