arm: tegra: Move driver files to drivers/platform
[linux-3.10.git] / arch / arm64 / mach-tegra / tegra21_init.c
1 /*
2  * arch/arm/mach-tegra/tegra21_init.c
3  *
4  * NVIDIA Tegra210 initialization support
5  *
6  * Copyright (C) 2013-2014 NVIDIA Corporation. All rights reserved.
7  *
8  * This software is licensed under the terms of the GNU General Public
9  * License version 2, as published by the Free Software Foundation, and
10  * may be copied, distributed, and modified under those terms.
11  *
12  * This program is distributed in the hope that it will be useful,
13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15  * GNU General Public License for more details.
16  *
17  */
18
19 #include <linux/kernel.h>
20 #include <linux/tegra-fuse.h>
21 #include <linux/platform_data/tegra_bpmp.h>
22 #include <mach/powergate.h>
23
24 #include <linux/platform/tegra/reset.h>
25 #include "apbio.h"
26 #include <linux/platform/tegra/clock.h>
27 #include <linux/platform/tegra/dvfs.h>
28 #include <linux/platform/tegra/common.h>
29 #include "devices.h"
30 #include "iomap.h"
31
32 #if defined(CONFIG_ARCH_TEGRA_21x_SOC)
33
34 #define MC_SECURITY_CFG2        0x7c
35
36 #define AHB_ARBITRATION_PRIORITY_CTRL           0x4
37 #define   AHB_PRIORITY_WEIGHT(x)        (((x) & 0x7) << 29)
38 #define   PRIORITY_SELECT_USB   BIT(6)
39 #define   PRIORITY_SELECT_USB2  BIT(18)
40 #define   PRIORITY_SELECT_USB3  BIT(17)
41 #define   PRIORITY_SELECT_SE BIT(14)
42
43 #define AHB_GIZMO_AHB_MEM               0xc
44 #define   ENB_FAST_REARBITRATE  BIT(2)
45 #define   DONT_SPLIT_AHB_WR     BIT(7)
46 #define   WR_WAIT_COMMIT_ON_1K  BIT(8)
47 #define   EN_USB_WAIT_COMMIT_ON_1K_STALL        BIT(9)
48
49 #define   RECOVERY_MODE BIT(31)
50 #define   BOOTLOADER_MODE       BIT(30)
51 #define   FORCED_RECOVERY_MODE  BIT(1)
52
53 #define AHB_GIZMO_USB           0x1c
54 #define AHB_GIZMO_USB2          0x78
55 #define AHB_GIZMO_USB3          0x7c
56 #define AHB_GIZMO_SE            0x4c
57 #define   IMMEDIATE     BIT(18)
58
59 #define AHB_MEM_PREFETCH_CFG3   0xe0
60 #define AHB_MEM_PREFETCH_CFG4   0xe4
61 #define AHB_MEM_PREFETCH_CFG1   0xec
62 #define AHB_MEM_PREFETCH_CFG2   0xf0
63 #define AHB_MEM_PREFETCH_CFG6   0xcc
64 #define   PREFETCH_ENB  BIT(31)
65 #define   MST_ID(x)     (((x) & 0x1f) << 26)
66 #define   AHBDMA_MST_ID MST_ID(5)
67 #define   USB_MST_ID    MST_ID(6)
68 #define   USB2_MST_ID   MST_ID(18)
69 #define   USB3_MST_ID   MST_ID(17)
70 #define   SE_MST_ID     MST_ID(14)
71 #define   ADDR_BNDRY(x) (((x) & 0xf) << 21)
72 #define   INACTIVITY_TIMEOUT(x) (((x) & 0xffff) << 0)
73
74
75 /* TODO: check  the correct init values */
76
77 static __initdata struct tegra_clk_init_table tegra21x_clk_init_table[] = {
78         /* name         parent          rate            enabled */
79         { "clk_m",      NULL,           0,              true },
80         { "emc",        NULL,           0,              true },
81         { "cpu",        NULL,           0,              true },
82         { "kfuse",      NULL,           0,              true },
83         { "fuse",       NULL,           0,              true },
84         { "sclk",       NULL,           0,              true },
85         { "pll_p",      NULL,           0,              true, TEGRA_CLK_INIT_PLATFORM_SI },
86         { "pll_p_out2", NULL,           204000000,      false, TEGRA_CLK_INIT_PLATFORM_SI },
87         { "sclk_mux",   "pll_p_out2",   204000000,      true, TEGRA_CLK_INIT_PLATFORM_SI },
88         { "sclk_div",   "sclk_mux",     102000000,      true, TEGRA_CLK_INIT_PLATFORM_SI },
89         { "hclk",       "sclk",         102000000,      true, TEGRA_CLK_INIT_PLATFORM_SI },
90         { "pclk",       "hclk",         51000000,       true, TEGRA_CLK_INIT_PLATFORM_SI },
91         { "pll_p_out3", NULL,           102000000,      true, TEGRA_CLK_INIT_PLATFORM_SI },
92         { "pll_p_out4", NULL,           204000000,      true, TEGRA_CLK_INIT_PLATFORM_SI },
93         { "pll_p_out5", NULL,           204000000,      true, TEGRA_CLK_INIT_PLATFORM_SI },
94         { "host1x",     "pll_p",        102000000,      false, TEGRA_CLK_INIT_PLATFORM_SI },
95         { "mselect",    "pll_p",        102000000,      true, TEGRA_CLK_INIT_PLATFORM_SI },
96         { "cl_dvfs_ref", "pll_p",       51000000,       true, TEGRA_CLK_INIT_PLATFORM_SI },
97         { "cl_dvfs_soc", "pll_p",       51000000,       true, TEGRA_CLK_INIT_PLATFORM_SI },
98 #ifdef CONFIG_TEGRA_SLOW_CSITE
99         { "csite",      "clk_m",        1000000,        true },
100 #else
101         { "csite",      NULL,           0,              true },
102 #endif
103         { "pll_u_out",  NULL,           0,              true },
104         { "pll_u_out1", NULL,           0,              true },
105         { "pll_u_out2", NULL,           0,              true },
106         { "pll_re_vco", NULL,           624000000,      true },
107         { "pll_re_out", NULL,           624000000,      false },
108         { "xusb_falcon_src",    "pll_p_out_xusb",   204000000,      false},
109         { "xusb_host_src",      "pll_p_out_xusb",   102000000,      false},
110         { "xusb_dev_src",       "pll_p_out_xusb",   102000000,      false},
111         { "xusb_ss_src",        "pll_u_480M",       120000000,      false},
112         { "xusb_ssp_src",       "xusb_ss_src",      120000000,      false},
113         { "xusb_hs_src",        "xusb_ss_src",      120000000,       false},
114         { "xusb_fs_src",        "pll_u_48M",        48000000,       false},
115         { "sdmmc1",     "pll_p",        46000000,       false},
116         { "sdmmc2",     "pll_p",        46000000,       false},
117         { "sdmmc3",     "pll_p",        46000000,       false},
118         { "sdmmc4",     "pll_p",        46000000,       false},
119         { "sdmmc1_ddr", "pll_p",        46000000,       false},
120         { "sdmmc2_ddr", "pll_p",        46000000,       false},
121         { "sdmmc3_ddr", "pll_p",        46000000,       false},
122         { "sdmmc4_ddr", "pll_p",        46000000,       false},
123         { "sdmmc_legacy", "pll_p",      46000000,       false},
124         { "tsec",       "pll_p",        204000000,      false},
125         { "cpu.mselect",        NULL,   102000000,      true},
126         { "gpu_gate",       NULL,           0,              true},
127         { "gpu_ref",        NULL,           0,              true},
128         { "gm20b.gbus",     NULL,           384000000,      false},
129         { "mc_capa",        "mc",           0,              true},
130         { "mc_cbpa",        "mc",           0,              true},
131         { "mc_ccpa",        "mc",           0,              true},
132         { "mc_cdpa",        "mc",           0,              true},
133 #ifdef CONFIG_TEGRA_PLLM_SCALED
134         { "vi",         "pll_p",        0,              false},
135         { "isp",        "pll_p",        0,              false},
136 #endif
137 #ifdef CONFIG_TEGRA_SOCTHERM
138         { "soc_therm",  "pll_p",        51000000,       false },
139         { "tsensor",    "clk_m",        500000,         false },
140 #endif
141         { "csite",      NULL,           0,              true },
142         { "adsp_cpu",   NULL,   600000000,              false },
143         { NULL,         NULL,           0,              0},
144
145 };
146
147 static __initdata struct tegra_clk_init_table tegra21x_cbus_init_table[] = {
148         /* Initialize c2bus, c3bus, or cbus at the end of the list
149            * after all the clocks are moved under the proper parents.
150         */
151         { "c2bus",      "pll_c2",       250000000,      false },
152         { "c3bus",      "pll_c3",       250000000,      false },
153         { "cbus",       "pll_c",        250000000,      false },
154         { "pll_c_out1", "pll_c",        100000000,      false },
155         { NULL,         NULL,           0,              0},
156 };
157
158 static __initdata struct tegra_clk_init_table tegra21x_sbus_init_table[] = {
159         /* Initialize sbus (system clock) users after cbus init PLLs */
160         { "sbc1.sclk",  NULL,           40000000,       false},
161         { "sbc2.sclk",  NULL,           40000000,       false},
162         { "sbc3.sclk",  NULL,           40000000,       false},
163         { "sbc4.sclk",  NULL,           40000000,       false},
164         { "boot.apb.sclk",  NULL,      136000000,       true },
165         { NULL,         NULL,           0,              0},
166 };
167
168 static __initdata struct tegra_clk_init_table uart_non_si_clk_init_data[] = {
169         { "uarta",      "clk_m",        0,      false},
170         { "uartb",      "clk_m",        0,      true},
171         { "uartc",      "clk_m",        0,      false},
172         { "uartd",      "clk_m",        0,      false},
173         { NULL,         NULL,           0,              0},
174 };
175
176 static void __init tegra_perf_init(void)
177 {
178         u32 reg;
179
180 #ifdef CONFIG_ARM64
181         asm volatile("mrs %0, PMCR_EL0" : "=r"(reg));
182         reg >>= 11;
183         reg = (1 << (reg & 0x1f))-1;
184         reg |= 0x80000000;
185         asm volatile("msr PMINTENCLR_EL1, %0" : : "r"(reg));
186         reg = 1;
187         asm volatile("msr PMUSERENR_EL0, %0" : : "r"(reg));
188 #endif
189 }
190
191 static inline unsigned long gizmo_readl(unsigned long offset)
192 {
193         return readl(IO_TO_VIRT(TEGRA_AHB_GIZMO_BASE + offset));
194 }
195
196 static inline void gizmo_writel(unsigned long value, unsigned long offset)
197 {
198         writel(value, IO_TO_VIRT(TEGRA_AHB_GIZMO_BASE + offset));
199 }
200
201 static void __init tegra_init_power(void)
202 {
203    /* TODO : Do the required power initilizations here */
204 #ifdef CONFIG_ARCH_TEGRA_HAS_PCIE
205         tegra_powergate_partition_with_clk_off(TEGRA_POWERGATE_PCIE);
206 #endif
207 }
208
209 static void __init tegra_init_ahb_gizmo_settings(void)
210 {
211         unsigned long val;
212
213         val = gizmo_readl(AHB_GIZMO_AHB_MEM);
214         val |= ENB_FAST_REARBITRATE | IMMEDIATE | DONT_SPLIT_AHB_WR;
215
216         val |= WR_WAIT_COMMIT_ON_1K | EN_USB_WAIT_COMMIT_ON_1K_STALL;
217         gizmo_writel(val, AHB_GIZMO_AHB_MEM);
218
219         val = gizmo_readl(AHB_GIZMO_USB);
220         val |= IMMEDIATE;
221         gizmo_writel(val, AHB_GIZMO_USB);
222
223         val = gizmo_readl(AHB_GIZMO_USB2);
224         val |= IMMEDIATE;
225         gizmo_writel(val, AHB_GIZMO_USB2);
226
227         val = gizmo_readl(AHB_ARBITRATION_PRIORITY_CTRL);
228         val |= PRIORITY_SELECT_USB | PRIORITY_SELECT_USB2 | PRIORITY_SELECT_USB3
229                 | AHB_PRIORITY_WEIGHT(7);
230         val |= PRIORITY_SELECT_SE;
231
232         gizmo_writel(val, AHB_ARBITRATION_PRIORITY_CTRL);
233
234         val = gizmo_readl(AHB_MEM_PREFETCH_CFG1);
235         val &= ~MST_ID(~0);
236         val |= PREFETCH_ENB | AHBDMA_MST_ID |
237                 ADDR_BNDRY(0xc) | INACTIVITY_TIMEOUT(0x1000);
238         ahb_gizmo_writel(val,
239                 IO_ADDRESS(TEGRA_AHB_GIZMO_BASE + AHB_MEM_PREFETCH_CFG1));
240
241         val = gizmo_readl(AHB_MEM_PREFETCH_CFG2);
242         val &= ~MST_ID(~0);
243         val |= PREFETCH_ENB | USB_MST_ID | ADDR_BNDRY(0xc) |
244                 INACTIVITY_TIMEOUT(0x1000);
245         ahb_gizmo_writel(val,
246                 IO_ADDRESS(TEGRA_AHB_GIZMO_BASE + AHB_MEM_PREFETCH_CFG3));
247
248         val = gizmo_readl(AHB_MEM_PREFETCH_CFG4);
249         val &= ~MST_ID(~0);
250         val |= PREFETCH_ENB | USB2_MST_ID | ADDR_BNDRY(0xc) |
251                 INACTIVITY_TIMEOUT(0x1000);
252         ahb_gizmo_writel(val,
253                 IO_ADDRESS(TEGRA_AHB_GIZMO_BASE + AHB_MEM_PREFETCH_CFG4));
254
255         val = gizmo_readl(AHB_MEM_PREFETCH_CFG6);
256         val &= ~MST_ID(~0);
257         val |= PREFETCH_ENB | SE_MST_ID | ADDR_BNDRY(0xc) |
258                 INACTIVITY_TIMEOUT(0x1000);
259         ahb_gizmo_writel(val,
260                 IO_ADDRESS(TEGRA_AHB_GIZMO_BASE + AHB_MEM_PREFETCH_CFG6));
261 }
262
263 void __init tegra21x_init_early(void)
264 {
265         display_tegra_dt_info();
266         tegra_apb_io_init();
267         tegra_perf_init();
268         tegra_init_fuse();
269         tegra_bpmp_init_early();
270         tegra21x_init_clocks();
271         tegra21x_init_dvfs();
272         tegra_common_init_clock();
273         tegra_clk_init_from_table(tegra21x_clk_init_table);
274         tegra_clk_init_cbus_plls_from_table(tegra21x_cbus_init_table);
275         tegra_clk_init_from_table(tegra21x_sbus_init_table);
276         if (!tegra_platform_is_silicon())
277                 tegra_clk_init_from_table(uart_non_si_clk_init_data);
278         tegra_powergate_init();
279         tegra_init_power();
280         tegra_init_ahb_gizmo_settings();
281 }
282 #endif