ARM64: DT: t210: sdhci: Enable periodic calibration
[linux-3.10.git] / arch / arm64 / boot / dts / tegra210-platforms / tegra210-sdhci.dtsi
1 /*
2  * Copyright (c) 2014-2015, NVIDIA CORPORATION.  All rights reserved.
3  *
4  * This program is free software; you can redistribute it and/or modify
5  * it under the terms of the GNU General Public License as published by
6  * the Free Software Foundation; either version 2 of the License, or
7  * (at your option) any later version.
8  *
9  * This program is distributed in the hope that it will be useful, but WITHOUT
10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
12  * more details.
13  *
14  * You should have received a copy of the GNU General Public License along
15  * with this program; if not, write to the Free Software Foundation, Inc.,
16  * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
17  */
18
19 / {
20         sdhci@700b0600 {
21                 tap-delay = <4>;
22                 trim-delay = <8>;
23                 nvidia,is-ddr-tap-delay;
24                 nvidia,ddr-tap-delay = <0>;
25                 mmc-ocr-mask = <0>;
26                 dqs-trim-delay = <17>;
27                 max-clk-limit = <200000000>;
28                 bus-width = <8>;
29                 built-in;
30                 calib-3v3-offsets = <0x0505>;
31                 calib-1v8-offsets = <0x0505>;
32                 compad-vref-3v3 = <0x7>;
33                 compad-vref-1v8 = <0x7>;
34                 nvidia,en-io-trim-volt;
35                 nvidia,is-emmc;
36                 nvidia,enable-cq;
37                 pll_source = "pll_p";
38         };
39
40         sdhci@700b0400 {
41                 tap-delay = <1>;
42                 trim-delay = <3>;
43                 max-clk-limit = <204000000>;
44                 ddr-clk-limit = <48000000>;
45                 bus-width = <4>;
46                 calib-3v3-offsets = <0x007D>;
47                 calib-1v8-offsets = <0x7B7B>;
48                 compad-vref-3v3 = <0x7>;
49                 compad-vref-1v8 = <0x7>;
50                 pll_source = "pll_p";
51                 nvidia,en-io-trim-volt;
52                 nvidia,en-periodic-calib;
53         };
54
55         sdhci@700b0200 {
56                 tap-delay = <4>;
57                 trim-delay = <8>;
58                 mmc-ocr-mask = <0>;
59                 max-clk-limit = <204000000>;
60                 ddr-clk-limit = <41000000>;
61                 bus-width = <4>;
62                 calib-3v3-offsets = <0x0505>;
63                 calib-1v8-offsets = <0x0505>;
64                 compad-vref-3v3 = <0x7>;
65                 compad-vref-1v8 = <0x7>;
66                 default-drive-type = <1>;
67                 pll_source = "pll_p";
68                 nvidia,en-io-trim-volt;
69         };
70
71         sdhci@700b0000 {
72                 tap-delay = <4>;
73                 trim-delay = <2>;
74                 max-clk-limit = <204000000>;
75                 ddr-clk-limit = <48000000>;
76                 bus-width = <4>;
77                 mmc-ocr-mask = <3>;
78                 calib-3v3-offsets = <0x007D>;
79                 calib-1v8-offsets = <0x7B7B>;
80                 compad-vref-3v3 = <0x7>;
81                 compad-vref-1v8 = <0x7>;
82                 cd-gpios = <&gpio TEGRA_GPIO_PZ1 0>;
83                 pll_source = "pll_p";
84                 nvidia,en-io-trim-volt;
85                 nvidia,en-periodic-calib;
86         };
87 };