27c3e03a3c36091d3ef62a1fdbc7da569ab47559
[linux-3.10.git] / arch / arm / mm / cache-l2x0.c
1 /*
2  * arch/arm/mm/cache-l2x0.c - L210/L220 cache controller support
3  *
4  * Copyright (C) 2007 ARM Limited
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License version 2 as
8  * published by the Free Software Foundation.
9  *
10  * This program is distributed in the hope that it will be useful,
11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13  * GNU General Public License for more details.
14  *
15  * You should have received a copy of the GNU General Public License
16  * along with this program; if not, write to the Free Software
17  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18  */
19 #include <linux/err.h>
20 #include <linux/init.h>
21 #include <linux/spinlock.h>
22 #include <linux/io.h>
23 #include <linux/of.h>
24 #include <linux/of_address.h>
25
26 #include <asm/cacheflush.h>
27 #include <asm/hardware/cache-l2x0.h>
28 #include "cache-aurora-l2.h"
29
30 #define CACHE_LINE_SIZE         32
31
32 static void __iomem *l2x0_base;
33 static DEFINE_RAW_SPINLOCK(l2x0_lock);
34 static u32 l2x0_way_mask;       /* Bitmask of active ways */
35 static u32 l2x0_size;
36 static u32 l2x0_cache_id;
37 static unsigned int l2x0_sets;
38 static unsigned int l2x0_ways;
39 static unsigned long sync_reg_offset = L2X0_CACHE_SYNC;
40
41 /* Aurora don't have the cache ID register available, so we have to
42  * pass it though the device tree */
43 static u32  cache_id_part_number_from_dt;
44
45 struct l2x0_regs l2x0_saved_regs;
46
47 struct l2x0_of_data {
48         void (*setup)(const struct device_node *, u32 *, u32 *);
49         void (*save)(void);
50         struct outer_cache_fns outer_cache;
51 };
52
53 static bool of_init = false;
54
55 static inline bool is_pl310_rev(int rev)
56 {
57         return (l2x0_cache_id &
58                 (L2X0_CACHE_ID_PART_MASK | L2X0_CACHE_ID_REV_MASK)) ==
59                         (L2X0_CACHE_ID_PART_L310 | rev);
60 }
61
62 static inline void cache_wait_way(void __iomem *reg, unsigned long mask)
63 {
64         /* wait for cache operation by line or way to complete */
65         while (readl_relaxed(reg) & mask)
66                 cpu_relax();
67 }
68
69 #ifdef CONFIG_CACHE_PL310
70 static inline void cache_wait(void __iomem *reg, unsigned long mask)
71 {
72         /* cache operations by line are atomic on PL310 */
73 }
74 #else
75 #define cache_wait      cache_wait_way
76 #endif
77
78 static inline void cache_sync(void)
79 {
80         void __iomem *base = l2x0_base;
81
82         writel_relaxed(0, base + sync_reg_offset);
83         cache_wait(base + L2X0_CACHE_SYNC, 1);
84 }
85
86 static inline void l2x0_clean_line(unsigned long addr)
87 {
88         void __iomem *base = l2x0_base;
89         cache_wait(base + L2X0_CLEAN_LINE_PA, 1);
90         writel_relaxed(addr, base + L2X0_CLEAN_LINE_PA);
91 }
92
93 static inline void l2x0_inv_line(unsigned long addr)
94 {
95         void __iomem *base = l2x0_base;
96         cache_wait(base + L2X0_INV_LINE_PA, 1);
97         writel_relaxed(addr, base + L2X0_INV_LINE_PA);
98 }
99
100 #if defined(CONFIG_PL310_ERRATA_588369) || defined(CONFIG_PL310_ERRATA_727915)
101 static inline void debug_writel(unsigned long val)
102 {
103         if (outer_cache.set_debug)
104                 outer_cache.set_debug(val);
105 }
106
107 static void pl310_set_debug(unsigned long val)
108 {
109         writel_relaxed(val, l2x0_base + L2X0_DEBUG_CTRL);
110 }
111 #else
112 /* Optimised out for non-errata case */
113 static inline void debug_writel(unsigned long val)
114 {
115 }
116
117 #define pl310_set_debug NULL
118 #endif
119
120 #ifdef CONFIG_PL310_ERRATA_588369
121 static inline void l2x0_flush_line(unsigned long addr)
122 {
123         void __iomem *base = l2x0_base;
124
125         /* Clean by PA followed by Invalidate by PA */
126         cache_wait(base + L2X0_CLEAN_LINE_PA, 1);
127         writel_relaxed(addr, base + L2X0_CLEAN_LINE_PA);
128         cache_wait(base + L2X0_INV_LINE_PA, 1);
129         writel_relaxed(addr, base + L2X0_INV_LINE_PA);
130 }
131 #else
132
133 static inline void l2x0_flush_line(unsigned long addr)
134 {
135         void __iomem *base = l2x0_base;
136         cache_wait(base + L2X0_CLEAN_INV_LINE_PA, 1);
137         writel_relaxed(addr, base + L2X0_CLEAN_INV_LINE_PA);
138 }
139 #endif
140
141 static void l2x0_cache_sync(void)
142 {
143         unsigned long flags;
144
145         raw_spin_lock_irqsave(&l2x0_lock, flags);
146         cache_sync();
147         raw_spin_unlock_irqrestore(&l2x0_lock, flags);
148 }
149
150 #ifdef CONFIG_PL310_ERRATA_727915
151 static void l2x0_for_each_set_way(void __iomem *reg)
152 {
153         int set;
154         int way;
155         unsigned long flags;
156
157         for (way = 0; way < l2x0_ways; way++) {
158                 raw_spin_lock_irqsave(&l2x0_lock, flags);
159                 for (set = 0; set < l2x0_sets; set++)
160                         writel_relaxed((way << 28) | (set << 5), reg);
161                 cache_sync();
162                 raw_spin_unlock_irqrestore(&l2x0_lock, flags);
163         }
164 }
165 #endif
166
167 static void __l2x0_flush_all(void)
168 {
169         debug_writel(0x03);
170         writel_relaxed(l2x0_way_mask, l2x0_base + L2X0_CLEAN_INV_WAY);
171         cache_wait_way(l2x0_base + L2X0_CLEAN_INV_WAY, l2x0_way_mask);
172         cache_sync();
173         debug_writel(0x00);
174 }
175
176 static void l2x0_flush_all(void)
177 {
178         unsigned long flags;
179
180 #ifdef CONFIG_PL310_ERRATA_727915
181         if (is_pl310_rev(REV_PL310_R2P0)) {
182                 l2x0_for_each_set_way(l2x0_base + L2X0_CLEAN_INV_LINE_IDX);
183                 return;
184         }
185 #endif
186
187         /* clean all ways */
188         raw_spin_lock_irqsave(&l2x0_lock, flags);
189         __l2x0_flush_all();
190         raw_spin_unlock_irqrestore(&l2x0_lock, flags);
191 }
192
193 static void l2x0_clean_all(void)
194 {
195         unsigned long flags;
196
197 #ifdef CONFIG_PL310_ERRATA_727915
198         if (is_pl310_rev(REV_PL310_R2P0)) {
199                 l2x0_for_each_set_way(l2x0_base + L2X0_CLEAN_LINE_IDX);
200                 return;
201         }
202 #endif
203
204         /* clean all ways */
205         raw_spin_lock_irqsave(&l2x0_lock, flags);
206         debug_writel(0x03);
207         writel_relaxed(l2x0_way_mask, l2x0_base + L2X0_CLEAN_WAY);
208         cache_wait_way(l2x0_base + L2X0_CLEAN_WAY, l2x0_way_mask);
209         cache_sync();
210         debug_writel(0x00);
211         raw_spin_unlock_irqrestore(&l2x0_lock, flags);
212 }
213
214 static void l2x0_inv_all(void)
215 {
216         unsigned long flags;
217
218         /* invalidate all ways */
219         raw_spin_lock_irqsave(&l2x0_lock, flags);
220         /* Invalidating when L2 is enabled is a nono */
221         BUG_ON(readl(l2x0_base + L2X0_CTRL) & L2X0_CTRL_EN);
222         writel_relaxed(l2x0_way_mask, l2x0_base + L2X0_INV_WAY);
223         cache_wait_way(l2x0_base + L2X0_INV_WAY, l2x0_way_mask);
224         cache_sync();
225         raw_spin_unlock_irqrestore(&l2x0_lock, flags);
226 }
227
228 static void l2x0_inv_range(unsigned long start, unsigned long end)
229 {
230         void __iomem *base = l2x0_base;
231         unsigned long flags;
232
233         raw_spin_lock_irqsave(&l2x0_lock, flags);
234         if (start & (CACHE_LINE_SIZE - 1)) {
235                 start &= ~(CACHE_LINE_SIZE - 1);
236                 debug_writel(0x03);
237                 l2x0_flush_line(start);
238                 debug_writel(0x00);
239                 start += CACHE_LINE_SIZE;
240         }
241
242         if (end & (CACHE_LINE_SIZE - 1)) {
243                 end &= ~(CACHE_LINE_SIZE - 1);
244                 debug_writel(0x03);
245                 l2x0_flush_line(end);
246                 debug_writel(0x00);
247         }
248
249         while (start < end) {
250                 unsigned long blk_end = start + min(end - start, 4096UL);
251
252                 while (start < blk_end) {
253                         l2x0_inv_line(start);
254                         start += CACHE_LINE_SIZE;
255                 }
256
257                 if (blk_end < end) {
258                         raw_spin_unlock_irqrestore(&l2x0_lock, flags);
259                         raw_spin_lock_irqsave(&l2x0_lock, flags);
260                 }
261         }
262         cache_wait(base + L2X0_INV_LINE_PA, 1);
263         cache_sync();
264         raw_spin_unlock_irqrestore(&l2x0_lock, flags);
265 }
266
267 static void l2x0_clean_range(unsigned long start, unsigned long end)
268 {
269         void __iomem *base = l2x0_base;
270         unsigned long flags;
271
272         if ((end - start) >= l2x0_size) {
273                 l2x0_clean_all();
274                 return;
275         }
276
277         raw_spin_lock_irqsave(&l2x0_lock, flags);
278         start &= ~(CACHE_LINE_SIZE - 1);
279         while (start < end) {
280                 unsigned long blk_end = start + min(end - start, 4096UL);
281
282                 while (start < blk_end) {
283                         l2x0_clean_line(start);
284                         start += CACHE_LINE_SIZE;
285                 }
286
287                 if (blk_end < end) {
288                         raw_spin_unlock_irqrestore(&l2x0_lock, flags);
289                         raw_spin_lock_irqsave(&l2x0_lock, flags);
290                 }
291         }
292         cache_wait(base + L2X0_CLEAN_LINE_PA, 1);
293         cache_sync();
294         raw_spin_unlock_irqrestore(&l2x0_lock, flags);
295 }
296
297 static void l2x0_flush_range(unsigned long start, unsigned long end)
298 {
299         void __iomem *base = l2x0_base;
300         unsigned long flags;
301
302         if ((end - start) >= l2x0_size) {
303                 l2x0_flush_all();
304                 return;
305         }
306
307         raw_spin_lock_irqsave(&l2x0_lock, flags);
308         start &= ~(CACHE_LINE_SIZE - 1);
309         while (start < end) {
310                 unsigned long blk_end = start + min(end - start, 4096UL);
311
312                 debug_writel(0x03);
313                 while (start < blk_end) {
314                         l2x0_flush_line(start);
315                         start += CACHE_LINE_SIZE;
316                 }
317                 debug_writel(0x00);
318
319                 if (blk_end < end) {
320                         raw_spin_unlock_irqrestore(&l2x0_lock, flags);
321                         raw_spin_lock_irqsave(&l2x0_lock, flags);
322                 }
323         }
324         cache_wait(base + L2X0_CLEAN_INV_LINE_PA, 1);
325         cache_sync();
326         raw_spin_unlock_irqrestore(&l2x0_lock, flags);
327 }
328
329 /* enables l2x0 after l2x0_disable, does not invalidate */
330 void l2x0_enable(void)
331 {
332         unsigned long flags;
333
334         raw_spin_lock_irqsave(&l2x0_lock, flags);
335         writel_relaxed(1, l2x0_base + L2X0_CTRL);
336         raw_spin_unlock_irqrestore(&l2x0_lock, flags);
337 }
338
339 static void l2x0_disable(void)
340 {
341         unsigned long flags;
342
343         raw_spin_lock_irqsave(&l2x0_lock, flags);
344         __l2x0_flush_all();
345         writel_relaxed(0, l2x0_base + L2X0_CTRL);
346         dsb();
347         raw_spin_unlock_irqrestore(&l2x0_lock, flags);
348 }
349
350 static void l2x0_unlock(u32 cache_id)
351 {
352         int lockregs;
353         int i;
354
355         switch (cache_id & L2X0_CACHE_ID_PART_MASK) {
356         case L2X0_CACHE_ID_PART_L310:
357                 lockregs = 8;
358                 break;
359         case AURORA_CACHE_ID:
360                 lockregs = 4;
361                 break;
362         default:
363                 /* L210 and unknown types */
364                 lockregs = 1;
365                 break;
366         }
367
368         for (i = 0; i < lockregs; i++) {
369                 writel_relaxed(0x0, l2x0_base + L2X0_LOCKDOWN_WAY_D_BASE +
370                                i * L2X0_LOCKDOWN_STRIDE);
371                 writel_relaxed(0x0, l2x0_base + L2X0_LOCKDOWN_WAY_I_BASE +
372                                i * L2X0_LOCKDOWN_STRIDE);
373         }
374 }
375
376 void l2x0_init(void __iomem *base, u32 aux_val, u32 aux_mask)
377 {
378         u32 aux;
379         u32 way_size = 0;
380         int way_size_shift = L2X0_WAY_SIZE_SHIFT;
381         const char *type;
382
383         l2x0_base = base;
384         if (cache_id_part_number_from_dt)
385                 l2x0_cache_id = cache_id_part_number_from_dt;
386         else
387                 l2x0_cache_id = readl_relaxed(l2x0_base + L2X0_CACHE_ID);
388         aux = readl_relaxed(l2x0_base + L2X0_AUX_CTRL);
389
390         /* Determine the number of ways */
391         switch (l2x0_cache_id & L2X0_CACHE_ID_PART_MASK) {
392         case L2X0_CACHE_ID_PART_L310:
393                 if (aux & (1 << 16))
394                         l2x0_ways = 16;
395                 else
396                         l2x0_ways = 8;
397                 type = "L310";
398 #ifdef CONFIG_PL310_ERRATA_753970
399                 /* Unmapped register. */
400                 sync_reg_offset = L2X0_DUMMY_REG;
401 #endif
402                 if ((l2x0_cache_id & L2X0_CACHE_ID_RTL_MASK) <= L2X0_CACHE_ID_RTL_R3P0)
403                         outer_cache.set_debug = pl310_set_debug;
404
405                 /*
406                  * Set bit 22 in the auxiliary control register. If this bit
407                  * is cleared, PL310 treats Normal Shared Non-cacheable
408                  * accesses as Cacheable no-allocate.
409                  */
410                 aux_val |= 1 << 22;
411                 break;
412         case L2X0_CACHE_ID_PART_L210:
413                 l2x0_ways = (aux >> 13) & 0xf;
414                 type = "L210";
415                 break;
416
417         case AURORA_CACHE_ID:
418                 sync_reg_offset = AURORA_SYNC_REG;
419                 l2x0_ways = (aux >> 13) & 0xf;
420                 l2x0_ways = 2 << ((l2x0_ways + 1) >> 2);
421                 way_size_shift = AURORA_WAY_SIZE_SHIFT;
422                 type = "Aurora";
423                 break;
424         default:
425                 /* Assume unknown chips have 8 ways */
426                 l2x0_ways = 8;
427                 type = "L2x0 series";
428                 break;
429         }
430
431         l2x0_way_mask = (1 << l2x0_ways) - 1;
432
433         /*
434          * L2 cache Size =  Way size * Number of ways
435          */
436         way_size = (aux & L2X0_AUX_CTRL_WAY_SIZE_MASK) >> 17;
437         way_size = SZ_1K << (way_size + way_size_shift);
438
439         l2x0_size = l2x0_ways * way_size;
440         l2x0_sets = way_size / CACHE_LINE_SIZE;
441
442         /*
443          * Check if l2x0 controller is already enabled.
444          * If you are booting from non-secure mode
445          * accessing the below registers will fault.
446          */
447         if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & L2X0_CTRL_EN)) {
448                 /* Make sure that I&D is not locked down when starting */
449                 l2x0_unlock(l2x0_cache_id);
450
451                 aux &= aux_mask;
452                 aux |= aux_val;
453
454                 /* l2x0 controller is disabled */
455                 writel_relaxed(aux, l2x0_base + L2X0_AUX_CTRL);
456
457                 l2x0_inv_all();
458
459                 /* enable L2X0 */
460                 writel_relaxed(L2X0_CTRL_EN, l2x0_base + L2X0_CTRL);
461         }
462
463         /* Re-read it in case some bits are reserved. */
464         aux = readl_relaxed(l2x0_base + L2X0_AUX_CTRL);
465
466         /* Save the value for resuming. */
467         l2x0_saved_regs.aux_ctrl = aux;
468
469         if (!of_init) {
470                 outer_cache.inv_range = l2x0_inv_range;
471                 outer_cache.clean_range = l2x0_clean_range;
472                 outer_cache.flush_range = l2x0_flush_range;
473                 outer_cache.sync = l2x0_cache_sync;
474                 outer_cache.flush_all = l2x0_flush_all;
475                 outer_cache.inv_all = l2x0_inv_all;
476                 outer_cache.disable = l2x0_disable;
477         }
478
479         pr_info_once("%s cache controller enabled\n", type);
480         pr_info_once("l2x0: %d ways, CACHE_ID 0x%08x, AUX_CTRL 0x%08x, Cache size: %d B\n",
481                         l2x0_ways, l2x0_cache_id, aux, l2x0_size);
482 }
483
484 #ifdef CONFIG_OF
485 static int l2_wt_override;
486
487 /*
488  * Note that the end addresses passed to Linux primitives are
489  * noninclusive, while the hardware cache range operations use
490  * inclusive start and end addresses.
491  */
492 static unsigned long calc_range_end(unsigned long start, unsigned long end)
493 {
494         /*
495          * Limit the number of cache lines processed at once,
496          * since cache range operations stall the CPU pipeline
497          * until completion.
498          */
499         if (end > start + MAX_RANGE_SIZE)
500                 end = start + MAX_RANGE_SIZE;
501
502         /*
503          * Cache range operations can't straddle a page boundary.
504          */
505         if (end > PAGE_ALIGN(start+1))
506                 end = PAGE_ALIGN(start+1);
507
508         return end;
509 }
510
511 /*
512  * Make sure 'start' and 'end' reference the same page, as L2 is PIPT
513  * and range operations only do a TLB lookup on the start address.
514  */
515 static void aurora_pa_range(unsigned long start, unsigned long end,
516                         unsigned long offset)
517 {
518         unsigned long flags;
519
520         raw_spin_lock_irqsave(&l2x0_lock, flags);
521         writel_relaxed(start, l2x0_base + AURORA_RANGE_BASE_ADDR_REG);
522         writel_relaxed(end, l2x0_base + offset);
523         raw_spin_unlock_irqrestore(&l2x0_lock, flags);
524
525         cache_sync();
526 }
527
528 static void aurora_inv_range(unsigned long start, unsigned long end)
529 {
530         /*
531          * round start and end adresses up to cache line size
532          */
533         start &= ~(CACHE_LINE_SIZE - 1);
534         end = ALIGN(end, CACHE_LINE_SIZE);
535
536         /*
537          * Invalidate all full cache lines between 'start' and 'end'.
538          */
539         while (start < end) {
540                 unsigned long range_end = calc_range_end(start, end);
541                 aurora_pa_range(start, range_end - CACHE_LINE_SIZE,
542                                 AURORA_INVAL_RANGE_REG);
543                 start = range_end;
544         }
545 }
546
547 static void aurora_clean_range(unsigned long start, unsigned long end)
548 {
549         /*
550          * If L2 is forced to WT, the L2 will always be clean and we
551          * don't need to do anything here.
552          */
553         if (!l2_wt_override) {
554                 start &= ~(CACHE_LINE_SIZE - 1);
555                 end = ALIGN(end, CACHE_LINE_SIZE);
556                 while (start != end) {
557                         unsigned long range_end = calc_range_end(start, end);
558                         aurora_pa_range(start, range_end - CACHE_LINE_SIZE,
559                                         AURORA_CLEAN_RANGE_REG);
560                         start = range_end;
561                 }
562         }
563 }
564
565 static void aurora_flush_range(unsigned long start, unsigned long end)
566 {
567         start &= ~(CACHE_LINE_SIZE - 1);
568         end = ALIGN(end, CACHE_LINE_SIZE);
569         while (start != end) {
570                 unsigned long range_end = calc_range_end(start, end);
571                 /*
572                  * If L2 is forced to WT, the L2 will always be clean and we
573                  * just need to invalidate.
574                  */
575                 if (l2_wt_override)
576                         aurora_pa_range(start, range_end - CACHE_LINE_SIZE,
577                                                         AURORA_INVAL_RANGE_REG);
578                 else
579                         aurora_pa_range(start, range_end - CACHE_LINE_SIZE,
580                                                         AURORA_FLUSH_RANGE_REG);
581                 start = range_end;
582         }
583 }
584
585 static void __init l2x0_of_setup(const struct device_node *np,
586                                  u32 *aux_val, u32 *aux_mask)
587 {
588         u32 data[2] = { 0, 0 };
589         u32 tag = 0;
590         u32 dirty = 0;
591         u32 val = 0, mask = 0;
592
593         of_property_read_u32(np, "arm,tag-latency", &tag);
594         if (tag) {
595                 mask |= L2X0_AUX_CTRL_TAG_LATENCY_MASK;
596                 val |= (tag - 1) << L2X0_AUX_CTRL_TAG_LATENCY_SHIFT;
597         }
598
599         of_property_read_u32_array(np, "arm,data-latency",
600                                    data, ARRAY_SIZE(data));
601         if (data[0] && data[1]) {
602                 mask |= L2X0_AUX_CTRL_DATA_RD_LATENCY_MASK |
603                         L2X0_AUX_CTRL_DATA_WR_LATENCY_MASK;
604                 val |= ((data[0] - 1) << L2X0_AUX_CTRL_DATA_RD_LATENCY_SHIFT) |
605                        ((data[1] - 1) << L2X0_AUX_CTRL_DATA_WR_LATENCY_SHIFT);
606         }
607
608         of_property_read_u32(np, "arm,dirty-latency", &dirty);
609         if (dirty) {
610                 mask |= L2X0_AUX_CTRL_DIRTY_LATENCY_MASK;
611                 val |= (dirty - 1) << L2X0_AUX_CTRL_DIRTY_LATENCY_SHIFT;
612         }
613
614         *aux_val &= ~mask;
615         *aux_val |= val;
616         *aux_mask &= ~mask;
617 }
618
619 static void __init pl310_of_setup(const struct device_node *np,
620                                   u32 *aux_val, u32 *aux_mask)
621 {
622         u32 data[3] = { 0, 0, 0 };
623         u32 tag[3] = { 0, 0, 0 };
624         u32 filter[2] = { 0, 0 };
625
626         of_property_read_u32_array(np, "arm,tag-latency", tag, ARRAY_SIZE(tag));
627         if (tag[0] && tag[1] && tag[2])
628                 writel_relaxed(
629                         ((tag[0] - 1) << L2X0_LATENCY_CTRL_RD_SHIFT) |
630                         ((tag[1] - 1) << L2X0_LATENCY_CTRL_WR_SHIFT) |
631                         ((tag[2] - 1) << L2X0_LATENCY_CTRL_SETUP_SHIFT),
632                         l2x0_base + L2X0_TAG_LATENCY_CTRL);
633
634         of_property_read_u32_array(np, "arm,data-latency",
635                                    data, ARRAY_SIZE(data));
636         if (data[0] && data[1] && data[2])
637                 writel_relaxed(
638                         ((data[0] - 1) << L2X0_LATENCY_CTRL_RD_SHIFT) |
639                         ((data[1] - 1) << L2X0_LATENCY_CTRL_WR_SHIFT) |
640                         ((data[2] - 1) << L2X0_LATENCY_CTRL_SETUP_SHIFT),
641                         l2x0_base + L2X0_DATA_LATENCY_CTRL);
642
643         of_property_read_u32_array(np, "arm,filter-ranges",
644                                    filter, ARRAY_SIZE(filter));
645         if (filter[1]) {
646                 writel_relaxed(ALIGN(filter[0] + filter[1], SZ_1M),
647                                l2x0_base + L2X0_ADDR_FILTER_END);
648                 writel_relaxed((filter[0] & ~(SZ_1M - 1)) | L2X0_ADDR_FILTER_EN,
649                                l2x0_base + L2X0_ADDR_FILTER_START);
650         }
651 }
652
653 static void __init pl310_save(void)
654 {
655         u32 l2x0_revision = readl_relaxed(l2x0_base + L2X0_CACHE_ID) &
656                 L2X0_CACHE_ID_RTL_MASK;
657
658         l2x0_saved_regs.tag_latency = readl_relaxed(l2x0_base +
659                 L2X0_TAG_LATENCY_CTRL);
660         l2x0_saved_regs.data_latency = readl_relaxed(l2x0_base +
661                 L2X0_DATA_LATENCY_CTRL);
662         l2x0_saved_regs.filter_end = readl_relaxed(l2x0_base +
663                 L2X0_ADDR_FILTER_END);
664         l2x0_saved_regs.filter_start = readl_relaxed(l2x0_base +
665                 L2X0_ADDR_FILTER_START);
666
667         if (l2x0_revision >= L2X0_CACHE_ID_RTL_R2P0) {
668                 /*
669                  * From r2p0, there is Prefetch offset/control register
670                  */
671                 l2x0_saved_regs.prefetch_ctrl = readl_relaxed(l2x0_base +
672                         L2X0_PREFETCH_CTRL);
673                 /*
674                  * From r3p0, there is Power control register
675                  */
676                 if (l2x0_revision >= L2X0_CACHE_ID_RTL_R3P0)
677                         l2x0_saved_regs.pwr_ctrl = readl_relaxed(l2x0_base +
678                                 L2X0_POWER_CTRL);
679         }
680 }
681
682 static void aurora_save(void)
683 {
684         l2x0_saved_regs.ctrl = readl_relaxed(l2x0_base + L2X0_CTRL);
685         l2x0_saved_regs.aux_ctrl = readl_relaxed(l2x0_base + L2X0_AUX_CTRL);
686 }
687
688 static void l2x0_resume(void)
689 {
690         if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & L2X0_CTRL_EN)) {
691                 /* restore aux ctrl and enable l2 */
692                 l2x0_unlock(readl_relaxed(l2x0_base + L2X0_CACHE_ID));
693
694                 writel_relaxed(l2x0_saved_regs.aux_ctrl, l2x0_base +
695                         L2X0_AUX_CTRL);
696
697                 l2x0_inv_all();
698
699                 writel_relaxed(L2X0_CTRL_EN, l2x0_base + L2X0_CTRL);
700         }
701 }
702
703 static void pl310_resume(void)
704 {
705         u32 l2x0_revision;
706
707         if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & L2X0_CTRL_EN)) {
708                 /* restore pl310 setup */
709                 writel_relaxed(l2x0_saved_regs.tag_latency,
710                         l2x0_base + L2X0_TAG_LATENCY_CTRL);
711                 writel_relaxed(l2x0_saved_regs.data_latency,
712                         l2x0_base + L2X0_DATA_LATENCY_CTRL);
713                 writel_relaxed(l2x0_saved_regs.filter_end,
714                         l2x0_base + L2X0_ADDR_FILTER_END);
715                 writel_relaxed(l2x0_saved_regs.filter_start,
716                         l2x0_base + L2X0_ADDR_FILTER_START);
717
718                 l2x0_revision = readl_relaxed(l2x0_base + L2X0_CACHE_ID) &
719                         L2X0_CACHE_ID_RTL_MASK;
720
721                 if (l2x0_revision >= L2X0_CACHE_ID_RTL_R2P0) {
722                         writel_relaxed(l2x0_saved_regs.prefetch_ctrl,
723                                 l2x0_base + L2X0_PREFETCH_CTRL);
724                         if (l2x0_revision >= L2X0_CACHE_ID_RTL_R3P0)
725                                 writel_relaxed(l2x0_saved_regs.pwr_ctrl,
726                                         l2x0_base + L2X0_POWER_CTRL);
727                 }
728         }
729
730         l2x0_resume();
731 }
732
733 static void aurora_resume(void)
734 {
735         if (!(readl(l2x0_base + L2X0_CTRL) & L2X0_CTRL_EN)) {
736                 writel_relaxed(l2x0_saved_regs.aux_ctrl,
737                                 l2x0_base + L2X0_AUX_CTRL);
738                 writel_relaxed(l2x0_saved_regs.ctrl, l2x0_base + L2X0_CTRL);
739         }
740 }
741
742 static void __init aurora_broadcast_l2_commands(void)
743 {
744         __u32 u;
745         /* Enable Broadcasting of cache commands to L2*/
746         __asm__ __volatile__("mrc p15, 1, %0, c15, c2, 0" : "=r"(u));
747         u |= AURORA_CTRL_FW;            /* Set the FW bit */
748         __asm__ __volatile__("mcr p15, 1, %0, c15, c2, 0\n" : : "r"(u));
749         isb();
750 }
751
752 static void __init aurora_of_setup(const struct device_node *np,
753                                 u32 *aux_val, u32 *aux_mask)
754 {
755         u32 val = AURORA_ACR_REPLACEMENT_TYPE_SEMIPLRU;
756         u32 mask =  AURORA_ACR_REPLACEMENT_MASK;
757
758         of_property_read_u32(np, "cache-id-part",
759                         &cache_id_part_number_from_dt);
760
761         /* Determine and save the write policy */
762         l2_wt_override = of_property_read_bool(np, "wt-override");
763
764         if (l2_wt_override) {
765                 val |= AURORA_ACR_FORCE_WRITE_THRO_POLICY;
766                 mask |= AURORA_ACR_FORCE_WRITE_POLICY_MASK;
767         }
768
769         *aux_val &= ~mask;
770         *aux_val |= val;
771         *aux_mask &= ~mask;
772 }
773
774 static const struct l2x0_of_data pl310_data = {
775         .setup = pl310_of_setup,
776         .save  = pl310_save,
777         .outer_cache = {
778                 .resume      = pl310_resume,
779                 .inv_range   = l2x0_inv_range,
780                 .clean_range = l2x0_clean_range,
781                 .flush_range = l2x0_flush_range,
782                 .sync        = l2x0_cache_sync,
783                 .flush_all   = l2x0_flush_all,
784                 .inv_all     = l2x0_inv_all,
785                 .disable     = l2x0_disable,
786         },
787 };
788
789 static const struct l2x0_of_data l2x0_data = {
790         .setup = l2x0_of_setup,
791         .save  = NULL,
792         .outer_cache = {
793                 .resume      = l2x0_resume,
794                 .inv_range   = l2x0_inv_range,
795                 .clean_range = l2x0_clean_range,
796                 .flush_range = l2x0_flush_range,
797                 .sync        = l2x0_cache_sync,
798                 .flush_all   = l2x0_flush_all,
799                 .inv_all     = l2x0_inv_all,
800                 .disable     = l2x0_disable,
801         },
802 };
803
804 static const struct l2x0_of_data aurora_with_outer_data = {
805         .setup = aurora_of_setup,
806         .save  = aurora_save,
807         .outer_cache = {
808                 .resume      = aurora_resume,
809                 .inv_range   = aurora_inv_range,
810                 .clean_range = aurora_clean_range,
811                 .flush_range = aurora_flush_range,
812                 .sync        = l2x0_cache_sync,
813                 .flush_all   = l2x0_flush_all,
814                 .inv_all     = l2x0_inv_all,
815                 .disable     = l2x0_disable,
816         },
817 };
818
819 static const struct l2x0_of_data aurora_no_outer_data = {
820         .setup = aurora_of_setup,
821         .save  = aurora_save,
822         .outer_cache = {
823                 .resume      = aurora_resume,
824         },
825 };
826
827 static const struct of_device_id l2x0_ids[] __initconst = {
828         { .compatible = "arm,pl310-cache", .data = (void *)&pl310_data },
829         { .compatible = "arm,l220-cache", .data = (void *)&l2x0_data },
830         { .compatible = "arm,l210-cache", .data = (void *)&l2x0_data },
831         { .compatible = "marvell,aurora-system-cache",
832           .data = (void *)&aurora_no_outer_data},
833         { .compatible = "marvell,aurora-outer-cache",
834           .data = (void *)&aurora_with_outer_data},
835         {}
836 };
837
838 int __init l2x0_of_init(u32 aux_val, u32 aux_mask)
839 {
840         struct device_node *np;
841         const struct l2x0_of_data *data;
842         struct resource res;
843
844         np = of_find_matching_node(NULL, l2x0_ids);
845         if (!np)
846                 return -ENODEV;
847
848         if (of_address_to_resource(np, 0, &res))
849                 return -ENODEV;
850
851         l2x0_base = ioremap(res.start, resource_size(&res));
852         if (!l2x0_base)
853                 return -ENOMEM;
854
855         l2x0_saved_regs.phy_base = res.start;
856
857         data = of_match_node(l2x0_ids, np)->data;
858
859         /* L2 configuration can only be changed if the cache is disabled */
860         if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & L2X0_CTRL_EN)) {
861                 if (data->setup)
862                         data->setup(np, &aux_val, &aux_mask);
863
864                 /* For aurora cache in no outer mode select the
865                  * correct mode using the coprocessor*/
866                 if (data == &aurora_no_outer_data)
867                         aurora_broadcast_l2_commands();
868         }
869
870         if (data->save)
871                 data->save();
872
873         of_init = true;
874         memcpy(&outer_cache, &data->outer_cache, sizeof(outer_cache));
875         l2x0_init(l2x0_base, aux_val, aux_mask);
876
877         return 0;
878 }
879 #endif