ARM: Tegra: Add CONFIG_TEGRA_USE_SECURE_KERNEL
[linux-3.10.git] / arch / arm / mm / cache-l2x0.c
1 /*
2  * arch/arm/mm/cache-l2x0.c - L210/L220 cache controller support
3  *
4  * Copyright (C) 2007 ARM Limited
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License version 2 as
8  * published by the Free Software Foundation.
9  *
10  * This program is distributed in the hope that it will be useful,
11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13  * GNU General Public License for more details.
14  *
15  * You should have received a copy of the GNU General Public License
16  * along with this program; if not, write to the Free Software
17  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18  */
19 #include <linux/err.h>
20 #include <linux/init.h>
21 #include <linux/spinlock.h>
22 #include <linux/io.h>
23 #include <linux/of.h>
24 #include <linux/of_address.h>
25
26 #include <asm/cacheflush.h>
27 #include <asm/hardware/cache-l2x0.h>
28 #include "cache-aurora-l2.h"
29
30 #define CACHE_LINE_SIZE         32
31
32 static void __iomem *l2x0_base;
33 static DEFINE_RAW_SPINLOCK(l2x0_lock);
34 static u32 l2x0_way_mask;       /* Bitmask of active ways */
35 static u32 l2x0_size;
36 static u32 l2x0_cache_id;
37 static unsigned int l2x0_sets;
38 static unsigned int l2x0_ways;
39 static unsigned long sync_reg_offset = L2X0_CACHE_SYNC;
40
41 /* Aurora don't have the cache ID register available, so we have to
42  * pass it though the device tree */
43 static u32  cache_id_part_number_from_dt;
44
45 struct l2x0_regs l2x0_saved_regs;
46
47 struct l2x0_of_data {
48         void (*setup)(const struct device_node *, u32 *, u32 *);
49         void (*save)(void);
50         struct outer_cache_fns outer_cache;
51 };
52
53 static bool of_init = false;
54
55 static inline bool is_pl310_rev(int rev)
56 {
57         return (l2x0_cache_id &
58                 (L2X0_CACHE_ID_PART_MASK | L2X0_CACHE_ID_REV_MASK)) ==
59                         (L2X0_CACHE_ID_PART_L310 | rev);
60 }
61
62 static inline void cache_wait_way(void __iomem *reg, unsigned long mask)
63 {
64         /* wait for cache operation by line or way to complete */
65         while (readl_relaxed(reg) & mask)
66                 cpu_relax();
67 }
68
69 #ifdef CONFIG_CACHE_PL310
70 static inline void cache_wait(void __iomem *reg, unsigned long mask)
71 {
72         /* cache operations by line are atomic on PL310 */
73 }
74 #else
75 #define cache_wait      cache_wait_way
76 #endif
77
78 static inline void cache_sync(void)
79 {
80         void __iomem *base = l2x0_base;
81
82         writel_relaxed(0, base + sync_reg_offset);
83         cache_wait(base + L2X0_CACHE_SYNC, 1);
84 }
85
86 static inline void l2x0_clean_line(unsigned long addr)
87 {
88         void __iomem *base = l2x0_base;
89         cache_wait(base + L2X0_CLEAN_LINE_PA, 1);
90         writel_relaxed(addr, base + L2X0_CLEAN_LINE_PA);
91 }
92
93 static inline void l2x0_inv_line(unsigned long addr)
94 {
95         void __iomem *base = l2x0_base;
96         cache_wait(base + L2X0_INV_LINE_PA, 1);
97         writel_relaxed(addr, base + L2X0_INV_LINE_PA);
98 }
99
100 #if !defined(CONFIG_TEGRA_USE_SECURE_KERNEL) && \
101         (defined(CONFIG_PL310_ERRATA_588369) || defined(CONFIG_PL310_ERRATA_727915))
102 static inline void debug_writel(unsigned long val)
103 {
104         if (outer_cache.set_debug)
105                 outer_cache.set_debug(val);
106 }
107
108 static void pl310_set_debug(unsigned long val)
109 {
110         writel_relaxed(val, l2x0_base + L2X0_DEBUG_CTRL);
111 }
112 #else
113 /* Optimised out for non-errata case */
114 static inline void debug_writel(unsigned long val)
115 {
116 }
117
118 #define pl310_set_debug NULL
119 #endif
120
121 #ifdef CONFIG_PL310_ERRATA_588369
122 static inline void l2x0_flush_line(unsigned long addr)
123 {
124         void __iomem *base = l2x0_base;
125
126         /* Clean by PA followed by Invalidate by PA */
127         cache_wait(base + L2X0_CLEAN_LINE_PA, 1);
128         writel_relaxed(addr, base + L2X0_CLEAN_LINE_PA);
129         cache_wait(base + L2X0_INV_LINE_PA, 1);
130         writel_relaxed(addr, base + L2X0_INV_LINE_PA);
131 }
132 #else
133
134 static inline void l2x0_flush_line(unsigned long addr)
135 {
136         void __iomem *base = l2x0_base;
137         cache_wait(base + L2X0_CLEAN_INV_LINE_PA, 1);
138         writel_relaxed(addr, base + L2X0_CLEAN_INV_LINE_PA);
139 }
140 #endif
141
142 static void l2x0_cache_sync(void)
143 {
144         unsigned long flags;
145
146         raw_spin_lock_irqsave(&l2x0_lock, flags);
147         cache_sync();
148         raw_spin_unlock_irqrestore(&l2x0_lock, flags);
149 }
150
151 #ifdef CONFIG_PL310_ERRATA_727915
152 static void l2x0_for_each_set_way(void __iomem *reg)
153 {
154         int set;
155         int way;
156         unsigned long flags;
157
158         for (way = 0; way < l2x0_ways; way++) {
159                 raw_spin_lock_irqsave(&l2x0_lock, flags);
160                 for (set = 0; set < l2x0_sets; set++)
161                         writel_relaxed((way << 28) | (set << 5), reg);
162                 cache_sync();
163                 raw_spin_unlock_irqrestore(&l2x0_lock, flags);
164         }
165 }
166 #endif
167
168 static void __l2x0_flush_all(void)
169 {
170         debug_writel(0x03);
171         writel_relaxed(l2x0_way_mask, l2x0_base + L2X0_CLEAN_INV_WAY);
172         cache_wait_way(l2x0_base + L2X0_CLEAN_INV_WAY, l2x0_way_mask);
173         cache_sync();
174         debug_writel(0x00);
175 }
176
177 static void l2x0_flush_all(void)
178 {
179         unsigned long flags;
180
181 #ifdef CONFIG_PL310_ERRATA_727915
182         if (is_pl310_rev(REV_PL310_R2P0) || is_pl310_rev(REV_PL310_R3P1_50)) {
183                 l2x0_for_each_set_way(l2x0_base + L2X0_CLEAN_INV_LINE_IDX);
184                 return;
185         }
186 #endif
187
188         /* clean all ways */
189         raw_spin_lock_irqsave(&l2x0_lock, flags);
190         __l2x0_flush_all();
191         raw_spin_unlock_irqrestore(&l2x0_lock, flags);
192 }
193
194 static void l2x0_clean_all(void)
195 {
196         unsigned long flags;
197
198 #ifdef CONFIG_PL310_ERRATA_727915
199         if (is_pl310_rev(REV_PL310_R2P0) || is_pl310_rev(REV_PL310_R3P1_50)) {
200                 l2x0_for_each_set_way(l2x0_base + L2X0_CLEAN_LINE_IDX);
201                 return;
202         }
203 #endif
204
205         /* clean all ways */
206         raw_spin_lock_irqsave(&l2x0_lock, flags);
207         debug_writel(0x03);
208         writel_relaxed(l2x0_way_mask, l2x0_base + L2X0_CLEAN_WAY);
209         cache_wait_way(l2x0_base + L2X0_CLEAN_WAY, l2x0_way_mask);
210         cache_sync();
211         debug_writel(0x00);
212         raw_spin_unlock_irqrestore(&l2x0_lock, flags);
213 }
214
215 static void l2x0_inv_all(void)
216 {
217         unsigned long flags;
218
219         /* invalidate all ways */
220         raw_spin_lock_irqsave(&l2x0_lock, flags);
221         /* Invalidating when L2 is enabled is a nono */
222         BUG_ON(readl(l2x0_base + L2X0_CTRL) & L2X0_CTRL_EN);
223         writel_relaxed(l2x0_way_mask, l2x0_base + L2X0_INV_WAY);
224         cache_wait_way(l2x0_base + L2X0_INV_WAY, l2x0_way_mask);
225         cache_sync();
226         raw_spin_unlock_irqrestore(&l2x0_lock, flags);
227 }
228
229 static void l2x0_inv_range(unsigned long start, unsigned long end)
230 {
231         void __iomem *base = l2x0_base;
232         unsigned long flags;
233
234         raw_spin_lock_irqsave(&l2x0_lock, flags);
235         if (start & (CACHE_LINE_SIZE - 1)) {
236                 start &= ~(CACHE_LINE_SIZE - 1);
237                 debug_writel(0x03);
238                 l2x0_flush_line(start);
239                 debug_writel(0x00);
240                 start += CACHE_LINE_SIZE;
241         }
242
243         if (end & (CACHE_LINE_SIZE - 1)) {
244                 end &= ~(CACHE_LINE_SIZE - 1);
245                 debug_writel(0x03);
246                 l2x0_flush_line(end);
247                 debug_writel(0x00);
248         }
249
250         while (start < end) {
251                 unsigned long blk_end = start + min(end - start, 4096UL);
252
253                 while (start < blk_end) {
254                         l2x0_inv_line(start);
255                         start += CACHE_LINE_SIZE;
256                 }
257
258                 if (blk_end < end) {
259                         raw_spin_unlock_irqrestore(&l2x0_lock, flags);
260                         raw_spin_lock_irqsave(&l2x0_lock, flags);
261                 }
262         }
263         cache_wait(base + L2X0_INV_LINE_PA, 1);
264         cache_sync();
265         raw_spin_unlock_irqrestore(&l2x0_lock, flags);
266 }
267
268 static void l2x0_clean_range(unsigned long start, unsigned long end)
269 {
270         void __iomem *base = l2x0_base;
271         unsigned long flags;
272
273         if ((end - start) >= l2x0_size) {
274                 l2x0_clean_all();
275                 return;
276         }
277
278         raw_spin_lock_irqsave(&l2x0_lock, flags);
279         start &= ~(CACHE_LINE_SIZE - 1);
280         while (start < end) {
281                 unsigned long blk_end = start + min(end - start, 4096UL);
282
283                 while (start < blk_end) {
284                         l2x0_clean_line(start);
285                         start += CACHE_LINE_SIZE;
286                 }
287
288                 if (blk_end < end) {
289                         raw_spin_unlock_irqrestore(&l2x0_lock, flags);
290                         raw_spin_lock_irqsave(&l2x0_lock, flags);
291                 }
292         }
293         cache_wait(base + L2X0_CLEAN_LINE_PA, 1);
294         cache_sync();
295         raw_spin_unlock_irqrestore(&l2x0_lock, flags);
296 }
297
298 static uint32_t l2x0_get_size(void)
299 {
300         return l2x0_size;
301 }
302
303 static void l2x0_flush_range(unsigned long start, unsigned long end)
304 {
305         void __iomem *base = l2x0_base;
306         unsigned long flags;
307
308         if ((end - start) >= l2x0_size) {
309                 l2x0_flush_all();
310                 return;
311         }
312
313         raw_spin_lock_irqsave(&l2x0_lock, flags);
314         start &= ~(CACHE_LINE_SIZE - 1);
315         while (start < end) {
316                 unsigned long blk_end = start + min(end - start, 4096UL);
317
318                 debug_writel(0x03);
319                 while (start < blk_end) {
320                         l2x0_flush_line(start);
321                         start += CACHE_LINE_SIZE;
322                 }
323                 debug_writel(0x00);
324
325                 if (blk_end < end) {
326                         raw_spin_unlock_irqrestore(&l2x0_lock, flags);
327                         raw_spin_lock_irqsave(&l2x0_lock, flags);
328                 }
329         }
330         cache_wait(base + L2X0_CLEAN_INV_LINE_PA, 1);
331         cache_sync();
332         raw_spin_unlock_irqrestore(&l2x0_lock, flags);
333 }
334
335 /* enables l2x0 after l2x0_disable, does not invalidate */
336 void l2x0_enable(void)
337 {
338         unsigned long flags;
339
340         raw_spin_lock_irqsave(&l2x0_lock, flags);
341         writel_relaxed(1, l2x0_base + L2X0_CTRL);
342         raw_spin_unlock_irqrestore(&l2x0_lock, flags);
343 }
344
345 static void l2x0_disable(void)
346 {
347         unsigned long flags;
348
349         raw_spin_lock_irqsave(&l2x0_lock, flags);
350         __l2x0_flush_all();
351         writel_relaxed(0, l2x0_base + L2X0_CTRL);
352         dsb();
353         raw_spin_unlock_irqrestore(&l2x0_lock, flags);
354 }
355
356 static void l2x0_unlock(u32 cache_id)
357 {
358         int lockregs;
359         int i;
360
361         switch (cache_id & L2X0_CACHE_ID_PART_MASK) {
362         case L2X0_CACHE_ID_PART_L310:
363                 lockregs = 8;
364                 break;
365         case AURORA_CACHE_ID:
366                 lockregs = 4;
367                 break;
368         default:
369                 /* L210 and unknown types */
370                 lockregs = 1;
371                 break;
372         }
373
374         for (i = 0; i < lockregs; i++) {
375                 writel_relaxed(0x0, l2x0_base + L2X0_LOCKDOWN_WAY_D_BASE +
376                                i * L2X0_LOCKDOWN_STRIDE);
377                 writel_relaxed(0x0, l2x0_base + L2X0_LOCKDOWN_WAY_I_BASE +
378                                i * L2X0_LOCKDOWN_STRIDE);
379         }
380 }
381
382 void l2x0_init(void __iomem *base, u32 aux_val, u32 aux_mask)
383 {
384         u32 aux;
385         u32 way_size = 0;
386         int way_size_shift = L2X0_WAY_SIZE_SHIFT;
387         const char *type;
388
389         l2x0_base = base;
390         if (cache_id_part_number_from_dt)
391                 l2x0_cache_id = cache_id_part_number_from_dt;
392         else
393                 l2x0_cache_id = readl_relaxed(l2x0_base + L2X0_CACHE_ID);
394         aux = readl_relaxed(l2x0_base + L2X0_AUX_CTRL);
395
396         /* Determine the number of ways */
397         switch (l2x0_cache_id & L2X0_CACHE_ID_PART_MASK) {
398         case L2X0_CACHE_ID_PART_L310:
399                 if (aux & (1 << 16))
400                         l2x0_ways = 16;
401                 else
402                         l2x0_ways = 8;
403                 type = "L310";
404 #ifdef CONFIG_PL310_ERRATA_753970
405                 /* Unmapped register. */
406                 sync_reg_offset = L2X0_DUMMY_REG;
407 #endif
408                 if ((l2x0_cache_id & L2X0_CACHE_ID_RTL_MASK) <= L2X0_CACHE_ID_RTL_R3P0)
409                         outer_cache.set_debug = pl310_set_debug;
410
411                 /*
412                  * Set bit 22 in the auxiliary control register. If this bit
413                  * is cleared, PL310 treats Normal Shared Non-cacheable
414                  * accesses as Cacheable no-allocate.
415                  */
416                 aux_val |= 1 << 22;
417                 break;
418         case L2X0_CACHE_ID_PART_L210:
419                 l2x0_ways = (aux >> 13) & 0xf;
420                 type = "L210";
421                 break;
422
423         case AURORA_CACHE_ID:
424                 sync_reg_offset = AURORA_SYNC_REG;
425                 l2x0_ways = (aux >> 13) & 0xf;
426                 l2x0_ways = 2 << ((l2x0_ways + 1) >> 2);
427                 way_size_shift = AURORA_WAY_SIZE_SHIFT;
428                 type = "Aurora";
429                 break;
430         default:
431                 /* Assume unknown chips have 8 ways */
432                 l2x0_ways = 8;
433                 type = "L2x0 series";
434                 break;
435         }
436
437         l2x0_way_mask = (1 << l2x0_ways) - 1;
438
439         /*
440          * L2 cache Size =  Way size * Number of ways
441          */
442         way_size = (aux & L2X0_AUX_CTRL_WAY_SIZE_MASK) >> 17;
443         way_size = SZ_1K << (way_size + way_size_shift);
444
445         l2x0_size = l2x0_ways * way_size;
446         l2x0_sets = way_size / CACHE_LINE_SIZE;
447
448         /*
449          * Check if l2x0 controller is already enabled.
450          * If you are booting from non-secure mode
451          * accessing the below registers will fault.
452          */
453         if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & L2X0_CTRL_EN)) {
454                 /* Make sure that I&D is not locked down when starting */
455                 l2x0_unlock(l2x0_cache_id);
456
457                 aux &= aux_mask;
458                 aux |= aux_val;
459
460                 /* l2x0 controller is disabled */
461                 writel_relaxed(aux, l2x0_base + L2X0_AUX_CTRL);
462
463                 l2x0_inv_all();
464
465                 /* enable L2X0 */
466                 writel_relaxed(L2X0_CTRL_EN, l2x0_base + L2X0_CTRL);
467         }
468
469         /* Re-read it in case some bits are reserved. */
470         aux = readl_relaxed(l2x0_base + L2X0_AUX_CTRL);
471
472         /* Save the value for resuming. */
473         l2x0_saved_regs.aux_ctrl = aux;
474
475         if (!of_init) {
476                 outer_cache.inv_range = l2x0_inv_range;
477                 outer_cache.clean_range = l2x0_clean_range;
478                 outer_cache.flush_range = l2x0_flush_range;
479                 outer_cache.get_size = l2x0_get_size;
480                 outer_cache.sync = l2x0_cache_sync;
481                 outer_cache.flush_all = l2x0_flush_all;
482                 outer_cache.clean_all = l2x0_clean_all;
483                 outer_cache.inv_all = l2x0_inv_all;
484                 outer_cache.disable = l2x0_disable;
485         }
486
487         pr_info_once("%s cache controller enabled\n", type);
488         pr_info_once("l2x0: %d ways, CACHE_ID 0x%08x, AUX_CTRL 0x%08x, Cache size: %d B\n",
489                         l2x0_ways, l2x0_cache_id, aux, l2x0_size);
490 }
491
492 #ifdef CONFIG_OF
493 static int l2_wt_override;
494
495 /*
496  * Note that the end addresses passed to Linux primitives are
497  * noninclusive, while the hardware cache range operations use
498  * inclusive start and end addresses.
499  */
500 static unsigned long calc_range_end(unsigned long start, unsigned long end)
501 {
502         /*
503          * Limit the number of cache lines processed at once,
504          * since cache range operations stall the CPU pipeline
505          * until completion.
506          */
507         if (end > start + MAX_RANGE_SIZE)
508                 end = start + MAX_RANGE_SIZE;
509
510         /*
511          * Cache range operations can't straddle a page boundary.
512          */
513         if (end > PAGE_ALIGN(start+1))
514                 end = PAGE_ALIGN(start+1);
515
516         return end;
517 }
518
519 /*
520  * Make sure 'start' and 'end' reference the same page, as L2 is PIPT
521  * and range operations only do a TLB lookup on the start address.
522  */
523 static void aurora_pa_range(unsigned long start, unsigned long end,
524                         unsigned long offset)
525 {
526         unsigned long flags;
527
528         raw_spin_lock_irqsave(&l2x0_lock, flags);
529         writel_relaxed(start, l2x0_base + AURORA_RANGE_BASE_ADDR_REG);
530         writel_relaxed(end, l2x0_base + offset);
531         raw_spin_unlock_irqrestore(&l2x0_lock, flags);
532
533         cache_sync();
534 }
535
536 static void aurora_inv_range(unsigned long start, unsigned long end)
537 {
538         /*
539          * round start and end adresses up to cache line size
540          */
541         start &= ~(CACHE_LINE_SIZE - 1);
542         end = ALIGN(end, CACHE_LINE_SIZE);
543
544         /*
545          * Invalidate all full cache lines between 'start' and 'end'.
546          */
547         while (start < end) {
548                 unsigned long range_end = calc_range_end(start, end);
549                 aurora_pa_range(start, range_end - CACHE_LINE_SIZE,
550                                 AURORA_INVAL_RANGE_REG);
551                 start = range_end;
552         }
553 }
554
555 static void aurora_clean_range(unsigned long start, unsigned long end)
556 {
557         /*
558          * If L2 is forced to WT, the L2 will always be clean and we
559          * don't need to do anything here.
560          */
561         if (!l2_wt_override) {
562                 start &= ~(CACHE_LINE_SIZE - 1);
563                 end = ALIGN(end, CACHE_LINE_SIZE);
564                 while (start != end) {
565                         unsigned long range_end = calc_range_end(start, end);
566                         aurora_pa_range(start, range_end - CACHE_LINE_SIZE,
567                                         AURORA_CLEAN_RANGE_REG);
568                         start = range_end;
569                 }
570         }
571 }
572
573 static void aurora_flush_range(unsigned long start, unsigned long end)
574 {
575         start &= ~(CACHE_LINE_SIZE - 1);
576         end = ALIGN(end, CACHE_LINE_SIZE);
577         while (start != end) {
578                 unsigned long range_end = calc_range_end(start, end);
579                 /*
580                  * If L2 is forced to WT, the L2 will always be clean and we
581                  * just need to invalidate.
582                  */
583                 if (l2_wt_override)
584                         aurora_pa_range(start, range_end - CACHE_LINE_SIZE,
585                                                         AURORA_INVAL_RANGE_REG);
586                 else
587                         aurora_pa_range(start, range_end - CACHE_LINE_SIZE,
588                                                         AURORA_FLUSH_RANGE_REG);
589                 start = range_end;
590         }
591 }
592
593 static void __init l2x0_of_setup(const struct device_node *np,
594                                  u32 *aux_val, u32 *aux_mask)
595 {
596         u32 data[2] = { 0, 0 };
597         u32 tag = 0;
598         u32 dirty = 0;
599         u32 val = 0, mask = 0;
600
601         of_property_read_u32(np, "arm,tag-latency", &tag);
602         if (tag) {
603                 mask |= L2X0_AUX_CTRL_TAG_LATENCY_MASK;
604                 val |= (tag - 1) << L2X0_AUX_CTRL_TAG_LATENCY_SHIFT;
605         }
606
607         of_property_read_u32_array(np, "arm,data-latency",
608                                    data, ARRAY_SIZE(data));
609         if (data[0] && data[1]) {
610                 mask |= L2X0_AUX_CTRL_DATA_RD_LATENCY_MASK |
611                         L2X0_AUX_CTRL_DATA_WR_LATENCY_MASK;
612                 val |= ((data[0] - 1) << L2X0_AUX_CTRL_DATA_RD_LATENCY_SHIFT) |
613                        ((data[1] - 1) << L2X0_AUX_CTRL_DATA_WR_LATENCY_SHIFT);
614         }
615
616         of_property_read_u32(np, "arm,dirty-latency", &dirty);
617         if (dirty) {
618                 mask |= L2X0_AUX_CTRL_DIRTY_LATENCY_MASK;
619                 val |= (dirty - 1) << L2X0_AUX_CTRL_DIRTY_LATENCY_SHIFT;
620         }
621
622         *aux_val &= ~mask;
623         *aux_val |= val;
624         *aux_mask &= ~mask;
625 }
626
627 static void __init pl310_of_setup(const struct device_node *np,
628                                   u32 *aux_val, u32 *aux_mask)
629 {
630         u32 data[3] = { 0, 0, 0 };
631         u32 tag[3] = { 0, 0, 0 };
632         u32 filter[2] = { 0, 0 };
633
634         of_property_read_u32_array(np, "arm,tag-latency", tag, ARRAY_SIZE(tag));
635         if (tag[0] && tag[1] && tag[2])
636                 writel_relaxed(
637                         ((tag[0] - 1) << L2X0_LATENCY_CTRL_RD_SHIFT) |
638                         ((tag[1] - 1) << L2X0_LATENCY_CTRL_WR_SHIFT) |
639                         ((tag[2] - 1) << L2X0_LATENCY_CTRL_SETUP_SHIFT),
640                         l2x0_base + L2X0_TAG_LATENCY_CTRL);
641
642         of_property_read_u32_array(np, "arm,data-latency",
643                                    data, ARRAY_SIZE(data));
644         if (data[0] && data[1] && data[2])
645                 writel_relaxed(
646                         ((data[0] - 1) << L2X0_LATENCY_CTRL_RD_SHIFT) |
647                         ((data[1] - 1) << L2X0_LATENCY_CTRL_WR_SHIFT) |
648                         ((data[2] - 1) << L2X0_LATENCY_CTRL_SETUP_SHIFT),
649                         l2x0_base + L2X0_DATA_LATENCY_CTRL);
650
651         of_property_read_u32_array(np, "arm,filter-ranges",
652                                    filter, ARRAY_SIZE(filter));
653         if (filter[1]) {
654                 writel_relaxed(ALIGN(filter[0] + filter[1], SZ_1M),
655                                l2x0_base + L2X0_ADDR_FILTER_END);
656                 writel_relaxed((filter[0] & ~(SZ_1M - 1)) | L2X0_ADDR_FILTER_EN,
657                                l2x0_base + L2X0_ADDR_FILTER_START);
658         }
659 }
660
661 static void __init pl310_save(void)
662 {
663         u32 l2x0_revision = readl_relaxed(l2x0_base + L2X0_CACHE_ID) &
664                 L2X0_CACHE_ID_RTL_MASK;
665
666         l2x0_saved_regs.tag_latency = readl_relaxed(l2x0_base +
667                 L2X0_TAG_LATENCY_CTRL);
668         l2x0_saved_regs.data_latency = readl_relaxed(l2x0_base +
669                 L2X0_DATA_LATENCY_CTRL);
670         l2x0_saved_regs.filter_end = readl_relaxed(l2x0_base +
671                 L2X0_ADDR_FILTER_END);
672         l2x0_saved_regs.filter_start = readl_relaxed(l2x0_base +
673                 L2X0_ADDR_FILTER_START);
674
675         if (l2x0_revision >= L2X0_CACHE_ID_RTL_R2P0) {
676                 /*
677                  * From r2p0, there is Prefetch offset/control register
678                  */
679                 l2x0_saved_regs.prefetch_ctrl = readl_relaxed(l2x0_base +
680                         L2X0_PREFETCH_CTRL);
681                 /*
682                  * From r3p0, there is Power control register
683                  */
684                 if (l2x0_revision >= L2X0_CACHE_ID_RTL_R3P0)
685                         l2x0_saved_regs.pwr_ctrl = readl_relaxed(l2x0_base +
686                                 L2X0_POWER_CTRL);
687         }
688 }
689
690 static void aurora_save(void)
691 {
692         l2x0_saved_regs.ctrl = readl_relaxed(l2x0_base + L2X0_CTRL);
693         l2x0_saved_regs.aux_ctrl = readl_relaxed(l2x0_base + L2X0_AUX_CTRL);
694 }
695
696 static void l2x0_resume(void)
697 {
698         if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & L2X0_CTRL_EN)) {
699                 /* restore aux ctrl and enable l2 */
700                 l2x0_unlock(readl_relaxed(l2x0_base + L2X0_CACHE_ID) &
701                         L2X0_CACHE_ID_PART_MASK);
702
703                 writel_relaxed(l2x0_saved_regs.aux_ctrl, l2x0_base +
704                         L2X0_AUX_CTRL);
705
706                 l2x0_inv_all();
707
708                 writel_relaxed(L2X0_CTRL_EN, l2x0_base + L2X0_CTRL);
709         }
710 }
711
712 static void pl310_resume(void)
713 {
714         u32 l2x0_revision;
715
716         if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & L2X0_CTRL_EN)) {
717                 /* restore pl310 setup */
718                 writel_relaxed(l2x0_saved_regs.tag_latency,
719                         l2x0_base + L2X0_TAG_LATENCY_CTRL);
720                 writel_relaxed(l2x0_saved_regs.data_latency,
721                         l2x0_base + L2X0_DATA_LATENCY_CTRL);
722                 writel_relaxed(l2x0_saved_regs.filter_end,
723                         l2x0_base + L2X0_ADDR_FILTER_END);
724                 writel_relaxed(l2x0_saved_regs.filter_start,
725                         l2x0_base + L2X0_ADDR_FILTER_START);
726
727                 l2x0_revision = readl_relaxed(l2x0_base + L2X0_CACHE_ID) &
728                         L2X0_CACHE_ID_RTL_MASK;
729
730                 if (l2x0_revision >= L2X0_CACHE_ID_RTL_R2P0) {
731                         writel_relaxed(l2x0_saved_regs.prefetch_ctrl,
732                                 l2x0_base + L2X0_PREFETCH_CTRL);
733                         if (l2x0_revision >= L2X0_CACHE_ID_RTL_R3P0)
734                                 writel_relaxed(l2x0_saved_regs.pwr_ctrl,
735                                         l2x0_base + L2X0_POWER_CTRL);
736                 }
737         }
738
739         l2x0_resume();
740 }
741
742 static void aurora_resume(void)
743 {
744         if (!(readl(l2x0_base + L2X0_CTRL) & L2X0_CTRL_EN)) {
745                 writel_relaxed(l2x0_saved_regs.aux_ctrl,
746                                 l2x0_base + L2X0_AUX_CTRL);
747                 writel_relaxed(l2x0_saved_regs.ctrl, l2x0_base + L2X0_CTRL);
748         }
749 }
750
751 static void __init aurora_broadcast_l2_commands(void)
752 {
753         __u32 u;
754         /* Enable Broadcasting of cache commands to L2*/
755         __asm__ __volatile__("mrc p15, 1, %0, c15, c2, 0" : "=r"(u));
756         u |= AURORA_CTRL_FW;            /* Set the FW bit */
757         __asm__ __volatile__("mcr p15, 1, %0, c15, c2, 0\n" : : "r"(u));
758         isb();
759 }
760
761 static void __init aurora_of_setup(const struct device_node *np,
762                                 u32 *aux_val, u32 *aux_mask)
763 {
764         u32 val = AURORA_ACR_REPLACEMENT_TYPE_SEMIPLRU;
765         u32 mask =  AURORA_ACR_REPLACEMENT_MASK;
766
767         of_property_read_u32(np, "cache-id-part",
768                         &cache_id_part_number_from_dt);
769
770         /* Determine and save the write policy */
771         l2_wt_override = of_property_read_bool(np, "wt-override");
772
773         if (l2_wt_override) {
774                 val |= AURORA_ACR_FORCE_WRITE_THRO_POLICY;
775                 mask |= AURORA_ACR_FORCE_WRITE_POLICY_MASK;
776         }
777
778         *aux_val &= ~mask;
779         *aux_val |= val;
780         *aux_mask &= ~mask;
781 }
782
783 static const struct l2x0_of_data pl310_data = {
784         .setup = pl310_of_setup,
785         .save  = pl310_save,
786         .outer_cache = {
787                 .resume      = pl310_resume,
788                 .inv_range   = l2x0_inv_range,
789                 .clean_range = l2x0_clean_range,
790                 .flush_range = l2x0_flush_range,
791                 .sync        = l2x0_cache_sync,
792                 .flush_all   = l2x0_flush_all,
793                 .inv_all     = l2x0_inv_all,
794                 .disable     = l2x0_disable,
795         },
796 };
797
798 static const struct l2x0_of_data l2x0_data = {
799         .setup = l2x0_of_setup,
800         .save  = NULL,
801         .outer_cache = {
802                 .resume      = l2x0_resume,
803                 .inv_range   = l2x0_inv_range,
804                 .clean_range = l2x0_clean_range,
805                 .flush_range = l2x0_flush_range,
806                 .sync        = l2x0_cache_sync,
807                 .flush_all   = l2x0_flush_all,
808                 .inv_all     = l2x0_inv_all,
809                 .disable     = l2x0_disable,
810         },
811 };
812
813 static const struct l2x0_of_data aurora_with_outer_data = {
814         .setup = aurora_of_setup,
815         .save  = aurora_save,
816         .outer_cache = {
817                 .resume      = aurora_resume,
818                 .inv_range   = aurora_inv_range,
819                 .clean_range = aurora_clean_range,
820                 .flush_range = aurora_flush_range,
821                 .sync        = l2x0_cache_sync,
822                 .flush_all   = l2x0_flush_all,
823                 .inv_all     = l2x0_inv_all,
824                 .disable     = l2x0_disable,
825         },
826 };
827
828 static const struct l2x0_of_data aurora_no_outer_data = {
829         .setup = aurora_of_setup,
830         .save  = aurora_save,
831         .outer_cache = {
832                 .resume      = aurora_resume,
833         },
834 };
835
836 static const struct of_device_id l2x0_ids[] __initconst = {
837         { .compatible = "arm,pl310-cache", .data = (void *)&pl310_data },
838         { .compatible = "arm,l220-cache", .data = (void *)&l2x0_data },
839         { .compatible = "arm,l210-cache", .data = (void *)&l2x0_data },
840         { .compatible = "marvell,aurora-system-cache",
841           .data = (void *)&aurora_no_outer_data},
842         { .compatible = "marvell,aurora-outer-cache",
843           .data = (void *)&aurora_with_outer_data},
844         {}
845 };
846
847 int __init l2x0_of_init(u32 aux_val, u32 aux_mask)
848 {
849         struct device_node *np;
850         const struct l2x0_of_data *data;
851         struct resource res;
852
853         np = of_find_matching_node(NULL, l2x0_ids);
854         if (!np)
855                 return -ENODEV;
856
857         if (of_address_to_resource(np, 0, &res))
858                 return -ENODEV;
859
860         l2x0_base = ioremap(res.start, resource_size(&res));
861         if (!l2x0_base)
862                 return -ENOMEM;
863
864         l2x0_saved_regs.phy_base = res.start;
865
866         data = of_match_node(l2x0_ids, np)->data;
867
868         /* L2 configuration can only be changed if the cache is disabled */
869         if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & L2X0_CTRL_EN)) {
870                 if (data->setup)
871                         data->setup(np, &aux_val, &aux_mask);
872
873                 /* For aurora cache in no outer mode select the
874                  * correct mode using the coprocessor*/
875                 if (data == &aurora_no_outer_data)
876                         aurora_broadcast_l2_commands();
877         }
878
879         if (data->save)
880                 data->save();
881
882         of_init = true;
883         memcpy(&outer_cache, &data->outer_cache, sizeof(outer_cache));
884         l2x0_init(l2x0_base, aux_val, aux_mask);
885
886         return 0;
887 }
888 #endif