ARM: vexpress: remove dependency on mach/* headers
[linux-3.10.git] / arch / arm / mach-vexpress / ct-ca9x4.c
1 /*
2  * Versatile Express Core Tile Cortex A9x4 Support
3  */
4 #include <linux/init.h>
5 #include <linux/gfp.h>
6 #include <linux/device.h>
7 #include <linux/dma-mapping.h>
8 #include <linux/platform_device.h>
9 #include <linux/amba/bus.h>
10 #include <linux/amba/clcd.h>
11 #include <linux/clkdev.h>
12
13 #include <asm/hardware/arm_timer.h>
14 #include <asm/hardware/cache-l2x0.h>
15 #include <asm/hardware/gic.h>
16 #include <asm/pmu.h>
17 #include <asm/smp_scu.h>
18 #include <asm/smp_twd.h>
19
20 #include <mach/ct-ca9x4.h>
21
22 #include <asm/hardware/timer-sp.h>
23
24 #include <asm/mach/map.h>
25 #include <asm/mach/time.h>
26
27 #include "core.h"
28
29 #include <mach/motherboard.h>
30 #include <mach/irqs.h>
31
32 #include <plat/clcd.h>
33
34 static struct map_desc ct_ca9x4_io_desc[] __initdata = {
35         {
36                 .virtual        = V2T_PERIPH,
37                 .pfn            = __phys_to_pfn(CT_CA9X4_MPIC),
38                 .length         = SZ_8K,
39                 .type           = MT_DEVICE,
40         },
41 };
42
43 static void __init ct_ca9x4_map_io(void)
44 {
45         iotable_init(ct_ca9x4_io_desc, ARRAY_SIZE(ct_ca9x4_io_desc));
46 }
47
48 #ifdef CONFIG_HAVE_ARM_TWD
49 static DEFINE_TWD_LOCAL_TIMER(twd_local_timer, A9_MPCORE_TWD, IRQ_LOCALTIMER);
50
51 static void __init ca9x4_twd_init(void)
52 {
53         int err = twd_local_timer_register(&twd_local_timer);
54         if (err)
55                 pr_err("twd_local_timer_register failed %d\n", err);
56 }
57 #else
58 #define ca9x4_twd_init()        do {} while(0)
59 #endif
60
61 static void __init ct_ca9x4_init_irq(void)
62 {
63         gic_init(0, 29, ioremap(A9_MPCORE_GIC_DIST, SZ_4K),
64                  ioremap(A9_MPCORE_GIC_CPU, SZ_256));
65         ca9x4_twd_init();
66 }
67
68 static void ct_ca9x4_clcd_enable(struct clcd_fb *fb)
69 {
70         u32 site = v2m_get_master_site();
71
72         /*
73          * Old firmware was using the "site" component of the command
74          * to control the DVI muxer (while it should be always 0 ie. MB).
75          * Newer firmware uses the data register. Keep both for compatibility.
76          */
77         v2m_cfg_write(SYS_CFG_MUXFPGA | SYS_CFG_SITE(site), site);
78         v2m_cfg_write(SYS_CFG_DVIMODE | SYS_CFG_SITE(SYS_CFG_SITE_MB), 2);
79 }
80
81 static int ct_ca9x4_clcd_setup(struct clcd_fb *fb)
82 {
83         unsigned long framesize = 1024 * 768 * 2;
84
85         fb->panel = versatile_clcd_get_panel("XVGA");
86         if (!fb->panel)
87                 return -EINVAL;
88
89         return versatile_clcd_setup_dma(fb, framesize);
90 }
91
92 static struct clcd_board ct_ca9x4_clcd_data = {
93         .name           = "CT-CA9X4",
94         .caps           = CLCD_CAP_5551 | CLCD_CAP_565,
95         .check          = clcdfb_check,
96         .decode         = clcdfb_decode,
97         .enable         = ct_ca9x4_clcd_enable,
98         .setup          = ct_ca9x4_clcd_setup,
99         .mmap           = versatile_clcd_mmap_dma,
100         .remove         = versatile_clcd_remove_dma,
101 };
102
103 static AMBA_AHB_DEVICE(clcd, "ct:clcd", 0, CT_CA9X4_CLCDC, IRQ_CT_CA9X4_CLCDC, &ct_ca9x4_clcd_data);
104 static AMBA_APB_DEVICE(dmc, "ct:dmc", 0, CT_CA9X4_DMC, IRQ_CT_CA9X4_DMC, NULL);
105 static AMBA_APB_DEVICE(smc, "ct:smc", 0, CT_CA9X4_SMC, IRQ_CT_CA9X4_SMC, NULL);
106 static AMBA_APB_DEVICE(gpio, "ct:gpio", 0, CT_CA9X4_GPIO, IRQ_CT_CA9X4_GPIO, NULL);
107
108 static struct amba_device *ct_ca9x4_amba_devs[] __initdata = {
109         &clcd_device,
110         &dmc_device,
111         &smc_device,
112         &gpio_device,
113 };
114
115
116 static struct v2m_osc ct_osc1 = {
117         .osc = 1,
118         .rate_min = 10000000,
119         .rate_max = 80000000,
120         .rate_default = 23750000,
121 };
122
123 static struct resource pmu_resources[] = {
124         [0] = {
125                 .start  = IRQ_CT_CA9X4_PMU_CPU0,
126                 .end    = IRQ_CT_CA9X4_PMU_CPU0,
127                 .flags  = IORESOURCE_IRQ,
128         },
129         [1] = {
130                 .start  = IRQ_CT_CA9X4_PMU_CPU1,
131                 .end    = IRQ_CT_CA9X4_PMU_CPU1,
132                 .flags  = IORESOURCE_IRQ,
133         },
134         [2] = {
135                 .start  = IRQ_CT_CA9X4_PMU_CPU2,
136                 .end    = IRQ_CT_CA9X4_PMU_CPU2,
137                 .flags  = IORESOURCE_IRQ,
138         },
139         [3] = {
140                 .start  = IRQ_CT_CA9X4_PMU_CPU3,
141                 .end    = IRQ_CT_CA9X4_PMU_CPU3,
142                 .flags  = IORESOURCE_IRQ,
143         },
144 };
145
146 static struct platform_device pmu_device = {
147         .name           = "arm-pmu",
148         .id             = ARM_PMU_DEVICE_CPU,
149         .num_resources  = ARRAY_SIZE(pmu_resources),
150         .resource       = pmu_resources,
151 };
152
153 static void __init ct_ca9x4_init(void)
154 {
155         int i;
156         struct clk *clk;
157
158 #ifdef CONFIG_CACHE_L2X0
159         void __iomem *l2x0_base = ioremap(CT_CA9X4_L2CC, SZ_4K);
160
161         /* set RAM latencies to 1 cycle for this core tile. */
162         writel(0, l2x0_base + L2X0_TAG_LATENCY_CTRL);
163         writel(0, l2x0_base + L2X0_DATA_LATENCY_CTRL);
164
165         l2x0_init(l2x0_base, 0x00400000, 0xfe0fffff);
166 #endif
167
168         ct_osc1.site = v2m_get_master_site();
169         clk = v2m_osc_register("ct:osc1", &ct_osc1);
170         clk_register_clkdev(clk, NULL, "ct:clcd");
171
172         for (i = 0; i < ARRAY_SIZE(ct_ca9x4_amba_devs); i++)
173                 amba_device_register(ct_ca9x4_amba_devs[i], &iomem_resource);
174
175         platform_device_register(&pmu_device);
176 }
177
178 #ifdef CONFIG_SMP
179 static void *ct_ca9x4_scu_base __initdata;
180
181 static void __init ct_ca9x4_init_cpu_map(void)
182 {
183         int i, ncores;
184
185         ct_ca9x4_scu_base = ioremap(A9_MPCORE_SCU, SZ_128);
186         if (WARN_ON(!ct_ca9x4_scu_base))
187                 return;
188
189         ncores = scu_get_core_count(ct_ca9x4_scu_base);
190
191         if (ncores > nr_cpu_ids) {
192                 pr_warn("SMP: %u cores greater than maximum (%u), clipping\n",
193                         ncores, nr_cpu_ids);
194                 ncores = nr_cpu_ids;
195         }
196
197         for (i = 0; i < ncores; ++i)
198                 set_cpu_possible(i, true);
199
200         set_smp_cross_call(gic_raise_softirq);
201 }
202
203 static void __init ct_ca9x4_smp_enable(unsigned int max_cpus)
204 {
205         scu_enable(ct_ca9x4_scu_base);
206 }
207 #endif
208
209 struct ct_desc ct_ca9x4_desc __initdata = {
210         .id             = V2M_CT_ID_CA9,
211         .name           = "CA9x4",
212         .map_io         = ct_ca9x4_map_io,
213         .init_irq       = ct_ca9x4_init_irq,
214         .init_tile      = ct_ca9x4_init,
215 #ifdef CONFIG_SMP
216         .init_cpu_map   = ct_ca9x4_init_cpu_map,
217         .smp_enable     = ct_ca9x4_smp_enable,
218 #endif
219 };