[PATCH] ARM: fixup irqflags breakage after ARM genirq merge
[linux-3.10.git] / arch / arm / mach-versatile / core.c
1 /*
2  *  linux/arch/arm/mach-versatile/core.c
3  *
4  *  Copyright (C) 1999 - 2003 ARM Limited
5  *  Copyright (C) 2000 Deep Blue Solutions Ltd
6  *
7  * This program is free software; you can redistribute it and/or modify
8  * it under the terms of the GNU General Public License as published by
9  * the Free Software Foundation; either version 2 of the License, or
10  * (at your option) any later version.
11  *
12  * This program is distributed in the hope that it will be useful,
13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15  * GNU General Public License for more details.
16  *
17  * You should have received a copy of the GNU General Public License
18  * along with this program; if not, write to the Free Software
19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
20  */
21 #include <linux/init.h>
22 #include <linux/device.h>
23 #include <linux/dma-mapping.h>
24 #include <linux/platform_device.h>
25 #include <linux/sysdev.h>
26 #include <linux/interrupt.h>
27 #include <linux/amba/bus.h>
28 #include <linux/amba/clcd.h>
29
30 #include <asm/system.h>
31 #include <asm/hardware.h>
32 #include <asm/io.h>
33 #include <asm/irq.h>
34 #include <asm/leds.h>
35 #include <asm/hardware/arm_timer.h>
36 #include <asm/hardware/icst307.h>
37 #include <asm/hardware/vic.h>
38
39 #include <asm/mach/arch.h>
40 #include <asm/mach/flash.h>
41 #include <asm/mach/irq.h>
42 #include <asm/mach/time.h>
43 #include <asm/mach/map.h>
44 #include <asm/mach/mmc.h>
45
46 #include "core.h"
47 #include "clock.h"
48
49 /*
50  * All IO addresses are mapped onto VA 0xFFFx.xxxx, where x.xxxx
51  * is the (PA >> 12).
52  *
53  * Setup a VA for the Versatile Vectored Interrupt Controller.
54  */
55 #define __io_address(n)         __io(IO_ADDRESS(n))
56 #define VA_VIC_BASE             __io_address(VERSATILE_VIC_BASE)
57 #define VA_SIC_BASE             __io_address(VERSATILE_SIC_BASE)
58
59 static void sic_mask_irq(unsigned int irq)
60 {
61         irq -= IRQ_SIC_START;
62         writel(1 << irq, VA_SIC_BASE + SIC_IRQ_ENABLE_CLEAR);
63 }
64
65 static void sic_unmask_irq(unsigned int irq)
66 {
67         irq -= IRQ_SIC_START;
68         writel(1 << irq, VA_SIC_BASE + SIC_IRQ_ENABLE_SET);
69 }
70
71 static struct irqchip sic_chip = {
72         .ack    = sic_mask_irq,
73         .mask   = sic_mask_irq,
74         .unmask = sic_unmask_irq,
75 };
76
77 static void
78 sic_handle_irq(unsigned int irq, struct irqdesc *desc, struct pt_regs *regs)
79 {
80         unsigned long status = readl(VA_SIC_BASE + SIC_IRQ_STATUS);
81
82         if (status == 0) {
83                 do_bad_IRQ(irq, desc, regs);
84                 return;
85         }
86
87         do {
88                 irq = ffs(status) - 1;
89                 status &= ~(1 << irq);
90
91                 irq += IRQ_SIC_START;
92
93                 desc = irq_desc + irq;
94                 desc_handle_irq(irq, desc, regs);
95         } while (status);
96 }
97
98 #if 1
99 #define IRQ_MMCI0A      IRQ_VICSOURCE22
100 #define IRQ_AACI        IRQ_VICSOURCE24
101 #define IRQ_ETH         IRQ_VICSOURCE25
102 #define PIC_MASK        0xFFD00000
103 #else
104 #define IRQ_MMCI0A      IRQ_SIC_MMCI0A
105 #define IRQ_AACI        IRQ_SIC_AACI
106 #define IRQ_ETH         IRQ_SIC_ETH
107 #define PIC_MASK        0
108 #endif
109
110 void __init versatile_init_irq(void)
111 {
112         unsigned int i;
113
114         vic_init(VA_VIC_BASE, IRQ_VIC_START, ~0);
115
116         set_irq_chained_handler(IRQ_VICSOURCE31, sic_handle_irq);
117
118         /* Do second interrupt controller */
119         writel(~0, VA_SIC_BASE + SIC_IRQ_ENABLE_CLEAR);
120
121         for (i = IRQ_SIC_START; i <= IRQ_SIC_END; i++) {
122                 if ((PIC_MASK & (1 << (i - IRQ_SIC_START))) == 0) {
123                         set_irq_chip(i, &sic_chip);
124                         set_irq_handler(i, do_level_IRQ);
125                         set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
126                 }
127         }
128
129         /*
130          * Interrupts on secondary controller from 0 to 8 are routed to
131          * source 31 on PIC.
132          * Interrupts from 21 to 31 are routed directly to the VIC on
133          * the corresponding number on primary controller. This is controlled
134          * by setting PIC_ENABLEx.
135          */
136         writel(PIC_MASK, VA_SIC_BASE + SIC_INT_PIC_ENABLE);
137 }
138
139 static struct map_desc versatile_io_desc[] __initdata = {
140         {
141                 .virtual        =  IO_ADDRESS(VERSATILE_SYS_BASE),
142                 .pfn            = __phys_to_pfn(VERSATILE_SYS_BASE),
143                 .length         = SZ_4K,
144                 .type           = MT_DEVICE
145         }, {
146                 .virtual        =  IO_ADDRESS(VERSATILE_SIC_BASE),
147                 .pfn            = __phys_to_pfn(VERSATILE_SIC_BASE),
148                 .length         = SZ_4K,
149                 .type           = MT_DEVICE
150         }, {
151                 .virtual        =  IO_ADDRESS(VERSATILE_VIC_BASE),
152                 .pfn            = __phys_to_pfn(VERSATILE_VIC_BASE),
153                 .length         = SZ_4K,
154                 .type           = MT_DEVICE
155         }, {
156                 .virtual        =  IO_ADDRESS(VERSATILE_SCTL_BASE),
157                 .pfn            = __phys_to_pfn(VERSATILE_SCTL_BASE),
158                 .length         = SZ_4K * 9,
159                 .type           = MT_DEVICE
160         },
161 #ifdef CONFIG_MACH_VERSATILE_AB
162         {
163                 .virtual        =  IO_ADDRESS(VERSATILE_GPIO0_BASE),
164                 .pfn            = __phys_to_pfn(VERSATILE_GPIO0_BASE),
165                 .length         = SZ_4K,
166                 .type           = MT_DEVICE
167         }, {
168                 .virtual        =  IO_ADDRESS(VERSATILE_IB2_BASE),
169                 .pfn            = __phys_to_pfn(VERSATILE_IB2_BASE),
170                 .length         = SZ_64M,
171                 .type           = MT_DEVICE
172         },
173 #endif
174 #ifdef CONFIG_DEBUG_LL
175         {
176                 .virtual        =  IO_ADDRESS(VERSATILE_UART0_BASE),
177                 .pfn            = __phys_to_pfn(VERSATILE_UART0_BASE),
178                 .length         = SZ_4K,
179                 .type           = MT_DEVICE
180         },
181 #endif
182 #ifdef CONFIG_PCI
183         {
184                 .virtual        =  IO_ADDRESS(VERSATILE_PCI_CORE_BASE),
185                 .pfn            = __phys_to_pfn(VERSATILE_PCI_CORE_BASE),
186                 .length         = SZ_4K,
187                 .type           = MT_DEVICE
188         }, {
189                 .virtual        =  VERSATILE_PCI_VIRT_BASE,
190                 .pfn            = __phys_to_pfn(VERSATILE_PCI_BASE),
191                 .length         = VERSATILE_PCI_BASE_SIZE,
192                 .type           = MT_DEVICE
193         }, {
194                 .virtual        =  VERSATILE_PCI_CFG_VIRT_BASE,
195                 .pfn            = __phys_to_pfn(VERSATILE_PCI_CFG_BASE),
196                 .length         = VERSATILE_PCI_CFG_BASE_SIZE,
197                 .type           = MT_DEVICE
198         },
199 #if 0
200         {
201                 .virtual        =  VERSATILE_PCI_VIRT_MEM_BASE0,
202                 .pfn            = __phys_to_pfn(VERSATILE_PCI_MEM_BASE0),
203                 .length         = SZ_16M,
204                 .type           = MT_DEVICE
205         }, {
206                 .virtual        =  VERSATILE_PCI_VIRT_MEM_BASE1,
207                 .pfn            = __phys_to_pfn(VERSATILE_PCI_MEM_BASE1),
208                 .length         = SZ_16M,
209                 .type           = MT_DEVICE
210         }, {
211                 .virtual        =  VERSATILE_PCI_VIRT_MEM_BASE2,
212                 .pfn            = __phys_to_pfn(VERSATILE_PCI_MEM_BASE2),
213                 .length         = SZ_16M,
214                 .type           = MT_DEVICE
215         },
216 #endif
217 #endif
218 };
219
220 void __init versatile_map_io(void)
221 {
222         iotable_init(versatile_io_desc, ARRAY_SIZE(versatile_io_desc));
223 }
224
225 #define VERSATILE_REFCOUNTER    (__io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_24MHz_OFFSET)
226
227 /*
228  * This is the Versatile sched_clock implementation.  This has
229  * a resolution of 41.7ns, and a maximum value of about 179s.
230  */
231 unsigned long long sched_clock(void)
232 {
233         unsigned long long v;
234
235         v = (unsigned long long)readl(VERSATILE_REFCOUNTER) * 125;
236         do_div(v, 3);
237
238         return v;
239 }
240
241
242 #define VERSATILE_FLASHCTRL    (__io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_FLASH_OFFSET)
243
244 static int versatile_flash_init(void)
245 {
246         u32 val;
247
248         val = __raw_readl(VERSATILE_FLASHCTRL);
249         val &= ~VERSATILE_FLASHPROG_FLVPPEN;
250         __raw_writel(val, VERSATILE_FLASHCTRL);
251
252         return 0;
253 }
254
255 static void versatile_flash_exit(void)
256 {
257         u32 val;
258
259         val = __raw_readl(VERSATILE_FLASHCTRL);
260         val &= ~VERSATILE_FLASHPROG_FLVPPEN;
261         __raw_writel(val, VERSATILE_FLASHCTRL);
262 }
263
264 static void versatile_flash_set_vpp(int on)
265 {
266         u32 val;
267
268         val = __raw_readl(VERSATILE_FLASHCTRL);
269         if (on)
270                 val |= VERSATILE_FLASHPROG_FLVPPEN;
271         else
272                 val &= ~VERSATILE_FLASHPROG_FLVPPEN;
273         __raw_writel(val, VERSATILE_FLASHCTRL);
274 }
275
276 static struct flash_platform_data versatile_flash_data = {
277         .map_name               = "cfi_probe",
278         .width                  = 4,
279         .init                   = versatile_flash_init,
280         .exit                   = versatile_flash_exit,
281         .set_vpp                = versatile_flash_set_vpp,
282 };
283
284 static struct resource versatile_flash_resource = {
285         .start                  = VERSATILE_FLASH_BASE,
286         .end                    = VERSATILE_FLASH_BASE + VERSATILE_FLASH_SIZE,
287         .flags                  = IORESOURCE_MEM,
288 };
289
290 static struct platform_device versatile_flash_device = {
291         .name                   = "armflash",
292         .id                     = 0,
293         .dev                    = {
294                 .platform_data  = &versatile_flash_data,
295         },
296         .num_resources          = 1,
297         .resource               = &versatile_flash_resource,
298 };
299
300 static struct resource smc91x_resources[] = {
301         [0] = {
302                 .start          = VERSATILE_ETH_BASE,
303                 .end            = VERSATILE_ETH_BASE + SZ_64K - 1,
304                 .flags          = IORESOURCE_MEM,
305         },
306         [1] = {
307                 .start          = IRQ_ETH,
308                 .end            = IRQ_ETH,
309                 .flags          = IORESOURCE_IRQ,
310         },
311 };
312
313 static struct platform_device smc91x_device = {
314         .name           = "smc91x",
315         .id             = 0,
316         .num_resources  = ARRAY_SIZE(smc91x_resources),
317         .resource       = smc91x_resources,
318 };
319
320 #define VERSATILE_SYSMCI        (__io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_MCI_OFFSET)
321
322 unsigned int mmc_status(struct device *dev)
323 {
324         struct amba_device *adev = container_of(dev, struct amba_device, dev);
325         u32 mask;
326
327         if (adev->res.start == VERSATILE_MMCI0_BASE)
328                 mask = 1;
329         else
330                 mask = 2;
331
332         return readl(VERSATILE_SYSMCI) & mask;
333 }
334
335 static struct mmc_platform_data mmc0_plat_data = {
336         .ocr_mask       = MMC_VDD_32_33|MMC_VDD_33_34,
337         .status         = mmc_status,
338 };
339
340 /*
341  * Clock handling
342  */
343 static const struct icst307_params versatile_oscvco_params = {
344         .ref            = 24000,
345         .vco_max        = 200000,
346         .vd_min         = 4 + 8,
347         .vd_max         = 511 + 8,
348         .rd_min         = 1 + 2,
349         .rd_max         = 127 + 2,
350 };
351
352 static void versatile_oscvco_set(struct clk *clk, struct icst307_vco vco)
353 {
354         void __iomem *sys_lock = __io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_LOCK_OFFSET;
355 #if defined(CONFIG_ARCH_VERSATILE_PB)
356         void __iomem *sys_osc = __io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_OSC4_OFFSET;
357 #elif defined(CONFIG_MACH_VERSATILE_AB)
358         void __iomem *sys_osc = __io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_OSC1_OFFSET;
359 #endif
360         u32 val;
361
362         val = readl(sys_osc) & ~0x7ffff;
363         val |= vco.v | (vco.r << 9) | (vco.s << 16);
364
365         writel(0xa05f, sys_lock);
366         writel(val, sys_osc);
367         writel(0, sys_lock);
368 }
369
370 static struct clk versatile_clcd_clk = {
371         .name   = "CLCDCLK",
372         .params = &versatile_oscvco_params,
373         .setvco = versatile_oscvco_set,
374 };
375
376 /*
377  * CLCD support.
378  */
379 #define SYS_CLCD_MODE_MASK      (3 << 0)
380 #define SYS_CLCD_MODE_888       (0 << 0)
381 #define SYS_CLCD_MODE_5551      (1 << 0)
382 #define SYS_CLCD_MODE_565_RLSB  (2 << 0)
383 #define SYS_CLCD_MODE_565_BLSB  (3 << 0)
384 #define SYS_CLCD_NLCDIOON       (1 << 2)
385 #define SYS_CLCD_VDDPOSSWITCH   (1 << 3)
386 #define SYS_CLCD_PWR3V5SWITCH   (1 << 4)
387 #define SYS_CLCD_ID_MASK        (0x1f << 8)
388 #define SYS_CLCD_ID_SANYO_3_8   (0x00 << 8)
389 #define SYS_CLCD_ID_UNKNOWN_8_4 (0x01 << 8)
390 #define SYS_CLCD_ID_EPSON_2_2   (0x02 << 8)
391 #define SYS_CLCD_ID_SANYO_2_5   (0x07 << 8)
392 #define SYS_CLCD_ID_VGA         (0x1f << 8)
393
394 static struct clcd_panel vga = {
395         .mode           = {
396                 .name           = "VGA",
397                 .refresh        = 60,
398                 .xres           = 640,
399                 .yres           = 480,
400                 .pixclock       = 39721,
401                 .left_margin    = 40,
402                 .right_margin   = 24,
403                 .upper_margin   = 32,
404                 .lower_margin   = 11,
405                 .hsync_len      = 96,
406                 .vsync_len      = 2,
407                 .sync           = 0,
408                 .vmode          = FB_VMODE_NONINTERLACED,
409         },
410         .width          = -1,
411         .height         = -1,
412         .tim2           = TIM2_BCD | TIM2_IPC,
413         .cntl           = CNTL_LCDTFT | CNTL_LCDVCOMP(1),
414         .bpp            = 16,
415 };
416
417 static struct clcd_panel sanyo_3_8_in = {
418         .mode           = {
419                 .name           = "Sanyo QVGA",
420                 .refresh        = 116,
421                 .xres           = 320,
422                 .yres           = 240,
423                 .pixclock       = 100000,
424                 .left_margin    = 6,
425                 .right_margin   = 6,
426                 .upper_margin   = 5,
427                 .lower_margin   = 5,
428                 .hsync_len      = 6,
429                 .vsync_len      = 6,
430                 .sync           = 0,
431                 .vmode          = FB_VMODE_NONINTERLACED,
432         },
433         .width          = -1,
434         .height         = -1,
435         .tim2           = TIM2_BCD,
436         .cntl           = CNTL_LCDTFT | CNTL_LCDVCOMP(1),
437         .bpp            = 16,
438 };
439
440 static struct clcd_panel sanyo_2_5_in = {
441         .mode           = {
442                 .name           = "Sanyo QVGA Portrait",
443                 .refresh        = 116,
444                 .xres           = 240,
445                 .yres           = 320,
446                 .pixclock       = 100000,
447                 .left_margin    = 20,
448                 .right_margin   = 10,
449                 .upper_margin   = 2,
450                 .lower_margin   = 2,
451                 .hsync_len      = 10,
452                 .vsync_len      = 2,
453                 .sync           = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
454                 .vmode          = FB_VMODE_NONINTERLACED,
455         },
456         .width          = -1,
457         .height         = -1,
458         .tim2           = TIM2_IVS | TIM2_IHS | TIM2_IPC,
459         .cntl           = CNTL_LCDTFT | CNTL_LCDVCOMP(1),
460         .bpp            = 16,
461 };
462
463 static struct clcd_panel epson_2_2_in = {
464         .mode           = {
465                 .name           = "Epson QCIF",
466                 .refresh        = 390,
467                 .xres           = 176,
468                 .yres           = 220,
469                 .pixclock       = 62500,
470                 .left_margin    = 3,
471                 .right_margin   = 2,
472                 .upper_margin   = 1,
473                 .lower_margin   = 0,
474                 .hsync_len      = 3,
475                 .vsync_len      = 2,
476                 .sync           = 0,
477                 .vmode          = FB_VMODE_NONINTERLACED,
478         },
479         .width          = -1,
480         .height         = -1,
481         .tim2           = TIM2_BCD | TIM2_IPC,
482         .cntl           = CNTL_LCDTFT | CNTL_LCDVCOMP(1),
483         .bpp            = 16,
484 };
485
486 /*
487  * Detect which LCD panel is connected, and return the appropriate
488  * clcd_panel structure.  Note: we do not have any information on
489  * the required timings for the 8.4in panel, so we presently assume
490  * VGA timings.
491  */
492 static struct clcd_panel *versatile_clcd_panel(void)
493 {
494         void __iomem *sys_clcd = __io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_CLCD_OFFSET;
495         struct clcd_panel *panel = &vga;
496         u32 val;
497
498         val = readl(sys_clcd) & SYS_CLCD_ID_MASK;
499         if (val == SYS_CLCD_ID_SANYO_3_8)
500                 panel = &sanyo_3_8_in;
501         else if (val == SYS_CLCD_ID_SANYO_2_5)
502                 panel = &sanyo_2_5_in;
503         else if (val == SYS_CLCD_ID_EPSON_2_2)
504                 panel = &epson_2_2_in;
505         else if (val == SYS_CLCD_ID_VGA)
506                 panel = &vga;
507         else {
508                 printk(KERN_ERR "CLCD: unknown LCD panel ID 0x%08x, using VGA\n",
509                         val);
510                 panel = &vga;
511         }
512
513         return panel;
514 }
515
516 /*
517  * Disable all display connectors on the interface module.
518  */
519 static void versatile_clcd_disable(struct clcd_fb *fb)
520 {
521         void __iomem *sys_clcd = __io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_CLCD_OFFSET;
522         u32 val;
523
524         val = readl(sys_clcd);
525         val &= ~SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH;
526         writel(val, sys_clcd);
527
528 #ifdef CONFIG_MACH_VERSATILE_AB
529         /*
530          * If the LCD is Sanyo 2x5 in on the IB2 board, turn the back-light off
531          */
532         if (fb->panel == &sanyo_2_5_in) {
533                 void __iomem *versatile_ib2_ctrl = __io_address(VERSATILE_IB2_CTRL);
534                 unsigned long ctrl;
535
536                 ctrl = readl(versatile_ib2_ctrl);
537                 ctrl &= ~0x01;
538                 writel(ctrl, versatile_ib2_ctrl);
539         }
540 #endif
541 }
542
543 /*
544  * Enable the relevant connector on the interface module.
545  */
546 static void versatile_clcd_enable(struct clcd_fb *fb)
547 {
548         void __iomem *sys_clcd = __io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_CLCD_OFFSET;
549         u32 val;
550
551         val = readl(sys_clcd);
552         val &= ~SYS_CLCD_MODE_MASK;
553
554         switch (fb->fb.var.green.length) {
555         case 5:
556                 val |= SYS_CLCD_MODE_5551;
557                 break;
558         case 6:
559                 val |= SYS_CLCD_MODE_565_RLSB;
560                 break;
561         case 8:
562                 val |= SYS_CLCD_MODE_888;
563                 break;
564         }
565
566         /*
567          * Set the MUX
568          */
569         writel(val, sys_clcd);
570
571         /*
572          * And now enable the PSUs
573          */
574         val |= SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH;
575         writel(val, sys_clcd);
576
577 #ifdef CONFIG_MACH_VERSATILE_AB
578         /*
579          * If the LCD is Sanyo 2x5 in on the IB2 board, turn the back-light on
580          */
581         if (fb->panel == &sanyo_2_5_in) {
582                 void __iomem *versatile_ib2_ctrl = __io_address(VERSATILE_IB2_CTRL);
583                 unsigned long ctrl;
584
585                 ctrl = readl(versatile_ib2_ctrl);
586                 ctrl |= 0x01;
587                 writel(ctrl, versatile_ib2_ctrl);
588         }
589 #endif
590 }
591
592 static unsigned long framesize = SZ_1M;
593
594 static int versatile_clcd_setup(struct clcd_fb *fb)
595 {
596         dma_addr_t dma;
597
598         fb->panel               = versatile_clcd_panel();
599
600         fb->fb.screen_base = dma_alloc_writecombine(&fb->dev->dev, framesize,
601                                                     &dma, GFP_KERNEL);
602         if (!fb->fb.screen_base) {
603                 printk(KERN_ERR "CLCD: unable to map framebuffer\n");
604                 return -ENOMEM;
605         }
606
607         fb->fb.fix.smem_start   = dma;
608         fb->fb.fix.smem_len     = framesize;
609
610         return 0;
611 }
612
613 static int versatile_clcd_mmap(struct clcd_fb *fb, struct vm_area_struct *vma)
614 {
615         return dma_mmap_writecombine(&fb->dev->dev, vma,
616                                      fb->fb.screen_base,
617                                      fb->fb.fix.smem_start,
618                                      fb->fb.fix.smem_len);
619 }
620
621 static void versatile_clcd_remove(struct clcd_fb *fb)
622 {
623         dma_free_writecombine(&fb->dev->dev, fb->fb.fix.smem_len,
624                               fb->fb.screen_base, fb->fb.fix.smem_start);
625 }
626
627 static struct clcd_board clcd_plat_data = {
628         .name           = "Versatile",
629         .check          = clcdfb_check,
630         .decode         = clcdfb_decode,
631         .disable        = versatile_clcd_disable,
632         .enable         = versatile_clcd_enable,
633         .setup          = versatile_clcd_setup,
634         .mmap           = versatile_clcd_mmap,
635         .remove         = versatile_clcd_remove,
636 };
637
638 #define AACI_IRQ        { IRQ_AACI, NO_IRQ }
639 #define AACI_DMA        { 0x80, 0x81 }
640 #define MMCI0_IRQ       { IRQ_MMCI0A,IRQ_SIC_MMCI0B }
641 #define MMCI0_DMA       { 0x84, 0 }
642 #define KMI0_IRQ        { IRQ_SIC_KMI0, NO_IRQ }
643 #define KMI0_DMA        { 0, 0 }
644 #define KMI1_IRQ        { IRQ_SIC_KMI1, NO_IRQ }
645 #define KMI1_DMA        { 0, 0 }
646
647 /*
648  * These devices are connected directly to the multi-layer AHB switch
649  */
650 #define SMC_IRQ         { NO_IRQ, NO_IRQ }
651 #define SMC_DMA         { 0, 0 }
652 #define MPMC_IRQ        { NO_IRQ, NO_IRQ }
653 #define MPMC_DMA        { 0, 0 }
654 #define CLCD_IRQ        { IRQ_CLCDINT, NO_IRQ }
655 #define CLCD_DMA        { 0, 0 }
656 #define DMAC_IRQ        { IRQ_DMAINT, NO_IRQ }
657 #define DMAC_DMA        { 0, 0 }
658
659 /*
660  * These devices are connected via the core APB bridge
661  */
662 #define SCTL_IRQ        { NO_IRQ, NO_IRQ }
663 #define SCTL_DMA        { 0, 0 }
664 #define WATCHDOG_IRQ    { IRQ_WDOGINT, NO_IRQ }
665 #define WATCHDOG_DMA    { 0, 0 }
666 #define GPIO0_IRQ       { IRQ_GPIOINT0, NO_IRQ }
667 #define GPIO0_DMA       { 0, 0 }
668 #define GPIO1_IRQ       { IRQ_GPIOINT1, NO_IRQ }
669 #define GPIO1_DMA       { 0, 0 }
670 #define RTC_IRQ         { IRQ_RTCINT, NO_IRQ }
671 #define RTC_DMA         { 0, 0 }
672
673 /*
674  * These devices are connected via the DMA APB bridge
675  */
676 #define SCI_IRQ         { IRQ_SCIINT, NO_IRQ }
677 #define SCI_DMA         { 7, 6 }
678 #define UART0_IRQ       { IRQ_UARTINT0, NO_IRQ }
679 #define UART0_DMA       { 15, 14 }
680 #define UART1_IRQ       { IRQ_UARTINT1, NO_IRQ }
681 #define UART1_DMA       { 13, 12 }
682 #define UART2_IRQ       { IRQ_UARTINT2, NO_IRQ }
683 #define UART2_DMA       { 11, 10 }
684 #define SSP_IRQ         { IRQ_SSPINT, NO_IRQ }
685 #define SSP_DMA         { 9, 8 }
686
687 /* FPGA Primecells */
688 AMBA_DEVICE(aaci,  "fpga:04", AACI,     NULL);
689 AMBA_DEVICE(mmc0,  "fpga:05", MMCI0,    &mmc0_plat_data);
690 AMBA_DEVICE(kmi0,  "fpga:06", KMI0,     NULL);
691 AMBA_DEVICE(kmi1,  "fpga:07", KMI1,     NULL);
692
693 /* DevChip Primecells */
694 AMBA_DEVICE(smc,   "dev:00",  SMC,      NULL);
695 AMBA_DEVICE(mpmc,  "dev:10",  MPMC,     NULL);
696 AMBA_DEVICE(clcd,  "dev:20",  CLCD,     &clcd_plat_data);
697 AMBA_DEVICE(dmac,  "dev:30",  DMAC,     NULL);
698 AMBA_DEVICE(sctl,  "dev:e0",  SCTL,     NULL);
699 AMBA_DEVICE(wdog,  "dev:e1",  WATCHDOG, NULL);
700 AMBA_DEVICE(gpio0, "dev:e4",  GPIO0,    NULL);
701 AMBA_DEVICE(gpio1, "dev:e5",  GPIO1,    NULL);
702 AMBA_DEVICE(rtc,   "dev:e8",  RTC,      NULL);
703 AMBA_DEVICE(sci0,  "dev:f0",  SCI,      NULL);
704 AMBA_DEVICE(uart0, "dev:f1",  UART0,    NULL);
705 AMBA_DEVICE(uart1, "dev:f2",  UART1,    NULL);
706 AMBA_DEVICE(uart2, "dev:f3",  UART2,    NULL);
707 AMBA_DEVICE(ssp0,  "dev:f4",  SSP,      NULL);
708
709 static struct amba_device *amba_devs[] __initdata = {
710         &dmac_device,
711         &uart0_device,
712         &uart1_device,
713         &uart2_device,
714         &smc_device,
715         &mpmc_device,
716         &clcd_device,
717         &sctl_device,
718         &wdog_device,
719         &gpio0_device,
720         &gpio1_device,
721         &rtc_device,
722         &sci0_device,
723         &ssp0_device,
724         &aaci_device,
725         &mmc0_device,
726         &kmi0_device,
727         &kmi1_device,
728 };
729
730 #ifdef CONFIG_LEDS
731 #define VA_LEDS_BASE (__io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_LED_OFFSET)
732
733 static void versatile_leds_event(led_event_t ledevt)
734 {
735         unsigned long flags;
736         u32 val;
737
738         local_irq_save(flags);
739         val = readl(VA_LEDS_BASE);
740
741         switch (ledevt) {
742         case led_idle_start:
743                 val = val & ~VERSATILE_SYS_LED0;
744                 break;
745
746         case led_idle_end:
747                 val = val | VERSATILE_SYS_LED0;
748                 break;
749
750         case led_timer:
751                 val = val ^ VERSATILE_SYS_LED1;
752                 break;
753
754         case led_halted:
755                 val = 0;
756                 break;
757
758         default:
759                 break;
760         }
761
762         writel(val, VA_LEDS_BASE);
763         local_irq_restore(flags);
764 }
765 #endif  /* CONFIG_LEDS */
766
767 void __init versatile_init(void)
768 {
769         int i;
770
771         clk_register(&versatile_clcd_clk);
772
773         platform_device_register(&versatile_flash_device);
774         platform_device_register(&smc91x_device);
775
776         for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
777                 struct amba_device *d = amba_devs[i];
778                 amba_device_register(d, &iomem_resource);
779         }
780
781 #ifdef CONFIG_LEDS
782         leds_event = versatile_leds_event;
783 #endif
784 }
785
786 /*
787  * Where is the timer (VA)?
788  */
789 #define TIMER0_VA_BASE           __io_address(VERSATILE_TIMER0_1_BASE)
790 #define TIMER1_VA_BASE          (__io_address(VERSATILE_TIMER0_1_BASE) + 0x20)
791 #define TIMER2_VA_BASE           __io_address(VERSATILE_TIMER2_3_BASE)
792 #define TIMER3_VA_BASE          (__io_address(VERSATILE_TIMER2_3_BASE) + 0x20)
793 #define VA_IC_BASE               __io_address(VERSATILE_VIC_BASE) 
794
795 /*
796  * How long is the timer interval?
797  */
798 #define TIMER_INTERVAL  (TICKS_PER_uSEC * mSEC_10)
799 #if TIMER_INTERVAL >= 0x100000
800 #define TIMER_RELOAD    (TIMER_INTERVAL >> 8)
801 #define TIMER_DIVISOR   (TIMER_CTRL_DIV256)
802 #define TICKS2USECS(x)  (256 * (x) / TICKS_PER_uSEC)
803 #elif TIMER_INTERVAL >= 0x10000
804 #define TIMER_RELOAD    (TIMER_INTERVAL >> 4)           /* Divide by 16 */
805 #define TIMER_DIVISOR   (TIMER_CTRL_DIV16)
806 #define TICKS2USECS(x)  (16 * (x) / TICKS_PER_uSEC)
807 #else
808 #define TIMER_RELOAD    (TIMER_INTERVAL)
809 #define TIMER_DIVISOR   (TIMER_CTRL_DIV1)
810 #define TICKS2USECS(x)  ((x) / TICKS_PER_uSEC)
811 #endif
812
813 /*
814  * Returns number of ms since last clock interrupt.  Note that interrupts
815  * will have been disabled by do_gettimeoffset()
816  */
817 static unsigned long versatile_gettimeoffset(void)
818 {
819         unsigned long ticks1, ticks2, status;
820
821         /*
822          * Get the current number of ticks.  Note that there is a race
823          * condition between us reading the timer and checking for
824          * an interrupt.  We get around this by ensuring that the
825          * counter has not reloaded between our two reads.
826          */
827         ticks2 = readl(TIMER0_VA_BASE + TIMER_VALUE) & 0xffff;
828         do {
829                 ticks1 = ticks2;
830                 status = __raw_readl(VA_IC_BASE + VIC_RAW_STATUS);
831                 ticks2 = readl(TIMER0_VA_BASE + TIMER_VALUE) & 0xffff;
832         } while (ticks2 > ticks1);
833
834         /*
835          * Number of ticks since last interrupt.
836          */
837         ticks1 = TIMER_RELOAD - ticks2;
838
839         /*
840          * Interrupt pending?  If so, we've reloaded once already.
841          *
842          * FIXME: Need to check this is effectively timer 0 that expires
843          */
844         if (status & IRQMASK_TIMERINT0_1)
845                 ticks1 += TIMER_RELOAD;
846
847         /*
848          * Convert the ticks to usecs
849          */
850         return TICKS2USECS(ticks1);
851 }
852
853 /*
854  * IRQ handler for the timer
855  */
856 static irqreturn_t versatile_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
857 {
858         write_seqlock(&xtime_lock);
859
860         // ...clear the interrupt
861         writel(1, TIMER0_VA_BASE + TIMER_INTCLR);
862
863         timer_tick(regs);
864
865         write_sequnlock(&xtime_lock);
866
867         return IRQ_HANDLED;
868 }
869
870 static struct irqaction versatile_timer_irq = {
871         .name           = "Versatile Timer Tick",
872         .flags          = IRQF_DISABLED | IRQF_TIMER,
873         .handler        = versatile_timer_interrupt,
874 };
875
876 /*
877  * Set up timer interrupt, and return the current time in seconds.
878  */
879 static void __init versatile_timer_init(void)
880 {
881         u32 val;
882
883         /* 
884          * set clock frequency: 
885          *      VERSATILE_REFCLK is 32KHz
886          *      VERSATILE_TIMCLK is 1MHz
887          */
888         val = readl(__io_address(VERSATILE_SCTL_BASE));
889         writel((VERSATILE_TIMCLK << VERSATILE_TIMER1_EnSel) |
890                (VERSATILE_TIMCLK << VERSATILE_TIMER2_EnSel) | 
891                (VERSATILE_TIMCLK << VERSATILE_TIMER3_EnSel) |
892                (VERSATILE_TIMCLK << VERSATILE_TIMER4_EnSel) | val,
893                __io_address(VERSATILE_SCTL_BASE));
894
895         /*
896          * Initialise to a known state (all timers off)
897          */
898         writel(0, TIMER0_VA_BASE + TIMER_CTRL);
899         writel(0, TIMER1_VA_BASE + TIMER_CTRL);
900         writel(0, TIMER2_VA_BASE + TIMER_CTRL);
901         writel(0, TIMER3_VA_BASE + TIMER_CTRL);
902
903         writel(TIMER_RELOAD, TIMER0_VA_BASE + TIMER_LOAD);
904         writel(TIMER_RELOAD, TIMER0_VA_BASE + TIMER_VALUE);
905         writel(TIMER_DIVISOR | TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC |
906                TIMER_CTRL_IE, TIMER0_VA_BASE + TIMER_CTRL);
907
908         /* 
909          * Make irqs happen for the system timer
910          */
911         setup_irq(IRQ_TIMERINT0_1, &versatile_timer_irq);
912 }
913
914 struct sys_timer versatile_timer = {
915         .init           = versatile_timer_init,
916         .offset         = versatile_gettimeoffset,
917 };