Merge branch 'depends/rmk/devel-stable' into next/cleanup
[linux-3.10.git] / arch / arm / mach-u300 / core.c
1 /*
2  *
3  * arch/arm/mach-u300/core.c
4  *
5  *
6  * Copyright (C) 2007-2010 ST-Ericsson SA
7  * License terms: GNU General Public License (GPL) version 2
8  * Core platform support, IRQ handling and device definitions.
9  * Author: Linus Walleij <linus.walleij@stericsson.com>
10  */
11 #include <linux/kernel.h>
12 #include <linux/init.h>
13 #include <linux/spinlock.h>
14 #include <linux/interrupt.h>
15 #include <linux/bitops.h>
16 #include <linux/device.h>
17 #include <linux/mm.h>
18 #include <linux/termios.h>
19 #include <linux/dmaengine.h>
20 #include <linux/amba/bus.h>
21 #include <linux/amba/serial.h>
22 #include <linux/platform_device.h>
23 #include <linux/gpio.h>
24 #include <linux/clk.h>
25 #include <linux/err.h>
26 #include <linux/mtd/nand.h>
27 #include <linux/mtd/fsmc.h>
28 #include <linux/dma-mapping.h>
29
30 #include <asm/types.h>
31 #include <asm/setup.h>
32 #include <asm/memory.h>
33 #include <asm/hardware/vic.h>
34 #include <asm/mach/map.h>
35 #include <asm/mach/irq.h>
36
37 #include <mach/coh901318.h>
38 #include <mach/hardware.h>
39 #include <mach/syscon.h>
40 #include <mach/dma_channels.h>
41
42 #include "clock.h"
43 #include "mmc.h"
44 #include "spi.h"
45 #include "i2c.h"
46
47 /*
48  * Static I/O mappings that are needed for booting the U300 platforms. The
49  * only things we need are the areas where we find the timer, syscon and
50  * intcon, since the remaining device drivers will map their own memory
51  * physical to virtual as the need arise.
52  */
53 static struct map_desc u300_io_desc[] __initdata = {
54         {
55                 .virtual        = U300_SLOW_PER_VIRT_BASE,
56                 .pfn            = __phys_to_pfn(U300_SLOW_PER_PHYS_BASE),
57                 .length         = SZ_64K,
58                 .type           = MT_DEVICE,
59         },
60         {
61                 .virtual        = U300_AHB_PER_VIRT_BASE,
62                 .pfn            = __phys_to_pfn(U300_AHB_PER_PHYS_BASE),
63                 .length         = SZ_32K,
64                 .type           = MT_DEVICE,
65         },
66         {
67                 .virtual        = U300_FAST_PER_VIRT_BASE,
68                 .pfn            = __phys_to_pfn(U300_FAST_PER_PHYS_BASE),
69                 .length         = SZ_32K,
70                 .type           = MT_DEVICE,
71         },
72 };
73
74 void __init u300_map_io(void)
75 {
76         iotable_init(u300_io_desc, ARRAY_SIZE(u300_io_desc));
77         /* We enable a real big DMA buffer if need be. */
78         init_consistent_dma_size(SZ_4M);
79 }
80
81 /*
82  * Declaration of devices found on the U300 board and
83  * their respective memory locations.
84  */
85
86 static struct amba_pl011_data uart0_plat_data = {
87 #ifdef CONFIG_COH901318
88         .dma_filter = coh901318_filter_id,
89         .dma_rx_param = (void *) U300_DMA_UART0_RX,
90         .dma_tx_param = (void *) U300_DMA_UART0_TX,
91 #endif
92 };
93
94 static struct amba_device uart0_device = {
95         .dev = {
96                 .coherent_dma_mask = ~0,
97                 .init_name = "uart0", /* Slow device at 0x3000 offset */
98                 .platform_data = &uart0_plat_data,
99         },
100         .res = {
101                 .start = U300_UART0_BASE,
102                 .end   = U300_UART0_BASE + SZ_4K - 1,
103                 .flags = IORESOURCE_MEM,
104         },
105         .irq = { IRQ_U300_UART0, NO_IRQ },
106 };
107
108 /* The U335 have an additional UART1 on the APP CPU */
109 #ifdef CONFIG_MACH_U300_BS335
110 static struct amba_pl011_data uart1_plat_data = {
111 #ifdef CONFIG_COH901318
112         .dma_filter = coh901318_filter_id,
113         .dma_rx_param = (void *) U300_DMA_UART1_RX,
114         .dma_tx_param = (void *) U300_DMA_UART1_TX,
115 #endif
116 };
117
118 static struct amba_device uart1_device = {
119         .dev = {
120                 .coherent_dma_mask = ~0,
121                 .init_name = "uart1", /* Fast device at 0x7000 offset */
122                 .platform_data = &uart1_plat_data,
123         },
124         .res = {
125                 .start = U300_UART1_BASE,
126                 .end   = U300_UART1_BASE + SZ_4K - 1,
127                 .flags = IORESOURCE_MEM,
128         },
129         .irq = { IRQ_U300_UART1, NO_IRQ },
130 };
131 #endif
132
133 static struct amba_device pl172_device = {
134         .dev = {
135                 .init_name = "pl172", /* AHB device at 0x4000 offset */
136                 .platform_data = NULL,
137         },
138         .res = {
139                 .start = U300_EMIF_CFG_BASE,
140                 .end   = U300_EMIF_CFG_BASE + SZ_4K - 1,
141                 .flags = IORESOURCE_MEM,
142         },
143 };
144
145
146 /*
147  * Everything within this next ifdef deals with external devices connected to
148  * the APP SPI bus.
149  */
150 static struct amba_device pl022_device = {
151         .dev = {
152                 .coherent_dma_mask = ~0,
153                 .init_name = "pl022", /* Fast device at 0x6000 offset */
154         },
155         .res = {
156                 .start = U300_SPI_BASE,
157                 .end   = U300_SPI_BASE + SZ_4K - 1,
158                 .flags = IORESOURCE_MEM,
159         },
160         .irq = {IRQ_U300_SPI, NO_IRQ },
161         /*
162          * This device has a DMA channel but the Linux driver does not use
163          * it currently.
164          */
165 };
166
167 static struct amba_device mmcsd_device = {
168         .dev = {
169                 .init_name = "mmci", /* Fast device at 0x1000 offset */
170                 .platform_data = NULL, /* Added later */
171         },
172         .res = {
173                 .start = U300_MMCSD_BASE,
174                 .end   = U300_MMCSD_BASE + SZ_4K - 1,
175                 .flags = IORESOURCE_MEM,
176         },
177         .irq = {IRQ_U300_MMCSD_MCIINTR0, IRQ_U300_MMCSD_MCIINTR1 },
178         /*
179          * This device has a DMA channel but the Linux driver does not use
180          * it currently.
181          */
182 };
183
184 /*
185  * The order of device declaration may be important, since some devices
186  * have dependencies on other devices being initialized first.
187  */
188 static struct amba_device *amba_devs[] __initdata = {
189         &uart0_device,
190 #ifdef CONFIG_MACH_U300_BS335
191         &uart1_device,
192 #endif
193         &pl022_device,
194         &pl172_device,
195         &mmcsd_device,
196 };
197
198 /* Here follows a list of all hw resources that the platform devices
199  * allocate. Note, clock dependencies are not included
200  */
201
202 static struct resource gpio_resources[] = {
203         {
204                 .start = U300_GPIO_BASE,
205                 .end   = (U300_GPIO_BASE + SZ_4K - 1),
206                 .flags = IORESOURCE_MEM,
207         },
208         {
209                 .name  = "gpio0",
210                 .start = IRQ_U300_GPIO_PORT0,
211                 .end   = IRQ_U300_GPIO_PORT0,
212                 .flags = IORESOURCE_IRQ,
213         },
214         {
215                 .name  = "gpio1",
216                 .start = IRQ_U300_GPIO_PORT1,
217                 .end   = IRQ_U300_GPIO_PORT1,
218                 .flags = IORESOURCE_IRQ,
219         },
220         {
221                 .name  = "gpio2",
222                 .start = IRQ_U300_GPIO_PORT2,
223                 .end   = IRQ_U300_GPIO_PORT2,
224                 .flags = IORESOURCE_IRQ,
225         },
226 #ifdef U300_COH901571_3
227         {
228                 .name  = "gpio3",
229                 .start = IRQ_U300_GPIO_PORT3,
230                 .end   = IRQ_U300_GPIO_PORT3,
231                 .flags = IORESOURCE_IRQ,
232         },
233         {
234                 .name  = "gpio4",
235                 .start = IRQ_U300_GPIO_PORT4,
236                 .end   = IRQ_U300_GPIO_PORT4,
237                 .flags = IORESOURCE_IRQ,
238         },
239 #ifdef CONFIG_MACH_U300_BS335
240         {
241                 .name  = "gpio5",
242                 .start = IRQ_U300_GPIO_PORT5,
243                 .end   = IRQ_U300_GPIO_PORT5,
244                 .flags = IORESOURCE_IRQ,
245         },
246         {
247                 .name  = "gpio6",
248                 .start = IRQ_U300_GPIO_PORT6,
249                 .end   = IRQ_U300_GPIO_PORT6,
250                 .flags = IORESOURCE_IRQ,
251         },
252 #endif /* CONFIG_MACH_U300_BS335 */
253 #endif /* U300_COH901571_3 */
254 };
255
256 static struct resource keypad_resources[] = {
257         {
258                 .start = U300_KEYPAD_BASE,
259                 .end   = U300_KEYPAD_BASE + SZ_4K - 1,
260                 .flags = IORESOURCE_MEM,
261         },
262         {
263                 .name  = "coh901461-press",
264                 .start = IRQ_U300_KEYPAD_KEYBF,
265                 .end   = IRQ_U300_KEYPAD_KEYBF,
266                 .flags = IORESOURCE_IRQ,
267         },
268         {
269                 .name  = "coh901461-release",
270                 .start = IRQ_U300_KEYPAD_KEYBR,
271                 .end   = IRQ_U300_KEYPAD_KEYBR,
272                 .flags = IORESOURCE_IRQ,
273         },
274 };
275
276 static struct resource rtc_resources[] = {
277         {
278                 .start = U300_RTC_BASE,
279                 .end   = U300_RTC_BASE + SZ_4K - 1,
280                 .flags = IORESOURCE_MEM,
281         },
282         {
283                 .start = IRQ_U300_RTC,
284                 .end   = IRQ_U300_RTC,
285                 .flags = IORESOURCE_IRQ,
286         },
287 };
288
289 /*
290  * Fsmc does have IRQs: #43 and #44 (NFIF and NFIF2)
291  * but these are not yet used by the driver.
292  */
293 static struct resource fsmc_resources[] = {
294         {
295                 .name  = "nand_data",
296                 .start = U300_NAND_CS0_PHYS_BASE,
297                 .end   = U300_NAND_CS0_PHYS_BASE + SZ_16K - 1,
298                 .flags = IORESOURCE_MEM,
299         },
300         {
301                 .name  = "fsmc_regs",
302                 .start = U300_NAND_IF_PHYS_BASE,
303                 .end   = U300_NAND_IF_PHYS_BASE + SZ_4K - 1,
304                 .flags = IORESOURCE_MEM,
305         },
306 };
307
308 static struct resource i2c0_resources[] = {
309         {
310                 .start = U300_I2C0_BASE,
311                 .end   = U300_I2C0_BASE + SZ_4K - 1,
312                 .flags = IORESOURCE_MEM,
313         },
314         {
315                 .start = IRQ_U300_I2C0,
316                 .end   = IRQ_U300_I2C0,
317                 .flags = IORESOURCE_IRQ,
318         },
319 };
320
321 static struct resource i2c1_resources[] = {
322         {
323                 .start = U300_I2C1_BASE,
324                 .end   = U300_I2C1_BASE + SZ_4K - 1,
325                 .flags = IORESOURCE_MEM,
326         },
327         {
328                 .start = IRQ_U300_I2C1,
329                 .end   = IRQ_U300_I2C1,
330                 .flags = IORESOURCE_IRQ,
331         },
332
333 };
334
335 static struct resource wdog_resources[] = {
336         {
337                 .start = U300_WDOG_BASE,
338                 .end   = U300_WDOG_BASE + SZ_4K - 1,
339                 .flags = IORESOURCE_MEM,
340         },
341         {
342                 .start = IRQ_U300_WDOG,
343                 .end   = IRQ_U300_WDOG,
344                 .flags = IORESOURCE_IRQ,
345         }
346 };
347
348 static struct resource dma_resource[] = {
349         {
350                 .start = U300_DMAC_BASE,
351                 .end = U300_DMAC_BASE + PAGE_SIZE - 1,
352                 .flags =  IORESOURCE_MEM,
353         },
354         {
355                 .start = IRQ_U300_DMA,
356                 .end = IRQ_U300_DMA,
357                 .flags =  IORESOURCE_IRQ,
358         }
359 };
360
361 #ifdef CONFIG_MACH_U300_BS335
362 /* points out all dma slave channels.
363  * Syntax is [A1, B1, A2, B2, .... ,-1,-1]
364  * Select all channels from A to B, end of list is marked with -1,-1
365  */
366 static int dma_slave_channels[] = {
367         U300_DMA_MSL_TX_0, U300_DMA_SPI_RX,
368         U300_DMA_UART1_TX, U300_DMA_UART1_RX, -1, -1};
369
370 /* points out all dma memcpy channels. */
371 static int dma_memcpy_channels[] = {
372         U300_DMA_GENERAL_PURPOSE_0, U300_DMA_GENERAL_PURPOSE_8, -1, -1};
373
374 #else /* CONFIG_MACH_U300_BS335 */
375
376 static int dma_slave_channels[] = {U300_DMA_MSL_TX_0, U300_DMA_SPI_RX, -1, -1};
377 static int dma_memcpy_channels[] = {
378         U300_DMA_GENERAL_PURPOSE_0, U300_DMA_GENERAL_PURPOSE_10, -1, -1};
379
380 #endif
381
382 /** register dma for memory access
383  *
384  * active  1 means dma intends to access memory
385  *         0 means dma wont access memory
386  */
387 static void coh901318_access_memory_state(struct device *dev, bool active)
388 {
389 }
390
391 #define flags_memcpy_config (COH901318_CX_CFG_CH_DISABLE | \
392                         COH901318_CX_CFG_RM_MEMORY_TO_MEMORY | \
393                         COH901318_CX_CFG_LCR_DISABLE | \
394                         COH901318_CX_CFG_TC_IRQ_ENABLE | \
395                         COH901318_CX_CFG_BE_IRQ_ENABLE)
396 #define flags_memcpy_lli_chained (COH901318_CX_CTRL_TC_ENABLE | \
397                         COH901318_CX_CTRL_BURST_COUNT_32_BYTES | \
398                         COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | \
399                         COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | \
400                         COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | \
401                         COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | \
402                         COH901318_CX_CTRL_MASTER_MODE_M1RW | \
403                         COH901318_CX_CTRL_TCP_DISABLE | \
404                         COH901318_CX_CTRL_TC_IRQ_DISABLE | \
405                         COH901318_CX_CTRL_HSP_DISABLE | \
406                         COH901318_CX_CTRL_HSS_DISABLE | \
407                         COH901318_CX_CTRL_DDMA_LEGACY | \
408                         COH901318_CX_CTRL_PRDD_SOURCE)
409 #define flags_memcpy_lli (COH901318_CX_CTRL_TC_ENABLE | \
410                         COH901318_CX_CTRL_BURST_COUNT_32_BYTES | \
411                         COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | \
412                         COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | \
413                         COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | \
414                         COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | \
415                         COH901318_CX_CTRL_MASTER_MODE_M1RW | \
416                         COH901318_CX_CTRL_TCP_DISABLE | \
417                         COH901318_CX_CTRL_TC_IRQ_DISABLE | \
418                         COH901318_CX_CTRL_HSP_DISABLE | \
419                         COH901318_CX_CTRL_HSS_DISABLE | \
420                         COH901318_CX_CTRL_DDMA_LEGACY | \
421                         COH901318_CX_CTRL_PRDD_SOURCE)
422 #define flags_memcpy_lli_last (COH901318_CX_CTRL_TC_ENABLE | \
423                         COH901318_CX_CTRL_BURST_COUNT_32_BYTES | \
424                         COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | \
425                         COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | \
426                         COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | \
427                         COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | \
428                         COH901318_CX_CTRL_MASTER_MODE_M1RW | \
429                         COH901318_CX_CTRL_TCP_DISABLE | \
430                         COH901318_CX_CTRL_TC_IRQ_ENABLE | \
431                         COH901318_CX_CTRL_HSP_DISABLE | \
432                         COH901318_CX_CTRL_HSS_DISABLE | \
433                         COH901318_CX_CTRL_DDMA_LEGACY | \
434                         COH901318_CX_CTRL_PRDD_SOURCE)
435
436 const struct coh_dma_channel chan_config[U300_DMA_CHANNELS] = {
437         {
438                 .number = U300_DMA_MSL_TX_0,
439                 .name = "MSL TX 0",
440                 .priority_high = 0,
441                 .dev_addr = U300_MSL_BASE + 0 * 0x40 + 0x20,
442         },
443         {
444                 .number = U300_DMA_MSL_TX_1,
445                 .name = "MSL TX 1",
446                 .priority_high = 0,
447                 .dev_addr = U300_MSL_BASE + 1 * 0x40 + 0x20,
448                 .param.config = COH901318_CX_CFG_CH_DISABLE |
449                                 COH901318_CX_CFG_LCR_DISABLE |
450                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
451                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
452                 .param.ctrl_lli_chained = 0 |
453                                 COH901318_CX_CTRL_TC_ENABLE |
454                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
455                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
456                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
457                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
458                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
459                                 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
460                                 COH901318_CX_CTRL_TCP_DISABLE |
461                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
462                                 COH901318_CX_CTRL_HSP_ENABLE |
463                                 COH901318_CX_CTRL_HSS_DISABLE |
464                                 COH901318_CX_CTRL_DDMA_LEGACY |
465                                 COH901318_CX_CTRL_PRDD_SOURCE,
466                 .param.ctrl_lli = 0 |
467                                 COH901318_CX_CTRL_TC_ENABLE |
468                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
469                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
470                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
471                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
472                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
473                                 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
474                                 COH901318_CX_CTRL_TCP_ENABLE |
475                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
476                                 COH901318_CX_CTRL_HSP_ENABLE |
477                                 COH901318_CX_CTRL_HSS_DISABLE |
478                                 COH901318_CX_CTRL_DDMA_LEGACY |
479                                 COH901318_CX_CTRL_PRDD_SOURCE,
480                 .param.ctrl_lli_last = 0 |
481                                 COH901318_CX_CTRL_TC_ENABLE |
482                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
483                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
484                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
485                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
486                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
487                                 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
488                                 COH901318_CX_CTRL_TCP_ENABLE |
489                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
490                                 COH901318_CX_CTRL_HSP_ENABLE |
491                                 COH901318_CX_CTRL_HSS_DISABLE |
492                                 COH901318_CX_CTRL_DDMA_LEGACY |
493                                 COH901318_CX_CTRL_PRDD_SOURCE,
494         },
495         {
496                 .number = U300_DMA_MSL_TX_2,
497                 .name = "MSL TX 2",
498                 .priority_high = 0,
499                 .dev_addr = U300_MSL_BASE + 2 * 0x40 + 0x20,
500                 .param.config = COH901318_CX_CFG_CH_DISABLE |
501                                 COH901318_CX_CFG_LCR_DISABLE |
502                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
503                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
504                 .param.ctrl_lli_chained = 0 |
505                                 COH901318_CX_CTRL_TC_ENABLE |
506                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
507                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
508                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
509                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
510                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
511                                 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
512                                 COH901318_CX_CTRL_TCP_DISABLE |
513                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
514                                 COH901318_CX_CTRL_HSP_ENABLE |
515                                 COH901318_CX_CTRL_HSS_DISABLE |
516                                 COH901318_CX_CTRL_DDMA_LEGACY |
517                                 COH901318_CX_CTRL_PRDD_SOURCE,
518                 .param.ctrl_lli = 0 |
519                                 COH901318_CX_CTRL_TC_ENABLE |
520                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
521                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
522                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
523                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
524                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
525                                 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
526                                 COH901318_CX_CTRL_TCP_ENABLE |
527                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
528                                 COH901318_CX_CTRL_HSP_ENABLE |
529                                 COH901318_CX_CTRL_HSS_DISABLE |
530                                 COH901318_CX_CTRL_DDMA_LEGACY |
531                                 COH901318_CX_CTRL_PRDD_SOURCE,
532                 .param.ctrl_lli_last = 0 |
533                                 COH901318_CX_CTRL_TC_ENABLE |
534                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
535                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
536                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
537                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
538                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
539                                 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
540                                 COH901318_CX_CTRL_TCP_ENABLE |
541                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
542                                 COH901318_CX_CTRL_HSP_ENABLE |
543                                 COH901318_CX_CTRL_HSS_DISABLE |
544                                 COH901318_CX_CTRL_DDMA_LEGACY |
545                                 COH901318_CX_CTRL_PRDD_SOURCE,
546                 .desc_nbr_max = 10,
547         },
548         {
549                 .number = U300_DMA_MSL_TX_3,
550                 .name = "MSL TX 3",
551                 .priority_high = 0,
552                 .dev_addr = U300_MSL_BASE + 3 * 0x40 + 0x20,
553                 .param.config = COH901318_CX_CFG_CH_DISABLE |
554                                 COH901318_CX_CFG_LCR_DISABLE |
555                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
556                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
557                 .param.ctrl_lli_chained = 0 |
558                                 COH901318_CX_CTRL_TC_ENABLE |
559                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
560                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
561                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
562                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
563                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
564                                 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
565                                 COH901318_CX_CTRL_TCP_DISABLE |
566                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
567                                 COH901318_CX_CTRL_HSP_ENABLE |
568                                 COH901318_CX_CTRL_HSS_DISABLE |
569                                 COH901318_CX_CTRL_DDMA_LEGACY |
570                                 COH901318_CX_CTRL_PRDD_SOURCE,
571                 .param.ctrl_lli = 0 |
572                                 COH901318_CX_CTRL_TC_ENABLE |
573                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
574                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
575                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
576                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
577                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
578                                 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
579                                 COH901318_CX_CTRL_TCP_ENABLE |
580                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
581                                 COH901318_CX_CTRL_HSP_ENABLE |
582                                 COH901318_CX_CTRL_HSS_DISABLE |
583                                 COH901318_CX_CTRL_DDMA_LEGACY |
584                                 COH901318_CX_CTRL_PRDD_SOURCE,
585                 .param.ctrl_lli_last = 0 |
586                                 COH901318_CX_CTRL_TC_ENABLE |
587                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
588                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
589                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
590                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
591                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
592                                 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
593                                 COH901318_CX_CTRL_TCP_ENABLE |
594                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
595                                 COH901318_CX_CTRL_HSP_ENABLE |
596                                 COH901318_CX_CTRL_HSS_DISABLE |
597                                 COH901318_CX_CTRL_DDMA_LEGACY |
598                                 COH901318_CX_CTRL_PRDD_SOURCE,
599         },
600         {
601                 .number = U300_DMA_MSL_TX_4,
602                 .name = "MSL TX 4",
603                 .priority_high = 0,
604                 .dev_addr = U300_MSL_BASE + 4 * 0x40 + 0x20,
605                 .param.config = COH901318_CX_CFG_CH_DISABLE |
606                                 COH901318_CX_CFG_LCR_DISABLE |
607                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
608                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
609                 .param.ctrl_lli_chained = 0 |
610                                 COH901318_CX_CTRL_TC_ENABLE |
611                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
612                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
613                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
614                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
615                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
616                                 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
617                                 COH901318_CX_CTRL_TCP_DISABLE |
618                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
619                                 COH901318_CX_CTRL_HSP_ENABLE |
620                                 COH901318_CX_CTRL_HSS_DISABLE |
621                                 COH901318_CX_CTRL_DDMA_LEGACY |
622                                 COH901318_CX_CTRL_PRDD_SOURCE,
623                 .param.ctrl_lli = 0 |
624                                 COH901318_CX_CTRL_TC_ENABLE |
625                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
626                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
627                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
628                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
629                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
630                                 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
631                                 COH901318_CX_CTRL_TCP_ENABLE |
632                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
633                                 COH901318_CX_CTRL_HSP_ENABLE |
634                                 COH901318_CX_CTRL_HSS_DISABLE |
635                                 COH901318_CX_CTRL_DDMA_LEGACY |
636                                 COH901318_CX_CTRL_PRDD_SOURCE,
637                 .param.ctrl_lli_last = 0 |
638                                 COH901318_CX_CTRL_TC_ENABLE |
639                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
640                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
641                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
642                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
643                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
644                                 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
645                                 COH901318_CX_CTRL_TCP_ENABLE |
646                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
647                                 COH901318_CX_CTRL_HSP_ENABLE |
648                                 COH901318_CX_CTRL_HSS_DISABLE |
649                                 COH901318_CX_CTRL_DDMA_LEGACY |
650                                 COH901318_CX_CTRL_PRDD_SOURCE,
651         },
652         {
653                 .number = U300_DMA_MSL_TX_5,
654                 .name = "MSL TX 5",
655                 .priority_high = 0,
656                 .dev_addr = U300_MSL_BASE + 5 * 0x40 + 0x20,
657         },
658         {
659                 .number = U300_DMA_MSL_TX_6,
660                 .name = "MSL TX 6",
661                 .priority_high = 0,
662                 .dev_addr = U300_MSL_BASE + 6 * 0x40 + 0x20,
663         },
664         {
665                 .number = U300_DMA_MSL_RX_0,
666                 .name = "MSL RX 0",
667                 .priority_high = 0,
668                 .dev_addr = U300_MSL_BASE + 0 * 0x40 + 0x220,
669         },
670         {
671                 .number = U300_DMA_MSL_RX_1,
672                 .name = "MSL RX 1",
673                 .priority_high = 0,
674                 .dev_addr = U300_MSL_BASE + 1 * 0x40 + 0x220,
675                 .param.config = COH901318_CX_CFG_CH_DISABLE |
676                                 COH901318_CX_CFG_LCR_DISABLE |
677                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
678                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
679                 .param.ctrl_lli_chained = 0 |
680                                 COH901318_CX_CTRL_TC_ENABLE |
681                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
682                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
683                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
684                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
685                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
686                                 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
687                                 COH901318_CX_CTRL_TCP_DISABLE |
688                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
689                                 COH901318_CX_CTRL_HSP_ENABLE |
690                                 COH901318_CX_CTRL_HSS_DISABLE |
691                                 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
692                                 COH901318_CX_CTRL_PRDD_DEST,
693                 .param.ctrl_lli = 0,
694                 .param.ctrl_lli_last = 0 |
695                                 COH901318_CX_CTRL_TC_ENABLE |
696                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
697                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
698                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
699                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
700                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
701                                 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
702                                 COH901318_CX_CTRL_TCP_DISABLE |
703                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
704                                 COH901318_CX_CTRL_HSP_ENABLE |
705                                 COH901318_CX_CTRL_HSS_DISABLE |
706                                 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
707                                 COH901318_CX_CTRL_PRDD_DEST,
708         },
709         {
710                 .number = U300_DMA_MSL_RX_2,
711                 .name = "MSL RX 2",
712                 .priority_high = 0,
713                 .dev_addr = U300_MSL_BASE + 2 * 0x40 + 0x220,
714                 .param.config = COH901318_CX_CFG_CH_DISABLE |
715                                 COH901318_CX_CFG_LCR_DISABLE |
716                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
717                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
718                 .param.ctrl_lli_chained = 0 |
719                                 COH901318_CX_CTRL_TC_ENABLE |
720                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
721                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
722                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
723                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
724                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
725                                 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
726                                 COH901318_CX_CTRL_TCP_DISABLE |
727                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
728                                 COH901318_CX_CTRL_HSP_ENABLE |
729                                 COH901318_CX_CTRL_HSS_DISABLE |
730                                 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
731                                 COH901318_CX_CTRL_PRDD_DEST,
732                 .param.ctrl_lli = 0 |
733                                 COH901318_CX_CTRL_TC_ENABLE |
734                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
735                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
736                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
737                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
738                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
739                                 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
740                                 COH901318_CX_CTRL_TCP_DISABLE |
741                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
742                                 COH901318_CX_CTRL_HSP_ENABLE |
743                                 COH901318_CX_CTRL_HSS_DISABLE |
744                                 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
745                                 COH901318_CX_CTRL_PRDD_DEST,
746                 .param.ctrl_lli_last = 0 |
747                                 COH901318_CX_CTRL_TC_ENABLE |
748                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
749                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
750                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
751                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
752                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
753                                 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
754                                 COH901318_CX_CTRL_TCP_DISABLE |
755                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
756                                 COH901318_CX_CTRL_HSP_ENABLE |
757                                 COH901318_CX_CTRL_HSS_DISABLE |
758                                 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
759                                 COH901318_CX_CTRL_PRDD_DEST,
760         },
761         {
762                 .number = U300_DMA_MSL_RX_3,
763                 .name = "MSL RX 3",
764                 .priority_high = 0,
765                 .dev_addr = U300_MSL_BASE + 3 * 0x40 + 0x220,
766                 .param.config = COH901318_CX_CFG_CH_DISABLE |
767                                 COH901318_CX_CFG_LCR_DISABLE |
768                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
769                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
770                 .param.ctrl_lli_chained = 0 |
771                                 COH901318_CX_CTRL_TC_ENABLE |
772                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
773                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
774                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
775                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
776                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
777                                 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
778                                 COH901318_CX_CTRL_TCP_DISABLE |
779                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
780                                 COH901318_CX_CTRL_HSP_ENABLE |
781                                 COH901318_CX_CTRL_HSS_DISABLE |
782                                 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
783                                 COH901318_CX_CTRL_PRDD_DEST,
784                 .param.ctrl_lli = 0 |
785                                 COH901318_CX_CTRL_TC_ENABLE |
786                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
787                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
788                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
789                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
790                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
791                                 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
792                                 COH901318_CX_CTRL_TCP_DISABLE |
793                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
794                                 COH901318_CX_CTRL_HSP_ENABLE |
795                                 COH901318_CX_CTRL_HSS_DISABLE |
796                                 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
797                                 COH901318_CX_CTRL_PRDD_DEST,
798                 .param.ctrl_lli_last = 0 |
799                                 COH901318_CX_CTRL_TC_ENABLE |
800                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
801                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
802                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
803                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
804                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
805                                 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
806                                 COH901318_CX_CTRL_TCP_DISABLE |
807                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
808                                 COH901318_CX_CTRL_HSP_ENABLE |
809                                 COH901318_CX_CTRL_HSS_DISABLE |
810                                 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
811                                 COH901318_CX_CTRL_PRDD_DEST,
812         },
813         {
814                 .number = U300_DMA_MSL_RX_4,
815                 .name = "MSL RX 4",
816                 .priority_high = 0,
817                 .dev_addr = U300_MSL_BASE + 4 * 0x40 + 0x220,
818                 .param.config = COH901318_CX_CFG_CH_DISABLE |
819                                 COH901318_CX_CFG_LCR_DISABLE |
820                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
821                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
822                 .param.ctrl_lli_chained = 0 |
823                                 COH901318_CX_CTRL_TC_ENABLE |
824                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
825                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
826                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
827                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
828                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
829                                 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
830                                 COH901318_CX_CTRL_TCP_DISABLE |
831                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
832                                 COH901318_CX_CTRL_HSP_ENABLE |
833                                 COH901318_CX_CTRL_HSS_DISABLE |
834                                 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
835                                 COH901318_CX_CTRL_PRDD_DEST,
836                 .param.ctrl_lli = 0 |
837                                 COH901318_CX_CTRL_TC_ENABLE |
838                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
839                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
840                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
841                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
842                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
843                                 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
844                                 COH901318_CX_CTRL_TCP_DISABLE |
845                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
846                                 COH901318_CX_CTRL_HSP_ENABLE |
847                                 COH901318_CX_CTRL_HSS_DISABLE |
848                                 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
849                                 COH901318_CX_CTRL_PRDD_DEST,
850                 .param.ctrl_lli_last = 0 |
851                                 COH901318_CX_CTRL_TC_ENABLE |
852                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
853                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
854                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
855                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
856                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
857                                 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
858                                 COH901318_CX_CTRL_TCP_DISABLE |
859                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
860                                 COH901318_CX_CTRL_HSP_ENABLE |
861                                 COH901318_CX_CTRL_HSS_DISABLE |
862                                 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
863                                 COH901318_CX_CTRL_PRDD_DEST,
864         },
865         {
866                 .number = U300_DMA_MSL_RX_5,
867                 .name = "MSL RX 5",
868                 .priority_high = 0,
869                 .dev_addr = U300_MSL_BASE + 5 * 0x40 + 0x220,
870                 .param.config = COH901318_CX_CFG_CH_DISABLE |
871                                 COH901318_CX_CFG_LCR_DISABLE |
872                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
873                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
874                 .param.ctrl_lli_chained = 0 |
875                                 COH901318_CX_CTRL_TC_ENABLE |
876                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
877                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
878                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
879                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
880                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
881                                 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
882                                 COH901318_CX_CTRL_TCP_DISABLE |
883                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
884                                 COH901318_CX_CTRL_HSP_ENABLE |
885                                 COH901318_CX_CTRL_HSS_DISABLE |
886                                 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
887                                 COH901318_CX_CTRL_PRDD_DEST,
888                 .param.ctrl_lli = 0 |
889                                 COH901318_CX_CTRL_TC_ENABLE |
890                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
891                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
892                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
893                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
894                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
895                                 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
896                                 COH901318_CX_CTRL_TCP_DISABLE |
897                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
898                                 COH901318_CX_CTRL_HSP_ENABLE |
899                                 COH901318_CX_CTRL_HSS_DISABLE |
900                                 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
901                                 COH901318_CX_CTRL_PRDD_DEST,
902                 .param.ctrl_lli_last = 0 |
903                                 COH901318_CX_CTRL_TC_ENABLE |
904                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
905                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
906                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
907                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
908                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
909                                 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
910                                 COH901318_CX_CTRL_TCP_DISABLE |
911                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
912                                 COH901318_CX_CTRL_HSP_ENABLE |
913                                 COH901318_CX_CTRL_HSS_DISABLE |
914                                 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
915                                 COH901318_CX_CTRL_PRDD_DEST,
916         },
917         {
918                 .number = U300_DMA_MSL_RX_6,
919                 .name = "MSL RX 6",
920                 .priority_high = 0,
921                 .dev_addr = U300_MSL_BASE + 6 * 0x40 + 0x220,
922         },
923         /*
924          * Don't set up device address, burst count or size of src
925          * or dst bus for this peripheral - handled by PrimeCell
926          * DMA extension.
927          */
928         {
929                 .number = U300_DMA_MMCSD_RX_TX,
930                 .name = "MMCSD RX TX",
931                 .priority_high = 0,
932                 .param.config = COH901318_CX_CFG_CH_DISABLE |
933                                 COH901318_CX_CFG_LCR_DISABLE |
934                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
935                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
936                 .param.ctrl_lli_chained = 0 |
937                                 COH901318_CX_CTRL_TC_ENABLE |
938                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
939                                 COH901318_CX_CTRL_TCP_ENABLE |
940                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
941                                 COH901318_CX_CTRL_HSP_ENABLE |
942                                 COH901318_CX_CTRL_HSS_DISABLE |
943                                 COH901318_CX_CTRL_DDMA_LEGACY,
944                 .param.ctrl_lli = 0 |
945                                 COH901318_CX_CTRL_TC_ENABLE |
946                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
947                                 COH901318_CX_CTRL_TCP_ENABLE |
948                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
949                                 COH901318_CX_CTRL_HSP_ENABLE |
950                                 COH901318_CX_CTRL_HSS_DISABLE |
951                                 COH901318_CX_CTRL_DDMA_LEGACY,
952                 .param.ctrl_lli_last = 0 |
953                                 COH901318_CX_CTRL_TC_ENABLE |
954                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
955                                 COH901318_CX_CTRL_TCP_DISABLE |
956                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
957                                 COH901318_CX_CTRL_HSP_ENABLE |
958                                 COH901318_CX_CTRL_HSS_DISABLE |
959                                 COH901318_CX_CTRL_DDMA_LEGACY,
960
961         },
962         {
963                 .number = U300_DMA_MSPRO_TX,
964                 .name = "MSPRO TX",
965                 .priority_high = 0,
966         },
967         {
968                 .number = U300_DMA_MSPRO_RX,
969                 .name = "MSPRO RX",
970                 .priority_high = 0,
971         },
972         /*
973          * Don't set up device address, burst count or size of src
974          * or dst bus for this peripheral - handled by PrimeCell
975          * DMA extension.
976          */
977         {
978                 .number = U300_DMA_UART0_TX,
979                 .name = "UART0 TX",
980                 .priority_high = 0,
981                 .param.config = COH901318_CX_CFG_CH_DISABLE |
982                                 COH901318_CX_CFG_LCR_DISABLE |
983                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
984                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
985                 .param.ctrl_lli_chained = 0 |
986                                 COH901318_CX_CTRL_TC_ENABLE |
987                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
988                                 COH901318_CX_CTRL_TCP_ENABLE |
989                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
990                                 COH901318_CX_CTRL_HSP_ENABLE |
991                                 COH901318_CX_CTRL_HSS_DISABLE |
992                                 COH901318_CX_CTRL_DDMA_LEGACY,
993                 .param.ctrl_lli = 0 |
994                                 COH901318_CX_CTRL_TC_ENABLE |
995                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
996                                 COH901318_CX_CTRL_TCP_ENABLE |
997                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
998                                 COH901318_CX_CTRL_HSP_ENABLE |
999                                 COH901318_CX_CTRL_HSS_DISABLE |
1000                                 COH901318_CX_CTRL_DDMA_LEGACY,
1001                 .param.ctrl_lli_last = 0 |
1002                                 COH901318_CX_CTRL_TC_ENABLE |
1003                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1004                                 COH901318_CX_CTRL_TCP_ENABLE |
1005                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1006                                 COH901318_CX_CTRL_HSP_ENABLE |
1007                                 COH901318_CX_CTRL_HSS_DISABLE |
1008                                 COH901318_CX_CTRL_DDMA_LEGACY,
1009         },
1010         {
1011                 .number = U300_DMA_UART0_RX,
1012                 .name = "UART0 RX",
1013                 .priority_high = 0,
1014                 .param.config = COH901318_CX_CFG_CH_DISABLE |
1015                                 COH901318_CX_CFG_LCR_DISABLE |
1016                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
1017                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
1018                 .param.ctrl_lli_chained = 0 |
1019                                 COH901318_CX_CTRL_TC_ENABLE |
1020                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1021                                 COH901318_CX_CTRL_TCP_ENABLE |
1022                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1023                                 COH901318_CX_CTRL_HSP_ENABLE |
1024                                 COH901318_CX_CTRL_HSS_DISABLE |
1025                                 COH901318_CX_CTRL_DDMA_LEGACY,
1026                 .param.ctrl_lli = 0 |
1027                                 COH901318_CX_CTRL_TC_ENABLE |
1028                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1029                                 COH901318_CX_CTRL_TCP_ENABLE |
1030                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1031                                 COH901318_CX_CTRL_HSP_ENABLE |
1032                                 COH901318_CX_CTRL_HSS_DISABLE |
1033                                 COH901318_CX_CTRL_DDMA_LEGACY,
1034                 .param.ctrl_lli_last = 0 |
1035                                 COH901318_CX_CTRL_TC_ENABLE |
1036                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1037                                 COH901318_CX_CTRL_TCP_ENABLE |
1038                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1039                                 COH901318_CX_CTRL_HSP_ENABLE |
1040                                 COH901318_CX_CTRL_HSS_DISABLE |
1041                                 COH901318_CX_CTRL_DDMA_LEGACY,
1042         },
1043         {
1044                 .number = U300_DMA_APEX_TX,
1045                 .name = "APEX TX",
1046                 .priority_high = 0,
1047         },
1048         {
1049                 .number = U300_DMA_APEX_RX,
1050                 .name = "APEX RX",
1051                 .priority_high = 0,
1052         },
1053         {
1054                 .number = U300_DMA_PCM_I2S0_TX,
1055                 .name = "PCM I2S0 TX",
1056                 .priority_high = 1,
1057                 .dev_addr = U300_PCM_I2S0_BASE + 0x14,
1058                 .param.config = COH901318_CX_CFG_CH_DISABLE |
1059                                 COH901318_CX_CFG_LCR_DISABLE |
1060                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
1061                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
1062                 .param.ctrl_lli_chained = 0 |
1063                                 COH901318_CX_CTRL_TC_ENABLE |
1064                                 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1065                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1066                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
1067                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1068                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
1069                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1070                                 COH901318_CX_CTRL_TCP_DISABLE |
1071                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1072                                 COH901318_CX_CTRL_HSP_ENABLE |
1073                                 COH901318_CX_CTRL_HSS_DISABLE |
1074                                 COH901318_CX_CTRL_DDMA_LEGACY |
1075                                 COH901318_CX_CTRL_PRDD_SOURCE,
1076                 .param.ctrl_lli = 0 |
1077                                 COH901318_CX_CTRL_TC_ENABLE |
1078                                 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1079                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1080                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
1081                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1082                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
1083                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1084                                 COH901318_CX_CTRL_TCP_ENABLE |
1085                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1086                                 COH901318_CX_CTRL_HSP_ENABLE |
1087                                 COH901318_CX_CTRL_HSS_DISABLE |
1088                                 COH901318_CX_CTRL_DDMA_LEGACY |
1089                                 COH901318_CX_CTRL_PRDD_SOURCE,
1090                 .param.ctrl_lli_last = 0 |
1091                                 COH901318_CX_CTRL_TC_ENABLE |
1092                                 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1093                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1094                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
1095                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1096                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
1097                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1098                                 COH901318_CX_CTRL_TCP_ENABLE |
1099                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1100                                 COH901318_CX_CTRL_HSP_ENABLE |
1101                                 COH901318_CX_CTRL_HSS_DISABLE |
1102                                 COH901318_CX_CTRL_DDMA_LEGACY |
1103                                 COH901318_CX_CTRL_PRDD_SOURCE,
1104         },
1105         {
1106                 .number = U300_DMA_PCM_I2S0_RX,
1107                 .name = "PCM I2S0 RX",
1108                 .priority_high = 1,
1109                 .dev_addr = U300_PCM_I2S0_BASE + 0x10,
1110                 .param.config = COH901318_CX_CFG_CH_DISABLE |
1111                                 COH901318_CX_CFG_LCR_DISABLE |
1112                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
1113                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
1114                 .param.ctrl_lli_chained = 0 |
1115                                 COH901318_CX_CTRL_TC_ENABLE |
1116                                 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1117                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1118                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
1119                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1120                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
1121                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1122                                 COH901318_CX_CTRL_TCP_DISABLE |
1123                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1124                                 COH901318_CX_CTRL_HSP_ENABLE |
1125                                 COH901318_CX_CTRL_HSS_DISABLE |
1126                                 COH901318_CX_CTRL_DDMA_LEGACY |
1127                                 COH901318_CX_CTRL_PRDD_DEST,
1128                 .param.ctrl_lli = 0 |
1129                                 COH901318_CX_CTRL_TC_ENABLE |
1130                                 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1131                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1132                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
1133                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1134                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
1135                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1136                                 COH901318_CX_CTRL_TCP_ENABLE |
1137                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1138                                 COH901318_CX_CTRL_HSP_ENABLE |
1139                                 COH901318_CX_CTRL_HSS_DISABLE |
1140                                 COH901318_CX_CTRL_DDMA_LEGACY |
1141                                 COH901318_CX_CTRL_PRDD_DEST,
1142                 .param.ctrl_lli_last = 0 |
1143                                 COH901318_CX_CTRL_TC_ENABLE |
1144                                 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1145                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1146                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
1147                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1148                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
1149                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1150                                 COH901318_CX_CTRL_TCP_ENABLE |
1151                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1152                                 COH901318_CX_CTRL_HSP_ENABLE |
1153                                 COH901318_CX_CTRL_HSS_DISABLE |
1154                                 COH901318_CX_CTRL_DDMA_LEGACY |
1155                                 COH901318_CX_CTRL_PRDD_DEST,
1156         },
1157         {
1158                 .number = U300_DMA_PCM_I2S1_TX,
1159                 .name = "PCM I2S1 TX",
1160                 .priority_high = 1,
1161                 .dev_addr =  U300_PCM_I2S1_BASE + 0x14,
1162                 .param.config = COH901318_CX_CFG_CH_DISABLE |
1163                                 COH901318_CX_CFG_LCR_DISABLE |
1164                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
1165                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
1166                 .param.ctrl_lli_chained = 0 |
1167                                 COH901318_CX_CTRL_TC_ENABLE |
1168                                 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1169                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1170                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
1171                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1172                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
1173                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1174                                 COH901318_CX_CTRL_TCP_DISABLE |
1175                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1176                                 COH901318_CX_CTRL_HSP_ENABLE |
1177                                 COH901318_CX_CTRL_HSS_DISABLE |
1178                                 COH901318_CX_CTRL_DDMA_LEGACY |
1179                                 COH901318_CX_CTRL_PRDD_SOURCE,
1180                 .param.ctrl_lli = 0 |
1181                                 COH901318_CX_CTRL_TC_ENABLE |
1182                                 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1183                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1184                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
1185                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1186                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
1187                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1188                                 COH901318_CX_CTRL_TCP_ENABLE |
1189                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1190                                 COH901318_CX_CTRL_HSP_ENABLE |
1191                                 COH901318_CX_CTRL_HSS_DISABLE |
1192                                 COH901318_CX_CTRL_DDMA_LEGACY |
1193                                 COH901318_CX_CTRL_PRDD_SOURCE,
1194                 .param.ctrl_lli_last = 0 |
1195                                 COH901318_CX_CTRL_TC_ENABLE |
1196                                 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1197                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1198                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
1199                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1200                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
1201                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1202                                 COH901318_CX_CTRL_TCP_ENABLE |
1203                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1204                                 COH901318_CX_CTRL_HSP_ENABLE |
1205                                 COH901318_CX_CTRL_HSS_DISABLE |
1206                                 COH901318_CX_CTRL_DDMA_LEGACY |
1207                                 COH901318_CX_CTRL_PRDD_SOURCE,
1208         },
1209         {
1210                 .number = U300_DMA_PCM_I2S1_RX,
1211                 .name = "PCM I2S1 RX",
1212                 .priority_high = 1,
1213                 .dev_addr = U300_PCM_I2S1_BASE + 0x10,
1214                 .param.config = COH901318_CX_CFG_CH_DISABLE |
1215                                 COH901318_CX_CFG_LCR_DISABLE |
1216                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
1217                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
1218                 .param.ctrl_lli_chained = 0 |
1219                                 COH901318_CX_CTRL_TC_ENABLE |
1220                                 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1221                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1222                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
1223                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1224                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
1225                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1226                                 COH901318_CX_CTRL_TCP_DISABLE |
1227                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1228                                 COH901318_CX_CTRL_HSP_ENABLE |
1229                                 COH901318_CX_CTRL_HSS_DISABLE |
1230                                 COH901318_CX_CTRL_DDMA_LEGACY |
1231                                 COH901318_CX_CTRL_PRDD_DEST,
1232                 .param.ctrl_lli = 0 |
1233                                 COH901318_CX_CTRL_TC_ENABLE |
1234                                 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1235                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1236                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
1237                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1238                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
1239                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1240                                 COH901318_CX_CTRL_TCP_ENABLE |
1241                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1242                                 COH901318_CX_CTRL_HSP_ENABLE |
1243                                 COH901318_CX_CTRL_HSS_DISABLE |
1244                                 COH901318_CX_CTRL_DDMA_LEGACY |
1245                                 COH901318_CX_CTRL_PRDD_DEST,
1246                 .param.ctrl_lli_last = 0 |
1247                                 COH901318_CX_CTRL_TC_ENABLE |
1248                                 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1249                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1250                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
1251                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1252                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
1253                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1254                                 COH901318_CX_CTRL_TCP_ENABLE |
1255                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1256                                 COH901318_CX_CTRL_HSP_ENABLE |
1257                                 COH901318_CX_CTRL_HSS_DISABLE |
1258                                 COH901318_CX_CTRL_DDMA_LEGACY |
1259                                 COH901318_CX_CTRL_PRDD_DEST,
1260         },
1261         {
1262                 .number = U300_DMA_XGAM_CDI,
1263                 .name = "XGAM CDI",
1264                 .priority_high = 0,
1265         },
1266         {
1267                 .number = U300_DMA_XGAM_PDI,
1268                 .name = "XGAM PDI",
1269                 .priority_high = 0,
1270         },
1271         /*
1272          * Don't set up device address, burst count or size of src
1273          * or dst bus for this peripheral - handled by PrimeCell
1274          * DMA extension.
1275          */
1276         {
1277                 .number = U300_DMA_SPI_TX,
1278                 .name = "SPI TX",
1279                 .priority_high = 0,
1280                 .param.config = COH901318_CX_CFG_CH_DISABLE |
1281                                 COH901318_CX_CFG_LCR_DISABLE |
1282                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
1283                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
1284                 .param.ctrl_lli_chained = 0 |
1285                                 COH901318_CX_CTRL_TC_ENABLE |
1286                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1287                                 COH901318_CX_CTRL_TCP_DISABLE |
1288                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1289                                 COH901318_CX_CTRL_HSP_ENABLE |
1290                                 COH901318_CX_CTRL_HSS_DISABLE |
1291                                 COH901318_CX_CTRL_DDMA_LEGACY,
1292                 .param.ctrl_lli = 0 |
1293                                 COH901318_CX_CTRL_TC_ENABLE |
1294                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1295                                 COH901318_CX_CTRL_TCP_DISABLE |
1296                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1297                                 COH901318_CX_CTRL_HSP_ENABLE |
1298                                 COH901318_CX_CTRL_HSS_DISABLE |
1299                                 COH901318_CX_CTRL_DDMA_LEGACY,
1300                 .param.ctrl_lli_last = 0 |
1301                                 COH901318_CX_CTRL_TC_ENABLE |
1302                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1303                                 COH901318_CX_CTRL_TCP_DISABLE |
1304                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1305                                 COH901318_CX_CTRL_HSP_ENABLE |
1306                                 COH901318_CX_CTRL_HSS_DISABLE |
1307                                 COH901318_CX_CTRL_DDMA_LEGACY,
1308         },
1309         {
1310                 .number = U300_DMA_SPI_RX,
1311                 .name = "SPI RX",
1312                 .priority_high = 0,
1313                 .param.config = COH901318_CX_CFG_CH_DISABLE |
1314                                 COH901318_CX_CFG_LCR_DISABLE |
1315                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
1316                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
1317                 .param.ctrl_lli_chained = 0 |
1318                                 COH901318_CX_CTRL_TC_ENABLE |
1319                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1320                                 COH901318_CX_CTRL_TCP_DISABLE |
1321                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1322                                 COH901318_CX_CTRL_HSP_ENABLE |
1323                                 COH901318_CX_CTRL_HSS_DISABLE |
1324                                 COH901318_CX_CTRL_DDMA_LEGACY,
1325                 .param.ctrl_lli = 0 |
1326                                 COH901318_CX_CTRL_TC_ENABLE |
1327                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1328                                 COH901318_CX_CTRL_TCP_DISABLE |
1329                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1330                                 COH901318_CX_CTRL_HSP_ENABLE |
1331                                 COH901318_CX_CTRL_HSS_DISABLE |
1332                                 COH901318_CX_CTRL_DDMA_LEGACY,
1333                 .param.ctrl_lli_last = 0 |
1334                                 COH901318_CX_CTRL_TC_ENABLE |
1335                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1336                                 COH901318_CX_CTRL_TCP_DISABLE |
1337                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1338                                 COH901318_CX_CTRL_HSP_ENABLE |
1339                                 COH901318_CX_CTRL_HSS_DISABLE |
1340                                 COH901318_CX_CTRL_DDMA_LEGACY,
1341
1342         },
1343         {
1344                 .number = U300_DMA_GENERAL_PURPOSE_0,
1345                 .name = "GENERAL 00",
1346                 .priority_high = 0,
1347
1348                 .param.config = flags_memcpy_config,
1349                 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1350                 .param.ctrl_lli = flags_memcpy_lli,
1351                 .param.ctrl_lli_last = flags_memcpy_lli_last,
1352         },
1353         {
1354                 .number = U300_DMA_GENERAL_PURPOSE_1,
1355                 .name = "GENERAL 01",
1356                 .priority_high = 0,
1357
1358                 .param.config = flags_memcpy_config,
1359                 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1360                 .param.ctrl_lli = flags_memcpy_lli,
1361                 .param.ctrl_lli_last = flags_memcpy_lli_last,
1362         },
1363         {
1364                 .number = U300_DMA_GENERAL_PURPOSE_2,
1365                 .name = "GENERAL 02",
1366                 .priority_high = 0,
1367
1368                 .param.config = flags_memcpy_config,
1369                 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1370                 .param.ctrl_lli = flags_memcpy_lli,
1371                 .param.ctrl_lli_last = flags_memcpy_lli_last,
1372         },
1373         {
1374                 .number = U300_DMA_GENERAL_PURPOSE_3,
1375                 .name = "GENERAL 03",
1376                 .priority_high = 0,
1377
1378                 .param.config = flags_memcpy_config,
1379                 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1380                 .param.ctrl_lli = flags_memcpy_lli,
1381                 .param.ctrl_lli_last = flags_memcpy_lli_last,
1382         },
1383         {
1384                 .number = U300_DMA_GENERAL_PURPOSE_4,
1385                 .name = "GENERAL 04",
1386                 .priority_high = 0,
1387
1388                 .param.config = flags_memcpy_config,
1389                 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1390                 .param.ctrl_lli = flags_memcpy_lli,
1391                 .param.ctrl_lli_last = flags_memcpy_lli_last,
1392         },
1393         {
1394                 .number = U300_DMA_GENERAL_PURPOSE_5,
1395                 .name = "GENERAL 05",
1396                 .priority_high = 0,
1397
1398                 .param.config = flags_memcpy_config,
1399                 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1400                 .param.ctrl_lli = flags_memcpy_lli,
1401                 .param.ctrl_lli_last = flags_memcpy_lli_last,
1402         },
1403         {
1404                 .number = U300_DMA_GENERAL_PURPOSE_6,
1405                 .name = "GENERAL 06",
1406                 .priority_high = 0,
1407
1408                 .param.config = flags_memcpy_config,
1409                 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1410                 .param.ctrl_lli = flags_memcpy_lli,
1411                 .param.ctrl_lli_last = flags_memcpy_lli_last,
1412         },
1413         {
1414                 .number = U300_DMA_GENERAL_PURPOSE_7,
1415                 .name = "GENERAL 07",
1416                 .priority_high = 0,
1417
1418                 .param.config = flags_memcpy_config,
1419                 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1420                 .param.ctrl_lli = flags_memcpy_lli,
1421                 .param.ctrl_lli_last = flags_memcpy_lli_last,
1422         },
1423         {
1424                 .number = U300_DMA_GENERAL_PURPOSE_8,
1425                 .name = "GENERAL 08",
1426                 .priority_high = 0,
1427
1428                 .param.config = flags_memcpy_config,
1429                 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1430                 .param.ctrl_lli = flags_memcpy_lli,
1431                 .param.ctrl_lli_last = flags_memcpy_lli_last,
1432         },
1433 #ifdef CONFIG_MACH_U300_BS335
1434         {
1435                 .number = U300_DMA_UART1_TX,
1436                 .name = "UART1 TX",
1437                 .priority_high = 0,
1438         },
1439         {
1440                 .number = U300_DMA_UART1_RX,
1441                 .name = "UART1 RX",
1442                 .priority_high = 0,
1443         }
1444 #else
1445         {
1446                 .number = U300_DMA_GENERAL_PURPOSE_9,
1447                 .name = "GENERAL 09",
1448                 .priority_high = 0,
1449
1450                 .param.config = flags_memcpy_config,
1451                 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1452                 .param.ctrl_lli = flags_memcpy_lli,
1453                 .param.ctrl_lli_last = flags_memcpy_lli_last,
1454         },
1455         {
1456                 .number = U300_DMA_GENERAL_PURPOSE_10,
1457                 .name = "GENERAL 10",
1458                 .priority_high = 0,
1459
1460                 .param.config = flags_memcpy_config,
1461                 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1462                 .param.ctrl_lli = flags_memcpy_lli,
1463                 .param.ctrl_lli_last = flags_memcpy_lli_last,
1464         }
1465 #endif
1466 };
1467
1468
1469 static struct coh901318_platform coh901318_platform = {
1470         .chans_slave = dma_slave_channels,
1471         .chans_memcpy = dma_memcpy_channels,
1472         .access_memory_state = coh901318_access_memory_state,
1473         .chan_conf = chan_config,
1474         .max_channels = U300_DMA_CHANNELS,
1475 };
1476
1477 static struct platform_device wdog_device = {
1478         .name = "coh901327_wdog",
1479         .id = -1,
1480         .num_resources = ARRAY_SIZE(wdog_resources),
1481         .resource = wdog_resources,
1482 };
1483
1484 static struct platform_device i2c0_device = {
1485         .name = "stu300",
1486         .id = 0,
1487         .num_resources = ARRAY_SIZE(i2c0_resources),
1488         .resource = i2c0_resources,
1489 };
1490
1491 static struct platform_device i2c1_device = {
1492         .name = "stu300",
1493         .id = 1,
1494         .num_resources = ARRAY_SIZE(i2c1_resources),
1495         .resource = i2c1_resources,
1496 };
1497
1498 static struct platform_device gpio_device = {
1499         .name = "u300-gpio",
1500         .id = -1,
1501         .num_resources = ARRAY_SIZE(gpio_resources),
1502         .resource = gpio_resources,
1503 };
1504
1505 static struct platform_device keypad_device = {
1506         .name = "keypad",
1507         .id = -1,
1508         .num_resources = ARRAY_SIZE(keypad_resources),
1509         .resource = keypad_resources,
1510 };
1511
1512 static struct platform_device rtc_device = {
1513         .name = "rtc-coh901331",
1514         .id = -1,
1515         .num_resources = ARRAY_SIZE(rtc_resources),
1516         .resource = rtc_resources,
1517 };
1518
1519 static struct mtd_partition u300_partitions[] = {
1520         {
1521                 .name = "bootrecords",
1522                 .offset = 0,
1523                 .size = SZ_128K,
1524         },
1525         {
1526                 .name = "free",
1527                 .offset = SZ_128K,
1528                 .size = 8064 * SZ_1K,
1529         },
1530         {
1531                 .name = "platform",
1532                 .offset = 8192 * SZ_1K,
1533                 .size = 253952 * SZ_1K,
1534         },
1535 };
1536
1537 static struct fsmc_nand_platform_data nand_platform_data = {
1538         .partitions = u300_partitions,
1539         .nr_partitions = ARRAY_SIZE(u300_partitions),
1540         .options = NAND_SKIP_BBTSCAN,
1541         .width = FSMC_NAND_BW8,
1542 };
1543
1544 static struct platform_device nand_device = {
1545         .name = "fsmc-nand",
1546         .id = -1,
1547         .resource = fsmc_resources,
1548         .num_resources = ARRAY_SIZE(fsmc_resources),
1549         .dev = {
1550                 .platform_data = &nand_platform_data,
1551         },
1552 };
1553
1554 static struct platform_device dma_device = {
1555         .name           = "coh901318",
1556         .id             = -1,
1557         .resource       = dma_resource,
1558         .num_resources  = ARRAY_SIZE(dma_resource),
1559         .dev = {
1560                 .platform_data = &coh901318_platform,
1561                 .coherent_dma_mask = ~0,
1562         },
1563 };
1564
1565 /*
1566  * Notice that AMBA devices are initialized before platform devices.
1567  *
1568  */
1569 static struct platform_device *platform_devs[] __initdata = {
1570         &dma_device,
1571         &i2c0_device,
1572         &i2c1_device,
1573         &keypad_device,
1574         &rtc_device,
1575         &gpio_device,
1576         &nand_device,
1577         &wdog_device,
1578 };
1579
1580 /*
1581  * Interrupts: the U300 platforms have two pl190 ARM PrimeCells connected
1582  * together so some interrupts are connected to the first one and some
1583  * to the second one.
1584  */
1585 void __init u300_init_irq(void)
1586 {
1587         u32 mask[2] = {0, 0};
1588         struct clk *clk;
1589         int i;
1590
1591         /* initialize clocking early, we want to clock the INTCON */
1592         u300_clock_init();
1593
1594         /* Clock the interrupt controller */
1595         clk = clk_get_sys("intcon", NULL);
1596         BUG_ON(IS_ERR(clk));
1597         clk_enable(clk);
1598
1599         for (i = 0; i < NR_IRQS; i++)
1600                 set_bit(i, (unsigned long *) &mask[0]);
1601         vic_init((void __iomem *) U300_INTCON0_VBASE, 0, mask[0], mask[0]);
1602         vic_init((void __iomem *) U300_INTCON1_VBASE, 32, mask[1], mask[1]);
1603 }
1604
1605
1606 /*
1607  * U300 platforms peripheral handling
1608  */
1609 struct db_chip {
1610         u16 chipid;
1611         const char *name;
1612 };
1613
1614 /*
1615  * This is a list of the Digital Baseband chips used in the U300 platform.
1616  */
1617 static struct db_chip db_chips[] __initdata = {
1618         {
1619                 .chipid = 0xb800,
1620                 .name = "DB3000",
1621         },
1622         {
1623                 .chipid = 0xc000,
1624                 .name = "DB3100",
1625         },
1626         {
1627                 .chipid = 0xc800,
1628                 .name = "DB3150",
1629         },
1630         {
1631                 .chipid = 0xd800,
1632                 .name = "DB3200",
1633         },
1634         {
1635                 .chipid = 0xe000,
1636                 .name = "DB3250",
1637         },
1638         {
1639                 .chipid = 0xe800,
1640                 .name = "DB3210",
1641         },
1642         {
1643                 .chipid = 0xf000,
1644                 .name = "DB3350 P1x",
1645         },
1646         {
1647                 .chipid = 0xf100,
1648                 .name = "DB3350 P2x",
1649         },
1650         {
1651                 .chipid = 0x0000, /* List terminator */
1652                 .name = NULL,
1653         }
1654 };
1655
1656 static void __init u300_init_check_chip(void)
1657 {
1658
1659         u16 val;
1660         struct db_chip *chip;
1661         const char *chipname;
1662         const char unknown[] = "UNKNOWN";
1663
1664         /* Read out and print chip ID */
1665         val = readw(U300_SYSCON_VBASE + U300_SYSCON_CIDR);
1666         /* This is in funky bigendian order... */
1667         val = (val & 0xFFU) << 8 | (val >> 8);
1668         chip = db_chips;
1669         chipname = unknown;
1670
1671         for ( ; chip->chipid; chip++) {
1672                 if (chip->chipid == (val & 0xFF00U)) {
1673                         chipname = chip->name;
1674                         break;
1675                 }
1676         }
1677         printk(KERN_INFO "Initializing U300 system on %s baseband chip " \
1678                "(chip ID 0x%04x)\n", chipname, val);
1679
1680 #ifdef CONFIG_MACH_U300_BS330
1681         if ((val & 0xFF00U) != 0xd800) {
1682                 printk(KERN_ERR "Platform configured for BS330 " \
1683                        "with DB3200 but %s detected, expect problems!",
1684                        chipname);
1685         }
1686 #endif
1687 #ifdef CONFIG_MACH_U300_BS335
1688         if ((val & 0xFF00U) != 0xf000 && (val & 0xFF00U) != 0xf100) {
1689                 printk(KERN_ERR "Platform configured for BS335 " \
1690                        " with DB3350 but %s detected, expect problems!",
1691                        chipname);
1692         }
1693 #endif
1694 #ifdef CONFIG_MACH_U300_BS365
1695         if ((val & 0xFF00U) != 0xe800) {
1696                 printk(KERN_ERR "Platform configured for BS365 " \
1697                        "with DB3210 but %s detected, expect problems!",
1698                        chipname);
1699         }
1700 #endif
1701
1702
1703 }
1704
1705 /*
1706  * Some devices and their resources require reserved physical memory from
1707  * the end of the available RAM. This function traverses the list of devices
1708  * and assigns actual addresses to these.
1709  */
1710 static void __init u300_assign_physmem(void)
1711 {
1712         unsigned long curr_start = __pa(high_memory);
1713         int i, j;
1714
1715         for (i = 0; i < ARRAY_SIZE(platform_devs); i++) {
1716                 for (j = 0; j < platform_devs[i]->num_resources; j++) {
1717                         struct resource *const res =
1718                           &platform_devs[i]->resource[j];
1719
1720                         if (IORESOURCE_MEM == res->flags &&
1721                                      0 == res->start) {
1722                                 res->start  = curr_start;
1723                                 res->end   += curr_start;
1724                                 curr_start += resource_size(res);
1725
1726                                 printk(KERN_INFO "core.c: Mapping RAM " \
1727                                        "%#x-%#x to device %s:%s\n",
1728                                         res->start, res->end,
1729                                        platform_devs[i]->name, res->name);
1730                         }
1731                 }
1732         }
1733 }
1734
1735 void __init u300_init_devices(void)
1736 {
1737         int i;
1738         u16 val;
1739
1740         /* Check what platform we run and print some status information */
1741         u300_init_check_chip();
1742
1743         /* Set system to run at PLL208, max performance, a known state. */
1744         val = readw(U300_SYSCON_VBASE + U300_SYSCON_CCR);
1745         val &= ~U300_SYSCON_CCR_CLKING_PERFORMANCE_MASK;
1746         writew(val, U300_SYSCON_VBASE + U300_SYSCON_CCR);
1747         /* Wait for the PLL208 to lock if not locked in yet */
1748         while (!(readw(U300_SYSCON_VBASE + U300_SYSCON_CSR) &
1749                  U300_SYSCON_CSR_PLL208_LOCK_IND));
1750         /* Initialize SPI device with some board specifics */
1751         u300_spi_init(&pl022_device);
1752
1753         /* Register the AMBA devices in the AMBA bus abstraction layer */
1754         for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
1755                 struct amba_device *d = amba_devs[i];
1756                 amba_device_register(d, &iomem_resource);
1757         }
1758
1759         u300_assign_physmem();
1760
1761         /* Register subdevices on the I2C buses */
1762         u300_i2c_register_board_devices();
1763
1764         /* Register the platform devices */
1765         platform_add_devices(platform_devs, ARRAY_SIZE(platform_devs));
1766
1767         /* Register subdevices on the SPI bus */
1768         u300_spi_register_board_devices();
1769
1770         /* Enable SEMI self refresh */
1771         val = readw(U300_SYSCON_VBASE + U300_SYSCON_SMCR) |
1772                 U300_SYSCON_SMCR_SEMI_SREFREQ_ENABLE;
1773         writew(val, U300_SYSCON_VBASE + U300_SYSCON_SMCR);
1774 }
1775
1776 static int core_module_init(void)
1777 {
1778         /*
1779          * This needs to be initialized later: it needs the input framework
1780          * to be initialized first.
1781          */
1782         return mmc_init(&mmcsd_device);
1783 }
1784 module_init(core_module_init);