b82a1be692f9f7a35a62a2356788ff19e9c18744
[linux-3.10.git] / arch / arm / mach-tegra / timer-t3.c
1 /*
2  * arch/arch/mach-tegra/timer-t3.c
3  *
4  * Copyright (c) 2011, NVIDIA Corporation.
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License as published by
8  * the Free Software Foundation; either version 2 of the License, or
9  * (at your option) any later version.
10  *
11  * This program is distributed in the hope that it will be useful, but WITHOUT
12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
14  * more details.
15  *
16  * You should have received a copy of the GNU General Public License along
17  * with this program; if not, write to the Free Software Foundation, Inc.,
18  * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
19  */
20
21 #include <linux/init.h>
22 #include <linux/err.h>
23 #include <linux/sched.h>
24 #include <linux/time.h>
25 #include <linux/interrupt.h>
26 #include <linux/irq.h>
27 #include <linux/clockchips.h>
28 #include <linux/clocksource.h>
29 #include <linux/clk.h>
30 #include <linux/io.h>
31 #include <linux/smp.h>
32 #include <linux/syscore_ops.h>
33 #include <linux/cpu.h>
34 #include <linux/export.h>
35
36 #include <asm/mach/time.h>
37 #include <asm/localtimer.h>
38 #include <asm/sched_clock.h>
39
40 #include <mach/hardware.h>
41 #include <mach/iomap.h>
42 #include <mach/irqs.h>
43
44 #include "board.h"
45 #include "clock.h"
46 #include "cpuidle.h"
47 #include "timer.h"
48
49 #define TEST_LP2_WAKE_TIMERS    0
50
51 /*
52  * Timers usage:
53  * TMR1 - used as general CPU timer.
54  * TMR2 - used by AVP.
55  * TMR3 - used by CPU0 for LP2 wakeup.
56  * TMR4 - used by CPU1 for LP2 wakeup.
57  * TMR5 - used by CPU2 for LP2 wakeup.
58  * TMR6 - used by CPU3 for LP2 wakeup.
59  * TMR7 - Free.
60  * TMR8 - Free.
61  * TMR9 - Free.
62  * TMR10 - used as source for watchdog controller 0.
63 */
64
65 #define TIMER1_OFFSET (TEGRA_TMR1_BASE-TEGRA_TMR1_BASE)
66 #define TIMER2_OFFSET (TEGRA_TMR2_BASE-TEGRA_TMR1_BASE)
67 #define TIMER3_OFFSET (TEGRA_TMR3_BASE-TEGRA_TMR1_BASE)
68 #define TIMER4_OFFSET (TEGRA_TMR4_BASE-TEGRA_TMR1_BASE)
69 #define TIMER5_OFFSET (TEGRA_TMR5_BASE-TEGRA_TMR1_BASE)
70 #define TIMER6_OFFSET (TEGRA_TMR6_BASE-TEGRA_TMR1_BASE)
71
72 static void __iomem *timer_reg_base = IO_ADDRESS(TEGRA_TMR1_BASE);
73 static cpumask_t wake_timer_ready;
74
75 #define timer_writel(value, reg) \
76         __raw_writel(value, timer_reg_base + (reg))
77 #define timer_readl(reg) \
78         __raw_readl(timer_reg_base + (reg))
79
80
81 #ifdef CONFIG_PM_SLEEP
82 static u32 lp2_wake_timers[] = {
83         TIMER3_OFFSET,
84 #ifdef CONFIG_SMP
85         TIMER4_OFFSET,
86         TIMER5_OFFSET,
87         TIMER6_OFFSET,
88 #endif
89 };
90
91 static irqreturn_t tegra_lp2wake_interrupt(int irq, void *dev_id)
92 {
93         int cpu = (int)dev_id;
94         int base;
95
96         base = lp2_wake_timers[cpu];
97         timer_writel(1<<30, base + TIMER_PCR);
98         return IRQ_HANDLED;
99 }
100
101 #define LP2_TIMER_IRQ_ACTION(cpu, irqnum) {                     \
102         .name           = "tmr_lp2wake_cpu" __stringify(cpu),   \
103         .flags          = IRQF_DISABLED,                        \
104         .handler        = tegra_lp2wake_interrupt,              \
105         .dev_id         = (void*)cpu,                           \
106         .irq            = irqnum }
107
108 static struct irqaction tegra_lp2wake_irq[] = {
109         LP2_TIMER_IRQ_ACTION(0, INT_TMR3),
110 #ifdef CONFIG_SMP
111         LP2_TIMER_IRQ_ACTION(1, INT_TMR4),
112         LP2_TIMER_IRQ_ACTION(2, INT_TMR5),
113         LP2_TIMER_IRQ_ACTION(3, INT_TMR6),
114 #endif
115 };
116
117 #ifdef CONFIG_SMP
118 #define hard_smp_processor_id()                                         \
119         ({                                                              \
120                 unsigned int cpunum;                                    \
121                 __asm__("\n"                                            \
122                         "1:     mrc p15, 0, %0, c0, c0, 5\n"            \
123                         "       .pushsection \".alt.smp.init\", \"a\"\n"\
124                         "       .long   1b\n"                           \
125                         "       mov     %0, #0\n"                       \
126                         "       .popsection"                            \
127                         : "=r" (cpunum));                               \
128                 cpunum &= 0x0F;                                         \
129         })
130 #define cpu_number()    hard_smp_processor_id()
131 #else
132 #define cpu_number()    0
133 #endif
134
135 /*
136  * To sanity test LP2 timer interrupts for CPU 0-3, enable this flag and check
137  * /proc/interrupts for timer interrupts. CPUs 0-3 should have one interrupt
138  * counted against them for tmr_lp2wake_cpu<n>, where <n> is the CPU number.
139  */
140 #if TEST_LP2_WAKE_TIMERS
141 static void test_lp2_wake_timer(unsigned int cpu)
142 {
143         unsigned long cycles = 50000;
144         unsigned int base = lp2_wake_timers[cpu];
145         static bool tested[4] = {false, false, false, false};
146
147         /* Don't repeat the test process on hotplug restart. */
148         if (!tested[cpu]) {
149                 timer_writel(0, base + TIMER_PTV);
150                 if (cycles) {
151                         u32 reg = 0x80000000ul | min(0x1ffffffful, cycles);
152                         timer_writel(reg, base + TIMER_PTV);
153                         tested[cpu] = true;
154                 }
155         }
156 }
157 #else
158 static inline void test_lp2_wake_timer(unsigned int cpu) {}
159 #endif
160
161 static void tegra3_register_wake_timer(unsigned int cpu)
162 {
163         int ret;
164
165         ret = setup_irq(tegra_lp2wake_irq[cpu].irq, &tegra_lp2wake_irq[cpu]);
166         if (ret) {
167                 pr_err("Failed to register LP2 timer IRQ for CPU %d: "
168                         "irq=%d, ret=%d\n", cpu,
169                         tegra_lp2wake_irq[cpu].irq, ret);
170                 goto fail;
171         }
172
173 #ifdef CONFIG_SMP
174         ret = irq_set_affinity(tegra_lp2wake_irq[cpu].irq, cpumask_of(cpu));
175         if (ret) {
176                 pr_err("Failed to set affinity for LP2 timer IRQ to "
177                         "CPU %d: irq=%d, ret=%d\n", cpu,
178                         tegra_lp2wake_irq[cpu].irq, ret);
179                 goto fail;
180         }
181 #endif
182         test_lp2_wake_timer(cpu);
183         cpumask_set_cpu(cpu, &wake_timer_ready);
184         return;
185 fail:
186         tegra_lp2_in_idle(false);
187 }
188
189 #if defined(CONFIG_PM_SLEEP) && defined(CONFIG_HOTPLUG_CPU)
190 static void tegra3_unregister_wake_timer(unsigned int cpu)
191 {
192         cpumask_clear_cpu(cpu, &wake_timer_ready);
193 #ifdef CONFIG_SMP
194         /* Reassign the affinity of the wake IRQ to CPU 0. */
195         (void)irq_set_affinity(tegra_lp2wake_irq[cpu].irq, cpumask_of(0));
196 #endif
197
198         /* Dispose of this IRQ. */
199         remove_irq(tegra_lp2wake_irq[cpu].irq, &tegra_lp2wake_irq[cpu]);
200 }
201 #endif
202
203 void tegra3_lp2_set_trigger(unsigned long cycles)
204 {
205         int cpu = cpu_number();
206         int base;
207
208         base = lp2_wake_timers[cpu];
209         timer_writel(0, base + TIMER_PTV);
210         if (cycles) {
211                 u32 reg = 0x80000000ul | min(0x1ffffffful, cycles);
212                 timer_writel(reg, base + TIMER_PTV);
213         }
214 }
215 EXPORT_SYMBOL(tegra3_lp2_set_trigger);
216
217 unsigned long tegra3_lp2_timer_remain(void)
218 {
219         int cpu = cpu_number();
220
221         return timer_readl(lp2_wake_timers[cpu] + TIMER_PCR) & 0x1ffffffful;
222 }
223
224 int tegra3_is_lp2_timer_ready(unsigned int cpu)
225 {
226         return cpumask_test_cpu(cpu, &wake_timer_ready);
227 }
228 #endif
229
230 void __init tegra3_init_timer(u32 *offset, int *irq, unsigned long rate)
231 {
232         switch (rate) {
233         case 12000000:
234                 timer_writel(0x000b, TIMERUS_USEC_CFG);
235                 break;
236         case 13000000:
237                 timer_writel(0x000c, TIMERUS_USEC_CFG);
238                 break;
239         case 19200000:
240                 timer_writel(0x045f, TIMERUS_USEC_CFG);
241                 break;
242         case 26000000:
243                 timer_writel(0x0019, TIMERUS_USEC_CFG);
244                 break;
245         case 16800000:
246                 timer_writel(0x0453, TIMERUS_USEC_CFG);
247                 break;
248         case 38400000:
249                 timer_writel(0x04BF, TIMERUS_USEC_CFG);
250                 break;
251         case 48000000:
252                 timer_writel(0x002F, TIMERUS_USEC_CFG);
253                 break;
254         default:
255                 WARN(1, "Unknown clock rate");
256         }
257
258 #ifdef CONFIG_PM_SLEEP
259 #ifdef CONFIG_SMP
260         /* For T30.A01 use INT_TMR_SHARED instead of INT_TMR6 for CPU3. */
261         if ((tegra_chip_id == TEGRA30) &&
262                 (tegra_revision == TEGRA_REVISION_A01))
263                         tegra_lp2wake_irq[3].irq = INT_TMR_SHARED;
264 #endif
265
266         tegra3_register_wake_timer(0);
267 #endif
268
269         *offset = TIMER1_OFFSET;
270         *irq = INT_TMR1;
271 }
272
273 #if defined(CONFIG_PM_SLEEP) && defined(CONFIG_HOTPLUG_CPU)
274 static int hotplug_notify(struct notifier_block *self,
275                                       unsigned long action, void *cpu)
276 {
277         if (action == CPU_ONLINE)
278                 tegra3_register_wake_timer((unsigned int)cpu);
279         else if (action == CPU_DOWN_PREPARE)
280                 tegra3_unregister_wake_timer((unsigned int)cpu);
281
282         return NOTIFY_OK;
283 }
284
285 static struct notifier_block __cpuinitdata hotplug_notifier_block = {
286         .notifier_call = hotplug_notify,
287 };
288
289 static int __init hotplug_cpu_register(void)
290 {
291         return register_cpu_notifier(&hotplug_notifier_block);
292 }
293 early_initcall(hotplug_cpu_register);
294 #endif