unknown changes from android-tegra-nv-3.4
[linux-3.10.git] / arch / arm / mach-tegra / timer-t3.c
1 /*
2  * arch/arch/mach-tegra/timer-t3.c
3  *
4  * Copyright (c) 2011-2012, NVIDIA Corporation.
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License as published by
8  * the Free Software Foundation; either version 2 of the License, or
9  * (at your option) any later version.
10  *
11  * This program is distributed in the hope that it will be useful, but WITHOUT
12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
14  * more details.
15  *
16  * You should have received a copy of the GNU General Public License along
17  * with this program; if not, write to the Free Software Foundation, Inc.,
18  * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
19  */
20
21 #include <linux/init.h>
22 #include <linux/err.h>
23 #include <linux/sched.h>
24 #include <linux/time.h>
25 #include <linux/interrupt.h>
26 #include <linux/irq.h>
27 #include <linux/clockchips.h>
28 #include <linux/clocksource.h>
29 #include <linux/clk.h>
30 #include <linux/io.h>
31 #include <linux/smp.h>
32 #include <linux/syscore_ops.h>
33 #include <linux/cpu.h>
34 #include <linux/export.h>
35
36 #include <asm/mach/time.h>
37 #include <asm/localtimer.h>
38 #include <asm/sched_clock.h>
39
40 #include <mach/iomap.h>
41 #include <mach/irqs.h>
42 #include <mach/hardware.h>
43
44 #include "board.h"
45 #include "clock.h"
46 #include "cpuidle.h"
47 #include "timer.h"
48 #include "fuse.h"
49
50 #define TEST_LP2_WAKE_TIMERS    0
51
52 /*
53  * Timers usage:
54  * TMR1 - used as general CPU timer.
55  * TMR2 - used by AVP.
56  * TMR3 - used by CPU0 for LP2 wakeup.
57  * TMR4 - used by CPU1 for LP2 wakeup.
58  * TMR5 - used by CPU2 for LP2 wakeup.
59  * TMR6 - used by CPU3 for LP2 wakeup.
60  * TMR7 - Free.
61  * TMR8 - Free.
62  * TMR9 - Free.
63  * TMR10 - used as source for watchdog controller 0.
64 */
65
66 #define TIMER1_OFFSET (TEGRA_TMR1_BASE-TEGRA_TMR1_BASE)
67 #define TIMER2_OFFSET (TEGRA_TMR2_BASE-TEGRA_TMR1_BASE)
68 #define TIMER3_OFFSET (TEGRA_TMR3_BASE-TEGRA_TMR1_BASE)
69 #define TIMER4_OFFSET (TEGRA_TMR4_BASE-TEGRA_TMR1_BASE)
70 #define TIMER5_OFFSET (TEGRA_TMR5_BASE-TEGRA_TMR1_BASE)
71 #define TIMER6_OFFSET (TEGRA_TMR6_BASE-TEGRA_TMR1_BASE)
72
73 static void __iomem *timer_reg_base = IO_ADDRESS(TEGRA_TMR1_BASE);
74 static cpumask_t wake_timer_ready;
75 static cpumask_t wake_timer_canceled;
76
77 #define timer_writel(value, reg) \
78         __raw_writel(value, timer_reg_base + (reg))
79 #define timer_readl(reg) \
80         __raw_readl(timer_reg_base + (reg))
81
82
83 #ifdef CONFIG_PM_SLEEP
84 static u32 lp2_wake_timers[] = {
85         TIMER3_OFFSET,
86 #ifdef CONFIG_SMP
87         TIMER4_OFFSET,
88         TIMER5_OFFSET,
89         TIMER6_OFFSET,
90 #endif
91 };
92
93 static irqreturn_t tegra_lp2wake_interrupt(int irq, void *dev_id)
94 {
95         int cpu = (int)dev_id;
96         int base;
97
98         base = lp2_wake_timers[cpu];
99         timer_writel(1<<30, base + TIMER_PCR);
100         return IRQ_HANDLED;
101 }
102
103 #define LP2_TIMER_IRQ_ACTION(cpu, irqnum) {                     \
104         .name           = "tmr_lp2wake_cpu" __stringify(cpu),   \
105         .flags          = IRQF_DISABLED,                        \
106         .handler        = tegra_lp2wake_interrupt,              \
107         .dev_id         = (void*)cpu,                           \
108         .irq            = irqnum }
109
110 static struct irqaction tegra_lp2wake_irq[] = {
111         LP2_TIMER_IRQ_ACTION(0, INT_TMR3),
112 #ifdef CONFIG_SMP
113         LP2_TIMER_IRQ_ACTION(1, INT_TMR4),
114         LP2_TIMER_IRQ_ACTION(2, INT_TMR5),
115         LP2_TIMER_IRQ_ACTION(3, INT_TMR6),
116 #endif
117 };
118
119 #ifdef CONFIG_SMP
120 #define hard_smp_processor_id()                                         \
121         ({                                                              \
122                 unsigned int cpunum;                                    \
123                 __asm__("\n"                                            \
124                         "1:     mrc p15, 0, %0, c0, c0, 5\n"            \
125                         "       .pushsection \".alt.smp.init\", \"a\"\n"\
126                         "       .long   1b\n"                           \
127                         "       mov     %0, #0\n"                       \
128                         "       .popsection"                            \
129                         : "=r" (cpunum));                               \
130                 cpunum &= 0x0F;                                         \
131         })
132 #define cpu_number()    hard_smp_processor_id()
133 #else
134 #define cpu_number()    0
135 #endif
136
137 /*
138  * To sanity test LP2 timer interrupts for CPU 0-3, enable this flag and check
139  * /proc/interrupts for timer interrupts. CPUs 0-3 should have one interrupt
140  * counted against them for tmr_lp2wake_cpu<n>, where <n> is the CPU number.
141  */
142 #if TEST_LP2_WAKE_TIMERS
143 static void test_lp2_wake_timer(unsigned int cpu)
144 {
145         unsigned long cycles = 50000;
146         unsigned int base = lp2_wake_timers[cpu];
147         static bool tested[4] = {false, false, false, false};
148
149         /* Don't repeat the test process on hotplug restart. */
150         if (!tested[cpu]) {
151                 timer_writel(0, base + TIMER_PTV);
152                 if (cycles) {
153                         u32 reg = 0x80000000ul | min(0x1ffffffful, cycles);
154                         timer_writel(reg, base + TIMER_PTV);
155                         tested[cpu] = true;
156                 }
157         }
158 }
159 #else
160 static inline void test_lp2_wake_timer(unsigned int cpu) {}
161 #endif
162
163 static int tegra3_resume_wake_timer(unsigned int cpu)
164 {
165 #ifdef CONFIG_SMP
166         int ret = irq_set_affinity(tegra_lp2wake_irq[cpu].irq, cpumask_of(cpu));
167         if (ret) {
168                 pr_err("Failed to set affinity for LP2 timer IRQ to "
169                         "CPU %d: irq=%d, ret=%d\n", cpu,
170                         tegra_lp2wake_irq[cpu].irq, ret);
171                 return ret;
172         }
173 #endif
174         cpumask_set_cpu(cpu, &wake_timer_ready);
175         return 0;
176 }
177
178 static void tegra3_register_wake_timer(unsigned int cpu)
179 {
180         int ret;
181
182         ret = setup_irq(tegra_lp2wake_irq[cpu].irq, &tegra_lp2wake_irq[cpu]);
183         if (ret) {
184                 pr_err("Failed to register LP2 timer IRQ for CPU %d: "
185                         "irq=%d, ret=%d\n", cpu,
186                         tegra_lp2wake_irq[cpu].irq, ret);
187                 goto fail;
188         }
189
190         ret = tegra3_resume_wake_timer(cpu);
191         if (ret)
192                 goto fail;
193
194         test_lp2_wake_timer(cpu);
195         return;
196 fail:
197         tegra_lp2_in_idle(false);
198 }
199
200 #if defined(CONFIG_PM_SLEEP) && defined(CONFIG_HOTPLUG_CPU)
201 static void tegra3_suspend_wake_timer(unsigned int cpu)
202 {
203         cpumask_clear_cpu(cpu, &wake_timer_ready);
204 #ifdef CONFIG_SMP
205         /* Reassign the affinity of the wake IRQ to CPU 0. */
206         (void)irq_set_affinity(tegra_lp2wake_irq[cpu].irq, cpumask_of(0));
207 #endif
208 }
209
210 static void tegra3_unregister_wake_timer(unsigned int cpu)
211 {
212         tegra3_suspend_wake_timer(cpu);
213
214         /* Dispose of this IRQ. */
215         remove_irq(tegra_lp2wake_irq[cpu].irq, &tegra_lp2wake_irq[cpu]);
216 }
217 #endif
218
219 void tegra3_lp2_set_trigger(unsigned long cycles)
220 {
221         int cpu = cpu_number();
222         int base;
223
224         base = lp2_wake_timers[cpu];
225         timer_writel(0, base + TIMER_PTV);
226         if (cycles) {
227                 u32 reg = 0x80000000ul | min(0x1ffffffful, cycles);
228                 timer_writel(reg, base + TIMER_PTV);
229         }
230 }
231 EXPORT_SYMBOL(tegra3_lp2_set_trigger);
232
233 unsigned long tegra3_lp2_timer_remain(void)
234 {
235         int cpu = cpu_number();
236
237         if (cpumask_test_and_clear_cpu(cpu, &wake_timer_canceled))
238                 return -ETIME;
239
240         return timer_readl(lp2_wake_timers[cpu] + TIMER_PCR) & 0x1ffffffful;
241 }
242
243 int tegra3_is_lp2_timer_ready(unsigned int cpu)
244 {
245         return cpumask_test_cpu(cpu, &wake_timer_ready);
246 }
247
248 void tegra3_lp2_timer_cancel_secondary(void)
249 {
250         int cpu;
251         int base;
252
253         for (cpu = 1; cpu < ARRAY_SIZE(lp2_wake_timers); cpu++) {
254                 base = lp2_wake_timers[cpu];
255                 cpumask_set_cpu(cpu, &wake_timer_canceled);
256                 timer_writel(0, base + TIMER_PTV);
257                 timer_writel(1<<30, base + TIMER_PCR);
258         }
259 }
260 #endif
261
262 void __init tegra30_init_timer(void)
263 {
264 #ifdef CONFIG_PM_SLEEP
265 #ifdef CONFIG_SMP
266         /* For T30.A01 use INT_TMR_SHARED instead of INT_TMR6 for CPU3. */
267         if ((tegra_get_chipid() == TEGRA_CHIPID_TEGRA3) &&
268                 (tegra_revision == TEGRA_REVISION_A01))
269                         tegra_lp2wake_irq[3].irq = INT_TMR_SHARED;
270 #endif
271
272         tegra3_register_wake_timer(0);
273 #endif
274 }
275
276 #if defined(CONFIG_PM_SLEEP) && defined(CONFIG_HOTPLUG_CPU)
277 static int hotplug_notify(struct notifier_block *self,
278                                       unsigned long action, void *cpu)
279 {
280         switch (action) {
281         case CPU_ONLINE:
282                 tegra3_register_wake_timer((unsigned int)cpu);
283                 break;
284         case CPU_ONLINE_FROZEN:
285                 tegra3_resume_wake_timer((unsigned int)cpu);
286                 break;
287         case CPU_DOWN_PREPARE:
288                 tegra3_unregister_wake_timer((unsigned int)cpu);
289                 break;
290         case CPU_DOWN_PREPARE_FROZEN:
291                 tegra3_suspend_wake_timer((unsigned int)cpu);
292                 break;
293         default:
294                 break;
295         }
296
297         return NOTIFY_OK;
298 }
299
300 static struct notifier_block __cpuinitdata hotplug_notifier_block = {
301         .notifier_call = hotplug_notify,
302 };
303
304 static int __init hotplug_cpu_register(void)
305 {
306         return register_cpu_notifier(&hotplug_notifier_block);
307 }
308 early_initcall(hotplug_cpu_register);
309 #endif