ARM: tegra: powermon: Fix copyrights from GPLv3 to GPLv2
[linux-3.10.git] / arch / arm / mach-tegra / tegra3_emc.h
1 /*
2  * arch/arm/mach-tegra/tegra3_emc.h
3  *
4  * Copyright (C) 2011-2013, NVIDIA CORPORATION. All rights reserved.
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License as published by
8  * the Free Software Foundation; either version 2 of the License, or
9  * (at your option) any later version.
10  *
11  * This program is distributed in the hope that it will be useful, but WITHOUT
12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
14  * more details.
15  *
16  * You should have received a copy of the GNU General Public License along
17  * with this program; if not, write to the Free Software Foundation, Inc.,
18  * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
19  *
20  */
21
22 #ifndef _MACH_TEGRA_TEGRA3_EMC_H
23 #define _MACH_TEGRA_TEGRA3_EMC_H
24
25 #include "tegra_emc.h"
26
27 #define TEGRA_EMC_BRIDGE_RATE_MIN       300000000
28 #define TEGRA_EMC_BRIDGE_MVOLTS_MIN     1200
29
30 extern u8 tegra_emc_bw_efficiency_boost;
31
32 int tegra30_init_emc(void);
33
34 #define EMC_INTSTATUS                           0x0
35 #define EMC_INTSTATUS_CLKCHANGE_COMPLETE        (0x1 << 4)
36
37 #define EMC_DBG                                 0x8
38 #define EMC_DBG_WRITE_MUX_ACTIVE                (0x1 << 1)
39
40 #define EMC_CFG                                 0xc
41 #define EMC_CFG_PERIODIC_QRST                   (0x1 << 21)
42 #define EMC_CFG_DYN_SREF_ENABLE                 (0x1 << 28)
43 #define EMC_CFG_PWR_MASK                        (0xF << 28)
44
45 #define EMC_REFCTRL                             0x20
46 #define EMC_REFCTRL_DEV_SEL_SHIFT               0
47 #define EMC_REFCTRL_DEV_SEL_MASK                (0x3 << EMC_REFCTRL_DEV_SEL_SHIFT)
48 #define EMC_REFCTRL_ENABLE                      (0x1 << 31)
49 #define EMC_REFCTRL_ENABLE_ALL(num)             \
50         ((((num > 1) ? 0 : 2) << EMC_REFCTRL_DEV_SEL_SHIFT) \
51          | EMC_REFCTRL_ENABLE)
52 #define EMC_REFCTRL_DISABLE_ALL(num)            \
53         (((num > 1) ? 0 : 2) << EMC_REFCTRL_DEV_SEL_SHIFT)
54
55 #define EMC_TIMING_CONTROL                      0x28
56 #define EMC_RC                                  0x2c
57 #define EMC_RFC                                 0x30
58 #define EMC_RAS                                 0x34
59 #define EMC_RP                                  0x38
60 #define EMC_R2W                                 0x3c
61 #define EMC_W2R                                 0x40
62 #define EMC_R2P                                 0x44
63 #define EMC_W2P                                 0x48
64 #define EMC_RD_RCD                              0x4c
65 #define EMC_WR_RCD                              0x50
66 #define EMC_RRD                                 0x54
67 #define EMC_REXT                                0x58
68 #define EMC_WDV                                 0x5c
69 #define EMC_QUSE                                0x60
70 #define EMC_QRST                                0x64
71 #define EMC_QSAFE                               0x68
72 #define EMC_RDV                                 0x6c
73 #define EMC_REFRESH                             0x70
74 #define EMC_BURST_REFRESH_NUM                   0x74
75 #define EMC_PDEX2WR                             0x78
76 #define EMC_PDEX2RD                             0x7c
77 #define EMC_PCHG2PDEN                           0x80
78 #define EMC_ACT2PDEN                            0x84
79 #define EMC_AR2PDEN                             0x88
80 #define EMC_RW2PDEN                             0x8c
81 #define EMC_TXSR                                0x90
82 #define EMC_TCKE                                0x94
83 #define EMC_TFAW                                0x98
84 #define EMC_TRPAB                               0x9c
85 #define EMC_TCLKSTABLE                          0xa0
86 #define EMC_TCLKSTOP                            0xa4
87 #define EMC_TREFBW                              0xa8
88 #define EMC_QUSE_EXTRA                          0xac
89 #define EMC_ODT_WRITE                           0xb0
90 #define EMC_ODT_READ                            0xb4
91 #define EMC_WEXT                                0xb8
92 #define EMC_CTT                                 0xbc
93
94 #define EMC_MRS_WAIT_CNT                        0xc8
95 #define EMC_MRS_WAIT_CNT_SHORT_WAIT_SHIFT       0
96 #define EMC_MRS_WAIT_CNT_SHORT_WAIT_MASK        \
97         (0x3FF << EMC_MRS_WAIT_CNT_SHORT_WAIT_SHIFT)
98 #define EMC_MRS_WAIT_CNT_LONG_WAIT_SHIFT        16
99 #define EMC_MRS_WAIT_CNT_LONG_WAIT_MASK         \
100         (0x3FF << EMC_MRS_WAIT_CNT_LONG_WAIT_SHIFT)
101
102 #define EMC_MRS                                 0xcc
103 #define EMC_MODE_SET_DLL_RESET                  (0x1 << 8)
104 #define EMC_MODE_SET_LONG_CNT                   (0x1 << 26)
105 #define EMC_EMRS                                0xd0
106 #define EMC_REF                                 0xd4
107 #define EMC_REF_FORCE_CMD                       1
108
109 #define EMC_SELF_REF                            0xe0
110 #define EMC_SELF_REF_CMD_ENABLED                (0x1 << 0)
111 #define EMC_SELF_REF_DEV_SEL_SHIFT              30
112 #define EMC_SELF_REF_DEV_SEL_MASK               (0x3 << EMC_SELF_REF_DEV_SEL_SHIFT)
113 enum {
114         DRAM_DEV_SEL_ALL = 0,
115         DRAM_DEV_SEL_0   = (2 << EMC_SELF_REF_DEV_SEL_SHIFT),
116         DRAM_DEV_SEL_1   = (1 << EMC_SELF_REF_DEV_SEL_SHIFT),
117 };
118 #define DRAM_BROADCAST(num)                     \
119         (((num) > 1) ? DRAM_DEV_SEL_ALL : DRAM_DEV_SEL_0)
120
121 #define EMC_MRW                                 0xe8
122 #define EMC_MRR                                 0xec
123 #define EMC_MRR_MA_SHIFT                        16
124 #define EMC_MRR_MA_MASK                         (0xFF << EMC_MRR_MA_SHIFT)
125 #define EMC_MRR_DATA_MASK                       ((0x1 << EMC_MRR_MA_SHIFT) - 1)
126 #define LPDDR2_MR4_TEMP_SHIFT                   0
127 #define LPDDR2_MR4_TEMP_MASK                    (0x7 << LPDDR2_MR4_TEMP_SHIFT)
128
129 #define EMC_XM2DQSPADCTRL3                      0xf8
130 #define EMC_XM2DQSPADCTRL3_VREF_ENABLE          (0x1 << 5)
131 #define EMC_FBIO_SPARE                          0x100
132
133 #define EMC_FBIO_CFG5                           0x104
134 #define EMC_CFG5_TYPE_SHIFT                     0x0
135 #define EMC_CFG5_TYPE_MASK                      (0x3 << EMC_CFG5_TYPE_SHIFT)
136 enum {
137         DRAM_TYPE_DDR3   = 0,
138         DRAM_TYPE_LPDDR2 = 2,
139 };
140 #define EMC_CFG5_QUSE_MODE_SHIFT                13
141 #define EMC_CFG5_QUSE_MODE_MASK                 (0x7 << EMC_CFG5_QUSE_MODE_SHIFT)
142 enum {
143         EMC_CFG5_QUSE_MODE_NORMAL = 0,
144         EMC_CFG5_QUSE_MODE_ALWAYS_ON,
145         EMC_CFG5_QUSE_MODE_INTERNAL_LPBK,
146         EMC_CFG5_QUSE_MODE_PULSE_INTERN,
147         EMC_CFG5_QUSE_MODE_PULSE_EXTERN,
148 };
149
150 #define EMC_FBIO_CFG6                           0x114
151 #define EMC_CFG_RSV                             0x120
152 #define EMC_AUTO_CAL_CONFIG                     0x2a4
153 #define EMC_AUTO_CAL_INTERVAL                   0x2a8
154 #define EMC_AUTO_CAL_STATUS                     0x2ac
155 #define EMC_AUTO_CAL_STATUS_ACTIVE              (0x1 << 31)
156 #define EMC_STATUS                              0x2b4
157 #define EMC_STATUS_TIMING_UPDATE_STALLED        (0x1 << 23)
158 #define EMC_STATUS_MRR_DIVLD                    (0x1 << 20)
159
160 #define EMC_CFG_2                               0x2b8
161 #define EMC_CFG_2_MODE_SHIFT                    0
162 #define EMC_CFG_2_MODE_MASK                     (0x7 << EMC_CFG_2_MODE_SHIFT)
163 #define EMC_CFG_2_SREF_MODE                     0x1
164 #define EMC_CFG_2_PD_MODE                       0x3
165
166 #define EMC_CFG_DIG_DLL                         0x2bc
167 #define EMC_CFG_DIG_DLL_PERIOD                  0x2c0
168 #define EMC_CTT_DURATION                        0x2d8
169 #define EMC_CTT_TERM_CTRL                       0x2dc
170 #define EMC_ZCAL_INTERVAL                       0x2e0
171 #define EMC_ZCAL_WAIT_CNT                       0x2e4
172
173 #define EMC_ZQ_CAL                              0x2ec
174 #define EMC_ZQ_CAL_CMD                          (0x1 << 0)
175 #define EMC_ZQ_CAL_LONG                         (0x1 << 4)
176 #define EMC_ZQ_CAL_LONG_CMD_DEV0                \
177         (DRAM_DEV_SEL_0 | EMC_ZQ_CAL_LONG | EMC_ZQ_CAL_CMD)
178 #define EMC_ZQ_CAL_LONG_CMD_DEV1                \
179         (DRAM_DEV_SEL_1 | EMC_ZQ_CAL_LONG | EMC_ZQ_CAL_CMD)
180
181 #define EMC_XM2CMDPADCTRL                       0x2f0
182 #define EMC_XM2DQSPADCTRL2                      0x2fc
183 #define EMC_XM2DQSPADCTRL2_VREF_ENABLE          (0x1 << 5)
184 #define EMC_XM2DQPADCTRL2                       0x304
185 #define EMC_XM2CLKPADCTRL                       0x308
186 #define EMC_XM2COMPPADCTRL                      0x30c
187 #define EMC_XM2COMPPADCTRL_VREF_CAL_ENABLE      (0x1 << 10)
188 #define EMC_XM2VTTGENPADCTRL                    0x310
189 #define EMC_XM2VTTGENPADCTRL2                   0x314
190 #define EMC_XM2QUSEPADCTRL                      0x318
191 #define EMC_XM2QUSEPADCTRL_IVREF_ENABLE         (0x1 << 4)
192 #define EMC_DLL_XFORM_DQS0                      0x328
193 #define EMC_DLL_XFORM_DQS1                      0x32c
194 #define EMC_DLL_XFORM_DQS2                      0x330
195 #define EMC_DLL_XFORM_DQS3                      0x334
196 #define EMC_DLL_XFORM_DQS4                      0x338
197 #define EMC_DLL_XFORM_DQS5                      0x33c
198 #define EMC_DLL_XFORM_DQS6                      0x340
199 #define EMC_DLL_XFORM_DQS7                      0x344
200 #define EMC_DLL_XFORM_QUSE0                     0x348
201 #define EMC_DLL_XFORM_QUSE1                     0x34c
202 #define EMC_DLL_XFORM_QUSE2                     0x350
203 #define EMC_DLL_XFORM_QUSE3                     0x354
204 #define EMC_DLL_XFORM_QUSE4                     0x358
205 #define EMC_DLL_XFORM_QUSE5                     0x35c
206 #define EMC_DLL_XFORM_QUSE6                     0x360
207 #define EMC_DLL_XFORM_QUSE7                     0x364
208 #define EMC_DLL_XFORM_DQ0                       0x368
209 #define EMC_DLL_XFORM_DQ1                       0x36c
210 #define EMC_DLL_XFORM_DQ2                       0x370
211 #define EMC_DLL_XFORM_DQ3                       0x374
212 #define EMC_DLI_TRIM_TXDQS0                     0x3a8
213 #define EMC_DLI_TRIM_TXDQS1                     0x3ac
214 #define EMC_DLI_TRIM_TXDQS2                     0x3b0
215 #define EMC_DLI_TRIM_TXDQS3                     0x3b4
216 #define EMC_DLI_TRIM_TXDQS4                     0x3b8
217 #define EMC_DLI_TRIM_TXDQS5                     0x3bc
218 #define EMC_DLI_TRIM_TXDQS6                     0x3c0
219 #define EMC_DLI_TRIM_TXDQS7                     0x3c4
220 #define EMC_STALL_BEFORE_CLKCHANGE              0x3c8
221 #define EMC_STALL_AFTER_CLKCHANGE               0x3cc
222 #define EMC_UNSTALL_RW_AFTER_CLKCHANGE          0x3d0
223 #define EMC_SEL_DPD_CTRL                        0x3d8
224 #define EMC_SEL_DPD_CTRL_QUSE_DPD_ENABLE        (0x1 << 9)
225 #define EMC_PRE_REFRESH_REQ_CNT                 0x3dc
226 #define EMC_DYN_SELF_REF_CONTROL                0x3e0
227 #define EMC_TXSRDLL                             0x3e4
228
229 #define MC_EMEM_ADR_CFG                         0x54
230 #define MC_EMEM_ARB_CFG                         0x90
231 #define MC_EMEM_ARB_CFG_CYCLE_MASK              0x1ff
232 #define MC_EMEM_ARB_CFG_EXTRA_TICK_SHIFT        16
233 #define MC_EMEM_ARB_CFG_EXTRA_TICK_MASK         \
234         (0x1f << MC_EMEM_ARB_CFG_EXTRA_TICK_SHIFT)
235 #define MC_EMEM_ARB_OUTSTANDING_REQ             0x94
236 #define MC_EMEM_ARB_OUTSTANDING_REQ_MAX_SHIFT   0
237 #define MC_EMEM_ARB_OUTSTANDING_REQ_MAX_MASK    \
238         (0x1FF << MC_EMEM_ARB_OUTSTANDING_REQ_MAX_SHIFT)
239 #define MC_EMEM_ARB_OUTSTANDING_REQ_HOLDOFF_OVERRIDE    (0x1 << 30)
240 #define MC_EMEM_ARB_OUTSTANDING_REQ_LIMIT_ENABLE        (0x1 << 31)
241 #define MC_EMEM_ARB_TIMING_RCD                  0x98
242 #define MC_EMEM_ARB_TIMING_RP                   0x9c
243 #define MC_EMEM_ARB_TIMING_RC                   0xa0
244 #define MC_EMEM_ARB_TIMING_RAS                  0xa4
245 #define MC_EMEM_ARB_TIMING_FAW                  0xa8
246 #define MC_EMEM_ARB_TIMING_RRD                  0xac
247 #define MC_EMEM_ARB_TIMING_RAP2PRE              0xb0
248 #define MC_EMEM_ARB_TIMING_WAP2PRE              0xb4
249 #define MC_EMEM_ARB_TIMING_R2R                  0xb8
250 #define MC_EMEM_ARB_TIMING_W2W                  0xbc
251 #define MC_EMEM_ARB_TIMING_R2W                  0xc0
252 #define MC_EMEM_ARB_TIMING_W2R                  0xc4
253 #define MC_EMEM_ARB_DA_TURNS                    0xd0
254 #define MC_EMEM_ARB_DA_COVERS                   0xd4
255 #define MC_EMEM_ARB_MISC0                       0xd8
256 #define MC_EMEM_ARB_MISC0_EMC_SAME_FREQ         (0x1 << 27)
257 #define MC_EMEM_ARB_MISC1                       0xdc
258 #define MC_EMEM_ARB_RING1_THROTTLE              0xe0
259 #define MC_EMEM_ARB_RING3_THROTTLE              0xe4
260 #define MC_EMEM_ARB_OVERRIDE                    0xe8
261 #define MC_EMEM_ARB_OVERRIDE_EACK_MASK          (0x3 << 0)
262 #define MC_TIMING_CONTROL                       0xfc
263 #define MC_VE_EXTRA_SNAP_LEVELS                 0x2d8
264 #define MC_LATENCY_ALLOWANCE_AFI                0x2e0
265 #define MC_LATENCY_ALLOWANCE_AVPC               0x2e4
266 #define MC_LATENCY_ALLOWANCE_DC_0               0x2e8
267 #define MC_LATENCY_ALLOWANCE_DC_1               0x2ec
268 #define MC_LATENCY_ALLOWANCE_DC_2               0x2f0
269 #define MC_LATENCY_ALLOWANCE_DCB_0              0x2f4
270 #define MC_LATENCY_ALLOWANCE_DCB_1              0x2f8
271 #define MC_LATENCY_ALLOWANCE_DCB_2              0x2fc
272 #define MC_LATENCY_ALLOWANCE_EPP_0              0x300
273 #define MC_LATENCY_ALLOWANCE_EPP_1              0x304
274 #define MC_LATENCY_ALLOWANCE_G2_0               0x308
275 #define MC_LATENCY_ALLOWANCE_G2_1               0x30c
276 #define MC_LATENCY_ALLOWANCE_HC_0               0x310
277 #define MC_LATENCY_ALLOWANCE_HC_1               0x314
278 #define MC_LATENCY_ALLOWANCE_HDA                0x318
279 #define MC_LATENCY_ALLOWANCE_ISP                0x31c
280 #define MC_LATENCY_ALLOWANCE_MPCORE             0x320
281 #define MC_LATENCY_ALLOWANCE_MPCORELP           0x324
282 #define MC_LATENCY_ALLOWANCE_MPE_0              0x328
283 #define MC_LATENCY_ALLOWANCE_MPE_1              0x32c
284 #define MC_LATENCY_ALLOWANCE_MPE_2              0x330
285 #define MC_LATENCY_ALLOWANCE_NV_0               0x334
286 #define MC_LATENCY_ALLOWANCE_NV_1               0x338
287 #define MC_LATENCY_ALLOWANCE_NV2_0              0x33c
288 #define MC_LATENCY_ALLOWANCE_NV2_1              0x340
289 #define MC_LATENCY_ALLOWANCE_PPCS_0             0x344
290 #define MC_LATENCY_ALLOWANCE_PPCS_1             0x348
291 #define MC_LATENCY_ALLOWANCE_PTC                0x34c
292 #define MC_LATENCY_ALLOWANCE_SATA               0x350
293 #define MC_LATENCY_ALLOWANCE_VDE_0              0x354
294 #define MC_LATENCY_ALLOWANCE_VDE_1              0x358
295 #define MC_LATENCY_ALLOWANCE_VDE_2              0x35c
296 #define MC_LATENCY_ALLOWANCE_VDE_3              0x360
297 #define MC_LATENCY_ALLOWANCE_VI_0               0x364
298 #define MC_LATENCY_ALLOWANCE_VI_1               0x368
299 #define MC_LATENCY_ALLOWANCE_VI_2               0x36c
300
301 #define MC_RESERVED_RSV                         0x3fc
302
303 #endif