085a1dc98b96cf75897aeee23ca6b2c83c7b3a78
[linux-3.10.git] / arch / arm / mach-tegra / tegra3_emc.h
1 /*
2  * arch/arm/mach-tegra/tegra3_emc.h
3  *
4  * Copyright (C) 2011 NVIDIA Corporation
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License as published by
8  * the Free Software Foundation; either version 2 of the License, or
9  * (at your option) any later version.
10  *
11  * This program is distributed in the hope that it will be useful, but WITHOUT
12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
14  * more details.
15  *
16  * You should have received a copy of the GNU General Public License along
17  * with this program; if not, write to the Free Software Foundation, Inc.,
18  * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
19  *
20  */
21
22 #ifndef _MACH_TEGRA_TEGRA3_EMC_H
23 #define _MACH_TEGRA_TEGRA3_EMC_H
24
25 #define EMC_INTSTATUS                           0x0
26 #define EMC_INTSTATUS_CLKCHANGE_COMPLETE        (0x1 << 4)
27
28 #define EMC_DBG                                 0x8
29 #define EMC_DBG_WRITE_MUX_ACTIVE                (0x1 << 1)
30
31 #define EMC_CFG                                 0xc
32 #define EMC_CFG_PERIODIC_QRST                   (0x1 << 21)
33 #define EMC_CFG_DYN_SREF_ENABLE                 (0x1 << 28)
34 #define EMC_CFG_PWR_MASK                        (0xF << 28)
35
36 #define EMC_REFCTRL                             0x20
37 #define EMC_REFCTRL_DEV_SEL_SHIFT               0
38 #define EMC_REFCTRL_DEV_SEL_MASK                (0x3 << EMC_REFCTRL_DEV_SEL_SHIFT)
39 #define EMC_REFCTRL_ENABLE                      (0x1 << 31)
40 #define EMC_REFCTRL_ENABLE_ALL(num)             \
41         ((((num > 1) ? 0 : 2) << EMC_REFCTRL_DEV_SEL_SHIFT) \
42          | EMC_REFCTRL_ENABLE)
43 #define EMC_REFCTRL_DISABLE_ALL(num)            \
44         (((num > 1) ? 0 : 2) << EMC_REFCTRL_DEV_SEL_SHIFT)
45
46 #define EMC_TIMING_CONTROL                      0x28
47 #define EMC_RC                                  0x2c
48 #define EMC_RFC                                 0x30
49 #define EMC_RAS                                 0x34
50 #define EMC_RP                                  0x38
51 #define EMC_R2W                                 0x3c
52 #define EMC_W2R                                 0x40
53 #define EMC_R2P                                 0x44
54 #define EMC_W2P                                 0x48
55 #define EMC_RD_RCD                              0x4c
56 #define EMC_WR_RCD                              0x50
57 #define EMC_RRD                                 0x54
58 #define EMC_REXT                                0x58
59 #define EMC_WDV                                 0x5c
60 #define EMC_QUSE                                0x60
61 #define EMC_QRST                                0x64
62 #define EMC_QSAFE                               0x68
63 #define EMC_RDV                                 0x6c
64 #define EMC_REFRESH                             0x70
65 #define EMC_BURST_REFRESH_NUM                   0x74
66 #define EMC_PDEX2WR                             0x78
67 #define EMC_PDEX2RD                             0x7c
68 #define EMC_PCHG2PDEN                           0x80
69 #define EMC_ACT2PDEN                            0x84
70 #define EMC_AR2PDEN                             0x88
71 #define EMC_RW2PDEN                             0x8c
72 #define EMC_TXSR                                0x90
73 #define EMC_TCKE                                0x94
74 #define EMC_TFAW                                0x98
75 #define EMC_TRPAB                               0x9c
76 #define EMC_TCLKSTABLE                          0xa0
77 #define EMC_TCLKSTOP                            0xa4
78 #define EMC_TREFBW                              0xa8
79 #define EMC_QUSE_EXTRA                          0xac
80 #define EMC_ODT_WRITE                           0xb0
81 #define EMC_ODT_READ                            0xb4
82 #define EMC_WEXT                                0xb8
83 #define EMC_CTT                                 0xbc
84
85 #define EMC_MRS_WAIT_CNT                        0xc8
86 #define EMC_MRS_WAIT_CNT_SHORT_WAIT_SHIFT       0
87 #define EMC_MRS_WAIT_CNT_SHORT_WAIT_MASK        \
88         (0x3FF << EMC_MRS_WAIT_CNT_SHORT_WAIT_SHIFT)
89 #define EMC_MRS_WAIT_CNT_LONG_WAIT_SHIFT        16
90 #define EMC_MRS_WAIT_CNT_LONG_WAIT_MASK         \
91         (0x3FF << EMC_MRS_WAIT_CNT_LONG_WAIT_SHIFT)
92
93 #define EMC_MRS                                 0xcc
94 #define EMC_MODE_SET_DLL_RESET                  (0x1 << 8)
95 #define EMC_MODE_SET_LONG_CNT                   (0x1 << 26)
96 #define EMC_EMRS                                0xd0
97
98 #define EMC_SELF_REF                            0xe0
99 #define EMC_SELF_REF_CMD_ENABLED                (0x1 << 0)
100 #define EMC_SELF_REF_DEV_SEL_SHIFT              30
101 #define EMC_SELF_REF_DEV_SEL_MASK               (0x3 << EMC_SELF_REF_DEV_SEL_SHIFT)
102 enum {
103         DRAM_DEV_SEL_ALL = 0,
104         DRAM_DEV_SEL_0   = (2 << EMC_SELF_REF_DEV_SEL_SHIFT),
105         DRAM_DEV_SEL_1   = (1 << EMC_SELF_REF_DEV_SEL_SHIFT),
106 };
107 #define DRAM_BROADCAST(num)                     \
108         (((num) > 1) ? DRAM_DEV_SEL_ALL : DRAM_DEV_SEL_0)
109
110 #define EMC_MRW                                 0xe8
111 #define EMC_MRR                                 0xec
112 #define EMC_XM2DQSPADCTRL3                      0xf8
113 #define EMC_XM2DQSPADCTRL3_VREF_ENABLE          (0x1 << 5)
114
115 #define EMC_FBIO_CFG5                           0x104
116 #define EMC_CFG5_TYPE_SHIFT                     0x0
117 #define EMC_CFG5_TYPE_MASK                      (0x3 << EMC_CFG5_TYPE_SHIFT)
118 enum {
119         DRAM_TYPE_DDR3   = 0,
120         DRAM_TYPE_LPDDR2 = 2,
121 };
122 #define EMC_CFG5_QUSE_MODE_SHIFT                13
123 #define EMC_CFG5_QUSE_MODE_MASK                 (0x7 << EMC_CFG5_QUSE_MODE_SHIFT)
124 enum {
125         EMC_CFG5_QUSE_MODE_NORMAL = 0,
126         EMC_CFG5_QUSE_MODE_ALWAYS_ON,
127         EMC_CFG5_QUSE_MODE_INTERNAL_LPBK,
128         EMC_CFG5_QUSE_MODE_PULSE_INTERN,
129         EMC_CFG5_QUSE_MODE_PULSE_EXTERN,
130 };
131
132 #define EMC_FBIO_CFG6                           0x114
133 #define EMC_AUTO_CAL_CONFIG                     0x2a4
134 #define EMC_AUTO_CAL_INTERVAL                   0x2a8
135 #define EMC_AUTO_CAL_STATUS                     0x2ac
136 #define EMC_AUTO_CAL_STATUS_ACTIVE              (0x1 << 31)
137 #define EMC_STATUS                              0x2b4
138 #define EMC_STATUS_TIMING_UPDATE_STALLED        (0x1 << 23)
139
140 #define EMC_CFG_2                               0x2b8
141 #define EMC_CFG_2_MODE_SHIFT                    0
142 #define EMC_CFG_2_MODE_MASK                     (0x7 << EMC_CFG_2_MODE_SHIFT)
143 #define EMC_CFG_2_SREF_MODE                     0x1
144 #define EMC_CFG_2_PD_MODE                       0x3
145
146 #define EMC_CFG_DIG_DLL                         0x2bc
147 #define EMC_CFG_DIG_DLL_PERIOD                  0x2c0
148 #define EMC_CTT_DURATION                        0x2d8
149 #define EMC_CTT_TERM_CTRL                       0x2dc
150 #define EMC_ZCAL_INTERVAL                       0x2e0
151 #define EMC_ZCAL_WAIT_CNT                       0x2e4
152
153 #define EMC_ZQ_CAL                              0x2ec
154 #define EMC_ZQ_CAL_CMD                          (0x1 << 0)
155 #define EMC_ZQ_CAL_LONG                         (0x1 << 4)
156 #define EMC_ZQ_CAL_LONG_CMD_DEV0                \
157         (DRAM_DEV_SEL_0 | EMC_ZQ_CAL_LONG | EMC_ZQ_CAL_CMD)
158 #define EMC_ZQ_CAL_LONG_CMD_DEV1                \
159         (DRAM_DEV_SEL_1 | EMC_ZQ_CAL_LONG | EMC_ZQ_CAL_CMD)
160
161 #define EMC_XM2CMDPADCTRL                       0x2f0
162 #define EMC_XM2DQSPADCTRL2                      0x2fc
163 #define EMC_XM2DQSPADCTRL2_VREF_ENABLE          (0x1 << 5)
164 #define EMC_XM2DQPADCTRL2                       0x304
165 #define EMC_XM2CLKPADCTRL                       0x308
166 #define EMC_XM2COMPPADCTRL                      0x30c
167 #define EMC_XM2COMPPADCTRL_VREF_CAL_ENABLE      (0x1 << 10)
168 #define EMC_XM2VTTGENPADCTRL                    0x310
169 #define EMC_XM2VTTGENPADCTRL2                   0x314
170 #define EMC_XM2QUSEPADCTRL                      0x318
171 #define EMC_XM2QUSEPADCTRL_IVREF_ENABLE         (0x1 << 4)
172 #define EMC_DLL_XFORM_DQS0                      0x328
173 #define EMC_DLL_XFORM_DQS1                      0x32c
174 #define EMC_DLL_XFORM_DQS2                      0x330
175 #define EMC_DLL_XFORM_DQS3                      0x334
176 #define EMC_DLL_XFORM_DQS4                      0x338
177 #define EMC_DLL_XFORM_DQS5                      0x33c
178 #define EMC_DLL_XFORM_DQS6                      0x340
179 #define EMC_DLL_XFORM_DQS7                      0x344
180 #define EMC_DLL_XFORM_QUSE0                     0x348
181 #define EMC_DLL_XFORM_QUSE1                     0x34c
182 #define EMC_DLL_XFORM_QUSE2                     0x350
183 #define EMC_DLL_XFORM_QUSE3                     0x354
184 #define EMC_DLL_XFORM_QUSE4                     0x358
185 #define EMC_DLL_XFORM_QUSE5                     0x35c
186 #define EMC_DLL_XFORM_QUSE6                     0x360
187 #define EMC_DLL_XFORM_QUSE7                     0x364
188 #define EMC_DLL_XFORM_DQ0                       0x368
189 #define EMC_DLL_XFORM_DQ1                       0x36c
190 #define EMC_DLL_XFORM_DQ2                       0x370
191 #define EMC_DLL_XFORM_DQ3                       0x374
192 #define EMC_DLI_TRIM_TXDQS0                     0x3a8
193 #define EMC_DLI_TRIM_TXDQS1                     0x3ac
194 #define EMC_DLI_TRIM_TXDQS2                     0x3b0
195 #define EMC_DLI_TRIM_TXDQS3                     0x3b4
196 #define EMC_DLI_TRIM_TXDQS4                     0x3b8
197 #define EMC_DLI_TRIM_TXDQS5                     0x3bc
198 #define EMC_DLI_TRIM_TXDQS6                     0x3c0
199 #define EMC_DLI_TRIM_TXDQS7                     0x3c4
200 #define EMC_STALL_BEFORE_CLKCHANGE              0x3c8
201 #define EMC_STALL_AFTER_CLKCHANGE               0x3cc
202 #define EMC_UNSTALL_RW_AFTER_CLKCHANGE          0x3d0
203 #define EMC_SEL_DPD_CTRL                        0x3d8
204 #define EMC_SEL_DPD_CTRL_QUSE_DPD_ENABLE        (0x1 << 9)
205 #define EMC_PRE_REFRESH_REQ_CNT                 0x3dc
206 #define EMC_DYN_SELF_REF_CONTROL                0x3e0
207 #define EMC_TXSRDLL                             0x3e4
208
209 #define MC_EMEM_ADR_CFG                         0x54
210 #define MC_EMEM_ARB_CFG                         0x90
211 #define MC_EMEM_ARB_OUTSTANDING_REQ             0x94
212 #define MC_EMEM_ARB_TIMING_RCD                  0x98
213 #define MC_EMEM_ARB_TIMING_RP                   0x9c
214 #define MC_EMEM_ARB_TIMING_RC                   0xa0
215 #define MC_EMEM_ARB_TIMING_RAS                  0xa4
216 #define MC_EMEM_ARB_TIMING_FAW                  0xa8
217 #define MC_EMEM_ARB_TIMING_RRD                  0xac
218 #define MC_EMEM_ARB_TIMING_RAP2PRE              0xb0
219 #define MC_EMEM_ARB_TIMING_WAP2PRE              0xb4
220 #define MC_EMEM_ARB_TIMING_R2R                  0xb8
221 #define MC_EMEM_ARB_TIMING_W2W                  0xbc
222 #define MC_EMEM_ARB_TIMING_R2W                  0xc0
223 #define MC_EMEM_ARB_TIMING_W2R                  0xc4
224 #define MC_EMEM_ARB_DA_TURNS                    0xd0
225 #define MC_EMEM_ARB_DA_COVERS                   0xd4
226 #define MC_EMEM_ARB_MISC0                       0xd8
227 #define MC_EMEM_ARB_MISC0_EMC_SAME_FREQ         (0x1 << 27)
228 #define MC_EMEM_ARB_RING1_THROTTLE              0xe0
229 #define MC_EMEM_ARB_OVERRIDE                    0xe8
230 #define MC_RESERVED_RSV                         0x3fc
231
232 #endif