ARM: tegra: loki: fix build error due to warning
[linux-3.10.git] / arch / arm / mach-tegra / tegra14_speedo.c
1 /*
2  * arch/arm/mach-tegra/tegra14_speedo.c
3  *
4  * Copyright (C) 2013 NVIDIA Corporation. All rights reserved.
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License as published by
8  * the Free Software Foundation; version 2 of the License.
9  *
10  * This program is distributed in the hope that it will be useful, but WITHOUT
11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13  * more details.
14  *
15  * You should have received a copy of the GNU General Public License along
16  * with this program; if not, write to the Free Software Foundation, Inc.,
17  * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
18  *
19  */
20
21 #include <linux/kernel.h>
22 #include <linux/io.h>
23 #include <linux/err.h>
24 #include <linux/bug.h>
25
26 #include <mach/tegra_fuse.h>
27 #include <linux/tegra-soc.h>
28 #include <linux/module.h>
29 #include <linux/moduleparam.h>
30
31 #include "fuse.h"
32 #include "iomap.h"
33
34 #define CPU_PROCESS_CORNERS_NUM         2
35 #define CORE_PROCESS_CORNERS_NUM        2
36 #define CPU_IDDQ_BITS                   13
37
38 #define TEGRA148_CPU_SPEEDO 2109
39 #define FUSE_CPU_IDDQ 0x118 /*FIXME: update T148 register*/
40 #define FUSE_CPU_SPEEDO_0 0x114
41 #define FUSE_CORE_SPEEDO_0 0x134
42 #define FUSE_SPARE_BIT_62_0 0x398
43 static int threshold_index;
44 static int cpu_process_id;
45 static int core_process_id;
46 static int cpu_speedo_id;
47 static int cpu_speedo_value;
48 static int soc_speedo_id;
49 static int package_id;
50 static int cpu_iddq_value;
51 static int core_speedo_value;
52
53 static int enable_app_profiles;
54
55 static const u32 cpu_process_speedos[][CPU_PROCESS_CORNERS_NUM] = {
56 /* proc_id  0,     1 */
57         {2070,     UINT_MAX}, /* [0]: threshold_index 0 */
58         {0,        UINT_MAX}, /* [1]: threshold_index 1 */
59 };
60
61 static const u32 core_process_speedos[][CORE_PROCESS_CORNERS_NUM] = {
62 /* proc_id  0,  1 */
63         {1295,  UINT_MAX}, /* [0]: threshold_index 0 */
64         {0,     UINT_MAX}, /* [1]: threshold_index 0 */
65 };
66
67 static void rev_sku_to_speedo_ids(int rev, int sku)
68 {
69
70         switch (sku) {
71         case 0x00: /* Eng */
72         case 0x07:
73                 cpu_speedo_id = 0;
74                 soc_speedo_id = 0;
75                 threshold_index = 0;
76                 break;
77
78         case 0x03:
79         case 0x83:
80                 cpu_speedo_id = 1;
81                 soc_speedo_id = 1;
82                 threshold_index = 1;
83                 break;
84
85         default:
86                 pr_err("Tegra14 Unknown SKU %d\n", sku);
87                 cpu_speedo_id = 0;
88                 soc_speedo_id = 0;
89                 threshold_index = 0;
90                 break;
91         }
92 }
93
94 void tegra_init_speedo_data(void)
95 {
96         int i;
97         cpu_speedo_value = 1024 + tegra_fuse_readl(FUSE_CPU_SPEEDO_0);
98         core_speedo_value = tegra_fuse_readl(FUSE_CORE_SPEEDO_0);
99
100         rev_sku_to_speedo_ids(tegra_revision, tegra_sku_id);
101
102         for (i = 0; i < CPU_PROCESS_CORNERS_NUM; i++) {
103                 if (cpu_speedo_value <
104                         cpu_process_speedos[threshold_index][i]) {
105                         break;
106                 }
107         }
108         cpu_process_id = i;
109
110         cpu_iddq_value = 0;
111         for (i = 0; i < CPU_IDDQ_BITS; i++) {
112                 cpu_iddq_value = (cpu_iddq_value << 1) +
113                 tegra_fuse_readl(FUSE_SPARE_BIT_62_0 - 4*i);
114         }
115
116         if (!cpu_iddq_value)
117                 cpu_iddq_value = tegra_fuse_readl(FUSE_CPU_IDDQ);
118
119
120         for (i = 0; i < CORE_PROCESS_CORNERS_NUM; i++) {
121                 if (core_speedo_value <
122                         core_process_speedos[threshold_index][i]) {
123                         break;
124                 }
125         }
126
127         core_process_id = i;
128
129         pr_info("Tegra14: CPU Speedo %d, Soc Speedo %d",
130                 cpu_speedo_value, core_speedo_value);
131         pr_info("Tegra14: CPU Speedo ID %d, Soc Speedo ID %d",
132                 cpu_speedo_id, soc_speedo_id);
133 }
134
135 int tegra_cpu_process_id(void)
136 {
137         return cpu_process_id;
138 }
139
140 int tegra_core_process_id(void)
141 {
142         return core_process_id;
143 }
144
145 int tegra_cpu_speedo_id(void)
146 {
147         return cpu_speedo_id;
148 }
149
150 int tegra_soc_speedo_id(void)
151 {
152         return soc_speedo_id;
153 }
154
155 int tegra_package_id(void)
156 {
157         return package_id;
158 }
159
160 int tegra_cpu_speedo_value(void)
161 {
162         return cpu_speedo_value;
163 }
164
165 int tegra_core_speedo_value(void)
166 {
167         return core_speedo_value;
168 }
169
170 /*
171  * CPU and core nominal voltage levels as determined by chip SKU and speedo
172  * (not final - can be lowered by dvfs tables and rail dependencies; the
173  * latter is resolved by the dvfs code)
174  */
175 int tegra_cpu_speedo_mv(void)
176 {
177         /* Not applicable on Tegra148 */
178         return -ENOSYS;
179 }
180
181 int tegra_core_speedo_mv(void)
182 {
183         switch (soc_speedo_id) {
184         case 0:
185                 return 1150;
186         case 1:
187                 return 1230;
188         default:
189                 BUG();
190         }
191 }
192
193 int tegra_get_cpu_iddq_value()
194 {
195         return cpu_iddq_value;
196 }
197
198 static int get_enable_app_profiles(char *val, const struct kernel_param *kp)
199 {
200         return param_get_uint(val, kp);
201 }
202
203 static struct kernel_param_ops tegra_profiles_ops = {
204         .get = get_enable_app_profiles,
205 };
206
207 module_param_cb(tegra_enable_app_profiles,
208         &tegra_profiles_ops, &enable_app_profiles, 0444);