ARM: tegra12: set CPU rate to 2.2GHz for sku 0x87
[linux-3.10.git] / arch / arm / mach-tegra / tegra14_emc.h
1 /*
2  * arch/arm/mach-tegra/tegra14_emc.h
3  *
4  * Copyright (c) 2013, NVIDIA Corporation. All rights reserved.
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License as published by
8  * the Free Software Foundation; version 2 of the License.
9  *
10  * This program is distributed in the hope that it will be useful, but WITHOUT
11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13  * more details.
14  *
15  * You should have received a copy of the GNU General Public License along
16  * with this program; if not, write to the Free Software Foundation, Inc.,
17  * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
18  *
19  */
20
21 #ifndef _MACH_TEGRA_TEGRA14_EMC_H
22 #define _MACH_TEGRA_TEGRA14_EMC_H
23
24 #include "tegra_emc.h"
25
26 int tegra14_emc_init(void);
27 extern u32 notrace tegra_read_usec_raw(void);
28
29 enum {
30         DRAM_DEV_SEL_ALL = 0,
31         DRAM_DEV_SEL_0   = (2 << 30),
32         DRAM_DEV_SEL_1   = (1 << 30),
33 };
34 #define DRAM_BROADCAST(num)                     \
35         (((num) > 1) ? DRAM_DEV_SEL_ALL : DRAM_DEV_SEL_0)
36
37 #define EMC_INTSTATUS                           0x0
38 #define EMC_INTSTATUS_CLKCHANGE_COMPLETE        (0x1 << 4)
39 #define EMC_INTSTATUS_DLL_LOCK_TIMEOUT_INT      (0x1 << 9)
40
41 #define EMC_DBG                                 0x8
42 #define EMC_DBG_WRITE_MUX_ACTIVE                (0x1 << 1)
43
44 #define EMC_CFG                                 0xc
45 #define EMC_CFG_DRAM_ACPD                       (0x1 << 29)
46 #define EMC_CFG_DYN_SREF_ENABLE                 (0x1 << 28)
47 #define EMC_CFG_PWR_MASK                        (0xF << 28)
48 #define EMC_CFG_MAN_PRE_WR                      (0x1 << 23)
49 #define EMC_CFG_MAN_PRE_RD                      (0x1 << 22)
50 #define EMC_CFG_PERIODIC_QRST                   (0x1 << 21)
51 #define EMC_CFG_EN_DYNAMIC_PUTERM               (0x1 << 20)
52 #define EMC_CFG_DLY_WR_DQ_HALF_CLOCK            (0x1 << 19)
53 #define EMC_CFG_DSR_VTTGEN_DRV_EN               (0x1 << 18)
54 #define EMC_CFG_EMC2PMACRO_CFG_BYPASS_DATAPIPE3 (0x1 << 7)
55 #define EMC_CFG_EMC2PMACRO_CFG_BYPASS_DATAPIPE2 (0x1 << 3)
56 #define EMC_CFG_EMC2PMACRO_CFG_BYPASS_DATAPIPE1 (0x1 << 2)
57 #define EMC_CFG_EMC2PMACRO_CFG_BYPASS_ADDRPIPE  (0x1 << 1)
58 #define EMC_CFG_UPDATE_MASK     \
59         (EMC_CFG_EMC2PMACRO_CFG_BYPASS_ADDRPIPE | \
60          EMC_CFG_EMC2PMACRO_CFG_BYPASS_DATAPIPE1 | \
61          EMC_CFG_EMC2PMACRO_CFG_BYPASS_DATAPIPE2 | \
62          EMC_CFG_EMC2PMACRO_CFG_BYPASS_DATAPIPE3 | \
63          EMC_CFG_DSR_VTTGEN_DRV_EN | \
64          EMC_CFG_DLY_WR_DQ_HALF_CLOCK | \
65          EMC_CFG_EN_DYNAMIC_PUTERM | \
66          EMC_CFG_PERIODIC_QRST | \
67          EMC_CFG_DRAM_ACPD)
68
69 #define EMC_ADR_CFG                             0x10
70 #define EMC_REFCTRL                             0x20
71 #define EMC_REFCTRL_DEV_SEL_SHIFT               0
72 #define EMC_REFCTRL_DEV_SEL_MASK                \
73         (0x3 << EMC_REFCTRL_DEV_SEL_SHIFT)
74 #define EMC_REFCTRL_ENABLE                      (0x1 << 31)
75 #define EMC_REFCTRL_ENABLE_ALL(num)             \
76         (((((num) > 1) ? 0 : 2) << EMC_REFCTRL_DEV_SEL_SHIFT) \
77          | EMC_REFCTRL_ENABLE)
78 #define EMC_REFCTRL_DISABLE_ALL(num)            \
79         ((((num) > 1) ? 0 : 2) << EMC_REFCTRL_DEV_SEL_SHIFT)
80
81 #define EMC_TIMING_CONTROL                      0x28
82 #define EMC_RC                                  0x2c
83 #define EMC_RFC                                 0x30
84 #define EMC_RAS                                 0x34
85 #define EMC_RP                                  0x38
86 #define EMC_R2W                                 0x3c
87 #define EMC_W2R                                 0x40
88 #define EMC_R2P                                 0x44
89 #define EMC_W2P                                 0x48
90 #define EMC_RD_RCD                              0x4c
91 #define EMC_WR_RCD                              0x50
92 #define EMC_RRD                                 0x54
93 #define EMC_REXT                                0x58
94 #define EMC_WDV                                 0x5c
95 #define EMC_QUSE                                0x60
96 #define EMC_QRST                                0x64
97 #define EMC_QSAFE                               0x68
98 #define EMC_RDV                                 0x6c
99 #define EMC_REFRESH                             0x70
100 #define EMC_BURST_REFRESH_NUM                   0x74
101 #define EMC_PDEX2WR                             0x78
102 #define EMC_PDEX2RD                             0x7c
103 #define EMC_PCHG2PDEN                           0x80
104 #define EMC_ACT2PDEN                            0x84
105 #define EMC_AR2PDEN                             0x88
106 #define EMC_RW2PDEN                             0x8c
107 #define EMC_TXSR                                0x90
108 #define EMC_TCKE                                0x94
109 #define EMC_TFAW                                0x98
110 #define EMC_TRPAB                               0x9c
111 #define EMC_TCLKSTABLE                          0xa0
112 #define EMC_TCLKSTOP                            0xa4
113 #define EMC_TREFBW                              0xa8
114 #define EMC_ODT_WRITE                           0xb0
115 #define EMC_ODT_READ                            0xb4
116 #define EMC_WEXT                                0xb8
117 #define EMC_CTT                                 0xbc
118 #define EMC_RFC_SLR                             0xc0
119 #define EMC_MRS_WAIT_CNT2                       0xc4
120
121 #define EMC_MRS_WAIT_CNT                        0xc8
122 #define EMC_MRS_WAIT_CNT                        0xc8
123 #define EMC_MRS_WAIT_CNT_SHORT_WAIT_SHIFT       0
124 #define EMC_MRS_WAIT_CNT_SHORT_WAIT_MASK        \
125         (0x3FF << EMC_MRS_WAIT_CNT_SHORT_WAIT_SHIFT)
126 #define EMC_MRS_WAIT_CNT_LONG_WAIT_SHIFT        16
127 #define EMC_MRS_WAIT_CNT_LONG_WAIT_MASK         \
128         (0x3FF << EMC_MRS_WAIT_CNT_LONG_WAIT_SHIFT)
129
130 #define EMC_MRS                                 0xcc
131 #define EMC_MODE_SET_DLL_RESET                  (0x1 << 8)
132 #define EMC_MODE_SET_LONG_CNT                   (0x1 << 26)
133 #define EMC_EMRS                                0xd0
134 #define EMC_REF                                 0xd4
135 #define EMC_REF_FORCE_CMD                       1
136 #define EMC_PRE                                 0xd8
137 #define EMC_NOP                                 0xdc
138
139 #define EMC_SELF_REF                            0xe0
140 #define EMC_SELF_REF_CMD_ENABLED                (0x1 << 0)
141 #define EMC_SELF_REF_DEV_SEL_SHIFT              30
142 #define EMC_SELF_REF_DEV_SEL_MASK               \
143         (0x3 << EMC_SELF_REF_DEV_SEL_SHIFT)
144
145 #define EMC_DPD                                 0xe4
146 #define EMC_MRW                                 0xe8
147
148 #define EMC_MRR                                 0xec
149 #define EMC_MRR_DEV_SEL_SHIFT                   30
150 #define EMC_MRR_DEV_SEL_MASK                    \
151         (0x3 << EMC_SELF_REF_DEV_SEL_SHIFT)
152 #define EMC_MRR_MA_SHIFT                        16
153 #define EMC_MRR_MA_MASK                         (0xFF << EMC_MRR_MA_SHIFT)
154 #define EMC_MRR_DATA_MASK                       ((0x1 << EMC_MRR_MA_SHIFT) - 1)
155 #define LPDDR2_MR4_TEMP_SHIFT                   0
156 #define LPDDR2_MR4_TEMP_MASK                    (0x7 << LPDDR2_MR4_TEMP_SHIFT)
157
158 #define EMC_CMDQ                                0xf0
159 #define EMC_MC2EMCQ                             0xf4
160 #define EMC_XM2DQSPADCTRL3                      0xf8
161 #define EMC_XM2DQSPADCTRL3_VREF_ENABLE          (0x1 << 5)
162 #define EMC_FBIO_SPARE                          0x100
163
164 #define EMC_FBIO_CFG5                           0x104
165 #define EMC_CFG5_TYPE_SHIFT                     0x0
166 #define EMC_CFG5_TYPE_MASK                      (0x3 << EMC_CFG5_TYPE_SHIFT)
167 enum {
168         DRAM_TYPE_DDR3   = 0,
169         DRAM_TYPE_LPDDR2 = 2,
170 };
171 #define EMC_CFG5_QUSE_MODE_SHIFT                13
172 #define EMC_CFG5_QUSE_MODE_MASK                 \
173         (0x7 << EMC_CFG5_QUSE_MODE_SHIFT)
174 enum {
175         EMC_CFG5_QUSE_MODE_NORMAL = 0,
176         EMC_CFG5_QUSE_MODE_ALWAYS_ON,
177         EMC_CFG5_QUSE_MODE_INTERNAL_LPBK,
178         EMC_CFG5_QUSE_MODE_PULSE_INTERN,
179         EMC_CFG5_QUSE_MODE_PULSE_EXTERN,
180         EMC_CFG5_QUSE_MODE_DIRECT_QUSE,
181 };
182
183 #define EMC_FBIO_WRPTR_EQ_2                     0x108
184 #define EMC_FBIO_CFG6                           0x114
185 #define EMC_FBIO_CFG7                           0x11c
186 #define EMC_CFG_RSV                             0x120
187 #define EMC_ACPD_CONTROL                        0x124
188 #define EMC_EMRS2                               0x12c
189 #define EMC_EMRS3                               0x130
190 #define EMC_MRW2                                0x134
191 #define EMC_MRW3                                0x138
192 #define EMC_MRW4                                0x13c
193 #define EMC_CLKEN_OVERRIDE                      0x140
194 #define EMC_R2R                                 0x144
195 #define EMC_W2W                                 0x148
196 #define EMC_EINPUT                              0x14c
197 #define EMC_EINPUT_DURATION                     0x150
198 #define EMC_PUTERM                              0x154
199 #define EMC_TCKESR                              0x158
200 #define EMC_TPD                                 0x15c
201
202 #define EMC_AUTO_CAL_CONFIG                     0x2a4
203 #define EMC_AUTO_CAL_INTERVAL                   0x2a8
204 #define EMC_AUTO_CAL_STATUS                     0x2ac
205 #define EMC_AUTO_CAL_STATUS_ACTIVE              (0x1 << 31)
206 #define EMC_REQ_CTRL                            0x2b0
207 #define EMC_STATUS                              0x2b4
208 #define EMC_STATUS_TIMING_UPDATE_STALLED        (0x1 << 23)
209 #define EMC_STATUS_MRR_DIVLD                    (0x1 << 20)
210
211 #define EMC_CFG_2                               0x2b8
212 #define EMC_CFG_2_MODE_SHIFT                    0
213 #define EMC_CFG_2_MODE_MASK                     (0x3 << EMC_CFG_2_MODE_SHIFT)
214 #define EMC_CFG_2_SREF_MODE                     0x1
215 #define EMC_CFG_2_PD_MODE                       0x3
216
217 #define EMC_CFG_DIG_DLL                         0x2bc
218 #define EMC_CFG_DIG_DLL_EN                      (0x1 << 0)
219 #define EMC_CFG_DIG_DLL_OVERRIDE_EN             (0x1 << 2)
220 #define EMC_CFG_DIG_DLL_STALL_ALL_TRAFFIC       (0x1 << 3)
221 #define EMC_CFG_DIG_DLL_STALL_RW_UNTIL_LOCK     (0x1 << 4)
222 #define EMC_CFG_DIG_DLL_RESET                   (0x1 << 30)
223 #define EMC_CFG_DIG_DLL_MODE_SHIFT              0x6
224 #define EMC_CFG_DIG_DLL_MODE_MASK               0x3
225 #define EMC_CFG_DIG_DLL_UDSET_SHIFT             0x8
226 #define EMC_CFG_DIG_DLL_UDSET_MASK              0xf
227 #define EMC_CFG_DIG_DLL_OVERRIDE_VAL_SHIFT      0x10
228 #define EMC_CFG_DIG_DLL_OVERRIDE_VAL_MASK       0x3ff
229 #define EMC_CFG_DIG_DLL_LOCK_LIMIT_SHIFT        0x1c /* 28 */
230 #define EMC_CFG_DIG_DLL_LOCK_LIMIT_MASK         0x3
231 #define EMC_CFG_DIG_DLL_USE_OVERRIDE_UNTIL_LOCK (0x1 << 31)
232
233 #define EMC_CFG_DIG_DLL_MODE_RUN_TIL_LOCK       0x1
234
235 #define EMC_CFG_DIG_DLL_PERIOD                  0x2c0
236 #define EMC_DIG_DLL_STATUS                      0x2c8
237 #define EMC_DIG_DLL_STATUS_ALARM                (0x1 << 14)
238 #define EMC_DIG_DLL_STATUS_LOCKED               (0x1 << 15)
239 #define EMC_DIG_DLL_STATUS_OUT                  0x3ff
240 #define EMC_RDV_MASK                            0x2cc
241 #define EMC_WDV_MASK                            0x2d0
242 #define EMC_CTT_DURATION                        0x2d8
243 #define EMC_CTT_TERM_CTRL                       0x2dc
244 #define EMC_ZCAL_INTERVAL                       0x2e0
245 #define EMC_ZCAL_WAIT_CNT                       0x2e4
246 #define EMC_ZCAL_MRW_CMD                        0x2e8
247
248 #define EMC_ZQ_CAL                              0x2ec
249 #define EMC_ZQ_CAL_DEV_SEL_SHIFT                30
250 #define EMC_ZQ_CAL_DEV_SEL_MASK                 \
251         (0x3 << EMC_SELF_REF_DEV_SEL_SHIFT)
252 #define EMC_ZQ_CAL_CMD                          (0x1 << 0)
253 #define EMC_ZQ_CAL_LONG                         (0x1 << 4)
254 #define EMC_ZQ_CAL_LONG_CMD_DEV0                \
255         (DRAM_DEV_SEL_0 | EMC_ZQ_CAL_LONG | EMC_ZQ_CAL_CMD)
256 #define EMC_ZQ_CAL_LONG_CMD_DEV1                \
257         (DRAM_DEV_SEL_1 | EMC_ZQ_CAL_LONG | EMC_ZQ_CAL_CMD)
258
259 #define EMC_XM2CMDPADCTRL                       0x2f0
260 #define EMC_XM2CMDPADCTRL2                      0x2f4
261 #define EMC_XM2DQSPADCTRL                       0x2f8
262 #define EMC_XM2DQSPADCTRL2                      0x2fc
263 #define EMC_XM2DQSPADCTRL2_VREF_DQ_ENABLE       (0x1 << 5)
264 #define EMC_XM2DQSPADCTRL2_RX_FT_REC_ENABLE     (0x1 << 0)
265 #define EMC_XM2DQPADCTRL                        0x300
266 #define EMC_XM2DQPADCTRL2                       0x304
267 #define EMC_XM2CLKPADCTRL                       0x308
268 #define EMC_XM2COMPPADCTRL                      0x30c
269 #define EMC_XM2COMPPADCTRL_VREF_CAL_ENABLE      (0x1 << 10)
270 #define EMC_XM2VTTGENPADCTRL                    0x310
271 #define EMC_XM2VTTGENPADCTRL2                   0x314
272 #define EMC_XM2COMPPADCTRL2                     0x318
273 #define EMC_EMCPADEN                            0x31c
274 #define EMC_XM2DQSPADCTRL4                      0x320
275 #define EMC_SCRATCH0                            0x324
276 #define EMC_DLL_XFORM_DQS0                      0x328
277 #define EMC_DLL_XFORM_DQS1                      0x32c
278 #define EMC_DLL_XFORM_DQS2                      0x330
279 #define EMC_DLL_XFORM_DQS3                      0x334
280 #define EMC_DLL_XFORM_DQS4                      0x338
281 #define EMC_DLL_XFORM_DQS5                      0x33c
282 #define EMC_DLL_XFORM_DQS6                      0x340
283 #define EMC_DLL_XFORM_DQS7                      0x344
284 #define EMC_DLL_XFORM_QUSE0                     0x348
285 #define EMC_DLL_XFORM_QUSE1                     0x34c
286 #define EMC_DLL_XFORM_QUSE2                     0x350
287 #define EMC_DLL_XFORM_QUSE3                     0x354
288 #define EMC_DLL_XFORM_QUSE4                     0x358
289 #define EMC_DLL_XFORM_QUSE5                     0x35c
290 #define EMC_DLL_XFORM_QUSE6                     0x360
291 #define EMC_DLL_XFORM_QUSE7                     0x364
292 #define EMC_DLL_XFORM_DQ0                       0x368
293 #define EMC_DLL_XFORM_DQ1                       0x36c
294 #define EMC_DLL_XFORM_DQ2                       0x370
295 #define EMC_DLL_XFORM_DQ3                       0x374
296 #define EMC_DLI_RX_TRIM0                        0x378
297 #define EMC_DLI_RX_TRIM1                        0x37c
298 #define EMC_DLI_RX_TRIM2                        0x380
299 #define EMC_DLI_RX_TRIM3                        0x384
300 #define EMC_DLI_RX_TRIM4                        0x388
301 #define EMC_DLI_RX_TRIM5                        0x38c
302 #define EMC_DLI_RX_TRIM6                        0x390
303 #define EMC_DLI_RX_TRIM7                        0x394
304 #define EMC_DLI_TX_TRIM0                        0x398
305 #define EMC_DLI_TX_TRIM1                        0x39c
306 #define EMC_DLI_TX_TRIM2                        0x3a0
307 #define EMC_DLI_TX_TRIM3                        0x3a4
308 #define EMC_DLI_TRIM_TXDQS0                     0x3a8
309 #define EMC_DLI_TRIM_TXDQS1                     0x3ac
310 #define EMC_DLI_TRIM_TXDQS2                     0x3b0
311 #define EMC_DLI_TRIM_TXDQS3                     0x3b4
312 #define EMC_DLI_TRIM_TXDQS4                     0x3b8
313 #define EMC_DLI_TRIM_TXDQS5                     0x3bc
314 #define EMC_DLI_TRIM_TXDQS6                     0x3c0
315 #define EMC_DLI_TRIM_TXDQS7                     0x3c4
316 #define EMC_STALL_THEN_EXE_AFTER_CLKCHANGE      0x3cc
317 #define EMC_AUTO_CAL_CLK_STATUS                 0x3d4
318 #define EMC_SEL_DPD_CTRL                        0x3d8
319 #define EMC_SEL_DPD_CTRL_DATA_DPD_ENABLE        (0x1 << 8)
320 #define EMC_PRE_REFRESH_REQ_CNT                 0x3dc
321 #define EMC_DYN_SELF_REF_CONTROL                0x3e0
322 #define EMC_TXSRDLL                             0x3e4
323 #define EMC_CCFIFO_ADDR                         0x3e8
324 #define EMC_CCFIFO_DATA                         0x3ec
325 #define EMC_CCFIFO_STATUS                       0x3f0
326 #define EMC_CDB_CNTL_2                          0x3f8
327 #define EMC_XM2CLKPADCTRL2                      0x3fc
328 #define EMC_SWIZZLE_RANK0_BYTE_CFG              0x400
329 #define EMC_SWIZZLE_RANK0_BYTE0                 0x404
330 #define EMC_SWIZZLE_RANK0_BYTE1                 0x408
331 #define EMC_SWIZZLE_RANK0_BYTE2                 0x40c
332 #define EMC_SWIZZLE_RANK0_BYTE3                 0x410
333 #define EMC_SWIZZLE_RANK1_BYTE_CFG              0x414
334 #define EMC_SWIZZLE_RANK1_BYTE0                 0x418
335 #define EMC_SWIZZLE_RANK1_BYTE1                 0x41c
336 #define EMC_SWIZZLE_RANK1_BYTE2                 0x420
337 #define EMC_SWIZZLE_RANK1_BYTE3                 0x424
338 #define EMC_CA_TRAINING_START                   0x428
339 #define EMC_CA_TRAINING_BUSY                    0x42c
340 #define EMC_CA_TRAINING_CFG                     0x430
341 #define EMC_CA_TRAINING_TIMING_CNTL1            0x434
342 #define EMC_CA_TRAINING_TIMING_CNTL2            0x438
343 #define EMC_CA_TRAINING_CA_LEAD_IN              0x43c
344 #define EMC_CA_TRAINING_CA                      0x440
345 #define EMC_CA_TRAINING_CA_LEAD_OUT             0x444
346 #define EMC_CA_TRAINING_RESULT1                 0x448
347 #define EMC_CA_TRAINING_RESULT2                 0x44c
348 #define EMC_CA_TRAINING_RESULT3                 0x450
349 #define EMC_CA_TRAINING_RESULT4                 0x454
350 #define EMC_AUTO_CAL_CONFIG2                    0x458
351 #define EMC_AUTO_CAL_CONFIG3                    0x45c
352 #define EMC_AUTO_CAL_STATUS2                    0x460
353 #define EMC_XM2CMDPADCTRL3                      0x464
354 #define EMC_IBDLY                               0x468
355 #define EMC_DLL_XFORM_ADDR0                     0x46c
356 #define EMC_DLL_XFORM_ADDR1                     0x470
357 #define EMC_DLL_XFORM_ADDR2                     0x474
358 #define EMC_DLI_ADDR_TRIM                       0x478
359 #define EMC_DSR_VTTGEN_DRV                      0x47c
360 #define EMC_TXDSRVTTGEN                         0x480
361 #define EMC_XM2CMDPADCTRL4                      0x484
362 #define EMC_PIPE_MACRO_CTL                      0x488
363 #define EMC_AUTO_CAL_STATUS3                    0x48c
364 #define EMC_QPOP                                0x490
365 #define EMC_QUSE_WIDTH                          0x494
366 #define EMC_PUTERM_WIDTH                        0x498
367 #define EMC_BGBIAS_CTL0                         0x49c
368
369 #define MC_EMEM_CFG                             0x50
370 #define MC_EMEM_ADR_CFG                         0x54
371 #define MC_EMEM_ADR_CFG_DEV0                    0x58
372 #define MC_EMEM_ADR_CFG_DEV1                    0x5c
373 #define MC_EMEM_ADR_CFG_BANK_MASK_0             0x64
374 #define MC_EMEM_ADR_CFG_BANK_MASK_1             0x68
375 #define MC_EMEM_ADR_CFG_BANK_MASK_2             0x6c
376
377 #define MC_BBCLL_EARB_CFG                       0x80
378 #define MC_EMEM_ARB_BBCLL_OVERRIDE              0x8c
379
380 #define MC_EMEM_ARB_CFG                         0x90
381 #define MC_EMEM_ARB_OUTSTANDING_REQ             0x94
382 #define MC_EMEM_ARB_TIMING_RCD                  0x98
383 #define MC_EMEM_ARB_TIMING_RP                   0x9c
384 #define MC_EMEM_ARB_TIMING_RC                   0xa0
385 #define MC_EMEM_ARB_TIMING_RAS                  0xa4
386 #define MC_EMEM_ARB_TIMING_FAW                  0xa8
387 #define MC_EMEM_ARB_TIMING_RRD                  0xac
388 #define MC_EMEM_ARB_TIMING_RAP2PRE              0xb0
389 #define MC_EMEM_ARB_TIMING_WAP2PRE              0xb4
390 #define MC_EMEM_ARB_TIMING_R2R                  0xb8
391 #define MC_EMEM_ARB_TIMING_W2W                  0xbc
392 #define MC_EMEM_ARB_TIMING_R2W                  0xc0
393 #define MC_EMEM_ARB_TIMING_W2R                  0xc4
394 #define MC_EMEM_ARB_DA_TURNS                    0xd0
395 #define MC_EMEM_ARB_DA_COVERS                   0xd4
396 #define MC_EMEM_ARB_MISC0                       0xd8
397 #define MC_EMEM_ARB_MISC0_EMC_SAME_FREQ         (0x1 << 27)
398 #define MC_EMEM_ARB_MISC1                       0xdc
399 #define MC_EMEM_ARB_RING1_THROTTLE              0xe0
400 #define MC_EMEM_ARB_RING3_THROTTLE              0xe4
401 #define MC_EMEM_ARB_OVERRIDE                    0xe8
402 #define MC_EMEM_ARB_RSV                         0xec
403
404 #define MC_BBC_MEM_REGIONS                      0xf0
405 #define MC_CLKEN_OVERRIDE                       0xf4
406 #define MC_TIMING_CONTROL_DBG                   0xf8
407 #define MC_TIMING_CONTROL                       0xfc
408
409 #define MC_EMEM_ARB_ISOCHRONOUS_2               0x210
410 #define MC_DIS_EXTRA_SNAP_LEVELS                0x2ac
411
412 #define MC_LATENCY_ALLOWANCE_AVPC_0             0x2e4
413 #define MC_LATENCY_ALLOWANCE_DC_0               0x2e8
414 #define MC_LATENCY_ALLOWANCE_DC_1               0x2ec
415 #define MC_LATENCY_ALLOWANCE_DC_2               0x2f0
416 #define MC_LATENCY_ALLOWANCE_DCB_0              0x2f4
417 #define MC_LATENCY_ALLOWANCE_DCB_1              0x2f8
418 #define MC_LATENCY_ALLOWANCE_DCB_2              0x2fc
419 #define MC_LATENCY_ALLOWANCE_EPP_0              0x300
420 #define MC_LATENCY_ALLOWANCE_EPP_1              0x304
421 #define MC_LATENCY_ALLOWANCE_G2_0               0x308
422 #define MC_LATENCY_ALLOWANCE_G2_1               0x30c
423 #define MC_LATENCY_ALLOWANCE_HC_0               0x310
424 #define MC_LATENCY_ALLOWANCE_HC_1               0x314
425 #define MC_LATENCY_ALLOWANCE_HDA_0              0x318
426 #define MC_LATENCY_ALLOWANCE_ISP_0              0x31c
427 #define MC_LATENCY_ALLOWANCE_MPCORE_0           0x320
428 #define MC_LATENCY_ALLOWANCE_MPCORELP_0         0x324
429 #define MC_LATENCY_ALLOWANCE_MSENC_0            0x328
430 #define MC_LATENCY_ALLOWANCE_NV_0               0x334
431 #define MC_LATENCY_ALLOWANCE_NV_1               0x338
432 #define MC_LATENCY_ALLOWANCE_NV2_0              0x33c
433 #define MC_LATENCY_ALLOWANCE_NV2_1              0x340
434 #define MC_LATENCY_ALLOWANCE_PPCS_0             0x344
435 #define MC_LATENCY_ALLOWANCE_PPCS_1             0x348
436 #define MC_LATENCY_ALLOWANCE_PTC_0              0x34c
437 #define MC_LATENCY_ALLOWANCE_VDE_0              0x354
438 #define MC_LATENCY_ALLOWANCE_VDE_1              0x358
439 #define MC_LATENCY_ALLOWANCE_VDE_2              0x35c
440 #define MC_LATENCY_ALLOWANCE_VDE_3              0x360
441 #define MC_LATENCY_ALLOWANCE_VI_0               0x364
442 #define MC_LATENCY_ALLOWANCE_VI_1               0x368
443 #define MC_LATENCY_ALLOWANCE_VI_2               0x36c
444 #define MC_LATENCY_ALLOWANCE_XUSB_0             0x37c
445 #define MC_LATENCY_ALLOWANCE_XUSB_1             0x380
446 #define MC_LATENCY_ALLOWANCE_NV_2               0x384
447 #define MC_LATENCY_ALLOWANCE_NV_3               0x388
448 #define MC_LATENCY_ALLOWANCE_EMUCIF_0           0x38c
449 #define MC_LATENCY_ALLOWANCE_TSEC_0             0x390
450 #define MC_LATENCY_ALLOWANCE_BBMCI_0            0x394
451
452 #define MC_VIDEO_PROTECT_VPR_OVERRIDE           0x418
453 #define MC_VIDEO_PROTECT_BOM                    0x648
454 #define MC_VIDEO_PROTECT_SIZE_MB                0x64c
455 #define MC_VIDEO_PROTECT_REG_CTRL               0x650
456
457 #define MC_SEC_CARVEOUT_BOM                     0x670
458 #define MC_SEC_CARVEOUT_SIZE_MB                 0x674
459 #define MC_SEC_CARVEOUT_REG_CTRL                0x678
460
461 #define MC_PTSA_GRANT_DECREMENT                 0x960
462
463 #define MC_RESERVED_RSV                         0x3fc
464 #define MC_RESERVED_RSV_1                       0x958
465
466 #define MC_EMEM_ARB_OUTSTANDING_REQ_RING3       0x66c
467 #define MC_EMEM_ARB_OVERRIDE_1                  0x968
468
469 #endif