ARM: tegra12: set CPU rate to 2.2GHz for sku 0x87
[linux-3.10.git] / arch / arm / mach-tegra / tegra12x_la.c
1 /*
2  * arch/arm/mach-tegra/tegra12x_la.c
3  *
4  * Copyright (C) 2013, NVIDIA CORPORATION. All rights reserved.
5  *
6  * This software is licensed under the terms of the GNU General Public
7  * License version 2, as published by the Free Software Foundation, and
8  * may be copied, distributed, and modified under those terms.
9  *
10  * This program is distributed in the hope that it will be useful,
11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13  * GNU General Public License for more details.
14  *
15  */
16
17 #include <linux/types.h>
18 #include <linux/clk.h>
19 #include <asm/io.h>
20 #include <mach/latency_allowance.h>
21 #include "la_priv.h"
22 #include "clock.h"
23 #include "iomap.h"
24
25
26 /*
27  * Note about fixed point arithmetic:
28  * ----------------------------------
29  * This file contains fixed point values and arithmetic due to the need to use
30  * floating point values. All fixed point values have the "_fp" or "_FP" suffix
31  * in their name. Macros used to convert between real and fixed point values are
32  * listed below:
33  *    - T12X_LA_FP_FACTOR
34  *    - T12X_LA_REAL_TO_FP(val)
35  *    - T12X_LA_FP_TO_REAL(val)
36  *
37  * Some scenarios require additional accuracy than what can be provided with
38  * T12X_LA_FP_FACTOR. For these special cases we use the following additional
39  * fixed point factor:- T12X_LA_ADDITIONAL_FP_FACTOR. Fixed point values which
40  * use the addtional fixed point factor have a suffix of "_fpa" or "_FPA" in
41  * their name. Macros used to convert between fpa values and other forms (i.e.
42  * fp and real) are as follows:
43  *    - T12X_LA_FP_TO_FPA(val)
44  *    - T12X_LA_FPA_TO_FP(val)
45  *    - T12X_LA_FPA_TO_REAL(val)
46  *    - T12X_LA_REAL_TO_FPA(val)
47  */
48
49
50 /* LA registers */
51 #define T12X_MC_LA_AFI_0                                0x2e0
52 #define T12X_MC_LA_AVPC_ARM7_0                          0x2e4
53 #define T12X_MC_LA_DC_0                                 0x2e8
54 #define T12X_MC_LA_DC_1                                 0x2ec
55 #define T12X_MC_LA_DC_2                                 0x2f0
56 #define T12X_MC_LA_DCB_0                                0x2f4
57 #define T12X_MC_LA_DCB_1                                0x2f8
58 #define T12X_MC_LA_DCB_2                                0x2fc
59 #define T12X_MC_LA_HC_0                                 0x310
60 #define T12X_MC_LA_HC_1                                 0x314
61 #define T12X_MC_LA_HDA_0                                0x318
62 #define T12X_MC_LA_MPCORE_0                             0x320
63 #define T12X_MC_LA_MPCORELP_0                           0x324
64 #define T12X_MC_LA_MSENC_0                              0x328
65 #define T12X_MC_LA_PPCS_0                               0x344
66 #define T12X_MC_LA_PPCS_1                               0x348
67 #define T12X_MC_LA_PTC_0                                0x34c
68 #define T12X_MC_LA_SATA_0                               0x350
69 #define T12X_MC_LA_VDE_0                                0x354
70 #define T12X_MC_LA_VDE_1                                0x358
71 #define T12X_MC_LA_VDE_2                                0x35c
72 #define T12X_MC_LA_VDE_3                                0x360
73 #define T12X_MC_LA_ISP2_0                               0x370
74 #define T12X_MC_LA_ISP2_1                               0x374
75 #define T12X_MC_LA_XUSB_0                               0x37c
76 #define T12X_MC_LA_XUSB_1                               0x380
77 #define T12X_MC_LA_ISP2B_0                              0x384
78 #define T12X_MC_LA_ISP2B_1                              0x388
79 #define T12X_MC_LA_TSEC_0                               0x390
80 #define T12X_MC_LA_VIC_0                                0x394
81 #define T12X_MC_LA_VI2_0                                0x398
82 #define T12X_MC_LA_GPU_0                                0x3ac
83 #define T12X_MC_LA_SDMMCA_0                             0x3b8
84 #define T12X_MC_LA_SDMMCAA_0                            0x3bc
85 #define T12X_MC_LA_SDMMC_0                              0x3c0
86 #define T12X_MC_LA_SDMMCAB_0                            0x3c4
87 #define T12X_MC_LA_DC_3                                 0x3c8
88 #define T12X_MC_SCALED_LA_DISPLAY0A_0   (IO_ADDRESS(TEGRA_MC_BASE) + 0x690)
89 #define T12X_MC_SCALED_LA_DISPLAY0A_0_LOW_SHIFT         0
90 #define T12X_MC_SCALED_LA_DISPLAY0A_0_LOW_MASK          (0xff << \
91                                 T12X_MC_SCALED_LA_DISPLAY0A_0_LOW_SHIFT)
92 #define T12X_MC_SCALED_LA_DISPLAY0A_0_HIGH_SHIFT        16
93 #define T12X_MC_SCALED_LA_DISPLAY0A_0_HIGH_MASK         (0xff << \
94                                 T12X_MC_SCALED_LA_DISPLAY0A_0_HIGH_SHIFT)
95 #define T12X_MC_SCALED_LA_DISPLAY0AB_0  (IO_ADDRESS(TEGRA_MC_BASE) + 0x694)
96 #define T12X_MC_SCALED_LA_DISPLAY0AB_0_LOW_SHIFT         0
97 #define T12X_MC_SCALED_LA_DISPLAY0AB_0_LOW_MASK         (0xff << \
98                                 T12X_MC_SCALED_LA_DISPLAY0AB_0_LOW_SHIFT)
99 #define T12X_MC_SCALED_LA_DISPLAY0AB_0_HIGH_SHIFT       16
100 #define T12X_MC_SCALED_LA_DISPLAY0AB_0_HIGH_MASK        (0xff << \
101                                 T12X_MC_SCALED_LA_DISPLAY0AB_0_HIGH_SHIFT)
102 #define T12X_MC_SCALED_LA_DISPLAY0B_0   (IO_ADDRESS(TEGRA_MC_BASE) + 0x698)
103 #define T12X_MC_SCALED_LA_DISPLAY0B_0_LOW_SHIFT         0
104 #define T12X_MC_SCALED_LA_DISPLAY0B_0_LOW_MASK          (0xff << \
105                                 T12X_MC_SCALED_LA_DISPLAY0B_0_LOW_SHIFT)
106 #define T12X_MC_SCALED_LA_DISPLAY0B_0_HIGH_SHIFT        16
107 #define T12X_MC_SCALED_LA_DISPLAY0B_0_HIGH_MASK         (0xff << \
108                                 T12X_MC_SCALED_LA_DISPLAY0B_0_HIGH_SHIFT)
109 #define T12X_MC_SCALED_LA_DISPLAY0BB_0  (IO_ADDRESS(TEGRA_MC_BASE) + 0x69c)
110 #define T12X_MC_SCALED_LA_DISPLAY0BB_0_LOW_SHIFT         0
111 #define T12X_MC_SCALED_LA_DISPLAY0BB_0_LOW_MASK         (0xff << \
112                                 T12X_MC_SCALED_LA_DISPLAY0BB_0_LOW_SHIFT)
113 #define T12X_MC_SCALED_LA_DISPLAY0BB_0_HIGH_SHIFT       16
114 #define T12X_MC_SCALED_LA_DISPLAY0BB_0_HIGH_MASK        (0xff << \
115                                 T12X_MC_SCALED_LA_DISPLAY0BB_0_HIGH_SHIFT)
116 #define T12X_MC_SCALED_LA_DISPLAY0C_0   (IO_ADDRESS(TEGRA_MC_BASE) + 0x6a0)
117 #define T12X_MC_SCALED_LA_DISPLAY0C_0_LOW_SHIFT         0
118 #define T12X_MC_SCALED_LA_DISPLAY0C_0_LOW_MASK          (0xff << \
119                                 T12X_MC_SCALED_LA_DISPLAY0C_0_LOW_SHIFT)
120 #define T12X_MC_SCALED_LA_DISPLAY0C_0_HIGH_SHIFT        16
121 #define T12X_MC_SCALED_LA_DISPLAY0C_0_HIGH_MASK         (0xff << \
122                                 T12X_MC_SCALED_LA_DISPLAY0C_0_HIGH_SHIFT)
123 #define T12X_MC_SCALED_LA_DISPLAY0CB_0  (IO_ADDRESS(TEGRA_MC_BASE) + 0x6a4)
124 #define T12X_MC_SCALED_LA_DISPLAY0CB_0_LOW_SHIFT         0
125 #define T12X_MC_SCALED_LA_DISPLAY0CB_0_LOW_MASK         (0xff << \
126                                 T12X_MC_SCALED_LA_DISPLAY0CB_0_LOW_SHIFT)
127 #define T12X_MC_SCALED_LA_DISPLAY0CB_0_HIGH_SHIFT       16
128 #define T12X_MC_SCALED_LA_DISPLAY0CB_0_HIGH_MASK        (0xff << \
129                                 T12X_MC_SCALED_LA_DISPLAY0CB_0_HIGH_SHIFT)
130
131 /* PTSA registers */
132 #define T12X_MC_DIS_PTSA_RATE_0         0x41c
133 #define T12X_MC_DIS_PTSA_MIN_0          0x420
134 #define T12X_MC_DIS_PTSA_MAX_0          0x424
135 #define T12X_MC_DISB_PTSA_RATE_0        0x428
136 #define T12X_MC_DISB_PTSA_MIN_0         0x42c
137 #define T12X_MC_DISB_PTSA_MAX_0         0x430
138 #define T12X_MC_VE_PTSA_RATE_0          0x434
139 #define T12X_MC_VE_PTSA_MIN_0           0x438
140 #define T12X_MC_VE_PTSA_MAX_0           0x43c
141 #define T12X_MC_RING2_PTSA_RATE_0       0x440
142 #define T12X_MC_RING2_PTSA_MIN_0        0x444
143 #define T12X_MC_RING2_PTSA_MAX_0        0x448
144 #define T12X_MC_MLL_MPCORER_PTSA_RATE_0 0x44c
145 #define T12X_MC_MLL_MPCORER_PTSA_MIN_0  0x450
146 #define T12X_MC_MLL_MPCORER_PTSA_MAX_0  0x454
147 #define T12X_MC_SMMU_SMMU_PTSA_RATE_0   0x458
148 #define T12X_MC_SMMU_SMMU_PTSA_MIN_0    0x45c
149 #define T12X_MC_SMMU_SMMU_PTSA_MAX_0    0x460
150 #define T12X_MC_R0_DIS_PTSA_MIN_0       0x468
151 #define T12X_MC_R0_DIS_PTSA_MAX_0       0x46c
152 #define T12X_MC_R0_DISB_PTSA_MIN_0      0x474
153 #define T12X_MC_R0_DISB_PTSA_MAX_0      0x478
154 #define T12X_MC_RING1_PTSA_RATE_0       0x47c
155 #define T12X_MC_RING1_PTSA_MIN_0        0x480
156 #define T12X_MC_RING1_PTSA_MAX_0        0x484
157 #define T12X_MC_A9AVPPC_PTSA_MIN_0      0x48c
158 #define T12X_MC_A9AVPPC_PTSA_MAX_0      0x490
159 #define T12X_MC_VE2_PTSA_RATE_0         0x494
160 #define T12X_MC_VE2_PTSA_MIN_0          0x498
161 #define T12X_MC_VE2_PTSA_MAX_0          0x49c
162 #define T12X_MC_ISP_PTSA_RATE_0         0x4a0
163 #define T12X_MC_ISP_PTSA_MIN_0          0x4a4
164 #define T12X_MC_ISP_PTSA_MAX_0          0x4a8
165 #define T12X_MC_PCX_PTSA_MIN_0          0x4b0
166 #define T12X_MC_PCX_PTSA_MAX_0          0x4b4
167 #define T12X_MC_SAX_PTSA_MIN_0          0x4bc
168 #define T12X_MC_SAX_PTSA_MAX_0          0x4c0
169 #define T12X_MC_MSE_PTSA_MIN_0          0x4c8
170 #define T12X_MC_MSE_PTSA_MAX_0          0x4cc
171 #define T12X_MC_SD_PTSA_MIN_0           0x4d4
172 #define T12X_MC_SD_PTSA_MAX_0           0x4d8
173 #define T12X_MC_AHB_PTSA_MIN_0          0x4e0
174 #define T12X_MC_AHB_PTSA_MAX_0          0x4e4
175 #define T12X_MC_APB_PTSA_MIN_0          0x4ec
176 #define T12X_MC_APB_PTSA_MAX_0          0x4f0
177 #define T12X_MC_AVP_PTSA_MIN_0          0x4f8
178 #define T12X_MC_AVP_PTSA_MAX_0          0x4fc
179 #define T12X_MC_VD_PTSA_MIN_0           0x504
180 #define T12X_MC_VD_PTSA_MAX_0           0x508
181 #define T12X_MC_FTOP_PTSA_MIN_0         0x510
182 #define T12X_MC_FTOP_PTSA_MAX_0         0x514
183 #define T12X_MC_HOST_PTSA_MIN_0         0x51c
184 #define T12X_MC_HOST_PTSA_MAX_0         0x520
185 #define T12X_MC_USBX_PTSA_MIN_0         0x528
186 #define T12X_MC_USBX_PTSA_MAX_0         0x52c
187 #define T12X_MC_USBD_PTSA_MIN_0         0x534
188 #define T12X_MC_USBD_PTSA_MAX_0         0x538
189 #define T12X_MC_GK_PTSA_MIN_0           0x540
190 #define T12X_MC_GK_PTSA_MAX_0           0x544
191 #define T12X_MC_AUD_PTSA_MIN_0          0x54c
192 #define T12X_MC_AUD_PTSA_MAX_0          0x550
193 #define T12X_MC_VICPC_PTSA_MIN_0        0x558
194 #define T12X_MC_VICPC_PTSA_MAX_0        0x55c
195
196 /* Misc registers */
197 #define T12X_MC_EMEM_ARB_MISC0_0        0xd8
198 #define     T12X_MC_EMC_SAME_FREQ_BIT   27
199 #define T12X_MC_TIMING_CONTROL_0        0xfc
200 #define T12X_MC_DIS_EXTRA_SNAP_LEVELS_0 0x2ac
201 #define T12X_MC_PTSA_GRANT_DECREMENT_0  0x960
202
203 /* Register naming macros */
204 #define T12X_MC_RA(r) \
205         (IO_ADDRESS(TEGRA_MC_BASE) + (T12X_MC_##r))
206 #define T12X_RA(r) \
207         (IO_ADDRESS(TEGRA_MC_BASE) + (T12X_MC_LA_##r))
208
209 /* Misc macros */
210 #define T12X_LA_FP_FACTOR                                       1000
211 #define T12X_LA_REAL_TO_FP(val)                 ((val) * T12X_LA_FP_FACTOR)
212 #define T12X_LA_FP_TO_REAL(val)                 ((val) / T12X_LA_FP_FACTOR)
213 #define T12X_LA_ADDITIONAL_FP_FACTOR                            10
214 #define T12X_LA_FP_TO_FPA(val)          ((val) * T12X_LA_ADDITIONAL_FP_FACTOR)
215 #define T12X_LA_FPA_TO_FP(val)          ((val) / T12X_LA_ADDITIONAL_FP_FACTOR)
216 #define T12X_LA_FPA_TO_REAL(val)                ((val) / \
217                                                 T12X_LA_FP_FACTOR / \
218                                                 T12X_LA_ADDITIONAL_FP_FACTOR)
219 #define T12X_LA_REAL_TO_FPA(val)                ((val) * \
220                                                 T12X_LA_FP_FACTOR * \
221                                                 T12X_LA_ADDITIONAL_FP_FACTOR)
222 #define T12X_LA_STATIC_LA_MINUS_SNAP_ARB_TO_ROW_SRT_EMCCLKS_FP  70000
223 #define T12X_LA_DRAM_WIDTH_BITS                                 64
224 #define T12X_LA_DISP_CATCHUP_FACTOR_FP                          1100
225 #define T12X_MC_PTSA_MIN_DEFAULT_MASK                           0x3f
226 #define T12X_MC_PTSA_MAX_DEFAULT_MASK                           0x3f
227 #define T12X_MC_PTSA_RATE_DEFAULT_MASK                          0xff
228 #define T12X_EMC_MIN_FREQ_MHZ_FP                                12500
229 #define T12X_EMC_MAX_FREQ_MHZ                                   1067
230 #define T12X_MC_MAX_FREQ_MHZ                                    533
231 #define T12X_MAX_GRANT_DEC                                      511
232 #define T12X_MAX_GD_FP                                          1996
233 #define T12X_LOW_GD_FP                          (T12X_MAX_GD_FP * \
234                                                 T12X_EMC_MIN_FREQ_MHZ_FP * \
235                                                 2 / \
236                                                 T12X_EMC_MAX_FREQ_MHZ/ \
237                                                 T12X_LA_FP_FACTOR)
238 #define T12X_MAX_GD_FPA                                         19961
239 #define T12X_LOW_GD_FPA                         (T12X_MAX_GD_FPA * \
240                                                 T12X_EMC_MIN_FREQ_MHZ_FP * \
241                                                 2 / \
242                                                 T12X_EMC_MAX_FREQ_MHZ/ \
243                                                 T12X_LA_FP_FACTOR)
244 #define T12X_MAX_DDA_RATE                                       255
245 #define T12X_EXP_TIME_EMCCLKS_FP                                88000
246 #define T12X_MAX_LA_NSEC                                        7650
247 /* Note:- T12X_DDA_BW_MARGIN_FP is supposed to be 1100. But
248           T12X_DDA_BW_MARGIN_FP has been increased to 1150 to compensate for
249           fixed point arithmetic errors. */
250 #define T12X_DDA_BW_MARGIN_FP                                   1100
251 #define T12X_1_DDA_FRAC_FP                                      10
252 #define T12X_MPCORER_CPU_RD_MARGIN_FP                           100
253 #define T12X_MIN_CYCLES_PER_GRANT                               2
254 #define T12X_EMEM_PTSA_MINMAX_WIDTH                             5
255 #define T12X_EMEM_PTSA_RATE_WIDTH                               8
256 #define T12X_RING1_FEEDER_SISO_ALLOC_DIV                        2
257 #define T12X_LA_USEC_TO_NSEC_FACTOR                             1000
258 #define T12X_LA_HZ_TO_MHZ_FACTOR                                1000000
259 #define T12X_LA(f, e, a, r, i, ss, la, clk) \
260 { \
261         .fifo_size_in_atoms = f, \
262         .expiration_in_ns = e, \
263         .reg_addr = T12X_RA(a), \
264         .mask = MASK(r), \
265         .shift = SHIFT(r), \
266         .id = ID(i), \
267         .name = __stringify(i), \
268         .scaling_supported = ss, \
269         .init_la = la, \
270         .la_ref_clk_mhz = clk \
271 }
272
273
274 struct la_client_info t12x_la_info_array[] = {
275         T12X_LA(0, 0, AFI_0, 7 : 0, AFIR, false, 28, 800),
276         T12X_LA(0, 0, AFI_0, 23 : 16, AFIW, false, 128, 800),
277         T12X_LA(0, 0, AVPC_ARM7_0, 7 : 0, AVPC_ARM7R, false, 4, 0),
278         T12X_LA(0, 0, AVPC_ARM7_0, 23 : 16, AVPC_ARM7W, false, 128, 800),
279         T12X_LA(0, 0, DC_0, 7 : 0, DISPLAY_0A, true, 80, 0),
280         T12X_LA(0, 0, DCB_0, 7 : 0, DISPLAY_0AB, true, 80, 0),
281         T12X_LA(0, 0, DC_0, 23 : 16, DISPLAY_0B, true, 80, 0),
282         T12X_LA(0, 0, DCB_0, 23 : 16, DISPLAY_0BB, true, 80, 0),
283         T12X_LA(0, 0, DC_1, 7 : 0, DISPLAY_0C, true, 80, 0),
284         T12X_LA(0, 0, DCB_1, 7 : 0, DISPLAY_0CB, true, 80, 0),
285         T12X_LA(0, 0, DC_3, 7 : 0, DISPLAYD, false, 80, 0),
286         T12X_LA(0, 0, DC_2, 7 : 0, DISPLAY_HC, false, 80, 0),
287         T12X_LA(0, 0, DCB_2, 7 : 0, DISPLAY_HCB, false, 80, 0),
288         T12X_LA(0, 0, DC_2, 23 : 16, DISPLAY_T, false, 80, 0),
289         T12X_LA(0, 0, GPU_0, 7 : 0, GPUSRD, false, 25, 800),
290         T12X_LA(0, 0, GPU_0, 23 : 16, GPUSWR, false, 128, 800),
291         T12X_LA(0, 0, HDA_0, 7 : 0, HDAR, false, 36, 0),
292         T12X_LA(0, 0, HDA_0, 23 : 16, HDAW, false, 128, 800),
293         T12X_LA(0, 0, TSEC_0, 7 : 0, TSECSRD, false, 60, 200),
294         T12X_LA(0, 0, TSEC_0, 23 : 16, TSECSWR, false, 128, 800),
295         T12X_LA(0, 0, HC_0, 7 : 0, HOST1X_DMAR, false, 22, 800),
296         T12X_LA(0, 0, HC_0, 23 : 16, HOST1XR, false, 80, 0),
297         T12X_LA(0, 0, HC_1, 7 : 0, HOST1XW, false, 128, 800),
298         T12X_LA(0, 0, ISP2_0, 7 : 0, ISP_RA, false, 54, 300),
299         T12X_LA(0, 0, ISP2_1, 7 : 0, ISP_WA, false, 128, 800),
300         T12X_LA(0, 0, ISP2_1, 23 : 16, ISP_WB, false, 128, 800),
301         T12X_LA(0, 0, ISP2B_0, 7 : 0, ISP_RAB, false, 54, 300),
302         T12X_LA(0, 0, ISP2B_1, 7 : 0, ISP_WAB, false, 128, 800),
303         T12X_LA(0, 0, ISP2B_1, 23 : 16, ISP_WBB, false, 128, 800),
304         T12X_LA(0, 0, MPCORELP_0, 7 : 0, MPCORE_LPR, false, 4, 0),
305         T12X_LA(0, 0, MPCORELP_0, 23 : 16, MPCORE_LPW, false, 128, 800),
306         T12X_LA(0, 0, MPCORE_0, 7 : 0, MPCORER, false, 4, 0),
307         T12X_LA(0, 0, MPCORE_0, 23 : 16, MPCOREW, false, 128, 800),
308         T12X_LA(0, 0, MSENC_0, 7 : 0, MSENCSRD, false, 24, 0),
309         T12X_LA(0, 0, MSENC_0, 23 : 16, MSENCSWR, false, 128, 800),
310         T12X_LA(0, 0, PPCS_1, 7 : 0, PPCS_AHBDMAW, true, 128, 800),
311         T12X_LA(0, 0, PPCS_0, 23 : 16, PPCS_AHBSLVR, false, 39, 408),
312         T12X_LA(0, 0, PPCS_1, 23 : 16, PPCS_AHBSLVW, false, 128, 800),
313         T12X_LA(0, 0, PTC_0, 7 : 0, PTCR, false, 0, 0),
314         T12X_LA(0, 0, SATA_0, 7 : 0, SATAR, false, 101, 400),
315         T12X_LA(0, 0, SATA_0, 23 : 16, SATAW, false, 128, 800),
316         T12X_LA(0, 0, SDMMC_0, 7 : 0, SDMMCR, false, 144, 248),
317         T12X_LA(0, 0, SDMMCA_0, 7 : 0, SDMMCRA, false, 144, 248),
318         T12X_LA(0, 0, SDMMCAA_0, 7 : 0, SDMMCRAA, false, 65, 248),
319         T12X_LA(0, 0, SDMMCAB_0, 7 : 0, SDMMCRAB, false, 65, 248),
320         T12X_LA(0, 0, SDMMC_0, 23 : 16, SDMMCW, false, 128, 800),
321         T12X_LA(0, 0, SDMMCA_0, 23 : 16, SDMMCWA, false, 128, 800),
322         T12X_LA(0, 0, SDMMCAA_0, 23 : 16, SDMMCWAA, false, 128, 800),
323         T12X_LA(0, 0, SDMMCAB_0, 23 : 16, SDMMCWAB, false, 128, 800),
324         T12X_LA(0, 0, VDE_0, 7 : 0, VDE_BSEVR, false, 255, 0),
325         T12X_LA(0, 0, VDE_2, 7 : 0, VDE_BSEVW, false, 128, 800),
326         T12X_LA(0, 0, VDE_2, 23 : 16, VDE_DBGW, false, 255, 0),
327         T12X_LA(0, 0, VDE_0, 23 : 16, VDE_MBER, false, 212, 200),
328         T12X_LA(0, 0, VDE_3, 7 : 0, VDE_MBEW, false, 128, 800),
329         T12X_LA(0, 0, VDE_1, 7 : 0, VDE_MCER, false, 41, 400),
330         T12X_LA(0, 0, VDE_1, 23 : 16, VDE_TPER, false, 81, 200),
331         T12X_LA(0, 0, VDE_3, 23 : 16, VDE_TPMW, false, 128, 800),
332         T12X_LA(0, 0, VIC_0, 7 : 0, VICSRD, false, 27, 800),
333         T12X_LA(0, 0, VIC_0, 23 : 16, VICSWR, false, 128, 800),
334         T12X_LA(0, 0, VI2_0, 7 : 0, VI_W, false, 128, 800),
335         T12X_LA(0, 0, XUSB_1, 7 : 0, XUSB_DEVR, false, 56, 400),
336         T12X_LA(0, 0, XUSB_1, 23 : 16, XUSB_DEVW, false, 128, 800),
337         T12X_LA(0, 0, XUSB_0, 7 : 0, XUSB_HOSTR, false, 56, 400),
338         T12X_LA(0, 0, XUSB_0, 23 : 16, XUSB_HOSTW, false, 128, 800),
339
340         /* end of list */
341         T12X_LA(0, 0, DC_3, 0 : 0, MAX_ID, false, 0, 0)
342 };
343
344 static struct la_chip_specific *cs;
345 const struct disp_client *tegra_la_disp_clients_info;
346 static unsigned int total_dc0_bw;
347 static unsigned int total_dc1_bw;
348 DEFINE_MUTEX(disp_and_camera_ptsa_lock);
349
350
351 unsigned int tegra12x_la_real_to_fp(unsigned int val)
352 {
353         return val * T12X_LA_FP_FACTOR;
354 }
355
356 unsigned int tegra12x_la_fp_to_real(unsigned int val)
357 {
358         return val / T12X_LA_FP_FACTOR;
359 }
360
361 static inline bool is_display_client(enum tegra_la_id id)
362 {
363         return ((id >= FIRST_DISP_CLIENT_ID) && (id <= LAST_DISP_CLIENT_ID));
364 }
365
366 static inline bool is_camera_client(enum tegra_la_id id)
367 {
368         return ((id >= FIRST_CAMERA_CLIENT_ID) &&
369                 (id <= LAST_CAMERA_CLIENT_ID));
370 }
371
372 unsigned int fraction2dda_fp(unsigned int fraction_fp,
373                                 unsigned int div,
374                                 unsigned int mask)
375 {
376         unsigned int dda = 0;
377         unsigned int f_fpa = T12X_LA_FP_TO_FPA(fraction_fp) / div;
378         int i = 0;
379         unsigned int r = 0;
380
381         for (i = 0; i < T12X_EMEM_PTSA_RATE_WIDTH; i++) {
382                 f_fpa *= 2;
383                 r = T12X_LA_FPA_TO_REAL(f_fpa);
384                 dda = (dda << 1) | (unsigned int)(r);
385                 f_fpa -= T12X_LA_REAL_TO_FPA(r);
386         }
387         if (f_fpa > 0) {
388                 /* Do not round up if the calculated dda is at the mask value
389                    already, it will overflow */
390                 if (dda != mask)
391                         dda++;          /* to round up dda value */
392         }
393
394         return min(dda, (unsigned int)T12X_MAX_DDA_RATE);
395 }
396
397 static void program_ptsa(void)
398 {
399         struct ptsa_info *p = &cs->ptsa_info;
400
401         writel(p->ptsa_grant_dec, T12X_MC_RA(PTSA_GRANT_DECREMENT_0));
402         writel(1, T12X_MC_RA(TIMING_CONTROL_0));
403
404         writel(p->dis_ptsa_rate, T12X_MC_RA(DIS_PTSA_RATE_0));
405         writel(p->dis_ptsa_min, T12X_MC_RA(DIS_PTSA_MIN_0));
406         writel(p->dis_ptsa_max, T12X_MC_RA(DIS_PTSA_MAX_0));
407
408         writel(p->disb_ptsa_rate, T12X_MC_RA(DISB_PTSA_RATE_0));
409         writel(p->disb_ptsa_min, T12X_MC_RA(DISB_PTSA_MIN_0));
410         writel(p->disb_ptsa_max, T12X_MC_RA(DISB_PTSA_MAX_0));
411
412         writel(p->ve_ptsa_rate, T12X_MC_RA(VE_PTSA_RATE_0));
413         writel(p->ve_ptsa_min, T12X_MC_RA(VE_PTSA_MIN_0));
414         writel(p->ve_ptsa_max, T12X_MC_RA(VE_PTSA_MAX_0));
415
416         writel(p->ve2_ptsa_rate, T12X_MC_RA(VE2_PTSA_RATE_0));
417         writel(p->ve2_ptsa_min, T12X_MC_RA(VE2_PTSA_MIN_0));
418         writel(p->ve2_ptsa_max, T12X_MC_RA(VE2_PTSA_MAX_0));
419
420         writel(p->ring2_ptsa_rate, T12X_MC_RA(RING2_PTSA_RATE_0));
421         writel(p->ring2_ptsa_min, T12X_MC_RA(RING2_PTSA_MIN_0));
422         writel(p->ring2_ptsa_max, T12X_MC_RA(RING2_PTSA_MAX_0));
423
424         /* FIXME:- Is bbc and bbcll_earb_cfg required for T124?
425         writel(p->bbc_ptsa_rate, T12X_MC_RA(BBC_PTSA_RATE_0));
426         writel(p->bbc_ptsa_min, T12X_MC_RA(BBC_PTSA_MIN_0));
427         writel(p->bbc_ptsa_max, T12X_MC_RA(BBC_PTSA_MAX_0));
428
429         writel(p->bbcll_earb_cfg, T12X_MC_RA(BBCLL_EARB_CFG_0));*/
430
431         writel(p->mpcorer_ptsa_rate, T12X_MC_RA(MLL_MPCORER_PTSA_RATE_0));
432         writel(p->mpcorer_ptsa_min, T12X_MC_RA(MLL_MPCORER_PTSA_MIN_0));
433         writel(p->mpcorer_ptsa_max, T12X_MC_RA(MLL_MPCORER_PTSA_MAX_0));
434
435         writel(p->smmu_ptsa_rate, T12X_MC_RA(SMMU_SMMU_PTSA_RATE_0));
436         writel(p->smmu_ptsa_min, T12X_MC_RA(SMMU_SMMU_PTSA_MIN_0));
437         writel(p->smmu_ptsa_max, T12X_MC_RA(SMMU_SMMU_PTSA_MAX_0));
438
439         writel(p->ring1_ptsa_rate, T12X_MC_RA(RING1_PTSA_RATE_0));
440         writel(p->ring1_ptsa_min, T12X_MC_RA(RING1_PTSA_MIN_0));
441         writel(p->ring1_ptsa_max, T12X_MC_RA(RING1_PTSA_MAX_0));
442
443         writel(p->dis_extra_snap_level, T12X_MC_RA(DIS_EXTRA_SNAP_LEVELS_0));
444         /* FIXME:- Is heg_extra_snap_level required for T124?
445         writel(p->heg_extra_snap_level, T12X_MC_RA(HEG_EXTRA_SNAP_LEVELS_0)); */
446
447         writel(p->isp_ptsa_rate, T12X_MC_RA(ISP_PTSA_RATE_0));
448         writel(p->isp_ptsa_min, T12X_MC_RA(ISP_PTSA_MIN_0));
449         writel(p->isp_ptsa_max, T12X_MC_RA(ISP_PTSA_MAX_0));
450
451         writel(p->a9avppc_ptsa_min, T12X_MC_RA(A9AVPPC_PTSA_MIN_0));
452         writel(p->a9avppc_ptsa_max, T12X_MC_RA(A9AVPPC_PTSA_MAX_0));
453
454         writel(p->avp_ptsa_min, T12X_MC_RA(AVP_PTSA_MIN_0));
455         writel(p->avp_ptsa_max, T12X_MC_RA(AVP_PTSA_MAX_0));
456
457         writel(p->r0_dis_ptsa_min, T12X_MC_RA(R0_DIS_PTSA_MIN_0));
458         writel(p->r0_dis_ptsa_max, T12X_MC_RA(R0_DIS_PTSA_MAX_0));
459
460         writel(p->r0_disb_ptsa_min, T12X_MC_RA(R0_DISB_PTSA_MIN_0));
461         writel(p->r0_disb_ptsa_max, T12X_MC_RA(R0_DISB_PTSA_MAX_0));
462
463         writel(p->vd_ptsa_min, T12X_MC_RA(VD_PTSA_MIN_0));
464         writel(p->vd_ptsa_max, T12X_MC_RA(VD_PTSA_MAX_0));
465
466         writel(p->mse_ptsa_min, T12X_MC_RA(MSE_PTSA_MIN_0));
467         writel(p->mse_ptsa_max, T12X_MC_RA(MSE_PTSA_MAX_0));
468
469         writel(p->gk_ptsa_min, T12X_MC_RA(GK_PTSA_MIN_0));
470         writel(p->gk_ptsa_max, T12X_MC_RA(GK_PTSA_MAX_0));
471
472         writel(p->vicpc_ptsa_min, T12X_MC_RA(VICPC_PTSA_MIN_0));
473         writel(p->vicpc_ptsa_max, T12X_MC_RA(VICPC_PTSA_MAX_0));
474
475         writel(p->apb_ptsa_min, T12X_MC_RA(APB_PTSA_MIN_0));
476         writel(p->apb_ptsa_max, T12X_MC_RA(APB_PTSA_MAX_0));
477
478         writel(p->pcx_ptsa_min, T12X_MC_RA(PCX_PTSA_MIN_0));
479         writel(p->pcx_ptsa_max, T12X_MC_RA(PCX_PTSA_MAX_0));
480
481         writel(p->host_ptsa_min, T12X_MC_RA(HOST_PTSA_MIN_0));
482         writel(p->host_ptsa_max, T12X_MC_RA(HOST_PTSA_MAX_0));
483
484         writel(p->ahb_ptsa_min, T12X_MC_RA(AHB_PTSA_MIN_0));
485         writel(p->ahb_ptsa_max, T12X_MC_RA(AHB_PTSA_MAX_0));
486
487         writel(p->sax_ptsa_min, T12X_MC_RA(SAX_PTSA_MIN_0));
488         writel(p->sax_ptsa_max, T12X_MC_RA(SAX_PTSA_MAX_0));
489
490         writel(p->aud_ptsa_min, T12X_MC_RA(AUD_PTSA_MIN_0));
491         writel(p->aud_ptsa_max, T12X_MC_RA(AUD_PTSA_MAX_0));
492
493         writel(p->sd_ptsa_min, T12X_MC_RA(SD_PTSA_MIN_0));
494         writel(p->sd_ptsa_max, T12X_MC_RA(SD_PTSA_MAX_0));
495
496         writel(p->usbx_ptsa_min, T12X_MC_RA(USBX_PTSA_MIN_0));
497         writel(p->usbx_ptsa_max, T12X_MC_RA(USBX_PTSA_MAX_0));
498
499         writel(p->usbd_ptsa_min, T12X_MC_RA(USBD_PTSA_MIN_0));
500         writel(p->usbd_ptsa_min, T12X_MC_RA(USBD_PTSA_MAX_0));
501
502         writel(p->ftop_ptsa_min, T12X_MC_RA(FTOP_PTSA_MIN_0));
503         writel(p->ftop_ptsa_max, T12X_MC_RA(FTOP_PTSA_MAX_0));
504 }
505
506 static void save_ptsa(void)
507 {
508         struct ptsa_info *p = &cs->ptsa_info;
509
510         p->ptsa_grant_dec = readl(T12X_MC_RA(PTSA_GRANT_DECREMENT_0));
511
512         p->dis_ptsa_rate = readl(T12X_MC_RA(DIS_PTSA_RATE_0));
513         p->dis_ptsa_min = readl(T12X_MC_RA(DIS_PTSA_MIN_0));
514         p->dis_ptsa_max = readl(T12X_MC_RA(DIS_PTSA_MAX_0));
515
516         p->disb_ptsa_rate = readl(T12X_MC_RA(DISB_PTSA_RATE_0));
517         p->disb_ptsa_min = readl(T12X_MC_RA(DISB_PTSA_MIN_0));
518         p->disb_ptsa_max = readl(T12X_MC_RA(DISB_PTSA_MAX_0));
519
520         p->ve_ptsa_rate = readl(T12X_MC_RA(VE_PTSA_RATE_0));
521         p->ve_ptsa_min = readl(T12X_MC_RA(VE_PTSA_MIN_0));
522         p->ve_ptsa_max = readl(T12X_MC_RA(VE_PTSA_MAX_0));
523
524         p->ve2_ptsa_rate = readl(T12X_MC_RA(VE2_PTSA_RATE_0));
525         p->ve2_ptsa_min = readl(T12X_MC_RA(VE2_PTSA_MIN_0));
526         p->ve2_ptsa_max = readl(T12X_MC_RA(VE2_PTSA_MAX_0));
527
528         p->ring2_ptsa_rate = readl(T12X_MC_RA(RING2_PTSA_RATE_0));
529         p->ring2_ptsa_min = readl(T12X_MC_RA(RING2_PTSA_MIN_0));
530         p->ring2_ptsa_max = readl(T12X_MC_RA(RING2_PTSA_MAX_0));
531
532         /* FIXME:- Is bbc and bbcll_earb_cfg required for T124?
533         p->bbc_ptsa_rate = readl(T12X_MC_RA(BBC_PTSA_RATE_0));
534         p->bbc_ptsa_min = readl(T12X_MC_RA(BBC_PTSA_MIN_0));
535         p->bbc_ptsa_max = readl(T12X_MC_RA(BBC_PTSA_MAX_0));
536
537         p->bbcll_earb_cfg = readl(T12X_MC_RA(BBCLL_EARB_CFG_0)); */
538
539         p->mpcorer_ptsa_rate = readl(T12X_MC_RA(MLL_MPCORER_PTSA_RATE_0));
540         p->mpcorer_ptsa_min = readl(T12X_MC_RA(MLL_MPCORER_PTSA_MIN_0));
541         p->mpcorer_ptsa_max = readl(T12X_MC_RA(MLL_MPCORER_PTSA_MAX_0));
542
543         p->smmu_ptsa_rate = readl(T12X_MC_RA(SMMU_SMMU_PTSA_RATE_0));
544         p->smmu_ptsa_min = readl(T12X_MC_RA(SMMU_SMMU_PTSA_MIN_0));
545         p->smmu_ptsa_max = readl(T12X_MC_RA(SMMU_SMMU_PTSA_MAX_0));
546
547         p->ring1_ptsa_rate = readl(T12X_MC_RA(RING1_PTSA_RATE_0));
548         p->ring1_ptsa_min = readl(T12X_MC_RA(RING1_PTSA_MIN_0));
549         p->ring1_ptsa_max = readl(T12X_MC_RA(RING1_PTSA_MAX_0));
550
551         p->dis_extra_snap_level = readl(T12X_MC_RA(DIS_EXTRA_SNAP_LEVELS_0));
552         /* FIXME:- Is heg_extra_snap_level required for T124?
553         p->heg_extra_snap_level = readl(T12X_MC_RA(HEG_EXTRA_SNAP_LEVELS_0)); */
554
555         p->isp_ptsa_rate = readl(T12X_MC_RA(ISP_PTSA_RATE_0));
556         p->isp_ptsa_min = readl(T12X_MC_RA(ISP_PTSA_MIN_0));
557         p->isp_ptsa_max = readl(T12X_MC_RA(ISP_PTSA_MAX_0));
558
559         p->a9avppc_ptsa_min = readl(T12X_MC_RA(A9AVPPC_PTSA_MIN_0));
560         p->a9avppc_ptsa_max = readl(T12X_MC_RA(A9AVPPC_PTSA_MAX_0));
561
562         p->avp_ptsa_min = readl(T12X_MC_RA(AVP_PTSA_MIN_0));
563         p->avp_ptsa_max = readl(T12X_MC_RA(AVP_PTSA_MAX_0));
564
565         p->r0_dis_ptsa_min = readl(T12X_MC_RA(R0_DIS_PTSA_MIN_0));
566         p->r0_dis_ptsa_max = readl(T12X_MC_RA(R0_DIS_PTSA_MAX_0));
567
568         p->r0_disb_ptsa_min = readl(T12X_MC_RA(R0_DISB_PTSA_MIN_0));
569         p->r0_disb_ptsa_min = readl(T12X_MC_RA(R0_DISB_PTSA_MAX_0));
570
571         p->vd_ptsa_min = readl(T12X_MC_RA(VD_PTSA_MIN_0));
572         p->vd_ptsa_max = readl(T12X_MC_RA(VD_PTSA_MAX_0));
573
574         p->mse_ptsa_min = readl(T12X_MC_RA(MSE_PTSA_MIN_0));
575         p->mse_ptsa_max = readl(T12X_MC_RA(MSE_PTSA_MAX_0));
576
577         p->gk_ptsa_min = readl(T12X_MC_RA(GK_PTSA_MIN_0));
578         p->gk_ptsa_max = readl(T12X_MC_RA(GK_PTSA_MAX_0));
579
580         p->vicpc_ptsa_min = readl(T12X_MC_RA(VICPC_PTSA_MIN_0));
581         p->vicpc_ptsa_min = readl(T12X_MC_RA(VICPC_PTSA_MAX_0));
582
583         p->apb_ptsa_min = readl(T12X_MC_RA(APB_PTSA_MIN_0));
584         p->apb_ptsa_max = readl(T12X_MC_RA(APB_PTSA_MAX_0));
585
586         p->pcx_ptsa_min = readl(T12X_MC_RA(PCX_PTSA_MIN_0));
587         p->pcx_ptsa_max = readl(T12X_MC_RA(PCX_PTSA_MAX_0));
588
589         p->host_ptsa_min = readl(T12X_MC_RA(HOST_PTSA_MIN_0));
590         p->host_ptsa_max = readl(T12X_MC_RA(HOST_PTSA_MAX_0));
591
592         p->ahb_ptsa_min = readl(T12X_MC_RA(AHB_PTSA_MIN_0));
593         p->ahb_ptsa_max = readl(T12X_MC_RA(AHB_PTSA_MAX_0));
594
595         p->sax_ptsa_min = readl(T12X_MC_RA(SAX_PTSA_MIN_0));
596         p->sax_ptsa_max = readl(T12X_MC_RA(SAX_PTSA_MAX_0));
597
598         p->aud_ptsa_min = readl(T12X_MC_RA(AUD_PTSA_MIN_0));
599         p->aud_ptsa_max = readl(T12X_MC_RA(AUD_PTSA_MAX_0));
600
601         p->sd_ptsa_min = readl(T12X_MC_RA(SD_PTSA_MIN_0));
602         p->sd_ptsa_max = readl(T12X_MC_RA(SD_PTSA_MAX_0));
603
604         p->usbx_ptsa_min = readl(T12X_MC_RA(USBX_PTSA_MIN_0));
605         p->usbx_ptsa_max = readl(T12X_MC_RA(USBX_PTSA_MAX_0));
606
607         p->usbd_ptsa_min = readl(T12X_MC_RA(USBD_PTSA_MIN_0));
608         p->usbd_ptsa_max = readl(T12X_MC_RA(USBD_PTSA_MAX_0));
609
610         p->ftop_ptsa_min = readl(T12X_MC_RA(FTOP_PTSA_MIN_0));
611         p->ftop_ptsa_max = readl(T12X_MC_RA(FTOP_PTSA_MAX_0));
612 }
613
614 static void t12x_init_ptsa(void)
615 {
616         struct clk *emc_clk __attribute__((unused));
617         unsigned long emc_freq_mhz __attribute__((unused));
618         unsigned int mc_freq_mhz;
619         unsigned long same_freq __attribute__((unused));
620         struct ptsa_info *p = &cs->ptsa_info;
621         unsigned int mpcorer_ptsa_rate_fp = 0;
622
623         /* get emc frequency */
624         emc_clk = clk_get(NULL, "emc");
625         emc_freq_mhz = clk_get_rate(emc_clk) /
626                         T12X_LA_HZ_TO_MHZ_FACTOR;
627         la_debug("**** emc clk_rate=%luMHz", emc_freq_mhz);
628
629         /* get mc frequency */
630         same_freq = (readl(T12X_MC_RA(EMEM_ARB_MISC0_0)) >>
631                         T12X_MC_EMC_SAME_FREQ_BIT) & 0x1;
632         mc_freq_mhz = same_freq ? emc_freq_mhz : emc_freq_mhz / 2;
633         la_debug("**** mc clk_rate=%uMHz", mc_freq_mhz);
634
635         /* compute initial value for grant dec */
636         p->ptsa_grant_dec = min(mc_freq_mhz *
637                                 T12X_MAX_GRANT_DEC /
638                                 T12X_MC_MAX_FREQ_MHZ,
639                                 (unsigned int)T12X_MAX_GRANT_DEC);
640
641         /* initialize PTSA reg values */
642         /* FIXME:- Program inital ptsa rates */
643         p->ve_ptsa_min = (unsigned int)(-5) &
644                                         T12X_MC_PTSA_MIN_DEFAULT_MASK;
645         p->ve_ptsa_max = (unsigned int)(31) &
646                                         T12X_MC_PTSA_MAX_DEFAULT_MASK;
647
648         p->isp_ptsa_min = (unsigned int)(-5) &
649                                         T12X_MC_PTSA_MIN_DEFAULT_MASK;
650         p->isp_ptsa_max = (unsigned int)(31) &
651                                         T12X_MC_PTSA_MAX_DEFAULT_MASK;
652
653         p->ve2_ptsa_min = (unsigned int)(-5) &
654                                         T12X_MC_PTSA_MIN_DEFAULT_MASK;
655         p->ve2_ptsa_max = (unsigned int)(31) &
656                                         T12X_MC_PTSA_MAX_DEFAULT_MASK;
657
658         p->a9avppc_ptsa_min = (unsigned int)(-5) &
659                                         T12X_MC_PTSA_MIN_DEFAULT_MASK;
660         p->a9avppc_ptsa_max = (unsigned int)(16) &
661                                         T12X_MC_PTSA_MAX_DEFAULT_MASK;
662
663         p->ring2_ptsa_min = (unsigned int)(-2) &
664                                         T12X_MC_PTSA_MIN_DEFAULT_MASK;
665         p->ring2_ptsa_max = (unsigned int)(0) &
666                                         T12X_MC_PTSA_MAX_DEFAULT_MASK;
667         p->ring2_ptsa_rate = 1 & T12X_MC_PTSA_RATE_DEFAULT_MASK;
668
669         p->dis_ptsa_min = (unsigned int)(-5) &
670                                         T12X_MC_PTSA_MIN_DEFAULT_MASK;
671         p->dis_ptsa_max = (unsigned int)(31) &
672                                         T12X_MC_PTSA_MAX_DEFAULT_MASK;
673
674         p->disb_ptsa_min = (unsigned int)(-5) &
675                                         T12X_MC_PTSA_MIN_DEFAULT_MASK;
676         p->disb_ptsa_max = (unsigned int)(31) &
677                                         T12X_MC_PTSA_MAX_DEFAULT_MASK;
678
679         p->ring1_ptsa_min = (unsigned int)(-5) &
680                                         T12X_MC_PTSA_MIN_DEFAULT_MASK;
681         p->ring1_ptsa_max = (unsigned int)(31) &
682                                         T12X_MC_PTSA_MAX_DEFAULT_MASK;
683
684         p->mpcorer_ptsa_min = (unsigned int)(-4) &
685                                         T12X_MC_PTSA_MIN_DEFAULT_MASK;
686         p->mpcorer_ptsa_max = (unsigned int)(4) &
687                                         T12X_MC_PTSA_MAX_DEFAULT_MASK;
688         /* allocate 10% for CPU read */
689         mpcorer_ptsa_rate_fp = T12X_MPCORER_CPU_RD_MARGIN_FP *
690                                 T12X_MAX_GRANT_DEC *
691                                 emc_freq_mhz /
692                                 T12X_EMC_MAX_FREQ_MHZ /
693                                 T12X_MIN_CYCLES_PER_GRANT;
694         /* between 200 and 400 MHz EMC freq, scale from 0 to 10% */
695         if (emc_freq_mhz < 400)
696                 mpcorer_ptsa_rate_fp *= (emc_freq_mhz - 200) / (400 - 200);
697         /* make sure mpcorer_ptsa_rate is at least 1 */
698         if (emc_freq_mhz < 200 || mpcorer_ptsa_rate_fp < T12X_LA_FP_FACTOR)
699                 mpcorer_ptsa_rate_fp = T12X_LA_FP_FACTOR;
700         /* round up */
701         if (mpcorer_ptsa_rate_fp % T12X_LA_FP_FACTOR != 0)
702                 mpcorer_ptsa_rate_fp += T12X_LA_FP_FACTOR;
703         p->mpcorer_ptsa_rate = T12X_LA_FP_TO_REAL(mpcorer_ptsa_rate_fp) &
704                                 T12X_MC_PTSA_RATE_DEFAULT_MASK;
705
706         p->smmu_ptsa_min = (unsigned int)(1) &
707                                         T12X_MC_PTSA_MIN_DEFAULT_MASK;
708         p->smmu_ptsa_max = (unsigned int)(1) &
709                                         T12X_MC_PTSA_MAX_DEFAULT_MASK;
710
711         p->r0_dis_ptsa_min = (unsigned int)(-5) &
712                                         T12X_MC_PTSA_MIN_DEFAULT_MASK;
713         p->r0_dis_ptsa_max = (unsigned int)(31) &
714                                         T12X_MC_PTSA_MAX_DEFAULT_MASK;
715
716         p->r0_disb_ptsa_min = (unsigned int)(-5) &
717                                         T12X_MC_PTSA_MIN_DEFAULT_MASK;
718         p->r0_disb_ptsa_max = (unsigned int)(31) &
719                                         T12X_MC_PTSA_MAX_DEFAULT_MASK;
720
721         p->vd_ptsa_min = (unsigned int)(-2) &
722                                         T12X_MC_PTSA_MIN_DEFAULT_MASK;
723         p->vd_ptsa_max = (unsigned int)(0) &
724                                         T12X_MC_PTSA_MAX_DEFAULT_MASK;
725
726         p->mse_ptsa_min = (unsigned int)(-2) &
727                                         T12X_MC_PTSA_MIN_DEFAULT_MASK;
728         p->mse_ptsa_max = (unsigned int)(0) &
729                                         T12X_MC_PTSA_MAX_DEFAULT_MASK;
730
731         p->gk_ptsa_min = (unsigned int)(-2) &
732                                         T12X_MC_PTSA_MIN_DEFAULT_MASK;
733         p->gk_ptsa_max = (unsigned int)(0) &
734                                         T12X_MC_PTSA_MAX_DEFAULT_MASK;
735
736         p->vicpc_ptsa_min = (unsigned int)(-2) &
737                                         T12X_MC_PTSA_MIN_DEFAULT_MASK;
738         p->vicpc_ptsa_max = (unsigned int)(0) &
739                                         T12X_MC_PTSA_MAX_DEFAULT_MASK;
740
741         p->apb_ptsa_min = (unsigned int)(-2) &
742                                         T12X_MC_PTSA_MIN_DEFAULT_MASK;
743         p->apb_ptsa_max = (unsigned int)(0) &
744                                         T12X_MC_PTSA_MAX_DEFAULT_MASK;
745
746         p->pcx_ptsa_min = (unsigned int)(-2) &
747                                         T12X_MC_PTSA_MIN_DEFAULT_MASK;
748         p->pcx_ptsa_max = (unsigned int)(0) &
749                                         T12X_MC_PTSA_MAX_DEFAULT_MASK;
750
751         p->host_ptsa_min = (unsigned int)(-2) &
752                                         T12X_MC_PTSA_MIN_DEFAULT_MASK;
753         p->host_ptsa_max = (unsigned int)(0) &
754                                         T12X_MC_PTSA_MAX_DEFAULT_MASK;
755
756         p->ahb_ptsa_min = (unsigned int)(-2) &
757                                         T12X_MC_PTSA_MIN_DEFAULT_MASK;
758         p->ahb_ptsa_max = (unsigned int)(0) &
759                                         T12X_MC_PTSA_MAX_DEFAULT_MASK;
760
761         p->sax_ptsa_min = (unsigned int)(-2) &
762                                         T12X_MC_PTSA_MIN_DEFAULT_MASK;
763         p->sax_ptsa_max = (unsigned int)(0) &
764                                         T12X_MC_PTSA_MAX_DEFAULT_MASK;
765
766         p->aud_ptsa_min = (unsigned int)(-2) &
767                                         T12X_MC_PTSA_MIN_DEFAULT_MASK;
768         p->aud_ptsa_max = (unsigned int)(0) &
769                                         T12X_MC_PTSA_MAX_DEFAULT_MASK;
770
771         p->sd_ptsa_min = (unsigned int)(-2) &
772                                         T12X_MC_PTSA_MIN_DEFAULT_MASK;
773         p->sd_ptsa_max = (unsigned int)(0) &
774                                         T12X_MC_PTSA_MAX_DEFAULT_MASK;
775
776         p->usbx_ptsa_min = (unsigned int)(-2) &
777                                         T12X_MC_PTSA_MIN_DEFAULT_MASK;
778         p->usbx_ptsa_max = (unsigned int)(0) &
779                                         T12X_MC_PTSA_MAX_DEFAULT_MASK;
780
781         p->usbd_ptsa_min = (unsigned int)(-2) &
782                                         T12X_MC_PTSA_MIN_DEFAULT_MASK;
783         p->usbd_ptsa_max = (unsigned int)(0) &
784                                         T12X_MC_PTSA_MAX_DEFAULT_MASK;
785
786         p->ftop_ptsa_min = (unsigned int)(-2) &
787                                         T12X_MC_PTSA_MIN_DEFAULT_MASK;
788         p->ftop_ptsa_max = (unsigned int)(0) &
789                                         T12X_MC_PTSA_MAX_DEFAULT_MASK;
790
791         p->avp_ptsa_min = (unsigned int)(-2) &
792                                         T12X_MC_PTSA_MIN_DEFAULT_MASK;
793         p->avp_ptsa_max = (unsigned int)(0) &
794                                         T12X_MC_PTSA_MAX_DEFAULT_MASK;
795
796         program_ptsa();
797 }
798
799 static void t12x_calc_disp_and_camera_ptsa(void)
800 {
801         struct ptsa_info *p = &cs->ptsa_info;
802         unsigned int ve_bw_fp = cs->camera_bw_array[CAMERA_IDX(VI_W)] *
803                                 T12X_DDA_BW_MARGIN_FP;
804         unsigned int ve2_bw_fp = 0;
805         unsigned int isp_bw_fp = 0;
806         unsigned int total_dc0_bw_fp = total_dc0_bw *
807                                         T12X_DDA_BW_MARGIN_FP;
808         unsigned int total_dc1_bw_fp = total_dc1_bw *
809                                         T12X_DDA_BW_MARGIN_FP;
810         unsigned int low_freq_bw_fp = T12X_EMC_MIN_FREQ_MHZ_FP *
811                                         2 *
812                                         T12X_LA_DRAM_WIDTH_BITS /
813                                         8;
814         unsigned int dis_frac_fp = T12X_LA_FPA_TO_FP(
815                                                 T12X_LOW_GD_FPA *
816                                                 total_dc0_bw_fp /
817                                                 low_freq_bw_fp);
818         unsigned int disb_frac_fp = T12X_LA_FPA_TO_FP(
819                                                 T12X_LOW_GD_FPA *
820                                                 total_dc1_bw_fp /
821                                                 low_freq_bw_fp);
822         unsigned int ring1_bw_fp = total_dc0_bw_fp +
823                                         total_dc1_bw_fp +
824                                         ve_bw_fp;
825         unsigned int total_iso_bw_fp = total_dc0_bw_fp + total_dc1_bw_fp;
826         unsigned int siso_bw_fp = 0;
827         int max_max = (1 << T12X_EMEM_PTSA_MINMAX_WIDTH) - 1;
828         int i = 0;
829
830
831         if (cs->agg_camera_array[AGG_CAMERA_ID(VE2)].is_hiso) {
832                 ve2_bw_fp = (cs->camera_bw_array[CAMERA_IDX(ISP_RAB)] +
833                                 cs->camera_bw_array[CAMERA_IDX(ISP_WAB)] +
834                                 cs->camera_bw_array[CAMERA_IDX(ISP_WBB)]) *
835                                 T12X_DDA_BW_MARGIN_FP;
836         } else {
837                 ve2_bw_fp = T12X_LA_REAL_TO_FP(
838                                 cs->camera_bw_array[CAMERA_IDX(ISP_RAB)] +
839                                 cs->camera_bw_array[CAMERA_IDX(ISP_WAB)] +
840                                 cs->camera_bw_array[CAMERA_IDX(ISP_WBB)]);
841         }
842
843         if (cs->agg_camera_array[AGG_CAMERA_ID(ISP)].is_hiso) {
844                 isp_bw_fp = (cs->camera_bw_array[CAMERA_IDX(ISP_RA)] +
845                                 cs->camera_bw_array[CAMERA_IDX(ISP_WA)] +
846                                 cs->camera_bw_array[CAMERA_IDX(ISP_WB)]) *
847                                 T12X_DDA_BW_MARGIN_FP;
848         } else {
849                 isp_bw_fp = T12X_LA_REAL_TO_FP(
850                                 cs->camera_bw_array[CAMERA_IDX(ISP_RA)] +
851                                 cs->camera_bw_array[CAMERA_IDX(ISP_WA)] +
852                                 cs->camera_bw_array[CAMERA_IDX(ISP_WB)]);
853         }
854
855         cs->agg_camera_array[AGG_CAMERA_ID(VE)].bw_fp = ve_bw_fp;
856         cs->agg_camera_array[AGG_CAMERA_ID(VE2)].bw_fp = ve2_bw_fp;
857         cs->agg_camera_array[AGG_CAMERA_ID(ISP)].bw_fp = isp_bw_fp;
858
859         ring1_bw_fp += ve2_bw_fp + isp_bw_fp;
860
861
862         for (i = 0; i < TEGRA_LA_AGG_CAMERA_NUM_CLIENTS; i++) {
863                 struct agg_camera_client_info *agg_client =
864                                                 &cs->agg_camera_array[i];
865
866                 if (agg_client->is_hiso) {
867                         agg_client->frac_fp = T12X_LA_FPA_TO_FP(
868                                                 T12X_LOW_GD_FPA *
869                                                 agg_client->bw_fp /
870                                                 low_freq_bw_fp);
871                         agg_client->ptsa_min = (unsigned int)(-5) &
872                                                 T12X_MC_PTSA_MIN_DEFAULT_MASK;
873                         agg_client->ptsa_max = (unsigned int)(max_max) &
874                                                 T12X_MC_PTSA_MAX_DEFAULT_MASK;
875
876                         total_iso_bw_fp += agg_client->bw_fp;
877                 } else {
878                         agg_client->frac_fp = T12X_1_DDA_FRAC_FP;
879                         agg_client->ptsa_min = (unsigned int)(-2) &
880                                                 T12X_MC_PTSA_MIN_DEFAULT_MASK;
881                         agg_client->ptsa_max = (unsigned int)(0) &
882                                                 T12X_MC_PTSA_MAX_DEFAULT_MASK;
883                 }
884         }
885
886
887         p->ring1_ptsa_min = (unsigned int)(-5) &
888                                         T12X_MC_PTSA_MIN_DEFAULT_MASK;
889         p->ring1_ptsa_max = (unsigned int)(max_max) &
890                                         T12X_MC_PTSA_MAX_DEFAULT_MASK;
891         siso_bw_fp = total_iso_bw_fp / T12X_RING1_FEEDER_SISO_ALLOC_DIV;
892         ring1_bw_fp += siso_bw_fp;
893         p->ring1_ptsa_rate =
894                         (fraction2dda_fp(T12X_LOW_GD_FP *
895                                                 ring1_bw_fp /
896                                                 low_freq_bw_fp,
897                                         4,
898                                         T12X_MC_PTSA_RATE_DEFAULT_MASK) +
899                                         1) &
900                         T12X_MC_PTSA_RATE_DEFAULT_MASK;
901         if (p->ring1_ptsa_rate == 0)
902                 p->ring1_ptsa_rate = 0x1;
903
904         p->dis_ptsa_min = (unsigned int)(-5) &
905                                         T12X_MC_PTSA_MIN_DEFAULT_MASK;
906         p->dis_ptsa_max = (unsigned int)(max_max) &
907                                         T12X_MC_PTSA_MAX_DEFAULT_MASK;
908         p->dis_ptsa_rate = fraction2dda_fp(dis_frac_fp,
909                                         4,
910                                         T12X_MC_PTSA_RATE_DEFAULT_MASK) &
911                                         T12X_MC_PTSA_RATE_DEFAULT_MASK;
912
913         p->disb_ptsa_min = (unsigned int)(-5) &
914                                         T12X_MC_PTSA_MIN_DEFAULT_MASK;
915         p->disb_ptsa_max = (unsigned int)(max_max) &
916                                         T12X_MC_PTSA_MAX_DEFAULT_MASK;
917         p->disb_ptsa_rate = fraction2dda_fp(disb_frac_fp,
918                                         4,
919                                         T12X_MC_PTSA_RATE_DEFAULT_MASK) &
920                                         T12X_MC_PTSA_RATE_DEFAULT_MASK;
921
922         p->ve_ptsa_min = cs->agg_camera_array[AGG_CAMERA_ID(VE)].ptsa_min &
923                                         T12X_MC_PTSA_MIN_DEFAULT_MASK;
924         p->ve_ptsa_max = cs->agg_camera_array[AGG_CAMERA_ID(VE)].ptsa_max &
925                                         T12X_MC_PTSA_MAX_DEFAULT_MASK;
926         p->ve_ptsa_rate = fraction2dda_fp(
927                                 cs->agg_camera_array[AGG_CAMERA_ID(VE)].frac_fp,
928                                 4,
929                                 T12X_MC_PTSA_RATE_DEFAULT_MASK) &
930                                 T12X_MC_PTSA_RATE_DEFAULT_MASK;
931
932         p->ve2_ptsa_min = cs->agg_camera_array[AGG_CAMERA_ID(VE2)].ptsa_min &
933                                         T12X_MC_PTSA_MIN_DEFAULT_MASK;
934         p->ve2_ptsa_max = cs->agg_camera_array[AGG_CAMERA_ID(VE2)].ptsa_max &
935                                         T12X_MC_PTSA_MAX_DEFAULT_MASK;
936         p->ve2_ptsa_rate = fraction2dda_fp(
937                         cs->agg_camera_array[AGG_CAMERA_ID(VE2)].frac_fp,
938                         4,
939                         T12X_MC_PTSA_RATE_DEFAULT_MASK) &
940                         T12X_MC_PTSA_RATE_DEFAULT_MASK;
941
942         p->isp_ptsa_min = cs->agg_camera_array[AGG_CAMERA_ID(ISP)].ptsa_min &
943                                         T12X_MC_PTSA_MIN_DEFAULT_MASK;
944         p->isp_ptsa_max = cs->agg_camera_array[AGG_CAMERA_ID(ISP)].ptsa_max &
945                                         T12X_MC_PTSA_MAX_DEFAULT_MASK;
946         p->isp_ptsa_rate = fraction2dda_fp(
947                         cs->agg_camera_array[AGG_CAMERA_ID(ISP)].frac_fp,
948                         4,
949                         T12X_MC_PTSA_RATE_DEFAULT_MASK) &
950                         T12X_MC_PTSA_RATE_DEFAULT_MASK;
951 }
952
953 static void t12x_update_display_ptsa_rate(unsigned int *disp_bw_array)
954 {
955         struct ptsa_info *p = &cs->ptsa_info;
956
957         t12x_calc_disp_and_camera_ptsa();
958
959         writel(p->ring1_ptsa_min, T12X_MC_RA(RING1_PTSA_MIN_0));
960         writel(p->ring1_ptsa_max, T12X_MC_RA(RING1_PTSA_MAX_0));
961         writel(p->ring1_ptsa_rate, T12X_MC_RA(RING1_PTSA_RATE_0));
962
963         writel(p->dis_ptsa_min, T12X_MC_RA(DIS_PTSA_MIN_0));
964         writel(p->dis_ptsa_max, T12X_MC_RA(DIS_PTSA_MAX_0));
965         writel(p->dis_ptsa_rate, T12X_MC_RA(DIS_PTSA_RATE_0));
966
967         writel(p->disb_ptsa_min, T12X_MC_RA(DISB_PTSA_MIN_0));
968         writel(p->disb_ptsa_max, T12X_MC_RA(DISB_PTSA_MAX_0));
969         writel(p->disb_ptsa_rate, T12X_MC_RA(DISB_PTSA_RATE_0));
970 }
971
972 static int t12x_update_camera_ptsa_rate(enum tegra_la_id id,
973                                         unsigned int bw_mbps,
974                                         int is_hiso)
975 {
976         struct ptsa_info *p = NULL;
977         int ret_code = 0;
978
979
980         mutex_lock(&disp_and_camera_ptsa_lock);
981
982
983         if (!is_camera_client(id)) {
984                 /* Non-camera clients should be handled by t12x_set_la(...) or
985                    t12x_set_disp_la(...). */
986                 pr_err("%s: Ignoring request from a non-camera client.\n",
987                         __func__);
988                 pr_err("%s: Non-camera clients should be handled by "
989                         "t12x_set_la(...) or t12x_set_disp_la(...).\n",
990                         __func__);
991                 ret_code = -1;
992                 goto exit;
993         }
994
995         if ((id == ID(VI_W)) &&
996                 (!is_hiso)) {
997                 pr_err("%s: VI is stating that its not HISO.\n", __func__);
998                 pr_err("%s: Ignoring and assuming that VI is HISO because VI "
999                         "is always supposed to be HISO.\n",
1000                         __func__);
1001                 is_hiso = 1;
1002         }
1003
1004
1005         p = &cs->ptsa_info;
1006
1007         if (id == ID(VI_W)) {
1008                 cs->agg_camera_array[AGG_CAMERA_ID(VE)].is_hiso = is_hiso;
1009         } else if ((id == ID(ISP_RAB)) ||
1010                         (id == ID(ISP_WAB)) ||
1011                         (id == ID(ISP_WBB))) {
1012                 cs->agg_camera_array[AGG_CAMERA_ID(VE2)].is_hiso = is_hiso;
1013         } else {
1014                 cs->agg_camera_array[AGG_CAMERA_ID(ISP)].is_hiso = is_hiso;
1015         }
1016
1017         cs->camera_bw_array[CAMERA_LA_IDX(id)] = bw_mbps;
1018
1019
1020         t12x_calc_disp_and_camera_ptsa();
1021
1022
1023         writel(p->ring1_ptsa_min, T12X_MC_RA(RING1_PTSA_MIN_0));
1024         writel(p->ring1_ptsa_max, T12X_MC_RA(RING1_PTSA_MAX_0));
1025         writel(p->ring1_ptsa_rate, T12X_MC_RA(RING1_PTSA_RATE_0));
1026
1027         writel(p->ve_ptsa_min, T12X_MC_RA(VE_PTSA_MIN_0));
1028         writel(p->ve_ptsa_max, T12X_MC_RA(VE_PTSA_MAX_0));
1029         writel(p->ve_ptsa_rate, T12X_MC_RA(VE_PTSA_RATE_0));
1030
1031         writel(p->ve2_ptsa_min, T12X_MC_RA(VE2_PTSA_MIN_0));
1032         writel(p->ve2_ptsa_max, T12X_MC_RA(VE2_PTSA_MAX_0));
1033         writel(p->ve2_ptsa_rate, T12X_MC_RA(VE2_PTSA_RATE_0));
1034
1035         writel(p->isp_ptsa_min, T12X_MC_RA(ISP_PTSA_MIN_0));
1036         writel(p->isp_ptsa_max, T12X_MC_RA(ISP_PTSA_MAX_0));
1037         writel(p->isp_ptsa_rate, T12X_MC_RA(ISP_PTSA_RATE_0));
1038
1039
1040 exit:
1041         mutex_unlock(&disp_and_camera_ptsa_lock);
1042
1043         return ret_code;
1044 }
1045
1046
1047 static void program_scaled_la(struct la_client_info *ci, int la)
1048 {
1049         unsigned long reg_write;
1050
1051         if (ci->id == ID(DISPLAY_0A)) {
1052                 reg_write = ((la << T12X_MC_SCALED_LA_DISPLAY0A_0_LOW_SHIFT) &
1053                         T12X_MC_SCALED_LA_DISPLAY0A_0_LOW_MASK) |
1054                         ((la << T12X_MC_SCALED_LA_DISPLAY0A_0_HIGH_SHIFT) &
1055                         T12X_MC_SCALED_LA_DISPLAY0A_0_HIGH_MASK);
1056                 writel(reg_write, T12X_MC_SCALED_LA_DISPLAY0A_0);
1057                 la_debug("reg_addr=0x%x, write=0x%x",
1058                 (u32)T12X_MC_SCALED_LA_DISPLAY0A_0, (u32)reg_write);
1059         } else if (ci->id == ID(DISPLAY_0AB)) {
1060                 reg_write = ((la << T12X_MC_SCALED_LA_DISPLAY0AB_0_LOW_SHIFT) &
1061                         T12X_MC_SCALED_LA_DISPLAY0AB_0_LOW_MASK) |
1062                         ((la << T12X_MC_SCALED_LA_DISPLAY0AB_0_HIGH_SHIFT) &
1063                         T12X_MC_SCALED_LA_DISPLAY0AB_0_HIGH_MASK);
1064                 writel(reg_write, T12X_MC_SCALED_LA_DISPLAY0AB_0);
1065                 la_debug("reg_addr=0x%x, write=0x%x",
1066                 (u32)T12X_MC_SCALED_LA_DISPLAY0AB_0, (u32)reg_write);
1067         } else if (ci->id == ID(DISPLAY_0B)) {
1068                 reg_write = ((la << T12X_MC_SCALED_LA_DISPLAY0B_0_LOW_SHIFT) &
1069                         T12X_MC_SCALED_LA_DISPLAY0B_0_LOW_MASK) |
1070                         ((la << T12X_MC_SCALED_LA_DISPLAY0B_0_HIGH_SHIFT) &
1071                         T12X_MC_SCALED_LA_DISPLAY0B_0_HIGH_MASK);
1072                 writel(reg_write, T12X_MC_SCALED_LA_DISPLAY0B_0);
1073                 la_debug("reg_addr=0x%x, write=0x%x",
1074                 (u32)T12X_MC_SCALED_LA_DISPLAY0B_0, (u32)reg_write);
1075         } else if (ci->id == ID(DISPLAY_0BB)) {
1076                 reg_write = ((la << T12X_MC_SCALED_LA_DISPLAY0BB_0_LOW_SHIFT) &
1077                         T12X_MC_SCALED_LA_DISPLAY0BB_0_LOW_MASK) |
1078                         ((la << T12X_MC_SCALED_LA_DISPLAY0BB_0_HIGH_SHIFT) &
1079                         T12X_MC_SCALED_LA_DISPLAY0BB_0_HIGH_MASK);
1080                 writel(reg_write, T12X_MC_SCALED_LA_DISPLAY0BB_0);
1081                 la_debug("reg_addr=0x%x, write=0x%x",
1082                 (u32)T12X_MC_SCALED_LA_DISPLAY0BB_0, (u32)reg_write);
1083         } else if (ci->id == ID(DISPLAY_0C)) {
1084                 reg_write = ((la << T12X_MC_SCALED_LA_DISPLAY0C_0_LOW_SHIFT) &
1085                         T12X_MC_SCALED_LA_DISPLAY0C_0_LOW_MASK) |
1086                         ((la << T12X_MC_SCALED_LA_DISPLAY0C_0_HIGH_SHIFT) &
1087                         T12X_MC_SCALED_LA_DISPLAY0C_0_HIGH_MASK);
1088                 writel(reg_write, T12X_MC_SCALED_LA_DISPLAY0C_0);
1089                 la_debug("reg_addr=0x%x, write=0x%x",
1090                 (u32)T12X_MC_SCALED_LA_DISPLAY0C_0, (u32)reg_write);
1091         } else if (ci->id == ID(DISPLAY_0CB)) {
1092                 reg_write = ((la << T12X_MC_SCALED_LA_DISPLAY0CB_0_LOW_SHIFT) &
1093                         T12X_MC_SCALED_LA_DISPLAY0CB_0_LOW_MASK) |
1094                         ((la << T12X_MC_SCALED_LA_DISPLAY0CB_0_HIGH_SHIFT) &
1095                         T12X_MC_SCALED_LA_DISPLAY0CB_0_HIGH_MASK);
1096                 writel(reg_write, T12X_MC_SCALED_LA_DISPLAY0CB_0);
1097                 la_debug("reg_addr=0x%x, write=0x%x",
1098                 (u32)T12X_MC_SCALED_LA_DISPLAY0CB_0, (u32)reg_write);
1099         }
1100 }
1101 static void program_la(struct la_client_info *ci, int la)
1102 {
1103         unsigned long reg_read;
1104         unsigned long reg_write;
1105
1106         BUG_ON(la > T12X_MC_LA_MAX_VALUE);
1107
1108         spin_lock(&cs->lock);
1109         reg_read = readl(ci->reg_addr);
1110         reg_write = (reg_read & ~ci->mask) |
1111                         (la << ci->shift);
1112         writel(reg_write, ci->reg_addr);
1113         ci->la_set = la;
1114         la_debug("reg_addr=0x%x, read=0x%x, write=0x%x",
1115                 (u32)ci->reg_addr, (u32)reg_read, (u32)reg_write);
1116
1117         program_scaled_la(ci, la);
1118
1119         spin_unlock(&cs->lock);
1120 }
1121
1122 static int t12x_set_la(enum tegra_la_id id,
1123                         unsigned int bw_mbps)
1124 {
1125         int idx = cs->id_to_index[id];
1126         struct la_client_info *ci = &cs->la_info_array[idx];
1127         unsigned int la_to_set = 0;
1128
1129         if (is_display_client(id)) {
1130                 /* Display clients should be handled by
1131                    t12x_set_disp_la(...). */
1132                 return -1;
1133         } else if (id == ID(MSENCSRD)) {
1134                 /* This is a special case. */
1135                 struct clk *emc_clk = clk_get(NULL, "emc");
1136                 unsigned int emc_freq_mhz = clk_get_rate(emc_clk) /
1137                                                 T12X_LA_HZ_TO_MHZ_FACTOR;
1138                 unsigned int val_1 = 53;
1139                 unsigned int val_2 = 24;
1140
1141                 if (210 > emc_freq_mhz)
1142                         val_1 = val_1 * 210 / emc_freq_mhz;
1143
1144                 if (574 > emc_freq_mhz)
1145                         val_2 = val_2 * 574 / emc_freq_mhz;
1146
1147                 la_to_set = min3((unsigned int)T12X_MC_LA_MAX_VALUE,
1148                                 val_1,
1149                                 val_2);
1150         } else if (ci->la_ref_clk_mhz != 0) {
1151                 /* In this case we need to scale LA with emc frequency. */
1152                 struct clk *emc_clk = clk_get(NULL, "emc");
1153                 unsigned long emc_freq_mhz = clk_get_rate(emc_clk) /
1154                                         (unsigned long)T12X_LA_HZ_TO_MHZ_FACTOR;
1155
1156                 if (ci->la_ref_clk_mhz <= emc_freq_mhz) {
1157                         la_to_set = min(ci->init_la,
1158                                 (unsigned int)T12X_MC_LA_MAX_VALUE);
1159                 } else {
1160                         la_to_set = min((unsigned int)(ci->init_la *
1161                                          ci->la_ref_clk_mhz / emc_freq_mhz),
1162                                 (unsigned int)T12X_MC_LA_MAX_VALUE);
1163                 }
1164         } else {
1165                 /* In this case we have a client with a static LA value. */
1166                 la_to_set = ci->init_la;
1167         }
1168
1169         program_la(ci, la_to_set);
1170         return 0;
1171 }
1172
1173 static int t12x_set_disp_la(enum tegra_la_id id,
1174                                 unsigned int bw_mbps,
1175                                 struct dc_to_la_params disp_params)
1176 {
1177         int idx = 0;
1178         struct la_client_info *ci = NULL;
1179         unsigned int la_to_set = 0;
1180         struct clk *emc_clk = NULL;
1181         unsigned long emc_freq_mhz = 0;
1182         unsigned int dvfs_time_nsec = 0;
1183         unsigned int dvfs_buffering_reqd_bytes = 0;
1184         unsigned int thresh_dvfs_bytes = 0;
1185         unsigned int total_buf_sz_bytes = 0;
1186         unsigned int effective_mccif_buf_sz = 0;
1187         unsigned int la_bw_upper_bound_nsec_fp = 0;
1188         unsigned int la_bw_upper_bound_nsec = 0;
1189         unsigned int la_nsec = 0;
1190
1191         if (!is_display_client(id)) {
1192                 /* Non-display clients should be handled by t12x_set_la(...). */
1193                 return -1;
1194         }
1195
1196         mutex_lock(&disp_and_camera_ptsa_lock);
1197         total_dc0_bw = disp_params.total_dc0_bw;
1198         total_dc1_bw = disp_params.total_dc1_bw;
1199         cs->update_display_ptsa_rate(cs->disp_bw_array);
1200         mutex_unlock(&disp_and_camera_ptsa_lock);
1201
1202         idx = cs->id_to_index[id];
1203         ci = &cs->la_info_array[idx];
1204         la_to_set = 0;
1205         emc_clk = clk_get(NULL, "emc");
1206         emc_freq_mhz = clk_get_rate(emc_clk) /
1207                         T12X_LA_HZ_TO_MHZ_FACTOR;
1208         dvfs_time_nsec = tegra_get_dvfs_time_nsec(emc_freq_mhz);
1209         dvfs_buffering_reqd_bytes = bw_mbps *
1210                                         dvfs_time_nsec /
1211                                         T12X_LA_USEC_TO_NSEC_FACTOR;
1212         thresh_dvfs_bytes =
1213                         disp_params.thresh_lwm_bytes +
1214                         dvfs_buffering_reqd_bytes +
1215                         disp_params.spool_up_buffering_adj_bytes;
1216         total_buf_sz_bytes =
1217                 cs->disp_clients[DISP_CLIENT_LA_ID(id)].line_buf_sz_bytes +
1218                 cs->disp_clients[DISP_CLIENT_LA_ID(id)].mccif_size_bytes;
1219         effective_mccif_buf_sz =
1220                 (cs->disp_clients[DISP_CLIENT_LA_ID(id)].line_buf_sz_bytes >
1221                 thresh_dvfs_bytes) ?
1222                 cs->disp_clients[DISP_CLIENT_LA_ID(id)].mccif_size_bytes :
1223                 total_buf_sz_bytes - thresh_dvfs_bytes;
1224
1225         la_bw_upper_bound_nsec_fp = effective_mccif_buf_sz *
1226                                         T12X_LA_FP_FACTOR /
1227                                         bw_mbps;
1228         la_bw_upper_bound_nsec_fp = la_bw_upper_bound_nsec_fp *
1229                                         T12X_LA_FP_FACTOR /
1230                                         T12X_LA_DISP_CATCHUP_FACTOR_FP;
1231         la_bw_upper_bound_nsec_fp =
1232                 la_bw_upper_bound_nsec_fp -
1233                 (T12X_LA_STATIC_LA_MINUS_SNAP_ARB_TO_ROW_SRT_EMCCLKS_FP +
1234                 T12X_EXP_TIME_EMCCLKS_FP) /
1235                 emc_freq_mhz;
1236         la_bw_upper_bound_nsec_fp *= T12X_LA_USEC_TO_NSEC_FACTOR;
1237         la_bw_upper_bound_nsec = T12X_LA_FP_TO_REAL(
1238                                                 la_bw_upper_bound_nsec_fp);
1239
1240
1241         la_nsec = min(la_bw_upper_bound_nsec,
1242                         (unsigned int)T12X_MAX_LA_NSEC);
1243
1244         la_to_set = min(la_nsec / cs->ns_per_tick,
1245                         (unsigned int)T12X_MC_LA_MAX_VALUE);
1246
1247         program_la(ci, la_to_set);
1248         return 0;
1249 }
1250
1251 static int t12x_la_suspend(void)
1252 {
1253         int i = 0;
1254         struct la_client_info *ci = NULL;
1255
1256         /* stashing LA and PTSA from registers is necessary
1257          * in order to get latest values programmed by DVFS.
1258          */
1259         for (i = 0; i < cs->la_info_array_size; i++) {
1260                 ci = &cs->la_info_array[i];
1261                 ci->la_set = (readl(ci->reg_addr) & ci->mask) >>
1262                                 ci->shift;
1263         }
1264
1265         save_ptsa();
1266         return 0;
1267 }
1268
1269 static void t12x_la_resume(void)
1270 {
1271         int i;
1272
1273         for (i = 0; i < cs->la_info_array_size; i++) {
1274                 if (cs->la_info_array[i].la_set)
1275                         program_la(&cs->la_info_array[i],
1276                                         cs->la_info_array[i].la_set);
1277         }
1278         program_ptsa();
1279 }
1280
1281 void tegra_la_get_t12x_specific(struct la_chip_specific *cs_la)
1282 {
1283         int i = 0;
1284
1285         cs_la->ns_per_tick = 30;
1286         cs_la->atom_size = 64;
1287         cs_la->la_max_value = T12X_MC_LA_MAX_VALUE;
1288         cs_la->la_info_array = t12x_la_info_array;
1289         cs_la->la_info_array_size = ARRAY_SIZE(t12x_la_info_array);
1290
1291         cs_la->la_params.fp_factor = T12X_LA_FP_FACTOR;
1292         cs_la->la_params.la_real_to_fp = tegra12x_la_real_to_fp;
1293         cs_la->la_params.la_fp_to_real = tegra12x_la_fp_to_real;
1294         cs_la->la_params.static_la_minus_snap_arb_to_row_srt_emcclks_fp =
1295                         T12X_LA_STATIC_LA_MINUS_SNAP_ARB_TO_ROW_SRT_EMCCLKS_FP;
1296         cs_la->la_params.dram_width_bits = T12X_LA_DRAM_WIDTH_BITS;
1297         cs_la->la_params.disp_catchup_factor_fp =
1298                                                 T12X_LA_DISP_CATCHUP_FACTOR_FP;
1299
1300         cs_la->init_ptsa = t12x_init_ptsa;
1301         cs_la->update_display_ptsa_rate = t12x_update_display_ptsa_rate;
1302         cs_la->update_camera_ptsa_rate = t12x_update_camera_ptsa_rate;
1303         cs_la->set_la = t12x_set_la;
1304         cs_la->set_disp_la = t12x_set_disp_la;
1305         cs_la->suspend = t12x_la_suspend;
1306         cs_la->resume = t12x_la_resume;
1307         cs = cs_la;
1308
1309         tegra_la_disp_clients_info = cs_la->disp_clients;
1310
1311         /* set some entries to zero */
1312         for (i = 0; i < NUM_CAMERA_CLIENTS; i++)
1313                 cs_la->camera_bw_array[i] = 0;
1314         for (i = 0; i < TEGRA_LA_AGG_CAMERA_NUM_CLIENTS; i++) {
1315                 cs_la->agg_camera_array[i].bw_fp = 0;
1316                 cs_la->agg_camera_array[i].frac_fp = 0;
1317                 cs_la->agg_camera_array[i].ptsa_min = 0;
1318                 cs_la->agg_camera_array[i].ptsa_max = 0;
1319                 cs_la->agg_camera_array[i].is_hiso = false;
1320         }
1321
1322         /* set mccif_size_bytes values */
1323         cs_la->disp_clients[DISP_CLIENT_ID(DISPLAY_0A)].mccif_size_bytes = 4096;
1324         cs_la->disp_clients[DISP_CLIENT_ID(DISPLAY_0B)].mccif_size_bytes = 5760;
1325         cs_la->disp_clients[DISP_CLIENT_ID(DISPLAY_0C)].mccif_size_bytes = 4096;
1326         cs_la->disp_clients[DISP_CLIENT_ID(DISPLAY_HC)].mccif_size_bytes = 2048;
1327         cs_la->disp_clients[DISP_CLIENT_ID(DISPLAY_0AB)].mccif_size_bytes =
1328                                                                         4096;
1329         cs_la->disp_clients[DISP_CLIENT_ID(DISPLAY_0BB)].mccif_size_bytes =
1330                                                                         4096;
1331         cs_la->disp_clients[DISP_CLIENT_ID(DISPLAY_0CB)].mccif_size_bytes =
1332                                                                         4096;
1333         cs_la->disp_clients[DISP_CLIENT_ID(DISPLAY_HCB)].mccif_size_bytes =
1334                                                                         2048;
1335         cs_la->disp_clients[DISP_CLIENT_ID(DISPLAY_T)].mccif_size_bytes = 4096;
1336         cs_la->disp_clients[DISP_CLIENT_ID(DISPLAYD)].mccif_size_bytes = 4096;
1337
1338         /* set line_buf_sz_bytes values */
1339         cs_la->disp_clients[DISP_CLIENT_ID(DISPLAY_0A)].line_buf_sz_bytes =
1340                                                                         133632;
1341         cs_la->disp_clients[DISP_CLIENT_ID(DISPLAY_0B)].line_buf_sz_bytes =
1342                                                                         53248;
1343         cs_la->disp_clients[DISP_CLIENT_ID(DISPLAY_0C)].line_buf_sz_bytes =
1344                                                                         53248;
1345         cs_la->disp_clients[DISP_CLIENT_ID(DISPLAY_HC)].line_buf_sz_bytes = 320;
1346         cs_la->disp_clients[DISP_CLIENT_ID(DISPLAY_0AB)].line_buf_sz_bytes =
1347                                                                         49152;
1348         cs_la->disp_clients[DISP_CLIENT_ID(DISPLAY_0BB)].line_buf_sz_bytes =
1349                                                                         49152;
1350         cs_la->disp_clients[DISP_CLIENT_ID(DISPLAY_0CB)].line_buf_sz_bytes =
1351                                                                         49152;
1352         cs_la->disp_clients[DISP_CLIENT_ID(DISPLAY_HCB)].line_buf_sz_bytes =
1353                                                                         320;
1354         cs_la->disp_clients[DISP_CLIENT_ID(DISPLAY_T)].line_buf_sz_bytes = 6144;
1355         cs_la->disp_clients[DISP_CLIENT_ID(DISPLAYD)].line_buf_sz_bytes = 6144;
1356
1357         /* set win_type values */
1358         cs_la->disp_clients[DISP_CLIENT_ID(DISPLAY_0A)].win_type =
1359                                                 TEGRA_LA_DISP_WIN_TYPE_FULL;
1360         cs_la->disp_clients[DISP_CLIENT_ID(DISPLAY_0B)].win_type =
1361                                                 TEGRA_LA_DISP_WIN_TYPE_FULLA;
1362         cs_la->disp_clients[DISP_CLIENT_ID(DISPLAY_0C)].win_type =
1363                                                 TEGRA_LA_DISP_WIN_TYPE_FULLA;
1364         cs_la->disp_clients[DISP_CLIENT_ID(DISPLAY_HC)].win_type =
1365                                                 TEGRA_LA_DISP_WIN_TYPE_CURSOR;
1366         cs_la->disp_clients[DISP_CLIENT_ID(DISPLAY_0AB)].win_type =
1367                                                 TEGRA_LA_DISP_WIN_TYPE_FULLB;
1368         cs_la->disp_clients[DISP_CLIENT_ID(DISPLAY_0BB)].win_type =
1369                                                 TEGRA_LA_DISP_WIN_TYPE_FULLB;
1370         cs_la->disp_clients[DISP_CLIENT_ID(DISPLAY_0CB)].win_type =
1371                                                 TEGRA_LA_DISP_WIN_TYPE_FULLB;
1372         cs_la->disp_clients[DISP_CLIENT_ID(DISPLAY_HCB)].win_type =
1373                                                 TEGRA_LA_DISP_WIN_TYPE_CURSOR;
1374         cs_la->disp_clients[DISP_CLIENT_ID(DISPLAY_T)].win_type =
1375                                                 TEGRA_LA_DISP_WIN_TYPE_SIMPLE;
1376         cs_la->disp_clients[DISP_CLIENT_ID(DISPLAYD)].win_type =
1377                                                 TEGRA_LA_DISP_WIN_TYPE_SIMPLE;
1378 }