ARM: tegra: loki: fix build error due to warning
[linux-3.10.git] / arch / arm / mach-tegra / tegra12_speedo.c
1 /*
2  * arch/arm/mach-tegra/tegra12_speedo.c
3  *
4  * Copyright (C) 2013 NVIDIA Corporation. All rights reserved.
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License as published by
8  * the Free Software Foundation; version 2 of the License.
9  *
10  * This program is distributed in the hope that it will be useful, but WITHOUT
11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13  * more details.
14  *
15  * You should have received a copy of the GNU General Public License along
16  * with this program; if not, write to the Free Software Foundation, Inc.,
17  * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
18  *
19  */
20
21 #include <linux/kernel.h>
22 #include <linux/io.h>
23 #include <linux/err.h>
24 #include <linux/bug.h>                  /* For BUG_ON.  */
25
26 #include <mach/tegra_fuse.h>
27 #include <linux/tegra-soc.h>
28 #include <linux/module.h>
29 #include <linux/moduleparam.h>
30
31 #include "fuse.h"
32 #include "iomap.h"
33
34 #define TEGRA124_CPU_SPEEDO 2271 /* FIXME: Get Correct Value */
35
36 #define CPU_PROCESS_CORNERS_NUM         2
37 #define GPU_PROCESS_CORNERS_NUM         2
38 #define CORE_PROCESS_CORNERS_NUM                2
39
40 #define FUSE_CPU_SPEEDO_0       0x114
41 #define FUSE_CPU_SPEEDO_1       0x12c
42 #define FUSE_CPU_SPEEDO_2       0x130
43 #define FUSE_SOC_SPEEDO_0       0x134
44 #define FUSE_SOC_SPEEDO_1       0x138
45 #define FUSE_SOC_SPEEDO_2       0x13c
46 #define FUSE_CPU_IDDQ           0x118
47 #define FUSE_SOC_IDDQ           0x140
48 #define FUSE_GPU_IDDQ           0x228
49 #define FUSE_FT_REV             0x128
50
51 static int threshold_index;
52 static int cpu_process_id;
53 static int core_process_id;
54 static int gpu_process_id;
55 static int cpu_speedo_id;
56 static int cpu_speedo_value;
57 static int soc_speedo_id;
58 static int gpu_speedo_id;
59 static int package_id;
60 static int cpu_iddq_value;
61 static int gpu_iddq_value;
62 static int soc_iddq_value;
63
64 static int cpu_speedo_0_value;
65 static int cpu_speedo_1_value;
66 static int soc_speedo_0_value;
67 static int soc_speedo_1_value;
68 static int soc_speedo_2_value;
69
70 static int gpu_speedo_value;
71
72 static int enable_app_profiles;
73
74 static const u32 cpu_process_speedos[][CPU_PROCESS_CORNERS_NUM] = {
75 /* proc_id  0,  1 */
76         {2190,  UINT_MAX}, /* [0]: threshold_index 0 */
77         {0,     UINT_MAX}, /* [1]: threshold_index 0 */
78 };
79
80 static const u32 gpu_process_speedos[][GPU_PROCESS_CORNERS_NUM] = {
81 /* proc_id  0,  1 */
82         {1965,  UINT_MAX}, /* [0]: threshold_index 0 */
83         {0,     UINT_MAX}, /* [1]: threshold_index 0 */
84 };
85
86 static const u32 core_process_speedos[][CORE_PROCESS_CORNERS_NUM] = {
87 /* proc_id  0,  1 */
88         {2101,  UINT_MAX}, /* [0]: threshold_index 0 */
89         {0,     UINT_MAX}, /* [1]: threshold_index 0 */
90 };
91
92 static void rev_sku_to_speedo_ids(int rev, int sku)
93 {
94         switch (sku) {
95         case 0x00: /* Engg sku */
96         case 0x0F:
97                 cpu_speedo_id = 0;
98                 soc_speedo_id = 0;
99                 gpu_speedo_id = 0;
100                 threshold_index = 0;
101                 break;
102         case 0x07:
103         case 0x81:
104                 cpu_speedo_id = 1;
105                 soc_speedo_id = 1;
106                 gpu_speedo_id = 1;
107                 threshold_index = 1;
108                 break;
109         default:
110                 pr_warn("Tegra12: Unknown SKU %d\n", sku);
111                 cpu_speedo_id = 0;
112                 soc_speedo_id = 0;
113                 gpu_speedo_id = 0;
114                 threshold_index = 0;
115                 break;
116         }
117 }
118
119 void tegra_init_speedo_data(void)
120 {
121         int i;
122
123         if (!tegra_platform_is_silicon()) {
124                 cpu_process_id  =  0;
125                 core_process_id =  0;
126                 gpu_process_id  = 0;
127                 cpu_speedo_id   = 0;
128                 soc_speedo_id   = 0;
129                 gpu_speedo_id   = 0;
130                 package_id = -1;
131                 cpu_speedo_value = 1777;
132                 cpu_speedo_0_value = 0;
133                 cpu_speedo_1_value = 0;
134                 soc_speedo_0_value = 0;
135                 soc_speedo_1_value = 0;
136                 soc_speedo_2_value = 0;
137                 soc_iddq_value = 0;
138                 gpu_iddq_value = 0;
139                 return;
140         }
141
142         cpu_speedo_0_value = tegra_fuse_readl(FUSE_CPU_SPEEDO_0);
143         cpu_speedo_1_value = tegra_fuse_readl(FUSE_CPU_SPEEDO_1);
144
145         /* GPU Speedo is stored in CPU_SPEEDO_2 */
146         gpu_speedo_value = tegra_fuse_readl(FUSE_CPU_SPEEDO_2);
147
148         soc_speedo_0_value = tegra_fuse_readl(FUSE_SOC_SPEEDO_0);
149         soc_speedo_1_value = tegra_fuse_readl(FUSE_SOC_SPEEDO_1);
150         soc_speedo_2_value = tegra_fuse_readl(FUSE_SOC_SPEEDO_2);
151
152         cpu_iddq_value = tegra_fuse_readl(FUSE_CPU_IDDQ);
153         soc_iddq_value = tegra_fuse_readl(FUSE_SOC_IDDQ);
154         gpu_iddq_value = tegra_fuse_readl(FUSE_GPU_IDDQ);
155
156         /* cpu_speedo_value = TEGRA124_CPU_SPEEDO; */
157         cpu_speedo_value = cpu_speedo_0_value;
158
159         if (cpu_speedo_value == 0) {
160                 cpu_speedo_value = 1900;
161                 pr_warn("Tegra12: Warning: Speedo value not fused. PLEASE FIX!!!!!!!!!!!\n");
162                 pr_warn("Tegra12: Warning: PLEASE USE BOARD WITH FUSED SPEEDO VALUE !!!!\n");
163         }
164
165         rev_sku_to_speedo_ids(tegra_revision, tegra_sku_id);
166
167         for (i = 0; i < GPU_PROCESS_CORNERS_NUM; i++) {
168                 if (gpu_speedo_value <
169                         gpu_process_speedos[threshold_index][i]) {
170                         break;
171                 }
172         }
173         gpu_process_id = i;
174
175         for (i = 0; i < CPU_PROCESS_CORNERS_NUM; i++) {
176                 if (cpu_speedo_value <
177                         cpu_process_speedos[threshold_index][i]) {
178                         break;
179                 }
180         }
181         cpu_process_id = i;
182
183         for (i = 0; i < CORE_PROCESS_CORNERS_NUM; i++) {
184                 if (soc_speedo_0_value <
185                         core_process_speedos[threshold_index][i]) {
186                         break;
187                 }
188         }
189         core_process_id = i;
190
191         pr_info("Tegra12: CPU Speedo ID %d, Soc Speedo ID %d, Gpu Speedo ID %d\n",
192                 cpu_speedo_id, soc_speedo_id, gpu_speedo_id);
193         pr_info("Tegra12: CPU Process ID %d,Soc Process ID %d,Gpu Process ID %d\n",
194                  cpu_process_id, core_process_id, gpu_process_id);
195 }
196
197 int tegra_cpu_process_id(void)
198 {
199         return cpu_process_id;
200 }
201
202 int tegra_core_process_id(void)
203 {
204         return core_process_id;
205 }
206
207 int tegra_gpu_process_id(void)
208 {
209         return gpu_process_id;
210 }
211
212 int tegra_cpu_speedo_id(void)
213 {
214         return cpu_speedo_id;
215 }
216
217 int tegra_soc_speedo_id(void)
218 {
219         return soc_speedo_id;
220 }
221
222 int tegra_gpu_speedo_id(void)
223 {
224         return gpu_speedo_id;
225 }
226
227 int tegra_package_id(void)
228 {
229         return package_id;
230 }
231
232 int tegra_cpu_speedo_value(void)
233 {
234         return cpu_speedo_value;
235 }
236
237 int tegra_cpu_speedo_0_value(void)
238 {
239         return cpu_speedo_0_value;
240 }
241
242 int tegra_cpu_speedo_1_value(void)
243 {
244         return cpu_speedo_1_value;
245 }
246
247 int tegra_gpu_speedo_value(void)
248 {
249         return gpu_speedo_value;
250 }
251
252 int tegra_soc_speedo_0_value(void)
253 {
254         return soc_speedo_0_value;
255 }
256
257 int tegra_soc_speedo_1_value(void)
258 {
259         return soc_speedo_1_value;
260 }
261
262 int tegra_soc_speedo_2_value(void)
263 {
264         return soc_speedo_2_value;
265 }
266 /*
267  * CPU and core nominal voltage levels as determined by chip SKU and speedo
268  * (not final - can be lowered by dvfs tables and rail dependencies; the
269  * latter is resolved by the dvfs code)
270  */
271 int tegra_cpu_speedo_mv(void)
272 {
273         /* Not applicable on Tegra12 */
274         return -ENOSYS;
275 }
276
277 int tegra_core_speedo_mv(void)
278 {
279         switch (soc_speedo_id) {
280         case 0:
281                 return 1150;
282         case 1:
283                 return 1150;
284         default:
285                 BUG();
286         }
287 }
288
289 int tegra_get_cpu_iddq_value(void)
290 {
291         return cpu_iddq_value;
292 }
293
294 int tegra_get_soc_iddq_value(void)
295 {
296         return soc_iddq_value;
297 }
298
299 int tegra_get_gpu_iddq_value(void)
300 {
301         return gpu_iddq_value;
302 }
303
304 static int get_enable_app_profiles(char *val, const struct kernel_param *kp)
305 {
306         return param_get_uint(val, kp);
307 }
308
309 static struct kernel_param_ops tegra_profiles_ops = {
310         .get = get_enable_app_profiles,
311 };
312
313 module_param_cb(tegra_enable_app_profiles,
314         &tegra_profiles_ops, &enable_app_profiles, 0444);