ARM: tegra12: set CPU rate to 2.2GHz for sku 0x87
[linux-3.10.git] / arch / arm / mach-tegra / tegra12_emc.h
1 /*
2  * arch/arm/mach-tegra/tegra12_emc.h
3  *
4  * Copyright (c) 2013, NVIDIA CORPORATION.  All rights reserved.
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License as published by
8  * the Free Software Foundation; either version 2 of the License, or
9  * (at your option) any later version.
10  *
11  * This program is distributed in the hope that it will be useful, but WITHOUT
12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
14  * more details.
15  *
16  * You should have received a copy of the GNU General Public License along
17  * with this program; if not, write to the Free Software Foundation, Inc.,
18  * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
19  *
20  */
21
22 #ifndef _MACH_TEGRA_TEGRA12_EMC_H
23 #define _MACH_TEGRA_TEGRA12_EMC_H
24
25 #include "tegra_emc.h"
26 #include <linux/platform_data/tegra_emc.h>
27
28 int tegra12_emc_init(void);
29
30 #ifdef CONFIG_TEGRA_USE_NCT
31 extern int tegra12_nct_emc_table_init(struct tegra12_emc_pdata *nct_emc_pdata);
32 #endif
33
34 enum {
35         DRAM_DEV_SEL_ALL = 0,
36         DRAM_DEV_SEL_0   = (2 << 30),
37         DRAM_DEV_SEL_1   = (1 << 30),
38 };
39
40 void tegra12_mc_holdoff_enable(void);
41
42 #define DRAM_BROADCAST(num)                     \
43         (((num) > 1) ? DRAM_DEV_SEL_ALL : DRAM_DEV_SEL_0)
44
45 #define EMC_INTSTATUS                           0x0
46 #define EMC_INTSTATUS_CLKCHANGE_COMPLETE        (0x1 << 4)
47
48 #define EMC_DBG                                 0x8
49 #define EMC_DBG_WRITE_MUX_ACTIVE                (0x1 << 1)
50
51 #define EMC_CFG                                 0xc
52 #define EMC_CFG_DRAM_CLKSTOP_PD         (0x1 << 31)
53 #define EMC_CFG_DRAM_CLKSTOP_SR         (0x1 << 30)
54 #define EMC_CFG_DRAM_ACPD                       (0x1 << 29)
55 #define EMC_CFG_DYN_SREF                        (0x1 << 28)
56 #define EMC_CFG_PWR_MASK                        ((0xF << 28) | (0x1 << 18))
57 #define EMC_CFG_REQACT_ASYNC            (0x1 << 26)
58 #define EMC_CFG_AUTO_PRE_WR                     (0x1 << 25)
59 #define EMC_CFG_AUTO_PRE_RD                     (0x1 << 24)
60 #define EMC_CFG_MAM_PRE_WR                      (0x1 << 23)
61 #define EMC_CFG_MAN_PRE_RD                      (0x1 << 22)
62 #define EMC_CFG_PERIODIC_QRST                   (0x1 << 21)
63 #define EMC_CFG_EN_DYNAMIC_PUTERM               (0x1 << 20)
64 #define EMC_CFG_DLY_WR_DQ_HALF_CLOCK            (0x1 << 19)
65 #define EMC_CFG_DSR_VTTGEN_DRV_EN               (0x1 << 18)
66 #define EMC_CFG_EMC2MC_CLK_RATIO                (0x3 << 16)
67 #define EMC_CFG_WAIT_FOR_ISP2B_READY_B4_CC      (0x1 << 9)
68 #define EMC_CFG_WAIT_FOR_VI2_READY_B4_CC        (0x1 << 8)
69 #define EMC_CFG_WAIT_FOR_ISP2_READY_B4_CC       (0x1 << 7)
70 #define EMC_CFG_INVERT_DQM                      (0x1 << 6)
71 #define EMC_CFG_WAIT_FOR_DISPLAYB_READY_B4_CC (0x1 << 5)
72 #define EMC_CFG_WAIT_FOR_DISPLAY_READY_B4_CC (0x1 << 4)
73 #define EMC_CFG_EMC2PMACRO_CFG_BYPASS_DATAPIPE2 (0x1 << 3)
74 #define EMC_CFG_EMC2PMACRO_CFG_BYPASS_DATAPIPE1 (0x1 << 2)
75 #define EMC_CFG_EMC2PMACRO_CFG_BYPASS_ADDRPIPE  (0x1 << 1)
76
77
78 #define EMC_ADR_CFG                             0x10
79 #define EMC_REFCTRL                             0x20
80 #define EMC_REFCTRL_DEV_SEL_SHIFT               0
81 #define EMC_REFCTRL_DEV_SEL_MASK                \
82         (0x3 << EMC_REFCTRL_DEV_SEL_SHIFT)
83 #define EMC_REFCTRL_ENABLE                      (0x1 << 31)
84 #define EMC_REFCTRL_ENABLE_ALL(num)             \
85         (((((num) > 1) ? 0 : 2) << EMC_REFCTRL_DEV_SEL_SHIFT) \
86          | EMC_REFCTRL_ENABLE)
87 #define EMC_REFCTRL_DISABLE_ALL(num)            \
88         ((((num) > 1) ? 0 : 2) << EMC_REFCTRL_DEV_SEL_SHIFT)
89
90 #define EMC_TIMING_CONTROL                      0x28
91 #define EMC_RC                                  0x2c
92 #define EMC_RFC                                 0x30
93 #define EMC_RAS                                 0x34
94 #define EMC_RP                                  0x38
95 #define EMC_R2W                                 0x3c
96 #define EMC_W2R                                 0x40
97 #define EMC_R2P                                 0x44
98 #define EMC_W2P                                 0x48
99 #define EMC_RD_RCD                              0x4c
100 #define EMC_WR_RCD                              0x50
101 #define EMC_RRD                                 0x54
102 #define EMC_REXT                                0x58
103 #define EMC_WDV                                 0x5c
104 #define EMC_QUSE                                0x60
105 #define EMC_QRST                                0x64
106 #define EMC_QSAFE                               0x68
107 #define EMC_RDV                                 0x6c
108 #define EMC_REFRESH                             0x70
109 #define EMC_BURST_REFRESH_NUM                   0x74
110 #define EMC_PDEX2WR                             0x78
111 #define EMC_PDEX2RD                             0x7c
112 #define EMC_PCHG2PDEN                           0x80
113 #define EMC_ACT2PDEN                            0x84
114 #define EMC_AR2PDEN                             0x88
115 #define EMC_RW2PDEN                             0x8c
116 #define EMC_TXSR                                0x90
117 #define EMC_TCKE                                0x94
118 #define EMC_TFAW                                0x98
119 #define EMC_TRPAB                               0x9c
120 #define EMC_TCLKSTABLE                          0xa0
121 #define EMC_TCLKSTOP                            0xa4
122 #define EMC_TREFBW                              0xa8
123 #define EMC_ODT_WRITE                           0xb0
124 #define EMC_ODT_READ                            0xb4
125 #define EMC_WEXT                                0xb8
126 #define EMC_CTT                                 0xbc
127 #define EMC_RFC_SLR                             0xc0
128 #define EMC_MRS_WAIT_CNT2                       0xc4
129
130 #define EMC_MRS_WAIT_CNT                        0xc8
131 #define EMC_MRS_WAIT_CNT_SHORT_WAIT_SHIFT       0
132 #define EMC_MRS_WAIT_CNT_SHORT_WAIT_MASK        \
133         (0x3FF << EMC_MRS_WAIT_CNT_SHORT_WAIT_SHIFT)
134 #define EMC_MRS_WAIT_CNT_LONG_WAIT_SHIFT        16
135 #define EMC_MRS_WAIT_CNT_LONG_WAIT_MASK         \
136         (0x3FF << EMC_MRS_WAIT_CNT_LONG_WAIT_SHIFT)
137
138 #define EMC_MRS                                 0xcc
139 #define EMC_MODE_SET_DLL_RESET                  (0x1 << 8)
140 #define EMC_MODE_SET_LONG_CNT                   (0x1 << 26)
141 #define EMC_EMRS                                0xd0
142 #define EMC_REF                                 0xd4
143 #define EMC_PRE                                 0xd8
144 #define EMC_NOP                                 0xdc
145
146 #define EMC_SELF_REF                            0xe0
147 #define EMC_SELF_REF_CMD_ENABLED                (0x1 << 0)
148 #define EMC_SELF_REF_DEV_SEL_SHIFT              30
149 #define EMC_SELF_REF_DEV_SEL_MASK               \
150         (0x3 << EMC_SELF_REF_DEV_SEL_SHIFT)
151
152 #define EMC_DPD                                 0xe4
153 #define EMC_MRW                                 0xe8
154
155 #define EMC_MRR                                 0xec
156 #define EMC_MRR_DEV_SEL_SHIFT                   30
157 #define EMC_MRR_DEV_SEL_MASK                    \
158         (0x3 << EMC_SELF_REF_DEV_SEL_SHIFT)
159 #define EMC_MRR_MA_SHIFT                        16
160 #define EMC_MRR_MA_MASK                         (0xFF << EMC_MRR_MA_SHIFT)
161 #define EMC_MRR_DATA_MASK                       ((0x1 << EMC_MRR_MA_SHIFT) - 1)
162 #define LPDDR2_MR4_TEMP_SHIFT                   0
163 #define LPDDR2_MR4_TEMP_MASK                    (0x7 << LPDDR2_MR4_TEMP_SHIFT)
164
165 #define EMC_CMDQ                                0xf0
166 #define EMC_MC2EMCQ                             0xf4
167 #define EMC_XM2DQSPADCTRL3                      0xf8
168 #define EMC_XM2DQSPADCTRL3_VREF_ENABLE          (0x1 << 5)
169 #define EMC_FBIO_SPARE                          0x100
170
171 #define EMC_FBIO_CFG5                           0x104
172 #define EMC_CFG5_TYPE_SHIFT                     0x0
173 #define EMC_CFG5_TYPE_MASK                      (0x3 << EMC_CFG5_TYPE_SHIFT)
174 enum {
175         DRAM_TYPE_DDR3   = 0,
176         DRAM_TYPE_LPDDR2 = 2,
177 };
178 #define EMC_CFG5_QUSE_MODE_SHIFT                13
179 #define EMC_CFG5_QUSE_MODE_MASK                 \
180         (0x7 << EMC_CFG5_QUSE_MODE_SHIFT)
181 enum {
182         EMC_CFG5_QUSE_MODE_NORMAL = 0,
183         EMC_CFG5_QUSE_MODE_ALWAYS_ON,
184         EMC_CFG5_QUSE_MODE_INTERNAL_LPBK,
185         EMC_CFG5_QUSE_MODE_PULSE_INTERN,
186         EMC_CFG5_QUSE_MODE_PULSE_EXTERN,
187         EMC_CFG5_QUSE_MODE_DIRECT_QUSE,
188 };
189
190 #define EMC_FBIO_WRPTR_EQ_2                     0x108
191 #define EMC_FBIO_CFG6                           0x114
192 #define EMC_CFG_RSV                             0x120
193 #define EMC_ACPD_CONTROL                        0x124
194 #define EMC_EMRS2                               0x12c
195 #define EMC_EMRS3                               0x130
196 #define EMC_MRW2                                0x134
197 #define EMC_MRW3                                0x138
198 #define EMC_MRW4                                0x13c
199 #define EMC_CLKEN_OVERRIDE                      0x140
200 #define EMC_R2R                                 0x144
201 #define EMC_W2W                                 0x148
202 #define EMC_EINPUT                              0x14c
203 #define EMC_EINPUT_DURATION                     0x150
204 #define EMC_PUTERM_EXTRA                        0x154
205 #define EMC_TCKESR                              0x158
206 #define EMC_TPD                                 0x15c
207
208 #define EMC_AUTO_CAL_CONFIG                     0x2a4
209 #define EMC_AUTO_CAL_CONFIG_AUTO_CAL_START_SHIFT 31
210 #define EMC_AUTO_CAL_INTERVAL                   0x2a8
211 #define EMC_AUTO_CAL_STATUS                     0x2ac
212 #define EMC_AUTO_CAL_STATUS_ACTIVE              (0x1 << 31)
213 #define EMC_AUTO_CAL_STATUS_SHIFT       31
214 #define EMC_REQ_CTRL                            0x2b0
215 #define EMC_STATUS                              0x2b4
216 #define EMC_STATUS_TIMING_UPDATE_STALLED        (0x1 << 23)
217 #define EMC_STATUS_MRR_DIVLD                    (0x1 << 20)
218
219 #define EMC_CFG_2                               0x2b8
220 #define EMC_CFG_2_MODE_SHIFT                    0
221 #define EMC_CFG_2_MODE_MASK                     (0x3 << EMC_CFG_2_MODE_SHIFT)
222 #define EMC_CFG_2_SREF_MODE                     0x1
223 #define EMC_CFG_2_PD_MODE                       0x3
224 #define EMC_CFG_2_DIS_STP_OB_CLK_DURING_NON_WR (0x1 << 6)
225
226 #define EMC_CFG_DIG_DLL                         0x2bc
227 #define EMC_CFG_DIG_DLL_PERIOD                  0x2c0
228 #define EMC_DIG_DLL_STATUS                      0x2c8
229 #define EMC_RDV_MASK                            0x2cc
230 #define EMC_WDV_MASK                            0x2d0
231 #define EMC_CTT_DURATION                        0x2d8
232 #define EMC_CTT_TERM_CTRL                       0x2dc
233 #define EMC_ZCAL_INTERVAL                       0x2e0
234 #define EMC_ZCAL_WAIT_CNT                       0x2e4
235 #define EMC_ZCAL_MRW_CMD                        0x2e8
236
237 #define EMC_ZQ_CAL                              0x2ec
238 #define EMC_ZQ_CAL_DEV_SEL_SHIFT                30
239 #define EMC_ZQ_CAL_DEV_SEL_MASK                 \
240         (0x3 << EMC_SELF_REF_DEV_SEL_SHIFT)
241 #define EMC_ZQ_CAL_CMD                          (0x1 << 0)
242 #define EMC_ZQ_CAL_LONG                         (0x1 << 4)
243 #define EMC_ZQ_CAL_LONG_CMD_DEV0                \
244         (DRAM_DEV_SEL_0 | EMC_ZQ_CAL_LONG | EMC_ZQ_CAL_CMD)
245 #define EMC_ZQ_CAL_LONG_CMD_DEV1                \
246         (DRAM_DEV_SEL_1 | EMC_ZQ_CAL_LONG | EMC_ZQ_CAL_CMD)
247
248 #define EMC_XM2CMDPADCTRL                       0x2f0
249 #define EMC_XM2CMDPADCTRL2                      0x2f4
250 #define EMC_XM2DQSPADCTRL                       0x2f8
251 #define EMC_XM2DQSPADCTRL2                      0x2fc
252 #define EMC_XM2DQSPADCTRL2_RX_FT_REC_ENABLE     (0x1 << 0)
253 #define EMC_XM2DQSPADCTRL2_VREF_ENABLE          (0x1 << 5)
254 #define EMC_XM2DQPADCTRL                        0x300
255 #define EMC_XM2DQPADCTRL2                       0x304
256 #define EMC_XM2CLKPADCTRL                       0x308
257 #define EMC_XM2COMPPADCTRL                      0x30c
258 #define EMC_XM2COMPPADCTRL_VREF_CAL_ENABLE      (0x1 << 10)
259 #define EMC_XM2VTTGENPADCTRL                    0x310
260 #define EMC_XM2VTTGENPADCTRL2                   0x314
261 #define EMC_XM2VTTGENPADCTRL3                   0x318
262 #define EMC_EMCPADEN                            0x31c
263 #define EMC_XM2DQSPADCTRL4                      0x320
264 #define EMC_SCRATCH0                            0x324
265 #define EMC_DLL_XFORM_DQS0                      0x328
266 #define EMC_DLL_XFORM_DQS1                      0x32c
267 #define EMC_DLL_XFORM_DQS2                      0x330
268 #define EMC_DLL_XFORM_DQS3                      0x334
269 #define EMC_DLL_XFORM_DQS4                      0x338
270 #define EMC_DLL_XFORM_DQS5                      0x33c
271 #define EMC_DLL_XFORM_DQS6                      0x340
272 #define EMC_DLL_XFORM_DQS7                      0x344
273 #define EMC_DLL_XFORM_QUSE0                     0x348
274 #define EMC_DLL_XFORM_QUSE1                     0x34c
275 #define EMC_DLL_XFORM_QUSE2                     0x350
276 #define EMC_DLL_XFORM_QUSE3                     0x354
277 #define EMC_DLL_XFORM_QUSE4                     0x358
278 #define EMC_DLL_XFORM_QUSE5                     0x35c
279 #define EMC_DLL_XFORM_QUSE6                     0x360
280 #define EMC_DLL_XFORM_QUSE7                     0x364
281 #define EMC_DLL_XFORM_DQ0                       0x368
282 #define EMC_DLL_XFORM_DQ1                       0x36c
283 #define EMC_DLL_XFORM_DQ2                       0x370
284 #define EMC_DLL_XFORM_DQ3                       0x374
285 #define EMC_DLI_RX_TRIM0                        0x378
286 #define EMC_DLI_RX_TRIM1                        0x37c
287 #define EMC_DLI_RX_TRIM2                        0x380
288 #define EMC_DLI_RX_TRIM3                        0x384
289 #define EMC_DLI_RX_TRIM4                        0x388
290 #define EMC_DLI_RX_TRIM5                        0x38c
291 #define EMC_DLI_RX_TRIM6                        0x390
292 #define EMC_DLI_RX_TRIM7                        0x394
293 #define EMC_DLI_TX_TRIM0                        0x398
294 #define EMC_DLI_TX_TRIM1                        0x39c
295 #define EMC_DLI_TX_TRIM2                        0x3a0
296 #define EMC_DLI_TX_TRIM3                        0x3a4
297 #define EMC_DLI_TRIM_TXDQS0                     0x3a8
298 #define EMC_DLI_TRIM_TXDQS1                     0x3ac
299 #define EMC_DLI_TRIM_TXDQS2                     0x3b0
300 #define EMC_DLI_TRIM_TXDQS3                     0x3b4
301 #define EMC_DLI_TRIM_TXDQS4                     0x3b8
302 #define EMC_DLI_TRIM_TXDQS5                     0x3bc
303 #define EMC_DLI_TRIM_TXDQS6                     0x3c0
304 #define EMC_DLI_TRIM_TXDQS7                     0x3c4
305 #define EMC_STALL_THEN_EXE_AFTER_CLKCHANGE      0x3cc
306 #define EMC_AUTO_CAL_CLK_STATUS                 0x3d4
307 #define EMC_SEL_DPD_CTRL                        0x3d8
308 #define EMC_SEL_DPD_CTRL_DATA_SEL_DPD   (0x1 << 8)
309 #define EMC_SEL_DPD_CTRL_ODT_SEL_DPD    (0x1 << 5)
310 #define EMC_SEL_DPD_CTRL_RESET_SEL_DPD  (0x1 << 4)
311 #define EMC_SEL_DPD_CTRL_CA_SEL_DPD     (0x1 << 3)
312 #define EMC_SEL_DPD_CTRL_CLK_SEL_DPD    (0x1 << 2)
313 #define EMC_SEL_DPD_CTRL_DDR3_MASK      \
314         ((0xf << 2) | (0x1 << 8))
315 #define EMC_SEL_DPD_CTRL_MASK \
316         ((0x3 << 2) | (0x1 << 5) | (0x1 << 8))
317 #define EMC_PRE_REFRESH_REQ_CNT                 0x3dc
318 #define EMC_DYN_SELF_REF_CONTROL                0x3e0
319 #define EMC_TXSRDLL                             0x3e4
320 #define EMC_CCFIFO_ADDR                         0x3e8
321 #define EMC_CCFIFO_DATA                         0x3ec
322 #define EMC_CCFIFO_STATUS                       0x3f0
323 #define EMC_CDB_CNTL_1                          0x3f4
324 #define EMC_CDB_CNTL_2                          0x3f8
325 #define EMC_XM2CLKPADCTRL2                      0x3fc
326 #define EMC_SWIZZLE_RANK0_BYTE_CFG              0x400
327 #define EMC_SWIZZLE_RANK0_BYTE0                 0x404
328 #define EMC_SWIZZLE_RANK0_BYTE1                 0x408
329 #define EMC_SWIZZLE_RANK0_BYTE2                 0x40c
330 #define EMC_SWIZZLE_RANK0_BYTE3                 0x410
331 #define EMC_SWIZZLE_RANK1_BYTE_CFG              0x414
332 #define EMC_SWIZZLE_RANK1_BYTE0                 0x418
333 #define EMC_SWIZZLE_RANK1_BYTE1                 0x41c
334 #define EMC_SWIZZLE_RANK1_BYTE2                 0x420
335 #define EMC_SWIZZLE_RANK1_BYTE3                 0x424
336 #define EMC_CA_TRAINING_START                   0x428
337 #define EMC_CA_TRAINING_BUSY                    0x42c
338 #define EMC_CA_TRAINING_CFG                     0x430
339 #define EMC_CA_TRAINING_TIMING_CNTL1            0x434
340 #define EMC_CA_TRAINING_TIMING_CNTL2            0x438
341 #define EMC_CA_TRAINING_CA_LEAD_IN              0x43c
342 #define EMC_CA_TRAINING_CA                      0x440
343 #define EMC_CA_TRAINING_CA_LEAD_OUT             0x444
344 #define EMC_CA_TRAINING_RESULT1                 0x448
345 #define EMC_CA_TRAINING_RESULT2                 0x44c
346 #define EMC_CA_TRAINING_RESULT3                 0x450
347 #define EMC_CA_TRAINING_RESULT4                 0x454
348 #define EMC_AUTO_CAL_CONFIG2                    0x458
349 #define EMC_AUTO_CAL_CONFIG3                    0x45c
350 #define EMC_AUTO_CAL_STATUS2                    0x460
351 #define EMC_XM2CMDPADCTRL3                      0x464
352 #define EMC_IBDLY                               0x468
353 #define EMC_DLL_XFORM_ADDR0                     0x46c
354 #define EMC_DLL_XFORM_ADDR1                     0x470
355 #define EMC_DLL_XFORM_ADDR2                     0x474
356 #define EMC_DLI_ADDR_TRIM                       0x478
357 #define EMC_DSR_VTTGEN_DRV                      0x47c
358 #define EMC_TXDSRVTTGEN                         0x480
359 #define EMC_XM2CMDPADCTRL4                      0x484
360 #define EMC_XM2CMDPADCTRL5                      0x488
361 #define EMC_DLL_XFORM_DQS8                      0x4a0
362 #define EMC_DLL_XFORM_DQS9                      0x4a4
363 #define EMC_DLL_XFORM_DQS10                     0x4a8
364 #define EMC_DLL_XFORM_DQS11                     0x4ac
365 #define EMC_DLL_XFORM_DQS12                     0x4b0
366 #define EMC_DLL_XFORM_DQS13                     0x4b4
367 #define EMC_DLL_XFORM_DQS14                     0x4b8
368 #define EMC_DLL_XFORM_DQS15                     0x4bc
369 #define EMC_DLL_XFORM_QUSE8                     0x4c0
370 #define EMC_DLL_XFORM_QUSE9                     0x4c4
371 #define EMC_DLL_XFORM_QUSE10                    0x4c8
372 #define EMC_DLL_XFORM_QUSE11                    0x4cc
373 #define EMC_DLL_XFORM_QUSE12                    0x4d0
374 #define EMC_DLL_XFORM_QUSE13                    0x4d4
375 #define EMC_DLL_XFORM_QUSE14                    0x4d8
376 #define EMC_DLL_XFORM_QUSE15                    0x4dc
377 #define EMC_DLL_XFORM_DQ4                               0x4e0
378 #define EMC_DLL_XFORM_DQ5                               0x4e4
379 #define EMC_DLL_XFORM_DQ6                               0x4e8
380 #define EMC_DLL_XFORM_DQ7                               0x4ec
381 #define EMC_DLI_TRIM_TXDQS8                             0x520
382 #define EMC_DLI_TRIM_TXDQS9                             0x524
383 #define EMC_DLI_TRIM_TXDQS10                            0x528
384 #define EMC_DLI_TRIM_TXDQS11                            0x52c
385 #define EMC_DLI_TRIM_TXDQS12                            0x530
386 #define EMC_DLI_TRIM_TXDQS13                            0x534
387 #define EMC_DLI_TRIM_TXDQS14                            0x538
388 #define EMC_DLI_TRIM_TXDQS15                            0x53c
389 #define EMC_CDB_CNTL_3                          0x540
390 #define EMC_XM2DQSPADCTRL5                      0x544
391 #define EMC_XM2DQSPADCTRL6                      0x548
392 #define EMC_XM2DQPADCTRL3                       0x54c
393 #define EMC_DLL_XFORM_ADDR3                     0x550
394 #define EMC_DLL_XFORM_ADDR4                     0x554
395 #define EMC_DLL_XFORM_ADDR5                     0x558
396 #define EMC_CFG_PIPE                            0x560
397 #define EMC_QPOP                                        0x564
398 #define EMC_QUSE_WIDTH                          0x568
399 #define EMC_PUTERM_WIDTH                        0x56c
400 #define EMC_BGBIAS_CTL0                         0x570
401 #define EMC_BGBIAS_CTL0_BIAS0_DSC_E_PWRD_IBIAS_RX_SHIFT 0x3
402 #define EMC_BGBIAS_CTL0_BIAS0_DSC_E_PWRD_IBIAS_VTTGEN_SHIFT     0x2
403 #define EMC_BGBIAS_CTL0_BIAS0_DSC_E_PWRD_SHIFT  0x1
404 #define EMC_PUTERM_ADJ                          0x574
405
406 #define MC_EMEM_CFG                             0x50
407 #define MC_EMEM_ADR_CFG                         0x54
408 #define MC_EMEM_ADR_CFG_DEV0                    0x58
409 #define MC_EMEM_ADR_CFG_DEV1                    0x5c
410 #define MC_EMEM_ADR_CFG_BANK_MASK_0             0x64
411 #define MC_EMEM_ADR_CFG_BANK_MASK_1             0x68
412 #define MC_EMEM_ADR_CFG_BANK_MASK_2             0x6c
413
414 #define MC_EMEM_ARB_CFG                         0x90
415 #define MC_EMEM_ARB_OUTSTANDING_REQ             0x94
416 #define MC_EMEM_ARB_TIMING_RCD                  0x98
417 #define MC_EMEM_ARB_TIMING_RP                   0x9c
418 #define MC_EMEM_ARB_TIMING_RC                   0xa0
419 #define MC_EMEM_ARB_TIMING_RAS                  0xa4
420 #define MC_EMEM_ARB_TIMING_FAW                  0xa8
421 #define MC_EMEM_ARB_TIMING_RRD                  0xac
422 #define MC_EMEM_ARB_TIMING_RAP2PRE              0xb0
423 #define MC_EMEM_ARB_TIMING_WAP2PRE              0xb4
424 #define MC_EMEM_ARB_TIMING_R2R                  0xb8
425 #define MC_EMEM_ARB_TIMING_W2W                  0xbc
426 #define MC_EMEM_ARB_TIMING_R2W                  0xc0
427 #define MC_EMEM_ARB_TIMING_W2R                  0xc4
428 #define MC_EMEM_ARB_DA_TURNS                    0xd0
429 #define MC_EMEM_ARB_DA_COVERS                   0xd4
430 #define MC_EMEM_ARB_MISC0                       0xd8
431 #define MC_EMEM_ARB_MISC0_EMC_SAME_FREQ         (0x1 << 27)
432 #define MC_EMEM_ARB_MISC1                       0xdc
433 #define MC_EMEM_ARB_RING1_THROTTLE              0xe0
434 #define MC_EMEM_ARB_RING3_THROTTLE              0xe4
435 #define MC_EMEM_ARB_OVERRIDE                    0xe8
436 #define MC_EMEM_ARB_RSV                         0xec
437
438 #define MC_CLKEN_OVERRIDE                       0xf4
439 #define MC_TIMING_CONTROL_DBG                   0xf8
440 #define MC_TIMING_CONTROL                       0xfc
441 #define MC_EMEM_ARB_ISOCHRONOUS_0               0x208
442 #define MC_EMEM_ARB_ISOCHRONOUS_1               0x20c
443 #define MC_EMEM_ARB_ISOCHRONOUS_2               0x210
444 #define MC_EMEM_ARB_HYSTERESIS_0_0              0x218
445 #define MC_EMEM_ARB_HYSTERESIS_1_0              0x21c
446 #define MC_EMEM_ARB_HYSTERESIS_2_0              0x220
447 #define MC_EMEM_ARB_HYSTERESIS_3_0              0x224
448
449 #define HYST_SATAR                              (0x1 << 31)
450 #define HYST_PPCSAHBSLVR                        (0x1 << 30)
451 #define HYST_PPCSAHBDMAR                        (0x1 << 29)
452 #define HYST_MSENCSRD                           (0x1 << 28)
453 #define HYST_HOST1XR                            (0x1 << 23)
454 #define HYST_HOST1XDMAR                         (0x1 << 22)
455 #define HYST_HDAR                               (0x1 << 21)
456 #define HYST_DISPLAYHCB                         (0x1 << 17)
457 #define HYST_DISPLAYHC                          (0x1 << 16)
458 #define HYST_AVPCARM7R                          (0x1 << 15)
459 #define HYST_AFIR                               (0x1 << 14)
460 #define HYST_DISPLAY0CB                         (0x1 << 6)
461 #define HYST_DISPLAY0C                          (0x1 << 5)
462 #define YST_DISPLAY0BB                          (0x1 << 4)
463 #define YST_DISPLAY0B                           (0x1 << 3)
464 #define YST_DISPLAY0AB                          (0x1 << 2)
465 #define YST_DISPLAY0A                           (0x1 << 1)
466 #define HYST_PTCR                               (0x1 << 0)
467
468 #define HYST_VDEDBGW                            (0x1 << 31)
469 #define HYST_VDEBSEVW                           (0x1 << 30)
470 #define HYST_SATAW                              (0x1 << 29)
471 #define HYST_PPCSAHBSLVW                        (0x1 << 28)
472 #define HYST_PPCSAHBDMAW                        (0x1 << 27)
473 #define HYST_MPCOREW                            (0x1 << 25)
474 #define HYST_MPCORELPW                          (0x1 << 24)
475 #define HYST_HOST1XW                            (0x1 << 22)
476 #define HYST_HDAW                               (0x1 << 21)
477 #define HYST_AVPCARM7W                          (0x1 << 18)
478 #define HYST_AFIW                               (0x1 << 17)
479 #define HYST_MSENCSWR                           (0x1 << 11)
480 #define YST_MPCORER                             (0x1 << 7)
481 #define YST_MPCORELPR                           (0x1 << 6)
482 #define YST_VDETPER                             (0x1 << 5)
483 #define YST_VDEMCER                             (0x1 << 4)
484 #define YST_VDEMBER                             (0x1 << 3)
485 #define YST_VDEBSEVR                            (0x1 << 2)
486
487 #define HYST_DISPLAYT                           (0x1 << 26)
488 #define HYST_GPUSWR                             (0x1 << 25)
489 #define HYST_GPUSRD                             (0x1 << 24)
490 #define HYST_A9AVPSCW                           (0x1 << 23)
491 #define HYST_A9AVPSCR                           (0x1 << 22)
492 #define HYST_TSECSWR                            (0x1 << 21)
493 #define HYST_TSECSRD                            (0x1 << 20)
494 #define HYST_ISPWBB                             (0x1 << 17)
495 #define HYST_ISPWAB                             (0x1 << 16)
496 #define HYST_ISPRAB                             (0x1 << 14)
497 #define HYST_XUSB_DEVW                          (0x1 << 13)
498 #define HYST_XUSB_DEVR                          (0x1 << 12)
499 #define HYST_XUSB_HOSTW                         (0x1 << 11)
500 #define HYST_XUSB_HOSTR                         (0x1 << 10)
501 #define YST_ISPWB                               (0x1 << 7)
502 #define YST_ISPWA                               (0x1 << 6)
503 #define YST_ISPRA                               (0x1 << 4)
504 #define YST_VDETPMW                             (0x1 << 1)
505 #define YST_VDEMBEW                             (0x1 << 0)
506
507 #define HYST_DISPLAYD                           (0x1 << 19)
508 #define HYST_VIW                                (0x1 << 18)
509 #define HYST_VICSWR                             (0x1 << 13)
510 #define HYST_VICSRD                             (0x1 << 12)
511 #define YST_SDMMCWAB                            (0x1 << 7)
512 #define YST_SDMMCW                              (0x1 << 6)
513 #define YST_SDMMCWAA                            (0x1 << 5)
514 #define YST_SDMMCWA                             (0x1 << 4)
515 #define YST_SDMMCRAB                            (0x1 << 3)
516 #define YST_SDMMCR                              (0x1 << 2)
517 #define YST_SDMMCRAA                            (0x1 << 1)
518 #define YST_SDMMCRA                             (0x1 << 0)
519
520 #define MC_DIS_EXTRA_SNAP_LEVELS                0x2ac
521
522 #define MC_LATENCY_ALLOWANCE_AFI_0              0x2e0
523 #define MC_LATENCY_ALLOWANCE_AVPC_0             0x2e4
524 #define MC_LATENCY_ALLOWANCE_DC_0               0x2e8
525 #define MC_LATENCY_ALLOWANCE_DC_1               0x2ec
526 #define MC_LATENCY_ALLOWANCE_DC_2               0x2f0
527 #define MC_LATENCY_ALLOWANCE_DCB_0              0x2f4
528 #define MC_LATENCY_ALLOWANCE_DCB_1              0x2f8
529 #define MC_LATENCY_ALLOWANCE_DCB_2              0x2fc
530 #define MC_LATENCY_ALLOWANCE_HC_0               0x310
531 #define MC_LATENCY_ALLOWANCE_HC_1               0x314
532 #define MC_LATENCY_ALLOWANCE_HDA_0              0x318
533 #define MC_LATENCY_ALLOWANCE_MPCORE_0   0x320
534 #define MC_LATENCY_ALLOWANCE_MPCORELP_0 0x324
535 #define MC_LATENCY_ALLOWANCE_MSENC_0    0x328
536 #define MC_LATENCY_ALLOWANCE_PPCS_0             0x344
537 #define MC_LATENCY_ALLOWANCE_PPCS_1             0x348
538 #define MC_LATENCY_ALLOWANCE_PTC_0              0x34c
539 #define MC_LATENCY_ALLOWANCE_SATA_0             0x350
540 #define MC_LATENCY_ALLOWANCE_VDE_0              0x354
541 #define MC_LATENCY_ALLOWANCE_VDE_1              0x358
542 #define MC_LATENCY_ALLOWANCE_VDE_2              0x35c
543 #define MC_LATENCY_ALLOWANCE_VDE_3              0x360
544 #define MC_LATENCY_ALLOWANCE_ISP2_0             0x370
545 #define MC_LATENCY_ALLOWANCE_ISP2_1             0x374
546 #define MC_LATENCY_ALLOWANCE_XUSB_0             0x37c
547 #define MC_LATENCY_ALLOWANCE_XUSB_1             0x380
548 #define MC_LATENCY_ALLOWANCE_ISP2B_0    0x384
549 #define MC_LATENCY_ALLOWANCE_ISP2B_1    0x388
550 #define MC_LATENCY_ALLOWANCE_TSEC_0             0x390
551 #define MC_LATENCY_ALLOWANCE_VIC_0              0x394
552 #define MC_LATENCY_ALLOWANCE_VI2_0              0x398
553 #define MC_LATENCY_ALLOWANCE_A9AVP_0    0x3a4
554 #define MC_LATENCY_ALLOWANCE_GPU_0              0x3ac
555 #define MC_LATENCY_ALLOWANCE_SDMMCA_0   0x3b8
556 #define MC_LATENCY_ALLOWANCE_SDMMCAA_0  0x3bc
557 #define MC_LATENCY_ALLOWANCE_SDMMC_0    0x3c0
558 #define MC_LATENCY_ALLOWANCE_SDMMCAB_0  0x3c4
559 #define MC_LATENCY_ALLOWANCE_DC_3               0x3c8
560
561 /* NOTE: this must match the # of MC_LATENCY_XXX above */
562 #define T12X_MC_LATENCY_ALLOWANCE_NUM_REGS 38
563
564 #define MC_VIDEO_PROTECT_VPR_OVERRIDE           0x418
565 #define MC_MLL_MPCORER_PTSA_RATE                        0x44c
566 #define MC_VIDEO_PROTECT_BOM                    0x648
567 #define MC_VIDEO_PROTECT_SIZE_MB                0x64c
568 #define MC_VIDEO_PROTECT_REG_CTRL               0x650
569
570 #define MC_SEC_CARVEOUT_BOM                     0x670
571 #define MC_SEC_CARVEOUT_SIZE_MB                 0x674
572 #define MC_SEC_CARVEOUT_REG_CTRL                0x678
573
574 #define MC_PTSA_GRANT_DECREMENT                 0x960
575
576 #define MC_RESERVED_RSV                         0x3fc
577 #define MC_RESERVED_RSV_1                       0x958
578
579 #define MC_EMEM_ARB_OUTSTANDING_REQ_RING3       0x66c
580 #define MC_EMEM_ARB_OVERRIDE_1                  0x968
581
582 #endif