ARM: tegra: powermon: Fix copyrights from GPLv3 to GPLv2
[linux-3.10.git] / arch / arm / mach-tegra / tegra12_emc.h
1 /*
2  * arch/arm/mach-tegra/tegra12_emc.h
3  *
4  * Copyright (C) 2013 NVIDIA Corporation
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License as published by
8  * the Free Software Foundation; either version 2 of the License, or
9  * (at your option) any later version.
10  *
11  * This program is distributed in the hope that it will be useful, but WITHOUT
12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
14  * more details.
15  *
16  * You should have received a copy of the GNU General Public License along
17  * with this program; if not, write to the Free Software Foundation, Inc.,
18  * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
19  *
20  */
21
22 #ifndef _MACH_TEGRA_TEGRA12_EMC_H
23 #define _MACH_TEGRA_TEGRA12_EMC_H
24
25 #include "tegra_emc.h"
26
27 int tegra12_emc_init(void);
28
29 enum {
30         DRAM_DEV_SEL_ALL = 0,
31         DRAM_DEV_SEL_0   = (2 << 30),
32         DRAM_DEV_SEL_1   = (1 << 30),
33 };
34 #define DRAM_BROADCAST(num)                     \
35         (((num) > 1) ? DRAM_DEV_SEL_ALL : DRAM_DEV_SEL_0)
36
37 #define EMC_INTSTATUS                           0x0
38 #define EMC_INTSTATUS_CLKCHANGE_COMPLETE        (0x1 << 4)
39
40 #define EMC_DBG                                 0x8
41 #define EMC_DBG_WRITE_MUX_ACTIVE                (0x1 << 1)
42
43 #define EMC_CFG                                 0xc
44 #define EMC_CFG_DRAM_ACPD                       (0x1 << 29)
45 #define EMC_CFG_DYN_SREF_ENABLE                 (0x1 << 28)
46 #define EMC_CFG_PWR_MASK                        (0xF << 28)
47 #define EMC_CFG_PERIODIC_QRST                   (0x1 << 21)
48 #define EMC_CFG_EN_DYNAMIC_PUTERM               (0x1 << 20)
49 #define EMC_CFG_DLY_WR_DQ_HALF_CLOCK            (0x1 << 19)
50 #define EMC_CFG_DSR_VTTGEN_DRV_EN               (0x1 << 18)
51 #define EMC_CFG_EMC2PMACRO_CFG_BYPASS_DATAPIPE2 (0x1 << 3)
52 #define EMC_CFG_EMC2PMACRO_CFG_BYPASS_DATAPIPE1 (0x1 << 2)
53 #define EMC_CFG_EMC2PMACRO_CFG_BYPASS_ADDRPIPE  (0x1 << 1)
54 #define EMC_CFG_UPDATE_MASK     \
55         (EMC_CFG_EMC2PMACRO_CFG_BYPASS_ADDRPIPE | \
56          EMC_CFG_EMC2PMACRO_CFG_BYPASS_DATAPIPE1 | \
57          EMC_CFG_EMC2PMACRO_CFG_BYPASS_DATAPIPE2 | \
58          EMC_CFG_DSR_VTTGEN_DRV_EN | \
59          EMC_CFG_DLY_WR_DQ_HALF_CLOCK | \
60          EMC_CFG_EN_DYNAMIC_PUTERM | \
61          EMC_CFG_PERIODIC_QRST | \
62          EMC_CFG_DRAM_ACPD)
63
64 #define EMC_ADR_CFG                             0x10
65 #define EMC_REFCTRL                             0x20
66 #define EMC_REFCTRL_DEV_SEL_SHIFT               0
67 #define EMC_REFCTRL_DEV_SEL_MASK                \
68         (0x3 << EMC_REFCTRL_DEV_SEL_SHIFT)
69 #define EMC_REFCTRL_ENABLE                      (0x1 << 31)
70 #define EMC_REFCTRL_ENABLE_ALL(num)             \
71         (((((num) > 1) ? 0 : 2) << EMC_REFCTRL_DEV_SEL_SHIFT) \
72          | EMC_REFCTRL_ENABLE)
73 #define EMC_REFCTRL_DISABLE_ALL(num)            \
74         ((((num) > 1) ? 0 : 2) << EMC_REFCTRL_DEV_SEL_SHIFT)
75
76 #define EMC_TIMING_CONTROL                      0x28
77 #define EMC_RC                                  0x2c
78 #define EMC_RFC                                 0x30
79 #define EMC_RAS                                 0x34
80 #define EMC_RP                                  0x38
81 #define EMC_R2W                                 0x3c
82 #define EMC_W2R                                 0x40
83 #define EMC_R2P                                 0x44
84 #define EMC_W2P                                 0x48
85 #define EMC_RD_RCD                              0x4c
86 #define EMC_WR_RCD                              0x50
87 #define EMC_RRD                                 0x54
88 #define EMC_REXT                                0x58
89 #define EMC_WDV                                 0x5c
90 #define EMC_QUSE                                0x60
91 #define EMC_QRST                                0x64
92 #define EMC_QSAFE                               0x68
93 #define EMC_RDV                                 0x6c
94 #define EMC_REFRESH                             0x70
95 #define EMC_BURST_REFRESH_NUM                   0x74
96 #define EMC_PDEX2WR                             0x78
97 #define EMC_PDEX2RD                             0x7c
98 #define EMC_PCHG2PDEN                           0x80
99 #define EMC_ACT2PDEN                            0x84
100 #define EMC_AR2PDEN                             0x88
101 #define EMC_RW2PDEN                             0x8c
102 #define EMC_TXSR                                0x90
103 #define EMC_TCKE                                0x94
104 #define EMC_TFAW                                0x98
105 #define EMC_TRPAB                               0x9c
106 #define EMC_TCLKSTABLE                          0xa0
107 #define EMC_TCLKSTOP                            0xa4
108 #define EMC_TREFBW                              0xa8
109 #define EMC_ODT_WRITE                           0xb0
110 #define EMC_ODT_READ                            0xb4
111 #define EMC_WEXT                                0xb8
112 #define EMC_CTT                                 0xbc
113 #define EMC_RFC_SLR                             0xc0
114 #define EMC_MRS_WAIT_CNT2                       0xc4
115
116 #define EMC_MRS_WAIT_CNT                        0xc8
117 #define EMC_MRS_WAIT_CNT_SHORT_WAIT_SHIFT       0
118 #define EMC_MRS_WAIT_CNT_SHORT_WAIT_MASK        \
119         (0x3FF << EMC_MRS_WAIT_CNT_SHORT_WAIT_SHIFT)
120 #define EMC_MRS_WAIT_CNT_LONG_WAIT_SHIFT        16
121 #define EMC_MRS_WAIT_CNT_LONG_WAIT_MASK         \
122         (0x3FF << EMC_MRS_WAIT_CNT_LONG_WAIT_SHIFT)
123
124 #define EMC_MRS                                 0xcc
125 #define EMC_MODE_SET_DLL_RESET                  (0x1 << 8)
126 #define EMC_MODE_SET_LONG_CNT                   (0x1 << 26)
127 #define EMC_EMRS                                0xd0
128 #define EMC_REF                                 0xd4
129 #define EMC_PRE                                 0xd8
130 #define EMC_NOP                                 0xdc
131
132 #define EMC_SELF_REF                            0xe0
133 #define EMC_SELF_REF_CMD_ENABLED                (0x1 << 0)
134 #define EMC_SELF_REF_DEV_SEL_SHIFT              30
135 #define EMC_SELF_REF_DEV_SEL_MASK               \
136         (0x3 << EMC_SELF_REF_DEV_SEL_SHIFT)
137
138 #define EMC_DPD                                 0xe4
139 #define EMC_MRW                                 0xe8
140
141 #define EMC_MRR                                 0xec
142 #define EMC_MRR_DEV_SEL_SHIFT                   30
143 #define EMC_MRR_DEV_SEL_MASK                    \
144         (0x3 << EMC_SELF_REF_DEV_SEL_SHIFT)
145 #define EMC_MRR_MA_SHIFT                        16
146 #define EMC_MRR_MA_MASK                         (0xFF << EMC_MRR_MA_SHIFT)
147 #define EMC_MRR_DATA_MASK                       ((0x1 << EMC_MRR_MA_SHIFT) - 1)
148 #define LPDDR2_MR4_TEMP_SHIFT                   0
149 #define LPDDR2_MR4_TEMP_MASK                    (0x7 << LPDDR2_MR4_TEMP_SHIFT)
150
151 #define EMC_CMDQ                                0xf0
152 #define EMC_MC2EMCQ                             0xf4
153 #define EMC_XM2DQSPADCTRL3                      0xf8
154 #define EMC_XM2DQSPADCTRL3_VREF_ENABLE          (0x1 << 5)
155 #define EMC_FBIO_SPARE                          0x100
156
157 #define EMC_FBIO_CFG5                           0x104
158 #define EMC_CFG5_TYPE_SHIFT                     0x0
159 #define EMC_CFG5_TYPE_MASK                      (0x3 << EMC_CFG5_TYPE_SHIFT)
160 enum {
161         DRAM_TYPE_DDR3   = 0,
162         DRAM_TYPE_LPDDR2 = 2,
163 };
164 #define EMC_CFG5_QUSE_MODE_SHIFT                13
165 #define EMC_CFG5_QUSE_MODE_MASK                 \
166         (0x7 << EMC_CFG5_QUSE_MODE_SHIFT)
167 enum {
168         EMC_CFG5_QUSE_MODE_NORMAL = 0,
169         EMC_CFG5_QUSE_MODE_ALWAYS_ON,
170         EMC_CFG5_QUSE_MODE_INTERNAL_LPBK,
171         EMC_CFG5_QUSE_MODE_PULSE_INTERN,
172         EMC_CFG5_QUSE_MODE_PULSE_EXTERN,
173         EMC_CFG5_QUSE_MODE_DIRECT_QUSE,
174 };
175
176 #define EMC_FBIO_WRPTR_EQ_2                     0x108
177 #define EMC_FBIO_CFG6                           0x114
178 #define EMC_CFG_RSV                             0x120
179 #define EMC_ACPD_CONTROL                        0x124
180 #define EMC_EMRS2                               0x12c
181 #define EMC_EMRS3                               0x130
182 #define EMC_MRW2                                0x134
183 #define EMC_MRW3                                0x138
184 #define EMC_MRW4                                0x13c
185 #define EMC_CLKEN_OVERRIDE                      0x140
186 #define EMC_R2R                                 0x144
187 #define EMC_W2W                                 0x148
188 #define EMC_EINPUT                              0x14c
189 #define EMC_EINPUT_DURATION                     0x150
190 #define EMC_PUTERM_EXTRA                        0x154
191 #define EMC_TCKESR                              0x158
192 #define EMC_TPD                                 0x15c
193
194 #define EMC_AUTO_CAL_CONFIG                     0x2a4
195 #define EMC_AUTO_CAL_INTERVAL                   0x2a8
196 #define EMC_AUTO_CAL_STATUS                     0x2ac
197 #define EMC_AUTO_CAL_STATUS_ACTIVE              (0x1 << 31)
198 #define EMC_REQ_CTRL                            0x2b0
199 #define EMC_STATUS                              0x2b4
200 #define EMC_STATUS_TIMING_UPDATE_STALLED        (0x1 << 23)
201 #define EMC_STATUS_MRR_DIVLD                    (0x1 << 20)
202
203 #define EMC_CFG_2                               0x2b8
204 #define EMC_CFG_2_MODE_SHIFT                    0
205 #define EMC_CFG_2_MODE_MASK                     (0x3 << EMC_CFG_2_MODE_SHIFT)
206 #define EMC_CFG_2_SREF_MODE                     0x1
207 #define EMC_CFG_2_PD_MODE                       0x3
208
209 #define EMC_CFG_DIG_DLL                         0x2bc
210 #define EMC_CFG_DIG_DLL_PERIOD                  0x2c0
211 #define EMC_DIG_DLL_STATUS                      0x2c8
212 #define EMC_RDV_MASK                            0x2cc
213 #define EMC_WDV_MASK                            0x2d0
214 #define EMC_CTT_DURATION                        0x2d8
215 #define EMC_CTT_TERM_CTRL                       0x2dc
216 #define EMC_ZCAL_INTERVAL                       0x2e0
217 #define EMC_ZCAL_WAIT_CNT                       0x2e4
218 #define EMC_ZCAL_MRW_CMD                        0x2e8
219
220 #define EMC_ZQ_CAL                              0x2ec
221 #define EMC_ZQ_CAL_DEV_SEL_SHIFT                30
222 #define EMC_ZQ_CAL_DEV_SEL_MASK                 \
223         (0x3 << EMC_SELF_REF_DEV_SEL_SHIFT)
224 #define EMC_ZQ_CAL_CMD                          (0x1 << 0)
225 #define EMC_ZQ_CAL_LONG                         (0x1 << 4)
226 #define EMC_ZQ_CAL_LONG_CMD_DEV0                \
227         (DRAM_DEV_SEL_0 | EMC_ZQ_CAL_LONG | EMC_ZQ_CAL_CMD)
228 #define EMC_ZQ_CAL_LONG_CMD_DEV1                \
229         (DRAM_DEV_SEL_1 | EMC_ZQ_CAL_LONG | EMC_ZQ_CAL_CMD)
230
231 #define EMC_XM2CMDPADCTRL                       0x2f0
232 #define EMC_XM2CMDPADCTRL2                      0x2f4
233 #define EMC_XM2DQSPADCTRL                       0x2f8
234 #define EMC_XM2DQSPADCTRL2                      0x2fc
235 #define EMC_XM2DQSPADCTRL2_RX_FT_REC_ENABLE     (0x1 << 0)
236 #define EMC_XM2DQSPADCTRL2_VREF_ENABLE          (0x1 << 5)
237 #define EMC_XM2DQPADCTRL                        0x300
238 #define EMC_XM2DQPADCTRL2                       0x304
239 #define EMC_XM2CLKPADCTRL                       0x308
240 #define EMC_XM2COMPPADCTRL                      0x30c
241 #define EMC_XM2COMPPADCTRL_VREF_CAL_ENABLE      (0x1 << 10)
242 #define EMC_XM2VTTGENPADCTRL                    0x310
243 #define EMC_XM2VTTGENPADCTRL2                   0x314
244 #define EMC_XM2VTTGENPADCTRL3                   0x318
245 #define EMC_EMCPADEN                            0x31c
246 #define EMC_XM2DQSPADCTRL4                      0x320
247 #define EMC_SCRATCH0                            0x324
248 #define EMC_DLL_XFORM_DQS0                      0x328
249 #define EMC_DLL_XFORM_DQS1                      0x32c
250 #define EMC_DLL_XFORM_DQS2                      0x330
251 #define EMC_DLL_XFORM_DQS3                      0x334
252 #define EMC_DLL_XFORM_DQS4                      0x338
253 #define EMC_DLL_XFORM_DQS5                      0x33c
254 #define EMC_DLL_XFORM_DQS6                      0x340
255 #define EMC_DLL_XFORM_DQS7                      0x344
256 #define EMC_DLL_XFORM_QUSE0                     0x348
257 #define EMC_DLL_XFORM_QUSE1                     0x34c
258 #define EMC_DLL_XFORM_QUSE2                     0x350
259 #define EMC_DLL_XFORM_QUSE3                     0x354
260 #define EMC_DLL_XFORM_QUSE4                     0x358
261 #define EMC_DLL_XFORM_QUSE5                     0x35c
262 #define EMC_DLL_XFORM_QUSE6                     0x360
263 #define EMC_DLL_XFORM_QUSE7                     0x364
264 #define EMC_DLL_XFORM_DQ0                       0x368
265 #define EMC_DLL_XFORM_DQ1                       0x36c
266 #define EMC_DLL_XFORM_DQ2                       0x370
267 #define EMC_DLL_XFORM_DQ3                       0x374
268 #define EMC_DLI_RX_TRIM0                        0x378
269 #define EMC_DLI_RX_TRIM1                        0x37c
270 #define EMC_DLI_RX_TRIM2                        0x380
271 #define EMC_DLI_RX_TRIM3                        0x384
272 #define EMC_DLI_RX_TRIM4                        0x388
273 #define EMC_DLI_RX_TRIM5                        0x38c
274 #define EMC_DLI_RX_TRIM6                        0x390
275 #define EMC_DLI_RX_TRIM7                        0x394
276 #define EMC_DLI_TX_TRIM0                        0x398
277 #define EMC_DLI_TX_TRIM1                        0x39c
278 #define EMC_DLI_TX_TRIM2                        0x3a0
279 #define EMC_DLI_TX_TRIM3                        0x3a4
280 #define EMC_DLI_TRIM_TXDQS0                     0x3a8
281 #define EMC_DLI_TRIM_TXDQS1                     0x3ac
282 #define EMC_DLI_TRIM_TXDQS2                     0x3b0
283 #define EMC_DLI_TRIM_TXDQS3                     0x3b4
284 #define EMC_DLI_TRIM_TXDQS4                     0x3b8
285 #define EMC_DLI_TRIM_TXDQS5                     0x3bc
286 #define EMC_DLI_TRIM_TXDQS6                     0x3c0
287 #define EMC_DLI_TRIM_TXDQS7                     0x3c4
288 #define EMC_STALL_THEN_EXE_AFTER_CLKCHANGE      0x3cc
289 #define EMC_AUTO_CAL_CLK_STATUS                 0x3d4
290 #define EMC_SEL_DPD_CTRL                        0x3d8
291 #define EMC_SEL_DPD_CTRL_QUSE_DPD_ENABLE        (0x1 << 9)
292 #define EMC_PRE_REFRESH_REQ_CNT                 0x3dc
293 #define EMC_DYN_SELF_REF_CONTROL                0x3e0
294 #define EMC_TXSRDLL                             0x3e4
295 #define EMC_CCFIFO_ADDR                         0x3e8
296 #define EMC_CCFIFO_DATA                         0x3ec
297 #define EMC_CCFIFO_STATUS                       0x3f0
298 #define EMC_CDB_CNTL_1                          0x3f4
299 #define EMC_CDB_CNTL_2                          0x3f8
300 #define EMC_XM2CLKPADCTRL2                      0x3fc
301 #define EMC_SWIZZLE_RANK0_BYTE_CFG              0x400
302 #define EMC_SWIZZLE_RANK0_BYTE0                 0x404
303 #define EMC_SWIZZLE_RANK0_BYTE1                 0x408
304 #define EMC_SWIZZLE_RANK0_BYTE2                 0x40c
305 #define EMC_SWIZZLE_RANK0_BYTE3                 0x410
306 #define EMC_SWIZZLE_RANK1_BYTE_CFG              0x414
307 #define EMC_SWIZZLE_RANK1_BYTE0                 0x418
308 #define EMC_SWIZZLE_RANK1_BYTE1                 0x41c
309 #define EMC_SWIZZLE_RANK1_BYTE2                 0x420
310 #define EMC_SWIZZLE_RANK1_BYTE3                 0x424
311 #define EMC_CA_TRAINING_START                   0x428
312 #define EMC_CA_TRAINING_BUSY                    0x42c
313 #define EMC_CA_TRAINING_CFG                     0x430
314 #define EMC_CA_TRAINING_TIMING_CNTL1            0x434
315 #define EMC_CA_TRAINING_TIMING_CNTL2            0x438
316 #define EMC_CA_TRAINING_CA_LEAD_IN              0x43c
317 #define EMC_CA_TRAINING_CA                      0x440
318 #define EMC_CA_TRAINING_CA_LEAD_OUT             0x444
319 #define EMC_CA_TRAINING_RESULT1                 0x448
320 #define EMC_CA_TRAINING_RESULT2                 0x44c
321 #define EMC_CA_TRAINING_RESULT3                 0x450
322 #define EMC_CA_TRAINING_RESULT4                 0x454
323 #define EMC_AUTO_CAL_CONFIG2                    0x458
324 #define EMC_AUTO_CAL_CONFIG3                    0x45c
325 #define EMC_AUTO_CAL_STATUS2                    0x460
326 #define EMC_XM2CMDPADCTRL3                      0x464
327 #define EMC_IBDLY                               0x468
328 #define EMC_DLL_XFORM_ADDR0                     0x46c
329 #define EMC_DLL_XFORM_ADDR1                     0x470
330 #define EMC_DLL_XFORM_ADDR2                     0x474
331 #define EMC_DLI_ADDR_TRIM                       0x478
332 #define EMC_DSR_VTTGEN_DRV                      0x47c
333 #define EMC_TXDSRVTTGEN                         0x480
334 #define EMC_XM2CMDPADCTRL4                      0x484
335 #define EMC_XM2CMDPADCTRL5                      0x488
336 #define EMC_DLL_XFORM_DQS8                      0x4a0
337 #define EMC_DLL_XFORM_DQS9                      0x4a4
338 #define EMC_DLL_XFORM_DQS10                     0x4a8
339 #define EMC_DLL_XFORM_DQS11                     0x4ac
340 #define EMC_DLL_XFORM_DQS12                     0x4b0
341 #define EMC_DLL_XFORM_DQS13                     0x4b4
342 #define EMC_DLL_XFORM_DQS14                     0x4b8
343 #define EMC_DLL_XFORM_DQS15                     0x4bc
344 #define EMC_DLL_XFORM_QUSE8                     0x4c0
345 #define EMC_DLL_XFORM_QUSE9                     0x4c4
346 #define EMC_DLL_XFORM_QUSE10                    0x4c8
347 #define EMC_DLL_XFORM_QUSE11                    0x4cc
348 #define EMC_DLL_XFORM_QUSE12                    0x4d0
349 #define EMC_DLL_XFORM_QUSE13                    0x4d4
350 #define EMC_DLL_XFORM_QUSE14                    0x4d8
351 #define EMC_DLL_XFORM_QUSE15                    0x4dc
352 #define EMC_DLL_XFORM_DQ4                               0x4e0
353 #define EMC_DLL_XFORM_DQ5                               0x4e4
354 #define EMC_DLL_XFORM_DQ6                               0x4e8
355 #define EMC_DLL_XFORM_DQ7                               0x4ec
356 #define EMC_DLI_TRIM_TXDQS8                             0x520
357 #define EMC_DLI_TRIM_TXDQS9                             0x524
358 #define EMC_DLI_TRIM_TXDQS10                            0x528
359 #define EMC_DLI_TRIM_TXDQS11                            0x52c
360 #define EMC_DLI_TRIM_TXDQS12                            0x530
361 #define EMC_DLI_TRIM_TXDQS13                            0x534
362 #define EMC_DLI_TRIM_TXDQS14                            0x538
363 #define EMC_DLI_TRIM_TXDQS15                            0x53c
364 #define EMC_CDB_CNTL_3                          0x540
365 #define EMC_XM2DQSPADCTRL5                      0x544
366 #define EMC_XM2DQSPADCTRL6                      0x548
367 #define EMC_XM2DQPADCTRL3                       0x54c
368 #define EMC_DLL_XFORM_ADDR3                     0x550
369 #define EMC_DLL_XFORM_ADDR4                     0x554
370 #define EMC_DLL_XFORM_ADDR5                     0x558
371 #define EMC_CFG_PIPE                            0x560
372 #define EMC_QPOP                                        0x564
373 #define EMC_QUSE_WIDTH                          0x568
374 #define EMC_PUTERM_WIDTH                        0x56c
375 #define EMC_BGBIAS_CTL0                         0x570
376 #define EMC_PUTERM_ADJ                          0x574
377
378 #define MC_EMEM_CFG                             0x50
379 #define MC_EMEM_ADR_CFG                         0x54
380 #define MC_EMEM_ADR_CFG_DEV0                    0x58
381 #define MC_EMEM_ADR_CFG_DEV1                    0x5c
382 #define MC_EMEM_ADR_CFG_BANK_MASK_0             0x64
383 #define MC_EMEM_ADR_CFG_BANK_MASK_1             0x68
384 #define MC_EMEM_ADR_CFG_BANK_MASK_2             0x6c
385
386 #define MC_EMEM_ARB_CFG                         0x90
387 #define MC_EMEM_ARB_OUTSTANDING_REQ             0x94
388 #define MC_EMEM_ARB_TIMING_RCD                  0x98
389 #define MC_EMEM_ARB_TIMING_RP                   0x9c
390 #define MC_EMEM_ARB_TIMING_RC                   0xa0
391 #define MC_EMEM_ARB_TIMING_RAS                  0xa4
392 #define MC_EMEM_ARB_TIMING_FAW                  0xa8
393 #define MC_EMEM_ARB_TIMING_RRD                  0xac
394 #define MC_EMEM_ARB_TIMING_RAP2PRE              0xb0
395 #define MC_EMEM_ARB_TIMING_WAP2PRE              0xb4
396 #define MC_EMEM_ARB_TIMING_R2R                  0xb8
397 #define MC_EMEM_ARB_TIMING_W2W                  0xbc
398 #define MC_EMEM_ARB_TIMING_R2W                  0xc0
399 #define MC_EMEM_ARB_TIMING_W2R                  0xc4
400 #define MC_EMEM_ARB_DA_TURNS                    0xd0
401 #define MC_EMEM_ARB_DA_COVERS                   0xd4
402 #define MC_EMEM_ARB_MISC0                       0xd8
403 #define MC_EMEM_ARB_MISC0_EMC_SAME_FREQ         (0x1 << 27)
404 #define MC_EMEM_ARB_MISC1                       0xdc
405 #define MC_EMEM_ARB_RING1_THROTTLE              0xe0
406 #define MC_EMEM_ARB_RING3_THROTTLE              0xe4
407 #define MC_EMEM_ARB_OVERRIDE                    0xe8
408 #define MC_EMEM_ARB_RSV                         0xec
409
410 #define MC_CLKEN_OVERRIDE                       0xf4
411 #define MC_TIMING_CONTROL_DBG                   0xf8
412 #define MC_TIMING_CONTROL                       0xfc
413 #define MC_EMEM_ARB_ISOCHRONOUS_0               0x208
414 #define MC_EMEM_ARB_ISOCHRONOUS_1               0x20c
415 #define MC_EMEM_ARB_ISOCHRONOUS_2               0x210
416 #define MC_DIS_EXTRA_SNAP_LEVELS                0x2ac
417
418 #define MC_LATENCY_ALLOWANCE_AFI_0              0x2e0
419 #define MC_LATENCY_ALLOWANCE_AVPC_0             0x2e4
420 #define MC_LATENCY_ALLOWANCE_DC_0               0x2e8
421 #define MC_LATENCY_ALLOWANCE_DC_1               0x2ec
422 #define MC_LATENCY_ALLOWANCE_DC_2               0x2f0
423 #define MC_LATENCY_ALLOWANCE_DCB_0              0x2f4
424 #define MC_LATENCY_ALLOWANCE_DCB_1              0x2f8
425 #define MC_LATENCY_ALLOWANCE_DCB_2              0x2fc
426 #define MC_LATENCY_ALLOWANCE_HC_0               0x310
427 #define MC_LATENCY_ALLOWANCE_HC_1               0x314
428 #define MC_LATENCY_ALLOWANCE_HDA_0              0x318
429 #define MC_LATENCY_ALLOWANCE_MPCORE_0   0x320
430 #define MC_LATENCY_ALLOWANCE_MPCORELP_0 0x324
431 #define MC_LATENCY_ALLOWANCE_MSENC_0    0x328
432 #define MC_LATENCY_ALLOWANCE_PPCS_0             0x344
433 #define MC_LATENCY_ALLOWANCE_PPCS_1             0x348
434 #define MC_LATENCY_ALLOWANCE_PTC_0              0x34c
435 #define MC_LATENCY_ALLOWANCE_SATA_0             0x350
436 #define MC_LATENCY_ALLOWANCE_VDE_0              0x354
437 #define MC_LATENCY_ALLOWANCE_VDE_1              0x358
438 #define MC_LATENCY_ALLOWANCE_VDE_2              0x35c
439 #define MC_LATENCY_ALLOWANCE_VDE_3              0x360
440 #define MC_LATENCY_ALLOWANCE_ISP2_0             0x370
441 #define MC_LATENCY_ALLOWANCE_ISP2_1             0x374
442 #define MC_LATENCY_ALLOWANCE_XUSB_0             0x37c
443 #define MC_LATENCY_ALLOWANCE_XUSB_1             0x380
444 #define MC_LATENCY_ALLOWANCE_ISP2B_0    0x384
445 #define MC_LATENCY_ALLOWANCE_ISP2B_1    0x388
446 #define MC_LATENCY_ALLOWANCE_TSEC_0             0x390
447 #define MC_LATENCY_ALLOWANCE_VIC_0              0x394
448 #define MC_LATENCY_ALLOWANCE_VI2_0              0x398
449 #define MC_LATENCY_ALLOWANCE_A9AVP_0    0x3a4
450 #define MC_LATENCY_ALLOWANCE_GPU_0              0x3ac
451 #define MC_LATENCY_ALLOWANCE_SDMMCA_0   0x3b8
452 #define MC_LATENCY_ALLOWANCE_SDMMCAA_0  0x3bc
453 #define MC_LATENCY_ALLOWANCE_SDMMC_0    0x3c0
454 #define MC_LATENCY_ALLOWANCE_SDMMCAB_0  0x3c4
455 #define MC_LATENCY_ALLOWANCE_DC_3               0x3c8
456
457 /* NOTE: this must match the # of MC_LATENCY_XXX above */
458 #define T12X_MC_LATENCY_ALLOWANCE_NUM_REGS 38
459
460 #define MC_VIDEO_PROTECT_VPR_OVERRIDE           0x418
461 #define MC_MLL_MPCORER_PTSA_RATE                        0x44c
462 #define MC_VIDEO_PROTECT_BOM                    0x648
463 #define MC_VIDEO_PROTECT_SIZE_MB                0x64c
464 #define MC_VIDEO_PROTECT_REG_CTRL               0x650
465
466 #define MC_SEC_CARVEOUT_BOM                     0x670
467 #define MC_SEC_CARVEOUT_SIZE_MB                 0x674
468 #define MC_SEC_CARVEOUT_REG_CTRL                0x678
469
470 #define MC_PTSA_GRANT_DECREMENT                 0x960
471
472 #define MC_RESERVED_RSV                         0x3fc
473 #define MC_RESERVED_RSV_1                       0x958
474
475 #define MC_EMEM_ARB_OUTSTANDING_REQ_RING3       0x66c
476 #define MC_EMEM_ARB_OVERRIDE_1                  0x968
477
478 #endif