arm: tegra: usb_phy: add support for t114 usb_phy
[linux-3.10.git] / arch / arm / mach-tegra / tegra11x_usb_phy.c
1 /*
2  * arch/arm/mach-tegra/tegra11x_usb_phy.c
3  *
4  * Copyright (C) 2012 NVIDIA Corporation
5  *
6  *
7  * This software is licensed under the terms of the GNU General Public
8  * License version 2, as published by the Free Software Foundation, and
9  * may be copied, distributed, and modified under those terms.
10  *
11  * This program is distributed in the hope that it will be useful,
12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14  * GNU General Public License for more details.
15  *
16  */
17 #include <linux/resource.h>
18 #include <linux/delay.h>
19 #include <linux/interrupt.h>
20 #include <linux/slab.h>
21 #include <linux/err.h>
22 #include <linux/platform_device.h>
23 #include <linux/io.h>
24 #include <linux/gpio.h>
25 #include <linux/interrupt.h>
26 #include <linux/clk.h>
27 #include <linux/regulator/consumer.h>
28 #include <linux/platform_data/tegra_usb.h>
29 #include <mach/iomap.h>
30 #include <mach/pinmux.h>
31 #include <mach/pinmux-t11.h>
32 #include "tegra_usb_phy.h"
33 #include "fuse.h"
34
35 #define USB_USBCMD              0x130
36 #define   USB_USBCMD_RS         (1 << 0)
37 #define   USB_CMD_RESET (1<<1)
38
39 #define USB_USBSTS              0x134
40 #define   USB_USBSTS_PCI        (1 << 2)
41 #define   USB_USBSTS_SRI        (1 << 7)
42 #define   USB_USBSTS_HCH        (1 << 12)
43
44 #define USB_TXFILLTUNING        0x154
45 #define USB_FIFO_TXFILL_THRES(x)   (((x) & 0x1f) << 16)
46 #define USB_FIFO_TXFILL_MASK    0x1f0000
47
48 #define USB_ASYNCLISTADDR       0x148
49
50 #define ICUSB_CTRL              0x15c
51
52 #define USB_PORTSC              0x174
53 #define   USB_PORTSC_WKOC       (1 << 22)
54 #define   USB_PORTSC_WKDS       (1 << 21)
55 #define   USB_PORTSC_WKCN       (1 << 20)
56 #define   USB_PORTSC_PTC(x)     (((x) & 0xf) << 16)
57 #define   USB_PORTSC_PP (1 << 12)
58 #define   USB_PORTSC_LS(x) (((x) & 0x3) << 10)
59 #define   USB_PORTSC_SUSP       (1 << 7)
60 #define   USB_PORTSC_RESUME     (1 << 6)
61 #define   USB_PORTSC_OCC        (1 << 5)
62 #define   USB_PORTSC_PEC        (1 << 3)
63 #define   USB_PORTSC_PE         (1 << 2)
64 #define   USB_PORTSC_CSC        (1 << 1)
65 #define   USB_PORTSC_CCS        (1 << 0)
66 #define   USB_PORTSC_RWC_BITS (USB_PORTSC_CSC | USB_PORTSC_PEC | USB_PORTSC_OCC)
67
68 #define HOSTPC1_DEVLC           0x1b4
69 #define   HOSTPC1_DEVLC_PHCD            (1 << 22)
70 #define   HOSTPC1_DEVLC_PTS(x)          (((x) & 0x7) << 29)
71 #define   HOSTPC1_DEVLC_PTS_MASK        7
72 #define   HOSTPC1_DEVLC_PTS_HSIC        4
73 #define   HOSTPC1_DEVLC_STS             (1 << 28)
74 #define   HOSTPC1_DEVLC_PSPD(x)         (((x) & 0x3) << 25)
75 #define   HOSTPC1_DEVLC_PSPD_MASK       3
76 #define   HOSTPC1_DEVLC_PSPD_HIGH_SPEED 2
77 #define   HOSTPC1_DEVLC_NYT_ASUS        1
78
79 #define USB_USBMODE             0x1f8
80 #define   USB_USBMODE_MASK              (3 << 0)
81 #define   USB_USBMODE_HOST              (3 << 0)
82 #define   USB_USBMODE_DEVICE            (2 << 0)
83
84 #define USB_SUSP_CTRL           0x400
85 #define   USB_WAKE_ON_CNNT_EN_DEV       (1 << 3)
86 #define   USB_WAKE_ON_DISCON_EN_DEV (1 << 4)
87 #define   USB_SUSP_CLR                  (1 << 5)
88 #define   USB_PHY_CLK_VALID             (1 << 7)
89 #define   USB_PHY_CLK_VALID_INT_ENB     (1 << 9)
90 #define   USB_PHY_CLK_VALID_INT_STS     (1 << 8)
91 #define   UTMIP_RESET                   (1 << 11)
92 #define   UTMIP_PHY_ENABLE              (1 << 12)
93 #define   ULPI_PHY_ENABLE               (1 << 13)
94 #define   UHSIC_RESET                   (1 << 14)
95 #define   USB_WAKEUP_DEBOUNCE_COUNT(x)  (((x) & 0x7) << 16)
96 #define   UHSIC_PHY_ENABLE              (1 << 19)
97 #define   ULPIS2S_SLV0_RESET            (1 << 20)
98 #define   ULPIS2S_SLV1_RESET            (1 << 21)
99 #define   ULPIS2S_LINE_RESET            (1 << 22)
100 #define   ULPI_PADS_RESET               (1 << 23)
101 #define   ULPI_PADS_CLKEN_RESET         (1 << 24)
102
103 #define USB_PHY_VBUS_WAKEUP_ID  0x408
104 #define   VDAT_DET_INT_EN       (1 << 16)
105 #define   VDAT_DET_CHG_DET      (1 << 17)
106 #define   VDAT_DET_STS          (1 << 18)
107 #define   USB_ID_STATUS         (1 << 2)
108
109 #define ULPIS2S_CTRL            0x418
110 #define   ULPIS2S_ENA                   (1 << 0)
111 #define   ULPIS2S_SUPPORT_DISCONNECT    (1 << 2)
112 #define   ULPIS2S_PLLU_MASTER_BLASTER60 (1 << 3)
113 #define   ULPIS2S_SPARE(x)              (((x) & 0xF) << 8)
114 #define   ULPIS2S_FORCE_ULPI_CLK_OUT    (1 << 12)
115 #define   ULPIS2S_DISCON_DONT_CHECK_SE0 (1 << 13)
116 #define   ULPIS2S_SUPPORT_HS_KEEP_ALIVE (1 << 14)
117 #define   ULPIS2S_DISABLE_STP_PU        (1 << 15)
118 #define   ULPIS2S_SLV0_CLAMP_XMIT       (1 << 16)
119
120 #define ULPI_TIMING_CTRL_0      0x424
121 #define   ULPI_CLOCK_OUT_DELAY(x)       ((x) & 0x1F)
122 #define   ULPI_OUTPUT_PINMUX_BYP        (1 << 10)
123 #define   ULPI_CLKOUT_PINMUX_BYP        (1 << 11)
124 #define   ULPI_SHADOW_CLK_LOOPBACK_EN   (1 << 12)
125 #define   ULPI_SHADOW_CLK_SEL           (1 << 13)
126 #define   ULPI_CORE_CLK_SEL             (1 << 14)
127 #define   ULPI_SHADOW_CLK_DELAY(x)      (((x) & 0x1F) << 16)
128 #define   ULPI_LBK_PAD_EN               (1 << 26)
129 #define   ULPI_LBK_PAD_E_INPUT_OR       (1 << 27)
130 #define   ULPI_CLK_OUT_ENA              (1 << 28)
131 #define   ULPI_CLK_PADOUT_ENA           (1 << 29)
132
133 #define ULPI_TIMING_CTRL_1      0x428
134 #define   ULPI_DATA_TRIMMER_LOAD        (1 << 0)
135 #define   ULPI_DATA_TRIMMER_SEL(x)      (((x) & 0x7) << 1)
136 #define   ULPI_STPDIRNXT_TRIMMER_LOAD   (1 << 16)
137 #define   ULPI_STPDIRNXT_TRIMMER_SEL(x) (((x) & 0x7) << 17)
138 #define   ULPI_DIR_TRIMMER_LOAD         (1 << 24)
139 #define   ULPI_DIR_TRIMMER_SEL(x)       (((x) & 0x7) << 25)
140
141 #define UTMIP_XCVR_CFG0         0x808
142 #define   UTMIP_XCVR_SETUP(x)                   (((x) & 0xf) << 0)
143 #define   UTMIP_XCVR_LSRSLEW(x)                 (((x) & 0x3) << 8)
144 #define   UTMIP_XCVR_LSFSLEW(x)                 (((x) & 0x3) << 10)
145 #define   UTMIP_FORCE_PD_POWERDOWN              (1 << 14)
146 #define   UTMIP_FORCE_PD2_POWERDOWN             (1 << 16)
147 #define   UTMIP_FORCE_PDZI_POWERDOWN            (1 << 18)
148 #define   UTMIP_XCVR_LSBIAS_SEL                 (1 << 21)
149 #define   UTMIP_XCVR_SETUP_MSB(x)               (((x) & 0x7) << 22)
150 #define   UTMIP_XCVR_HSSLEW_MSB(x)              (((x) & 0x7f) << 25)
151 #define   UTMIP_XCVR_MAX_OFFSET         2
152 #define   UTMIP_XCVR_SETUP_MAX_VALUE    0x7f
153 #define   UTMIP_XCVR_SETUP_MIN_VALUE    0
154 #define   XCVR_SETUP_MSB_CALIB(x) ((x) >> 4)
155
156 #define UTMIP_BIAS_CFG0         0x80c
157 #define   UTMIP_OTGPD                   (1 << 11)
158 #define   UTMIP_BIASPD                  (1 << 10)
159 #define   UTMIP_HSSQUELCH_LEVEL(x)      (((x) & 0x3) << 0)
160 #define   UTMIP_HSDISCON_LEVEL(x)       (((x) & 0x3) << 2)
161 #define   UTMIP_HSDISCON_LEVEL_MSB      (1 << 24)
162
163 #define UTMIP_HSRX_CFG0         0x810
164 #define   UTMIP_ELASTIC_LIMIT(x)        (((x) & 0x1f) << 10)
165 #define   UTMIP_IDLE_WAIT(x)            (((x) & 0x1f) << 15)
166
167 #define UTMIP_HSRX_CFG1         0x814
168 #define   UTMIP_HS_SYNC_START_DLY(x)    (((x) & 0x1f) << 1)
169
170 #define UTMIP_TX_CFG0           0x820
171 #define   UTMIP_FS_PREABMLE_J           (1 << 19)
172 #define   UTMIP_HS_DISCON_DISABLE       (1 << 8)
173
174 #define UTMIP_DEBOUNCE_CFG0 0x82c
175 #define   UTMIP_BIAS_DEBOUNCE_A(x)      (((x) & 0xffff) << 0)
176
177 #define UTMIP_BAT_CHRG_CFG0 0x830
178 #define   UTMIP_PD_CHRG                 (1 << 0)
179 #define   UTMIP_ON_SINK_EN              (1 << 2)
180 #define   UTMIP_OP_SRC_EN               (1 << 3)
181
182 #define UTMIP_XCVR_CFG1         0x838
183 #define   UTMIP_FORCE_PDDISC_POWERDOWN  (1 << 0)
184 #define   UTMIP_FORCE_PDCHRP_POWERDOWN  (1 << 2)
185 #define   UTMIP_FORCE_PDDR_POWERDOWN    (1 << 4)
186 #define   UTMIP_XCVR_TERM_RANGE_ADJ(x)  (((x) & 0xf) << 18)
187
188 #define UTMIP_BIAS_CFG1         0x83c
189 #define   UTMIP_BIAS_PDTRK_COUNT(x) (((x) & 0x1f) << 3)
190 #define   UTMIP_BIAS_PDTRK_POWERDOWN    (1 << 0)
191 #define   UTMIP_BIAS_PDTRK_POWERUP      (1 << 1)
192
193 #define UTMIP_MISC_CFG0         0x824
194 #define   UTMIP_DPDM_OBSERVE            (1 << 26)
195 #define   UTMIP_DPDM_OBSERVE_SEL(x) (((x) & 0xf) << 27)
196 #define   UTMIP_DPDM_OBSERVE_SEL_FS_J   UTMIP_DPDM_OBSERVE_SEL(0xf)
197 #define   UTMIP_DPDM_OBSERVE_SEL_FS_K   UTMIP_DPDM_OBSERVE_SEL(0xe)
198 #define   UTMIP_DPDM_OBSERVE_SEL_FS_SE1 UTMIP_DPDM_OBSERVE_SEL(0xd)
199 #define   UTMIP_DPDM_OBSERVE_SEL_FS_SE0 UTMIP_DPDM_OBSERVE_SEL(0xc)
200 #define   UTMIP_SUSPEND_EXIT_ON_EDGE    (1 << 22)
201 #define   FORCE_PULLDN_DM       (1 << 8)
202 #define   FORCE_PULLDN_DP       (1 << 9)
203 #define   COMB_TERMS            (1 << 0)
204 #define   ALWAYS_FREE_RUNNING_TERMS (1 << 1)
205
206 #define UTMIP_SPARE_CFG0        0x834
207 #define   FUSE_SETUP_SEL                (1 << 3)
208 #define   FUSE_ATERM_SEL                (1 << 4)
209
210 #define UTMIP_PMC_WAKEUP0               0x84c
211 #define   EVENT_INT_ENB                 (1 << 0)
212
213 #define UTMIP_BIAS_STS0                 0x840
214 #define   UTMIP_RCTRL_VAL(x)            (((x) & 0xffff) << 0)
215 #define   UTMIP_TCTRL_VAL(x)            (((x) & (0xffff << 16)) >> 16)
216
217 #define UHSIC_PLL_CFG1                          0xc04
218 #define   UHSIC_XTAL_FREQ_COUNT(x)              (((x) & 0xfff) << 0)
219 #define   UHSIC_PLLU_ENABLE_DLY_COUNT(x)        (((x) & 0x1f) << 14)
220
221 #define UHSIC_HSRX_CFG0                         0xc08
222 #define   UHSIC_ELASTIC_UNDERRUN_LIMIT(x)       (((x) & 0x1f) << 2)
223 #define   UHSIC_ELASTIC_OVERRUN_LIMIT(x)        (((x) & 0x1f) << 8)
224 #define   UHSIC_IDLE_WAIT(x)                    (((x) & 0x1f) << 13)
225
226 #define UHSIC_HSRX_CFG1                         0xc0c
227 #define   UHSIC_HS_SYNC_START_DLY(x)            (((x) & 0x1f) << 1)
228
229 #define UHSIC_TX_CFG0                           0xc10
230 #define UHSIC_HS_READY_WAIT_FOR_VALID   (1 << 9)
231 #define UHSIC_MISC_CFG0                         0xc14
232 #define   UHSIC_SUSPEND_EXIT_ON_EDGE            (1 << 7)
233 #define   UHSIC_DETECT_SHORT_CONNECT            (1 << 8)
234 #define   UHSIC_FORCE_XCVR_MODE                 (1 << 15)
235 #define   UHSIC_DISABLE_BUSRESET                (1 << 20)
236 #define UHSIC_MISC_CFG1                         0xc18
237 #define   UHSIC_PLLU_STABLE_COUNT(x)            (((x) & 0xfff) << 2)
238
239 #define UHSIC_PADS_CFG0                         0xc1c
240 #define   UHSIC_TX_RTUNEN                       0xf000
241 #define   UHSIC_TX_RTUNE(x)                     (((x) & 0xf) << 12)
242
243 #define UHSIC_PADS_CFG1                         0xc20
244 #define   UHSIC_PD_BG                           (1 << 2)
245 #define   UHSIC_PD_TX                           (1 << 3)
246 #define   UHSIC_PD_TRK                          (1 << 4)
247 #define   UHSIC_PD_RX                           (1 << 5)
248 #define   UHSIC_PD_ZI                           (1 << 6)
249 #define   UHSIC_RX_SEL                          (1 << 7)
250 #define   UHSIC_RPD_DATA                        (1 << 9)
251 #define   UHSIC_RPD_STROBE                      (1 << 10)
252 #define   UHSIC_RPU_DATA                        (1 << 11)
253 #define   UHSIC_RPU_STROBE                      (1 << 12)
254
255 #define UHSIC_STAT_CFG0                 0xc28
256 #define   UHSIC_CONNECT_DETECT                  (1 << 0)
257
258 #define PMC_USB_DEBOUNCE                        0xec
259 #define   UTMIP_LINE_DEB_CNT(x)                 (((x) & 0xf) << 16)
260
261 #define PMC_USB_AO                              0xf0
262 #define PMC_POWER_DOWN_MASK                     0xffff
263 #define HSIC_RESERVED_P0                        (3 << 14)
264 #define HSIC_STOBE_VAL_PD_P0                    (1 << 13)
265 #define HSIC_DATA_VAL_PD_P0                     (1 << 12)
266 #define USB_ID_PD(inst)                         (1 << ((4*(inst))+3))
267 #define VBUS_WAKEUP_PD(inst)                    (1 << ((4*(inst))+2))
268 #define   USBON_VAL_PD(inst)                    (1 << ((4*(inst))+1))
269 #define   USBON_VAL_PD_P2                       (1 << 9)
270 #define   USBON_VAL_PD_P1                       (1 << 5)
271 #define   USBON_VAL_PD_P0                       (1 << 1)
272 #define   USBOP_VAL_PD(inst)                    (1 << (4*(inst)))
273 #define   USBOP_VAL_PD_P2                       (1 << 8)
274 #define   USBOP_VAL_PD_P1                       (1 << 4)
275 #define   USBOP_VAL_PD_P0                       (1 << 0)
276 #define   PMC_USB_AO_PD_P2                      (0xf << 8)
277 #define   PMC_USB_AO_ID_PD_P0                   (1 << 3)
278 #define   PMC_USB_AO_VBUS_WAKEUP_PD_P0  (1 << 2)
279
280 #define PMC_TRIGGERS                    0x1ec
281 #define   UTMIP_CLR_WALK_PTR(inst)      (1 << (inst))
282 #define   UTMIP_CLR_WALK_PTR_P2         (1 << 2)
283 #define   UTMIP_CLR_WALK_PTR_P1         (1 << 1)
284 #define   UTMIP_CLR_WALK_PTR_P0         (1 << 0)
285 #define   UTMIP_CAP_CFG(inst)   (1 << ((inst)+4))
286 #define   UTMIP_CAP_CFG_P2              (1 << 6)
287 #define   UTMIP_CAP_CFG_P1              (1 << 5)
288 #define   UTMIP_CAP_CFG_P0              (1 << 4)
289 #define   UTMIP_CLR_WAKE_ALARM(inst)            (1 << ((inst)+12))
290 #define   UTMIP_CLR_WAKE_ALARM_P2       (1 << 14)
291
292 #define PMC_PAD_CFG             (0x1f4)
293
294 #define PMC_UTMIP_TERM_PAD_CFG  0x1f8
295 #define   PMC_TCTRL_VAL(x)      (((x) & 0x1f) << 5)
296 #define   PMC_RCTRL_VAL(x)      (((x) & 0x1f) << 0)
297
298 #define UHSIC_SLEEPWALK_REG             0x210
299 #define UHSIC_DATA_RPD_D                (1 << 25)
300 #define UHSIC_STRB_RPD_D                (1 << 24)
301 #define UHSIC_DATA_RPD_C                (1 << 17)
302 #define UHSIC_STRB_RPD_C                (1 << 16)
303 #define UHSIC_DATA_RPD_B                (1 << 9)
304 #define UHSIC_STRB_RPD_B                (1 << 8)
305 #define UHSIC_DATA_RPD_A                (1 << 1)
306 #define UHSIC_STRB_RPD_A                (1 << 0)
307
308 #define PMC_SLEEP_CFG                   0x1fc
309 #define   UTMIP_TCTRL_USE_PMC(inst) (1 << ((8*(inst))+3))
310 #define   UTMIP_TCTRL_USE_PMC_P2                (1 << 19)
311 #define   UTMIP_TCTRL_USE_PMC_P1                (1 << 11)
312 #define   UTMIP_TCTRL_USE_PMC_P0                (1 << 3)
313 #define   UTMIP_RCTRL_USE_PMC(inst) (1 << ((8*(inst))+2))
314 #define   UTMIP_RCTRL_USE_PMC_P2                (1 << 18)
315 #define   UTMIP_RCTRL_USE_PMC_P1                (1 << 10)
316 #define   UTMIP_RCTRL_USE_PMC_P0                (1 << 2)
317 #define   UTMIP_FSLS_USE_PMC(inst)      (1 << ((8*(inst))+1))
318 #define   UTMIP_FSLS_USE_PMC_P2         (1 << 17)
319 #define   UTMIP_FSLS_USE_PMC_P1         (1 << 9)
320 #define   UTMIP_FSLS_USE_PMC_P0         (1 << 1)
321 #define   UTMIP_MASTER_ENABLE(inst) (1 << (8*(inst)))
322 #define   UTMIP_MASTER_ENABLE_P2                (1 << 16)
323 #define   UTMIP_MASTER_ENABLE_P1                (1 << 8)
324 #define   UTMIP_MASTER_ENABLE_P0                (1 << 0)
325 #define UHSIC_MASTER_ENABLE_P0          (1 << 24)
326 #define UHSIC_WAKE_VAL_P0(x)            (((x) & 0xf) << 28)
327
328 #define PMC_SLEEPWALK_CFG               0x200
329 #define   UTMIP_LINEVAL_WALK_EN(inst) (1 << ((8*(inst))+7))
330 #define   UTMIP_LINEVAL_WALK_EN_P2      (1 << 23)
331 #define   UTMIP_LINEVAL_WALK_EN_P1      (1 << 15)
332 #define   UTMIP_LINEVAL_WALK_EN_P0      (1 << 7)
333 #define   UTMIP_WAKE_VAL(inst, x) (((x) & 0xf) << ((8*(inst))+4))
334 #define   UTMIP_WAKE_VAL_P2(x)          (((x) & 0xf) << 20)
335 #define   UTMIP_WAKE_VAL_P1(x)          (((x) & 0xf) << 12)
336 #define   UTMIP_WAKE_VAL_P0(x)          (((x) & 0xf) << 4)
337 #define   WAKE_VAL_NONE         0xc
338 #define   WAKE_VAL_ANY                  0xF
339 #define   WAKE_VAL_FSJ                  0x2
340 #define   WAKE_VAL_FSK                  0x1
341 #define   WAKE_VAL_SE0                  0x0
342
343 #define PMC_SLEEPWALK_REG(inst)         (0x204 + (4*(inst)))
344 #define   UTMIP_USBOP_RPD_A     (1 << 0)
345 #define   UTMIP_USBON_RPD_A     (1 << 1)
346 #define   UTMIP_AP_A                    (1 << 4)
347 #define   UTMIP_AN_A                    (1 << 5)
348 #define   UTMIP_HIGHZ_A         (1 << 6)
349 #define   UTMIP_USBOP_RPD_B     (1 << 8)
350 #define   UTMIP_USBON_RPD_B     (1 << 9)
351 #define   UTMIP_AP_B                    (1 << 12)
352 #define   UTMIP_AN_B                    (1 << 13)
353 #define   UTMIP_HIGHZ_B         (1 << 14)
354 #define   UTMIP_USBOP_RPD_C     (1 << 16)
355 #define   UTMIP_USBON_RPD_C     (1 << 17)
356 #define   UTMIP_AP_C            (1 << 20)
357 #define   UTMIP_AN_C            (1 << 21)
358 #define   UTMIP_HIGHZ_C         (1 << 22)
359 #define   UTMIP_USBOP_RPD_D     (1 << 24)
360 #define   UTMIP_USBON_RPD_D     (1 << 25)
361 #define   UTMIP_AP_D            (1 << 28)
362 #define   UTMIP_AN_D            (1 << 29)
363 #define   UTMIP_HIGHZ_D         (1 << 30)
364
365 #define UTMIP_UHSIC_STATUS              0x214
366 #define   UTMIP_WALK_PTR_VAL(inst)      (0x3 << ((inst)*2))
367 #define   UTMIP_USBOP_VAL(inst)         (1 << ((2*(inst)) + 8))
368 #define   UTMIP_USBOP_VAL_P2            (1 << 12)
369 #define   UTMIP_USBOP_VAL_P1            (1 << 10)
370 #define   UTMIP_USBOP_VAL_P0            (1 << 8)
371 #define   UTMIP_USBON_VAL(inst)         (1 << ((2*(inst)) + 9))
372 #define   UTMIP_USBON_VAL_P2            (1 << 13)
373 #define   UTMIP_USBON_VAL_P1            (1 << 11)
374 #define   UTMIP_USBON_VAL_P0            (1 << 9)
375 #define   UTMIP_WAKE_ALARM(inst)                (1 << ((inst) + 16))
376 #define   UTMIP_WAKE_ALARM_P2   (1 << 18)
377 #define   UTMIP_WAKE_ALARM_P1   (1 << 17)
378 #define   UTMIP_WAKE_ALARM_P0   (1 << 16)
379 #define   UTMIP_WALK_PTR(inst)  (1 << ((inst)*2))
380 #define   UTMIP_WALK_PTR_P2     (1 << 4)
381 #define   UTMIP_WALK_PTR_P1     (1 << 2)
382 #define   UTMIP_WALK_PTR_P0     (1 << 0)
383
384 #define USB1_PREFETCH_ID               6
385 #define USB2_PREFETCH_ID               18
386 #define USB3_PREFETCH_ID               17
387
388 #define PMC_UTMIP_UHSIC_FAKE            0x218
389 #define   USBON_VAL(inst)       (1 << ((4*(inst))+1))
390 #define   USBON_VAL_P2                  (1 << 9)
391 #define   USBON_VAL_P1                  (1 << 5)
392 #define   USBON_VAL_P0                  (1 << 1)
393 #define   USBOP_VAL(inst)       (1 << (4*(inst)))
394 #define   USBOP_VAL_P2                  (1 << 8)
395 #define   USBOP_VAL_P1                  (1 << 4)
396 #define   USBOP_VAL_P0                  (1 << 0)
397
398 #define PMC_UTMIP_BIAS_MASTER_CNTRL 0x30c
399 #define   BIAS_MASTER_PROG_VAL          (1 << 1)
400
401 #define PMC_UTMIP_MASTER_CONFIG         0x310
402 #define   UTMIP_PWR(inst)               (1 << (inst))
403
404 #define FUSE_USB_CALIB_0                0x1F0
405 #define   FUSE_USB_CALIB_XCVR_SETUP(x)  (((x) & 0x7F) << 0)
406
407 /* These values (in milli second) are taken from the battery charging spec */
408 #define TDP_SRC_ON_MS    100
409 #define TDPSRC_CON_MS    40
410
411 #ifdef DEBUG
412 #define DBG(stuff...)   pr_info("tegra11x_usb_phy: " stuff)
413 #else
414 #define DBG(stuff...)   do {} while (0)
415 #endif
416
417 static u32 utmip_rctrl_val, utmip_tctrl_val;
418 static DEFINE_SPINLOCK(utmip_pad_lock);
419 static int utmip_pad_count;
420
421 static struct tegra_xtal_freq utmip_freq_table[] = {
422         {
423                 .freq = 12000000,
424                 .enable_delay = 0x02,
425                 .stable_count = 0x2F,
426                 .active_delay = 0x04,
427                 .xtal_freq_count = 0x76,
428                 .debounce = 0x7530,
429                 .pdtrk_count = 5,
430         },
431         {
432                 .freq = 13000000,
433                 .enable_delay = 0x02,
434                 .stable_count = 0x33,
435                 .active_delay = 0x05,
436                 .xtal_freq_count = 0x7F,
437                 .debounce = 0x7EF4,
438                 .pdtrk_count = 5,
439         },
440         {
441                 .freq = 19200000,
442                 .enable_delay = 0x03,
443                 .stable_count = 0x4B,
444                 .active_delay = 0x06,
445                 .xtal_freq_count = 0xBB,
446                 .debounce = 0xBB80,
447                 .pdtrk_count = 7,
448         },
449         {
450                 .freq = 26000000,
451                 .enable_delay = 0x04,
452                 .stable_count = 0x66,
453                 .active_delay = 0x09,
454                 .xtal_freq_count = 0xFE,
455                 .debounce = 0xFDE8,
456                 .pdtrk_count = 9,
457         },
458 };
459
460 static struct tegra_xtal_freq uhsic_freq_table[] = {
461         {
462                 .freq = 12000000,
463                 .enable_delay = 0x02,
464                 .stable_count = 0x2F,
465                 .active_delay = 0x0,
466                 .xtal_freq_count = 0x1CA,
467         },
468         {
469                 .freq = 13000000,
470                 .enable_delay = 0x02,
471                 .stable_count = 0x33,
472                 .active_delay = 0x0,
473                 .xtal_freq_count = 0x1F0,
474         },
475         {
476                 .freq = 19200000,
477                 .enable_delay = 0x03,
478                 .stable_count = 0x4B,
479                 .active_delay = 0x0,
480                 .xtal_freq_count = 0x2DD,
481         },
482         {
483                 .freq = 26000000,
484                 .enable_delay = 0x04,
485                 .stable_count = 0x66,
486                 .active_delay = 0x0,
487                 .xtal_freq_count = 0x3E0,
488         },
489 };
490
491 static int usb_phy_init(struct tegra_usb_phy *phy)
492 {
493         unsigned long val;
494         void __iomem *base = phy->regs;
495
496         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
497
498         val = readl(base + HOSTPC1_DEVLC);
499         val &= ~HOSTPC1_DEVLC_STS;
500         val &= ~HOSTPC1_DEVLC_NYT_ASUS;
501         writel(val, base + HOSTPC1_DEVLC);
502
503         return 0;
504 }
505
506 static void usb_phy_fence_read(struct tegra_usb_phy *phy)
507 {
508         /* Fence read for coherency of AHB master intiated writes */
509         if (phy->inst == 0)
510                 readb(IO_ADDRESS(IO_PPCS_PHYS + USB1_PREFETCH_ID));
511         else if (phy->inst == 1)
512                 readb(IO_ADDRESS(IO_PPCS_PHYS + USB2_PREFETCH_ID));
513         else if (phy->inst == 2)
514                 readb(IO_ADDRESS(IO_PPCS_PHYS + USB3_PREFETCH_ID));
515
516         return;
517 }
518
519 static void utmip_setup_pmc_wake_detect(struct tegra_usb_phy *phy)
520 {
521         unsigned long val, pmc_pad_cfg_val;
522         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
523         unsigned  int inst = phy->inst;
524         void __iomem *base = phy->regs;
525         bool port_connected;
526         enum usb_phy_port_speed port_speed;
527
528         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
529
530         /* check for port connect status */
531         val = readl(base + USB_PORTSC);
532         port_connected = val & USB_PORTSC_CCS;
533
534         if (!port_connected)
535                 return;
536
537         port_speed = (readl(base + HOSTPC1_DEVLC) >> 25) &
538                 HOSTPC1_DEVLC_PSPD_MASK;
539         /*Set PMC MASTER bits to do the following
540         * a. Take over the UTMI drivers
541         * b. set up such that it will take over resume
542         *        if remote wakeup is detected
543         * Prepare PMC to take over suspend-wake detect-drive resume until USB
544         * controller ready
545         */
546
547         /* disable master enable in PMC */
548         val = readl(pmc_base + PMC_SLEEP_CFG);
549         val &= ~UTMIP_MASTER_ENABLE(inst);
550         writel(val, pmc_base + PMC_SLEEP_CFG);
551
552         /* UTMIP_PWR_PX=1 for power savings mode */
553         val = readl(pmc_base + PMC_UTMIP_MASTER_CONFIG);
554         val |= UTMIP_PWR(inst);
555         writel(val, pmc_base + PMC_UTMIP_MASTER_CONFIG);
556
557         /* config debouncer */
558         val = readl(pmc_base + PMC_USB_DEBOUNCE);
559         val &= ~UTMIP_LINE_DEB_CNT(~0);
560         val |= UTMIP_LINE_DEB_CNT(4);
561         writel(val, pmc_base + PMC_USB_DEBOUNCE);
562
563         /* Make sure nothing is happening on the line with respect to PMC */
564         val = readl(pmc_base + PMC_UTMIP_UHSIC_FAKE);
565         val &= ~USBOP_VAL(inst);
566         val &= ~USBON_VAL(inst);
567         writel(val, pmc_base + PMC_UTMIP_UHSIC_FAKE);
568
569         /* Make sure wake value for line is none */
570         val = readl(pmc_base + PMC_SLEEPWALK_CFG);
571         val &= ~UTMIP_LINEVAL_WALK_EN(inst);
572         writel(val, pmc_base + PMC_SLEEPWALK_CFG);
573         val = readl(pmc_base + PMC_SLEEP_CFG);
574         val &= ~UTMIP_WAKE_VAL(inst, ~0);
575         val |= UTMIP_WAKE_VAL(inst, WAKE_VAL_NONE);
576         writel(val, pmc_base + PMC_SLEEP_CFG);
577
578         /* turn off pad detectors */
579         val = readl(pmc_base + PMC_USB_AO);
580         val |= (USBOP_VAL_PD(inst) | USBON_VAL_PD(inst));
581         writel(val, pmc_base + PMC_USB_AO);
582
583         /* Remove fake values and make synchronizers work a bit */
584         val = readl(pmc_base + PMC_UTMIP_UHSIC_FAKE);
585         val &= ~USBOP_VAL(inst);
586         val &= ~USBON_VAL(inst);
587         writel(val, pmc_base + PMC_UTMIP_UHSIC_FAKE);
588
589         /* Enable which type of event can trigger a walk,
590         in this case usb_line_wake */
591         val = readl(pmc_base + PMC_SLEEPWALK_CFG);
592         val |= UTMIP_LINEVAL_WALK_EN(inst);
593         writel(val, pmc_base + PMC_SLEEPWALK_CFG);
594
595         /* Enable which type of event can trigger a walk,
596         * in this case usb_line_wake */
597         val = readl(pmc_base + PMC_SLEEPWALK_CFG);
598         val |= UTMIP_LINEVAL_WALK_EN(inst);
599         writel(val, pmc_base + PMC_SLEEPWALK_CFG);
600
601         /* Clear the walk pointers and wake alarm */
602         val = readl(pmc_base + PMC_TRIGGERS);
603         val |= UTMIP_CLR_WAKE_ALARM(inst) | UTMIP_CLR_WALK_PTR(inst);
604         writel(val, pmc_base + PMC_TRIGGERS);
605
606
607         /* Capture FS/LS pad configurations */
608         pmc_pad_cfg_val = readl(pmc_base + PMC_PAD_CFG);
609         val = readl(pmc_base + PMC_TRIGGERS);
610         val |= UTMIP_CAP_CFG(inst);
611         writel(val, pmc_base + PMC_TRIGGERS);
612         udelay(1);
613         pmc_pad_cfg_val = readl(pmc_base + PMC_PAD_CFG);
614
615         /* BIAS MASTER_ENABLE=0 */
616         val = readl(pmc_base + PMC_UTMIP_BIAS_MASTER_CNTRL);
617         val &= ~BIAS_MASTER_PROG_VAL;
618         writel(val, pmc_base + PMC_UTMIP_BIAS_MASTER_CNTRL);
619
620         /* program walk sequence, maintain a J, followed by a driven K
621         * to signal a resume once an wake event is detected */
622         val = readl(pmc_base + PMC_SLEEPWALK_REG(inst));
623         val &= ~UTMIP_AP_A;
624         val |= UTMIP_USBOP_RPD_A | UTMIP_USBON_RPD_A | UTMIP_AN_A |UTMIP_HIGHZ_A |
625                 UTMIP_USBOP_RPD_B | UTMIP_USBON_RPD_B | UTMIP_AP_B | UTMIP_AN_B |
626                 UTMIP_USBOP_RPD_C | UTMIP_USBON_RPD_C | UTMIP_AP_C | UTMIP_AN_C |
627                 UTMIP_USBOP_RPD_D | UTMIP_USBON_RPD_D | UTMIP_AP_D | UTMIP_AN_D;
628         writel(val, pmc_base + PMC_SLEEPWALK_REG(inst));
629
630         if (port_speed == USB_PHY_PORT_SPEED_LOW) {
631                 val = readl(pmc_base + PMC_SLEEPWALK_REG(inst));
632                 val &= ~(UTMIP_AN_B | UTMIP_HIGHZ_B | UTMIP_AN_C |
633                         UTMIP_HIGHZ_C | UTMIP_AN_D | UTMIP_HIGHZ_D);
634                 writel(val, pmc_base + PMC_SLEEPWALK_REG(inst));
635         } else {
636                 val = readl(pmc_base + PMC_SLEEPWALK_REG(inst));
637                 val &= ~(UTMIP_AP_B | UTMIP_HIGHZ_B | UTMIP_AP_C |
638                         UTMIP_HIGHZ_C | UTMIP_AP_D | UTMIP_HIGHZ_D);
639                 writel(val, pmc_base + PMC_SLEEPWALK_REG(inst));
640         }
641
642         /* turn on pad detectors */
643         val = readl(pmc_base + PMC_USB_AO);
644         val &= ~(USBOP_VAL_PD(inst) | USBON_VAL_PD(inst));
645         writel(val, pmc_base + PMC_USB_AO);
646
647         /* Add small delay before usb detectors provide stable line values */
648         mdelay(1);
649
650         /* Program thermally encoded RCTRL_VAL, TCTRL_VAL into PMC space */
651         val = readl(pmc_base + PMC_UTMIP_TERM_PAD_CFG);
652         val = PMC_TCTRL_VAL(utmip_tctrl_val) | PMC_RCTRL_VAL(utmip_rctrl_val);
653         writel(val, pmc_base + PMC_UTMIP_TERM_PAD_CFG);
654
655         phy->remote_wakeup = false;
656
657         /* Turn over pad configuration to PMC  for line wake events*/
658         val = readl(pmc_base + PMC_SLEEP_CFG);
659         val &= ~UTMIP_WAKE_VAL(inst, ~0);
660         val |= UTMIP_WAKE_VAL(inst, WAKE_VAL_ANY);
661         val |= UTMIP_RCTRL_USE_PMC(inst) | UTMIP_TCTRL_USE_PMC(inst);
662         val |= UTMIP_MASTER_ENABLE(inst) | UTMIP_FSLS_USE_PMC(inst);
663         writel(val, pmc_base + PMC_SLEEP_CFG);
664
665         val = readl(base + UTMIP_PMC_WAKEUP0);
666         val |= EVENT_INT_ENB;
667         writel(val, base + UTMIP_PMC_WAKEUP0);
668 }
669
670 static void utmip_phy_disable_pmc_bus_ctrl(struct tegra_usb_phy *phy)
671 {
672         unsigned long val;
673         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
674         unsigned  int inst = phy->inst;
675         void __iomem *base = phy->regs;
676
677         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
678
679         val = readl(pmc_base + PMC_SLEEP_CFG);
680         val &= ~UTMIP_WAKE_VAL(inst, 0xF);
681         val |= UTMIP_WAKE_VAL(inst, WAKE_VAL_NONE);
682         writel(val, pmc_base + PMC_SLEEP_CFG);
683
684         val = readl(pmc_base + PMC_TRIGGERS);
685         val |= UTMIP_CLR_WAKE_ALARM(inst) | UTMIP_CLR_WALK_PTR(inst);
686         writel(val, pmc_base + PMC_TRIGGERS);
687
688         val = readl(base + UTMIP_PMC_WAKEUP0);
689         val &= ~EVENT_INT_ENB;
690         writel(val, base + UTMIP_PMC_WAKEUP0);
691
692         /* Disable PMC master mode by clearing MASTER_EN */
693         val = readl(pmc_base + PMC_SLEEP_CFG);
694         val &= ~(UTMIP_RCTRL_USE_PMC(inst) | UTMIP_TCTRL_USE_PMC(inst) |
695                         UTMIP_FSLS_USE_PMC(inst) | UTMIP_MASTER_ENABLE(inst));
696         writel(val, pmc_base + PMC_SLEEP_CFG);
697
698         val = readl(pmc_base + PMC_TRIGGERS);
699         val &= ~UTMIP_CAP_CFG(inst);
700         writel(val, pmc_base + PMC_TRIGGERS);
701
702         /* turn off pad detectors */
703         val = readl(pmc_base + PMC_USB_AO);
704         val |= (USBOP_VAL_PD(inst) | USBON_VAL_PD(inst));
705         writel(val, pmc_base + PMC_USB_AO);
706
707         phy->remote_wakeup = false;
708 }
709
710 static bool utmi_phy_remotewake_detected(struct tegra_usb_phy *phy)
711 {
712         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
713         void __iomem *base = phy->regs;
714         unsigned  int inst = phy->inst;
715         u32 val;
716
717         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
718         val = readl(base + UTMIP_PMC_WAKEUP0);
719         if (val & EVENT_INT_ENB) {
720                 val = readl(pmc_base + UTMIP_UHSIC_STATUS);
721                 if (UTMIP_WAKE_ALARM(inst) & val) {
722                         val = readl(pmc_base + PMC_SLEEP_CFG);
723                         val &= ~UTMIP_WAKE_VAL(inst, 0xF);
724                         val |= UTMIP_WAKE_VAL(inst, WAKE_VAL_NONE);
725                         writel(val, pmc_base + PMC_SLEEP_CFG);
726
727                         val = readl(pmc_base + PMC_TRIGGERS);
728                         val |= UTMIP_CLR_WAKE_ALARM(inst) |
729                                 UTMIP_CLR_WALK_PTR(inst);
730                         writel(val, pmc_base + PMC_TRIGGERS);
731
732                         val = readl(base + UTMIP_PMC_WAKEUP0);
733                         val &= ~EVENT_INT_ENB;
734                         writel(val, base + UTMIP_PMC_WAKEUP0);
735                         phy->remote_wakeup = true;
736                         return true;
737                 }
738         }
739         return false;
740 }
741
742 static void utmi_phy_enable_trking_data(struct tegra_usb_phy *phy)
743 {
744         void __iomem *base = IO_ADDRESS(TEGRA_USB_BASE);
745         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
746         static bool init_done = false;
747         u32 val;
748
749         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
750
751         /* Should be done only once after system boot */
752         if (init_done)
753                 return;
754
755         clk_enable(phy->utmi_pad_clk);
756         /* Bias pad MASTER_ENABLE=1 */
757         val = readl(pmc_base + PMC_UTMIP_BIAS_MASTER_CNTRL);
758         val |= BIAS_MASTER_PROG_VAL;
759         writel(val, pmc_base + PMC_UTMIP_BIAS_MASTER_CNTRL);
760
761         /* Setting the tracking length time */
762         val = readl(base + UTMIP_BIAS_CFG1);
763         val &= ~UTMIP_BIAS_PDTRK_COUNT(~0);
764         val |= UTMIP_BIAS_PDTRK_COUNT(5);
765         writel(val, base + UTMIP_BIAS_CFG1);
766
767         /* Bias PDTRK is Shared and MUST be done from USB1 ONLY, PD_TRK=0 */
768         val = readl(base + UTMIP_BIAS_CFG1);
769         val &= ~UTMIP_BIAS_PDTRK_POWERDOWN;
770         writel(val, base + UTMIP_BIAS_CFG1);
771
772         val = readl(base + UTMIP_BIAS_CFG1);
773         val |= UTMIP_BIAS_PDTRK_POWERUP;
774         writel(val, base + UTMIP_BIAS_CFG1);
775
776         /* Wait for 25usec */
777         udelay(25);
778
779         /* Bias pad MASTER_ENABLE=0 */
780         val = readl(pmc_base + PMC_UTMIP_BIAS_MASTER_CNTRL);
781         val &= ~BIAS_MASTER_PROG_VAL;
782         writel(val, pmc_base + PMC_UTMIP_BIAS_MASTER_CNTRL);
783
784         /* Wait for 1usec */
785         udelay(1);
786
787         /* Bias pad MASTER_ENABLE=1 */
788         val = readl(pmc_base + PMC_UTMIP_BIAS_MASTER_CNTRL);
789         val |= BIAS_MASTER_PROG_VAL;
790         writel(val, pmc_base + PMC_UTMIP_BIAS_MASTER_CNTRL);
791
792         /* Read RCTRL and TCTRL from UTMIP space */
793         val = readl(base + UTMIP_BIAS_STS0);
794         utmip_rctrl_val = ffz(UTMIP_RCTRL_VAL(val));
795         utmip_tctrl_val = ffz(UTMIP_TCTRL_VAL(val));
796
797         /* PD_TRK=1 */
798         val = readl(base + UTMIP_BIAS_CFG1);
799         val |= UTMIP_BIAS_PDTRK_POWERDOWN;
800         writel(val, base + UTMIP_BIAS_CFG1);
801
802         /* Program thermally encoded RCTRL_VAL, TCTRL_VAL into PMC space */
803         val = readl(pmc_base + PMC_UTMIP_TERM_PAD_CFG);
804         val = PMC_TCTRL_VAL(utmip_tctrl_val) | PMC_RCTRL_VAL(utmip_rctrl_val);
805         writel(val, pmc_base + PMC_UTMIP_TERM_PAD_CFG);
806         clk_disable(phy->utmi_pad_clk);
807         init_done = true;
808 }
809
810 static void utmip_powerdown_pmc_wake_detect(struct tegra_usb_phy *phy)
811 {
812         unsigned long val;
813         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
814         unsigned  int inst = phy->inst;
815
816         /* power down UTMIP interfaces */
817         val = readl(pmc_base + PMC_UTMIP_MASTER_CONFIG);
818         val |= UTMIP_PWR(inst);
819         writel(val, pmc_base + PMC_UTMIP_MASTER_CONFIG);
820
821         /* setup sleep walk usb controller */
822         val = UTMIP_USBOP_RPD_A | UTMIP_USBON_RPD_A | UTMIP_HIGHZ_A |
823                 UTMIP_USBOP_RPD_B | UTMIP_USBON_RPD_B | UTMIP_HIGHZ_B |
824                 UTMIP_USBOP_RPD_C | UTMIP_USBON_RPD_C | UTMIP_HIGHZ_C |
825                 UTMIP_USBOP_RPD_D | UTMIP_USBON_RPD_D | UTMIP_HIGHZ_D;
826         writel(val, pmc_base + PMC_SLEEPWALK_REG(inst));
827
828         /* Program thermally encoded RCTRL_VAL, TCTRL_VAL into PMC space */
829         val = readl(pmc_base + PMC_UTMIP_TERM_PAD_CFG);
830         val = PMC_TCTRL_VAL(utmip_tctrl_val) | PMC_RCTRL_VAL(utmip_rctrl_val);
831         writel(val, pmc_base + PMC_UTMIP_TERM_PAD_CFG);
832
833         /* Turn over pad configuration to PMC */
834         val = readl(pmc_base + PMC_SLEEP_CFG);
835         val &= ~UTMIP_WAKE_VAL(inst, ~0);
836         val |= UTMIP_WAKE_VAL(inst, WAKE_VAL_NONE) |
837                 UTMIP_RCTRL_USE_PMC(inst) | UTMIP_TCTRL_USE_PMC(inst) |
838                 UTMIP_FSLS_USE_PMC(inst) | UTMIP_MASTER_ENABLE(inst);
839         writel(val, pmc_base + PMC_SLEEP_CFG);
840 }
841
842 static void utmip_powerup_pmc_wake_detect(struct tegra_usb_phy *phy)
843 {
844         unsigned long val;
845         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
846         unsigned  int inst = phy->inst;
847
848         /* Disable PMC master mode by clearing MASTER_EN */
849         val = readl(pmc_base + PMC_SLEEP_CFG);
850         val &= ~(UTMIP_RCTRL_USE_PMC(inst) | UTMIP_TCTRL_USE_PMC(inst) |
851                         UTMIP_FSLS_USE_PMC(inst) | UTMIP_MASTER_ENABLE(inst));
852         writel(val, pmc_base + PMC_SLEEP_CFG);
853         mdelay(1);
854 }
855
856 static void uhsic_powerdown_pmc_wake_detect(struct tegra_usb_phy *phy)
857 {
858         unsigned long val;
859         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
860
861         /* turn on pad detectors for HSIC*/
862         val = readl(pmc_base + PMC_USB_AO);
863         val |= (HSIC_RESERVED_P0 | HSIC_STOBE_VAL_PD_P0 | HSIC_DATA_VAL_PD_P0);
864         writel(val, pmc_base + PMC_USB_AO);
865
866         /* enable pull downs on HSIC PMC */
867         val = UHSIC_STRB_RPD_A | UHSIC_DATA_RPD_A | UHSIC_STRB_RPD_B |
868                 UHSIC_DATA_RPD_B | UHSIC_STRB_RPD_C | UHSIC_DATA_RPD_C |
869                 UHSIC_STRB_RPD_D | UHSIC_DATA_RPD_D;
870         writel(val, pmc_base + UHSIC_SLEEPWALK_REG);
871
872         /* Turn over pad configuration to PMC */
873         val = readl(pmc_base + PMC_SLEEP_CFG);
874         val &= ~UHSIC_WAKE_VAL_P0(~0);
875         val |= UHSIC_WAKE_VAL_P0(WAKE_VAL_NONE) | UHSIC_MASTER_ENABLE_P0;
876         writel(val, pmc_base + PMC_SLEEP_CFG);
877 }
878
879 static void uhsic_powerup_pmc_wake_detect(struct tegra_usb_phy *phy)
880 {
881         unsigned long val;
882         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
883
884         /* turn on pad detectors for HSIC*/
885         val = readl(pmc_base + PMC_USB_AO);
886         val &= ~(HSIC_RESERVED_P0 | HSIC_STOBE_VAL_PD_P0 | HSIC_DATA_VAL_PD_P0);
887         writel(val, pmc_base + PMC_USB_AO);
888
889         /* Disable PMC master mode by clearing MASTER_EN */
890         val = readl(pmc_base + PMC_SLEEP_CFG);
891         val &= ~(UHSIC_MASTER_ENABLE_P0);
892         writel(val, pmc_base + PMC_SLEEP_CFG);
893         mdelay(1);
894 }
895
896 static void usb_phy_power_down_pmc(void)
897 {
898         unsigned long val;
899         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
900
901         /* power down all 3 UTMIP interfaces */
902         val = readl(pmc_base + PMC_UTMIP_MASTER_CONFIG);
903         val |= UTMIP_PWR(0) | UTMIP_PWR(1) | UTMIP_PWR(2);
904         writel(val, pmc_base + PMC_UTMIP_MASTER_CONFIG);
905
906         /* turn on pad detectors */
907         writel(PMC_POWER_DOWN_MASK, pmc_base + PMC_USB_AO);
908
909         /* setup sleep walk fl all 3 usb controllers */
910         val = UTMIP_USBOP_RPD_A | UTMIP_USBON_RPD_A | UTMIP_HIGHZ_A |
911                 UTMIP_USBOP_RPD_B | UTMIP_USBON_RPD_B | UTMIP_HIGHZ_B |
912                 UTMIP_USBOP_RPD_C | UTMIP_USBON_RPD_C | UTMIP_HIGHZ_C |
913                 UTMIP_USBOP_RPD_D | UTMIP_USBON_RPD_D | UTMIP_HIGHZ_D;
914         writel(val, pmc_base + PMC_SLEEPWALK_REG(0));
915         writel(val, pmc_base + PMC_SLEEPWALK_REG(1));
916         writel(val, pmc_base + PMC_SLEEPWALK_REG(2));
917
918         /* enable pull downs on HSIC PMC */
919         val = UHSIC_STRB_RPD_A | UHSIC_DATA_RPD_A | UHSIC_STRB_RPD_B |
920                 UHSIC_DATA_RPD_B | UHSIC_STRB_RPD_C | UHSIC_DATA_RPD_C |
921                 UHSIC_STRB_RPD_D | UHSIC_DATA_RPD_D;
922         writel(val, pmc_base + UHSIC_SLEEPWALK_REG);
923
924         /* Turn over pad configuration to PMC */
925         val = readl(pmc_base + PMC_SLEEP_CFG);
926         val &= ~UTMIP_WAKE_VAL(0, ~0);
927         val &= ~UTMIP_WAKE_VAL(1, ~0);
928         val &= ~UTMIP_WAKE_VAL(2, ~0);
929         val &= ~UHSIC_WAKE_VAL_P0(~0);
930         val |= UTMIP_WAKE_VAL(0, WAKE_VAL_NONE) | UHSIC_WAKE_VAL_P0(WAKE_VAL_NONE) |
931         UTMIP_WAKE_VAL(1, WAKE_VAL_NONE) | UTMIP_WAKE_VAL(2, WAKE_VAL_NONE) |
932         UTMIP_RCTRL_USE_PMC(0) | UTMIP_RCTRL_USE_PMC(1) | UTMIP_RCTRL_USE_PMC(2) |
933         UTMIP_TCTRL_USE_PMC(0) | UTMIP_TCTRL_USE_PMC(1) | UTMIP_TCTRL_USE_PMC(2) |
934         UTMIP_FSLS_USE_PMC(0) | UTMIP_FSLS_USE_PMC(1) | UTMIP_FSLS_USE_PMC(2) |
935         UTMIP_MASTER_ENABLE(0) | UTMIP_MASTER_ENABLE(1) | UTMIP_MASTER_ENABLE(2) |
936         UHSIC_MASTER_ENABLE_P0;
937         writel(val, pmc_base + PMC_SLEEP_CFG);
938 }
939
940 static int usb_phy_bringup_host_controller(struct tegra_usb_phy *phy)
941 {
942         unsigned long val;
943         void __iomem *base = phy->regs;
944
945         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
946         DBG("USB_USBSTS[0x%x] USB_PORTSC[0x%x] port_speed[%d]\n",
947                 readl(base + USB_USBSTS), readl(base + USB_PORTSC),
948                                                         phy->port_speed);
949
950         /* Enable Port Power */
951         val = readl(base + USB_PORTSC);
952         val |= USB_PORTSC_PP;
953         writel(val, base + USB_PORTSC);
954         udelay(10);
955
956         /* Check if the phy resume from LP0. When the phy resume from LP0
957          * USB register will be reset.to zero */
958         if (!readl(base + USB_ASYNCLISTADDR)) {
959                 /* Program the field PTC based on the saved speed mode */
960                 val = readl(base + USB_PORTSC);
961                 val &= ~USB_PORTSC_PTC(~0);
962                 if (phy->port_speed == USB_PHY_PORT_SPEED_HIGH)
963                         val |= USB_PORTSC_PTC(5);
964                 else if (phy->port_speed == USB_PHY_PORT_SPEED_FULL)
965                         val |= USB_PORTSC_PTC(6);
966                 else if (phy->port_speed == USB_PHY_PORT_SPEED_LOW)
967                         val |= USB_PORTSC_PTC(7);
968                 writel(val, base + USB_PORTSC);
969                 udelay(10);
970
971                 /* Disable test mode by setting PTC field to NORMAL_OP */
972                 val = readl(base + USB_PORTSC);
973                 val &= ~USB_PORTSC_PTC(~0);
974                 writel(val, base + USB_PORTSC);
975                 udelay(10);
976         }
977
978         /* Poll until CCS is enabled */
979         if (usb_phy_reg_status_wait(base + USB_PORTSC, USB_PORTSC_CCS,
980                                                  USB_PORTSC_CCS, 2000)) {
981                 pr_err("%s: timeout waiting for USB_PORTSC_CCS\n", __func__);
982         }
983
984         /* Poll until PE is enabled */
985         if (usb_phy_reg_status_wait(base + USB_PORTSC, USB_PORTSC_PE,
986                                                  USB_PORTSC_PE, 2000)) {
987                 pr_err("%s: timeout waiting for USB_PORTSC_PE\n", __func__);
988         }
989
990         /* Clear the PCI status, to avoid an interrupt taken upon resume */
991         val = readl(base + USB_USBSTS);
992         val |= USB_USBSTS_PCI;
993         writel(val, base + USB_USBSTS);
994
995         /* Put controller in suspend mode by writing 1 to SUSP bit of PORTSC */
996         val = readl(base + USB_PORTSC);
997         if ((val & USB_PORTSC_PP) && (val & USB_PORTSC_PE)) {
998                 val |= USB_PORTSC_SUSP;
999                 writel(val, base + USB_PORTSC);
1000                 /* Need a 4ms delay before the controller goes to suspend */
1001                 mdelay(4);
1002
1003                 /* Wait until port suspend completes */
1004                 if (usb_phy_reg_status_wait(base + USB_PORTSC, USB_PORTSC_SUSP,
1005                                                  USB_PORTSC_SUSP, 1000)) {
1006                         pr_err("%s: timeout waiting for PORT_SUSPEND\n",
1007                                                                 __func__);
1008                 }
1009         }
1010
1011         DBG("USB_USBSTS[0x%x] USB_PORTSC[0x%x]\n",
1012                         readl(base + USB_USBSTS), readl(base + USB_PORTSC));
1013         return 0;
1014 }
1015
1016 static void usb_phy_wait_for_sof(struct tegra_usb_phy *phy)
1017 {
1018         unsigned long val;
1019         void __iomem *base = phy->regs;
1020
1021         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1022
1023         val = readl(base + USB_USBSTS);
1024         writel(val, base + USB_USBSTS);
1025         udelay(20);
1026         /* wait for two SOFs */
1027         if (usb_phy_reg_status_wait(base + USB_USBSTS, USB_USBSTS_SRI,
1028                 USB_USBSTS_SRI, 2500))
1029                 pr_err("%s: timeout waiting for SOF\n", __func__);
1030
1031         val = readl(base + USB_USBSTS);
1032         writel(val, base + USB_USBSTS);
1033         if (usb_phy_reg_status_wait(base + USB_USBSTS, USB_USBSTS_SRI, 0, 2500))
1034                 pr_err("%s: timeout waiting for SOF\n", __func__);
1035
1036         if (usb_phy_reg_status_wait(base + USB_USBSTS, USB_USBSTS_SRI,
1037                         USB_USBSTS_SRI, 2500))
1038                 pr_err("%s: timeout waiting for SOF\n", __func__);
1039
1040         udelay(20);
1041 }
1042
1043 static unsigned int utmi_phy_xcvr_setup_value(struct tegra_usb_phy *phy)
1044 {
1045         struct tegra_utmi_config *cfg = &phy->pdata->u_cfg.utmi;
1046         signed long val;
1047
1048         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1049
1050         if (cfg->xcvr_use_fuses) {
1051                 val = FUSE_USB_CALIB_XCVR_SETUP(
1052                                 tegra_fuse_readl(FUSE_USB_CALIB_0));
1053                 if (cfg->xcvr_setup_offset <= UTMIP_XCVR_MAX_OFFSET)
1054                         val = val + cfg->xcvr_setup_offset;
1055
1056                 if (val > UTMIP_XCVR_SETUP_MAX_VALUE) {
1057                         val = UTMIP_XCVR_SETUP_MAX_VALUE;
1058                         pr_info("%s: reset XCVR_SETUP to max value\n",
1059                                  __func__);
1060                 } else if (val < UTMIP_XCVR_SETUP_MIN_VALUE) {
1061                         val = UTMIP_XCVR_SETUP_MIN_VALUE;
1062                         pr_info("%s: reset XCVR_SETUP to min value\n",
1063                                  __func__);
1064                 }
1065         } else {
1066                 val = cfg->xcvr_setup;
1067         }
1068
1069         return (unsigned int) val;
1070 }
1071
1072 static int utmi_phy_open(struct tegra_usb_phy *phy)
1073 {
1074         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
1075         unsigned long parent_rate, val;
1076         int i;
1077
1078         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1079
1080         phy->utmi_pad_clk = clk_get_sys("utmip-pad", NULL);
1081         if (IS_ERR(phy->utmi_pad_clk)) {
1082                 pr_err("%s: can't get utmip pad clock\n", __func__);
1083                 return PTR_ERR(phy->utmi_pad_clk);
1084         }
1085
1086         phy->utmi_xcvr_setup = utmi_phy_xcvr_setup_value(phy);
1087
1088         parent_rate = clk_get_rate(clk_get_parent(phy->pllu_clk));
1089         for (i = 0; i < ARRAY_SIZE(utmip_freq_table); i++) {
1090                 if (utmip_freq_table[i].freq == parent_rate) {
1091                         phy->freq = &utmip_freq_table[i];
1092                         break;
1093                 }
1094         }
1095         if (!phy->freq) {
1096                 pr_err("invalid pll_u parent rate %ld\n", parent_rate);
1097                 return -EINVAL;
1098         }
1099
1100         /* Power-up the VBUS detector for UTMIP PHY */
1101         val = readl(pmc_base + PMC_USB_AO);
1102         val &= ~(PMC_USB_AO_VBUS_WAKEUP_PD_P0 | PMC_USB_AO_ID_PD_P0);
1103         writel((val | PMC_USB_AO_PD_P2), (pmc_base + PMC_USB_AO));
1104
1105         utmip_powerup_pmc_wake_detect(phy);
1106
1107         return 0;
1108 }
1109
1110 static void utmi_phy_close(struct tegra_usb_phy *phy)
1111 {
1112         unsigned long val;
1113         void __iomem *base = phy->regs;
1114
1115         DBG("%s inst:[%d]\n", __func__, phy->inst);
1116
1117         /* Disable PHY clock valid interrupts while going into suspend*/
1118         if (phy->pdata->u_data.host.hot_plug) {
1119                 val = readl(base + USB_SUSP_CTRL);
1120                 val &= ~USB_PHY_CLK_VALID_INT_ENB;
1121                 writel(val, base + USB_SUSP_CTRL);
1122         }
1123
1124         val = readl(base + USB_PORTSC);
1125         val |= USB_PORTSC_WKCN;
1126         writel(val, base + USB_PORTSC);
1127
1128         clk_put(phy->utmi_pad_clk);
1129 }
1130
1131 static int utmi_phy_pad_power_on(struct tegra_usb_phy *phy)
1132 {
1133         unsigned long val, flags;
1134         void __iomem *pad_base =  IO_ADDRESS(TEGRA_USB_BASE);
1135
1136         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1137
1138         clk_enable(phy->utmi_pad_clk);
1139
1140         spin_lock_irqsave(&utmip_pad_lock, flags);
1141         utmip_pad_count++;
1142
1143         val = readl(pad_base + UTMIP_BIAS_CFG0);
1144         val &= ~(UTMIP_OTGPD | UTMIP_BIASPD);
1145         val |= UTMIP_HSSQUELCH_LEVEL(0x2) | UTMIP_HSDISCON_LEVEL(0x1) |
1146                 UTMIP_HSDISCON_LEVEL_MSB;
1147         writel(val, pad_base + UTMIP_BIAS_CFG0);
1148
1149         spin_unlock_irqrestore(&utmip_pad_lock, flags);
1150
1151         clk_disable(phy->utmi_pad_clk);
1152
1153         return 0;
1154 }
1155
1156 static int utmi_phy_pad_power_off(struct tegra_usb_phy *phy)
1157 {
1158         unsigned long val, flags;
1159         void __iomem *pad_base =  IO_ADDRESS(TEGRA_USB_BASE);
1160
1161         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1162
1163         clk_enable(phy->utmi_pad_clk);
1164         spin_lock_irqsave(&utmip_pad_lock, flags);
1165
1166         if (!utmip_pad_count) {
1167                 pr_err("%s: utmip pad already powered off\n", __func__);
1168                 goto out;
1169         }
1170         if (--utmip_pad_count == 0) {
1171                 val = readl(pad_base + UTMIP_BIAS_CFG0);
1172                 val |= UTMIP_OTGPD | UTMIP_BIASPD;
1173                 val &= ~(UTMIP_HSSQUELCH_LEVEL(~0) | UTMIP_HSDISCON_LEVEL(~0) |
1174                         UTMIP_HSDISCON_LEVEL_MSB);
1175                 writel(val, pad_base + UTMIP_BIAS_CFG0);
1176         }
1177 out:
1178         spin_unlock_irqrestore(&utmip_pad_lock, flags);
1179         clk_disable(phy->utmi_pad_clk);
1180
1181         return 0;
1182 }
1183
1184 static int utmi_phy_irq(struct tegra_usb_phy *phy)
1185 {
1186         void __iomem *base = phy->regs;
1187         unsigned long val = 0;
1188
1189         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1190         DBG("USB_USBSTS[0x%x] USB_PORTSC[0x%x]\n",
1191                         readl(base + USB_USBSTS), readl(base + USB_PORTSC));
1192         DBG("USB_USBMODE[0x%x] USB_USBCMD[0x%x]\n",
1193                         readl(base + USB_USBMODE), readl(base + USB_USBCMD));
1194
1195         usb_phy_fence_read(phy);
1196         /* check if there is any remote wake event */
1197         if (utmi_phy_remotewake_detected(phy))
1198                 pr_info("%s: utmip remote wake detected\n", __func__);
1199
1200         if (phy->pdata->u_data.host.hot_plug) {
1201                 val = readl(base + USB_SUSP_CTRL);
1202                 if ((val  & USB_PHY_CLK_VALID_INT_STS)) {
1203                         val &= ~USB_PHY_CLK_VALID_INT_ENB |
1204                                         USB_PHY_CLK_VALID_INT_STS;
1205                         writel(val , (base + USB_SUSP_CTRL));
1206                         pr_info("%s: usb device plugged-in\n", __func__);
1207                         val = readl(base + USB_USBSTS);
1208                         if (!(val  & USB_USBSTS_PCI))
1209                                 return IRQ_NONE;
1210                         val = readl(base + USB_PORTSC);
1211                         val &= ~(USB_PORTSC_WKCN | USB_PORTSC_RWC_BITS);
1212                         writel(val , (base + USB_PORTSC));
1213                 }
1214         }
1215
1216         return IRQ_HANDLED;
1217 }
1218
1219 static void utmi_phy_enable_obs_bus(struct tegra_usb_phy *phy)
1220 {
1221         unsigned long val;
1222         void __iomem *base = phy->regs;
1223
1224         /* (2LS WAR)is not required for LS and FS devices and is only for HS */
1225         if ((phy->port_speed == USB_PHY_PORT_SPEED_LOW) ||
1226                 (phy->port_speed == USB_PHY_PORT_SPEED_FULL)) {
1227                 /* do not enable the OBS bus */
1228                 val = readl(base + UTMIP_MISC_CFG0);
1229                 val &= ~(UTMIP_DPDM_OBSERVE_SEL(~0));
1230                 writel(val, base + UTMIP_MISC_CFG0);
1231                 DBG("%s(%d) Disable OBS bus\n", __func__, __LINE__);
1232                 return;
1233         }
1234         /* Force DP/DM pulldown active for Host mode */
1235         val = readl(base + UTMIP_MISC_CFG0);
1236         val |= FORCE_PULLDN_DM | FORCE_PULLDN_DP |
1237                         COMB_TERMS | ALWAYS_FREE_RUNNING_TERMS;
1238         writel(val, base + UTMIP_MISC_CFG0);
1239         val = readl(base + UTMIP_MISC_CFG0);
1240         val &= ~UTMIP_DPDM_OBSERVE_SEL(~0);
1241         if (phy->port_speed == USB_PHY_PORT_SPEED_LOW)
1242                 val |= UTMIP_DPDM_OBSERVE_SEL_FS_J;
1243         else
1244                 val |= UTMIP_DPDM_OBSERVE_SEL_FS_K;
1245         writel(val, base + UTMIP_MISC_CFG0);
1246         udelay(1);
1247
1248         val = readl(base + UTMIP_MISC_CFG0);
1249         val |= UTMIP_DPDM_OBSERVE;
1250         writel(val, base + UTMIP_MISC_CFG0);
1251         udelay(10);
1252         DBG("%s(%d) Enable OBS bus\n", __func__, __LINE__);
1253 }
1254
1255 static void utmi_phy_disable_obs_bus(struct tegra_usb_phy *phy)
1256 {
1257         unsigned long val;
1258         void __iomem *base = phy->regs;
1259
1260         /* check if OBS bus is already enabled */
1261         val = readl(base + UTMIP_MISC_CFG0);
1262         if (val & UTMIP_DPDM_OBSERVE) {
1263                 /* Change the UTMIP OBS bus to drive SE0 */
1264                 val = readl(base + UTMIP_MISC_CFG0);
1265                 val &= ~UTMIP_DPDM_OBSERVE_SEL(~0);
1266                 val |= UTMIP_DPDM_OBSERVE_SEL_FS_SE0;
1267                 writel(val, base + UTMIP_MISC_CFG0);
1268
1269                 /* Wait for 3us(2 LS bit times) */
1270                 udelay(3);
1271
1272                 /* Release UTMIP OBS bus */
1273                 val = readl(base + UTMIP_MISC_CFG0);
1274                 val &= ~UTMIP_DPDM_OBSERVE;
1275                 writel(val, base + UTMIP_MISC_CFG0);
1276
1277                 /* Release DP/DM pulldown for Host mode */
1278                 val = readl(base + UTMIP_MISC_CFG0);
1279                 val &= ~(FORCE_PULLDN_DM | FORCE_PULLDN_DP |
1280                                 COMB_TERMS | ALWAYS_FREE_RUNNING_TERMS);
1281                 writel(val, base + UTMIP_MISC_CFG0);
1282         }
1283 }
1284
1285 static int utmi_phy_post_resume(struct tegra_usb_phy *phy)
1286 {
1287         unsigned long val;
1288         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
1289         unsigned  int inst = phy->inst;
1290
1291         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1292         val = readl(pmc_base + PMC_SLEEP_CFG);
1293         /* if PMC is not disabled by now then disable it */
1294         if (val & UTMIP_MASTER_ENABLE(inst)) {
1295                 utmip_phy_disable_pmc_bus_ctrl(phy);
1296         }
1297
1298         utmi_phy_disable_obs_bus(phy);
1299
1300         return 0;
1301 }
1302
1303 static int utmi_phy_pre_resume(struct tegra_usb_phy *phy, bool remote_wakeup)
1304 {
1305         unsigned long val;
1306         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
1307         unsigned  int inst = phy->inst;
1308
1309         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1310         val = readl(pmc_base + PMC_SLEEP_CFG);
1311         if (val & UTMIP_MASTER_ENABLE(inst)) {
1312                 if (!remote_wakeup)
1313                         utmip_phy_disable_pmc_bus_ctrl(phy);
1314         } else {
1315                 utmi_phy_enable_obs_bus(phy);
1316         }
1317
1318         return 0;
1319 }
1320
1321 static int utmi_phy_power_off(struct tegra_usb_phy *phy)
1322 {
1323         unsigned long val;
1324         void __iomem *base = phy->regs;
1325
1326         DBG("%s(%d) inst:[%d] BEGIN\n", __func__, __LINE__, phy->inst);
1327         if (!phy->phy_clk_on) {
1328                 DBG("%s(%d) inst:[%d] phy clk is already off\n",
1329                                         __func__, __LINE__, phy->inst);
1330                 return 0;
1331         }
1332
1333         if (phy->pdata->op_mode == TEGRA_USB_OPMODE_DEVICE) {
1334                 utmip_powerdown_pmc_wake_detect(phy);
1335
1336                 val = readl(base + USB_SUSP_CTRL);
1337                 val &= ~USB_WAKEUP_DEBOUNCE_COUNT(~0);
1338                 val |= USB_WAKE_ON_CNNT_EN_DEV | USB_WAKEUP_DEBOUNCE_COUNT(5);
1339                 writel(val, base + USB_SUSP_CTRL);
1340
1341                 val = readl(base + UTMIP_BAT_CHRG_CFG0);
1342                 val |= UTMIP_PD_CHRG;
1343                 writel(val, base + UTMIP_BAT_CHRG_CFG0);
1344         } else {
1345                 utmip_setup_pmc_wake_detect(phy);
1346         }
1347
1348         if (!phy->pdata->u_data.host.hot_plug) {
1349                 val = readl(base + UTMIP_XCVR_CFG0);
1350                 val |= (UTMIP_FORCE_PD_POWERDOWN | UTMIP_FORCE_PD2_POWERDOWN |
1351                          UTMIP_FORCE_PDZI_POWERDOWN);
1352                 writel(val, base + UTMIP_XCVR_CFG0);
1353         }
1354
1355         val = readl(base + UTMIP_XCVR_CFG1);
1356         val |= UTMIP_FORCE_PDDISC_POWERDOWN | UTMIP_FORCE_PDCHRP_POWERDOWN |
1357                    UTMIP_FORCE_PDDR_POWERDOWN;
1358         writel(val, base + UTMIP_XCVR_CFG1);
1359
1360         val = readl(base + UTMIP_BIAS_CFG1);
1361         val |= UTMIP_BIAS_PDTRK_COUNT(0x5);
1362         writel(val, base + UTMIP_BIAS_CFG1);
1363
1364         utmi_phy_pad_power_off(phy);
1365
1366         phy->port_speed = (readl(base + HOSTPC1_DEVLC) >> 25) &
1367                         HOSTPC1_DEVLC_PSPD_MASK;
1368
1369         if (phy->pdata->u_data.host.hot_plug) {
1370                 bool enable_hotplug = true;
1371                 /* if it is OTG port then make sure to enable hot-plug feature
1372                    only if host adaptor is connected, i.e id is low */
1373                 if (phy->pdata->port_otg) {
1374                         val = readl(base + USB_PHY_VBUS_WAKEUP_ID);
1375                         enable_hotplug = (val & USB_ID_STATUS) ? false : true;
1376                 }
1377                 if (enable_hotplug) {
1378                         val = readl(base + USB_PORTSC);
1379                         val |= USB_PORTSC_WKCN;
1380                         writel(val, base + USB_PORTSC);
1381
1382                         val = readl(base + USB_SUSP_CTRL);
1383                         val |= USB_PHY_CLK_VALID_INT_ENB;
1384                         writel(val, base + USB_SUSP_CTRL);
1385                 } else {
1386                         /* Disable PHY clock valid interrupts while going into suspend*/
1387                         val = readl(base + USB_SUSP_CTRL);
1388                         val &= ~USB_PHY_CLK_VALID_INT_ENB;
1389                         writel(val, base + USB_SUSP_CTRL);
1390                 }
1391         }
1392
1393         if (phy->inst == 0) {
1394                         val = readl(base + USB_SUSP_CTRL);
1395                         val |= UTMIP_RESET;
1396                         writel(val, base + USB_SUSP_CTRL);
1397         }
1398
1399         val = readl(base + HOSTPC1_DEVLC);
1400         val |= HOSTPC1_DEVLC_PHCD;
1401         writel(val, base + HOSTPC1_DEVLC);
1402
1403         if (usb_phy_reg_status_wait(base + USB_SUSP_CTRL, USB_PHY_CLK_VALID,
1404                                                                 0, 2500))
1405                 pr_warn("%s: timeout waiting for phy to stabilize\n", __func__);
1406
1407         phy->phy_clk_on = false;
1408         phy->hw_accessible = false;
1409
1410         DBG("%s(%d) inst:[%d] END\n", __func__, __LINE__, phy->inst);
1411
1412         return 0;
1413 }
1414
1415
1416 static int utmi_phy_power_on(struct tegra_usb_phy *phy)
1417 {
1418         unsigned long val;
1419         void __iomem *base = phy->regs;
1420         struct tegra_utmi_config *config = &phy->pdata->u_cfg.utmi;
1421
1422         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1423         if (phy->phy_clk_on) {
1424                 DBG("%s(%d) inst:[%d] phy clk is already On\n",
1425                                         __func__, __LINE__, phy->inst);
1426                 return 0;
1427         }
1428         val = readl(base + USB_SUSP_CTRL);
1429         val |= UTMIP_RESET;
1430         writel(val, base + USB_SUSP_CTRL);
1431
1432         val = readl(base + UTMIP_TX_CFG0);
1433         val |= UTMIP_FS_PREABMLE_J;
1434         writel(val, base + UTMIP_TX_CFG0);
1435
1436         val = readl(base + UTMIP_HSRX_CFG0);
1437         val &= ~(UTMIP_IDLE_WAIT(~0) | UTMIP_ELASTIC_LIMIT(~0));
1438         val |= UTMIP_IDLE_WAIT(config->idle_wait_delay);
1439         val |= UTMIP_ELASTIC_LIMIT(config->elastic_limit);
1440         writel(val, base + UTMIP_HSRX_CFG0);
1441
1442         val = readl(base + UTMIP_HSRX_CFG1);
1443         val &= ~UTMIP_HS_SYNC_START_DLY(~0);
1444         val |= UTMIP_HS_SYNC_START_DLY(config->hssync_start_delay);
1445         writel(val, base + UTMIP_HSRX_CFG1);
1446
1447         val = readl(base + UTMIP_DEBOUNCE_CFG0);
1448         val &= ~UTMIP_BIAS_DEBOUNCE_A(~0);
1449         val |= UTMIP_BIAS_DEBOUNCE_A(phy->freq->debounce);
1450         writel(val, base + UTMIP_DEBOUNCE_CFG0);
1451
1452         val = readl(base + UTMIP_MISC_CFG0);
1453         val &= ~UTMIP_SUSPEND_EXIT_ON_EDGE;
1454         writel(val, base + UTMIP_MISC_CFG0);
1455
1456         if (phy->pdata->op_mode == TEGRA_USB_OPMODE_DEVICE) {
1457                 val = readl(base + USB_SUSP_CTRL);
1458                 val &= ~(USB_WAKE_ON_CNNT_EN_DEV | USB_WAKE_ON_DISCON_EN_DEV);
1459                 writel(val, base + USB_SUSP_CTRL);
1460
1461                 val = readl(base + UTMIP_BAT_CHRG_CFG0);
1462                 val &= ~UTMIP_PD_CHRG;
1463                 writel(val, base + UTMIP_BAT_CHRG_CFG0);
1464         } else {
1465                 val = readl(base + UTMIP_BAT_CHRG_CFG0);
1466                 val |= UTMIP_PD_CHRG;
1467                 writel(val, base + UTMIP_BAT_CHRG_CFG0);
1468         }
1469
1470         utmi_phy_pad_power_on(phy);
1471
1472         val = readl(base + UTMIP_XCVR_CFG0);
1473         val &= ~(UTMIP_XCVR_LSBIAS_SEL | UTMIP_FORCE_PD_POWERDOWN |
1474                  UTMIP_FORCE_PD2_POWERDOWN | UTMIP_FORCE_PDZI_POWERDOWN |
1475                  UTMIP_XCVR_SETUP(~0) | UTMIP_XCVR_LSFSLEW(~0) |
1476                  UTMIP_XCVR_LSRSLEW(~0) | UTMIP_XCVR_HSSLEW_MSB(~0));
1477         val |= UTMIP_XCVR_SETUP(phy->utmi_xcvr_setup);
1478         val |= UTMIP_XCVR_SETUP_MSB(XCVR_SETUP_MSB_CALIB(phy->utmi_xcvr_setup));
1479         val |= UTMIP_XCVR_LSFSLEW(config->xcvr_lsfslew);
1480         val |= UTMIP_XCVR_LSRSLEW(config->xcvr_lsrslew);
1481         val |= UTMIP_XCVR_HSSLEW_MSB(0x8);
1482         writel(val, base + UTMIP_XCVR_CFG0);
1483
1484         val = readl(base + UTMIP_XCVR_CFG1);
1485         val &= ~(UTMIP_FORCE_PDDISC_POWERDOWN | UTMIP_FORCE_PDCHRP_POWERDOWN |
1486                  UTMIP_FORCE_PDDR_POWERDOWN | UTMIP_XCVR_TERM_RANGE_ADJ(~0));
1487         val |= UTMIP_XCVR_TERM_RANGE_ADJ(config->term_range_adj);
1488         writel(val, base + UTMIP_XCVR_CFG1);
1489
1490         val = readl(base + UTMIP_BIAS_CFG1);
1491         val &= ~UTMIP_BIAS_PDTRK_COUNT(~0);
1492         val |= UTMIP_BIAS_PDTRK_COUNT(phy->freq->pdtrk_count);
1493         writel(val, base + UTMIP_BIAS_CFG1);
1494
1495         val = readl(base + UTMIP_SPARE_CFG0);
1496         val &= ~FUSE_SETUP_SEL;
1497         val |= FUSE_ATERM_SEL;
1498         writel(val, base + UTMIP_SPARE_CFG0);
1499
1500         val = readl(base + USB_SUSP_CTRL);
1501         val |= UTMIP_PHY_ENABLE;
1502         writel(val, base + USB_SUSP_CTRL);
1503
1504         val = readl(base + USB_SUSP_CTRL);
1505         val &= ~UTMIP_RESET;
1506         writel(val, base + USB_SUSP_CTRL);
1507
1508         val = readl(base + HOSTPC1_DEVLC);
1509         val &= ~HOSTPC1_DEVLC_PHCD;
1510         writel(val, base + HOSTPC1_DEVLC);
1511
1512         if (usb_phy_reg_status_wait(base + USB_SUSP_CTRL,
1513                 USB_PHY_CLK_VALID, USB_PHY_CLK_VALID, 2500))
1514                 pr_warn("%s: timeout waiting for phy to stabilize\n", __func__);
1515
1516         utmi_phy_enable_trking_data(phy);
1517
1518         if (phy->inst == 2)
1519                 writel(0, base + ICUSB_CTRL);
1520
1521         val = readl(base + USB_USBMODE);
1522         val &= ~USB_USBMODE_MASK;
1523         if (phy->pdata->op_mode == TEGRA_USB_OPMODE_HOST)
1524                 val |= USB_USBMODE_HOST;
1525         else
1526                 val |= USB_USBMODE_DEVICE;
1527         writel(val, base + USB_USBMODE);
1528
1529         val = readl(base + HOSTPC1_DEVLC);
1530         val &= ~HOSTPC1_DEVLC_PTS(~0);
1531         val |= HOSTPC1_DEVLC_STS;
1532         writel(val, base + HOSTPC1_DEVLC);
1533
1534         if (phy->pdata->op_mode == TEGRA_USB_OPMODE_DEVICE)
1535                 utmip_powerup_pmc_wake_detect(phy);
1536         phy->phy_clk_on = true;
1537         phy->hw_accessible = true;
1538         DBG("%s(%d) End\n", __func__, __LINE__);
1539
1540         return 0;
1541 }
1542
1543 static void utmi_phy_restore_start(struct tegra_usb_phy *phy)
1544 {
1545         unsigned long val;
1546         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
1547         int inst = phy->inst;
1548
1549         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1550         val = readl(pmc_base + UTMIP_UHSIC_STATUS);
1551         /* check whether we wake up from the remote resume */
1552         if (UTMIP_WALK_PTR_VAL(inst) & val) {
1553                 phy->remote_wakeup = true;
1554         } else {
1555                 if (!((UTMIP_USBON_VAL(phy->inst) |
1556                         UTMIP_USBOP_VAL(phy->inst)) & val)) {
1557                                 utmip_phy_disable_pmc_bus_ctrl(phy);
1558                 }
1559         }
1560         utmi_phy_enable_obs_bus(phy);
1561 }
1562
1563 static void utmi_phy_restore_end(struct tegra_usb_phy *phy)
1564 {
1565         unsigned long val;
1566         void __iomem *base = phy->regs;
1567         int wait_time_us = 3000; /* FPR should be set by this time */
1568
1569         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1570         /* check whether we wake up from the remote resume */
1571         if (phy->remote_wakeup) {
1572                 /* wait until FPR bit is set automatically on remote resume */
1573                 do {
1574                         val = readl(base + USB_PORTSC);
1575                         udelay(1);
1576                         if (wait_time_us == 0)
1577                                 return;
1578                         wait_time_us--;
1579                 } while (!(val & USB_PORTSC_RESUME));
1580                 /* wait for 25 ms to port resume complete */
1581                 msleep(25);
1582                 /* disable PMC master control */
1583                 utmip_phy_disable_pmc_bus_ctrl(phy);
1584
1585                 /* Clear PCI and SRI bits to avoid an interrupt upon resume */
1586                 val = readl(base + USB_USBSTS);
1587                 writel(val, base + USB_USBSTS);
1588                 /* wait to avoid SOF if there is any */
1589                 if (usb_phy_reg_status_wait(base + USB_USBSTS,
1590                         USB_USBSTS_SRI, USB_USBSTS_SRI, 2500) < 0) {
1591                         pr_err("%s: timeout waiting for SOF\n", __func__);
1592                 }
1593                 utmi_phy_post_resume(phy);
1594         }
1595 }
1596
1597 static int utmi_phy_resume(struct tegra_usb_phy *phy)
1598 {
1599         int status = 0;
1600         unsigned long val;
1601         void __iomem *base = phy->regs;
1602
1603         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1604         if (phy->pdata->op_mode == TEGRA_USB_OPMODE_HOST) {
1605                 if (phy->port_speed < USB_PHY_PORT_SPEED_UNKNOWN) {
1606                         utmi_phy_restore_start(phy);
1607                         usb_phy_bringup_host_controller(phy);
1608                         utmi_phy_restore_end(phy);
1609                 } else {
1610                         /* device is plugged in when system is in LP0 */
1611                         /* bring up the controller from LP0*/
1612                         val = readl(base + USB_USBCMD);
1613                         val |= USB_CMD_RESET;
1614                         writel(val, base + USB_USBCMD);
1615
1616                         if (usb_phy_reg_status_wait(base + USB_USBCMD,
1617                                 USB_CMD_RESET, 0, 2500) < 0) {
1618                                 pr_err("%s: timeout waiting for reset\n", __func__);
1619                         }
1620
1621                         val = readl(base + USB_USBMODE);
1622                         val &= ~USB_USBMODE_MASK;
1623                         val |= USB_USBMODE_HOST;
1624                         writel(val, base + USB_USBMODE);
1625
1626                         val = readl(base + HOSTPC1_DEVLC);
1627                         val &= ~HOSTPC1_DEVLC_PTS(~0);
1628                         val |= HOSTPC1_DEVLC_STS;
1629                         writel(val, base + HOSTPC1_DEVLC);
1630
1631                         writel(USB_USBCMD_RS, base + USB_USBCMD);
1632
1633                         if (usb_phy_reg_status_wait(base + USB_USBCMD,
1634                                 USB_USBCMD_RS, USB_USBCMD_RS, 2500) < 0) {
1635                                 pr_err("%s: timeout waiting for run bit\n", __func__);
1636                         }
1637
1638                         /* Enable Port Power */
1639                         val = readl(base + USB_PORTSC);
1640                         val |= USB_PORTSC_PP;
1641                         writel(val, base + USB_PORTSC);
1642                         udelay(10);
1643
1644                         DBG("USB_USBSTS[0x%x] USB_PORTSC[0x%x]\n",
1645                         readl(base + USB_USBSTS), readl(base + USB_PORTSC));
1646                 }
1647         }
1648
1649         return status;
1650 }
1651
1652 static bool utmi_phy_charger_detect(struct tegra_usb_phy *phy)
1653 {
1654         unsigned long val;
1655         void __iomem *base = phy->regs;
1656         bool status;
1657
1658         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1659         if (phy->pdata->op_mode != TEGRA_USB_OPMODE_DEVICE) {
1660                 /* Charger detection is not there for ULPI
1661                  * return Charger not available */
1662                 return false;
1663         }
1664
1665         /* Enable charger detection logic */
1666         val = readl(base + UTMIP_BAT_CHRG_CFG0);
1667         val |= UTMIP_OP_SRC_EN | UTMIP_ON_SINK_EN;
1668         writel(val, base + UTMIP_BAT_CHRG_CFG0);
1669
1670         /* Source should be on for 100 ms as per USB charging spec */
1671         msleep(TDP_SRC_ON_MS);
1672
1673         val = readl(base + USB_PHY_VBUS_WAKEUP_ID);
1674         /* If charger is not connected disable the interrupt */
1675         val &= ~VDAT_DET_INT_EN;
1676         val |= VDAT_DET_CHG_DET;
1677         writel(val, base + USB_PHY_VBUS_WAKEUP_ID);
1678
1679         val = readl(base + USB_PHY_VBUS_WAKEUP_ID);
1680         if (val & VDAT_DET_STS)
1681                 status = true;
1682         else
1683                 status = false;
1684
1685         /* Disable charger detection logic */
1686         val = readl(base + UTMIP_BAT_CHRG_CFG0);
1687         val &= ~(UTMIP_OP_SRC_EN | UTMIP_ON_SINK_EN);
1688         writel(val, base + UTMIP_BAT_CHRG_CFG0);
1689
1690         /* Delay of 40 ms before we pull the D+ as per battery charger spec */
1691         msleep(TDPSRC_CON_MS);
1692
1693         return status;
1694 }
1695
1696 static int uhsic_phy_open(struct tegra_usb_phy *phy)
1697 {
1698         unsigned long parent_rate;
1699         int i;
1700
1701         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1702         parent_rate = clk_get_rate(clk_get_parent(phy->pllu_clk));
1703         for (i = 0; i < ARRAY_SIZE(uhsic_freq_table); i++) {
1704                 if (uhsic_freq_table[i].freq == parent_rate) {
1705                         phy->freq = &uhsic_freq_table[i];
1706                         break;
1707                 }
1708         }
1709         if (!phy->freq) {
1710                 pr_err("invalid pll_u parent rate %ld\n", parent_rate);
1711                 return -EINVAL;
1712         }
1713
1714         uhsic_powerup_pmc_wake_detect(phy);
1715
1716         return 0;
1717 }
1718
1719 static int uhsic_phy_irq(struct tegra_usb_phy *phy)
1720 {
1721         usb_phy_fence_read(phy);
1722         return IRQ_HANDLED;
1723 }
1724
1725 static int uhsic_phy_power_on(struct tegra_usb_phy *phy)
1726 {
1727         unsigned long val;
1728         void __iomem *base = phy->regs;
1729         struct tegra_hsic_config *config = &phy->pdata->u_cfg.hsic;
1730
1731         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1732
1733         utmip_powerup_pmc_wake_detect(phy);
1734
1735         if (phy->phy_clk_on) {
1736                 DBG("%s(%d) inst:[%d] phy clk is already On\n",
1737                                         __func__, __LINE__, phy->inst);
1738                 return 0;
1739         }
1740
1741         val = readl(base + UHSIC_PADS_CFG1);
1742         val &= ~(UHSIC_PD_BG | UHSIC_PD_TX | UHSIC_PD_TRK | UHSIC_PD_RX |
1743                         UHSIC_PD_ZI | UHSIC_RPD_DATA | UHSIC_RPD_STROBE);
1744         val |= UHSIC_RX_SEL;
1745         writel(val, base + UHSIC_PADS_CFG1);
1746         udelay(2);
1747
1748         val = readl(base + USB_SUSP_CTRL);
1749         val |= UHSIC_RESET;
1750         writel(val, base + USB_SUSP_CTRL);
1751         udelay(30);
1752
1753         val = readl(base + USB_SUSP_CTRL);
1754         val |= UHSIC_PHY_ENABLE;
1755         writel(val, base + USB_SUSP_CTRL);
1756
1757         val = readl(base + UHSIC_HSRX_CFG0);
1758         val |= UHSIC_IDLE_WAIT(config->idle_wait_delay);
1759         val |= UHSIC_ELASTIC_UNDERRUN_LIMIT(config->elastic_underrun_limit);
1760         val |= UHSIC_ELASTIC_OVERRUN_LIMIT(config->elastic_overrun_limit);
1761         writel(val, base + UHSIC_HSRX_CFG0);
1762
1763         val = readl(base + UHSIC_HSRX_CFG1);
1764         val |= UHSIC_HS_SYNC_START_DLY(config->sync_start_delay);
1765         writel(val, base + UHSIC_HSRX_CFG1);
1766
1767         /* WAR HSIC TX */
1768         val = readl(base + UHSIC_TX_CFG0);
1769         val &= ~UHSIC_HS_READY_WAIT_FOR_VALID;
1770         writel(val, base + UHSIC_TX_CFG0);
1771
1772         val = readl(base + UHSIC_MISC_CFG0);
1773         val |= UHSIC_SUSPEND_EXIT_ON_EDGE;
1774         /* Disable generic bus reset, to allow AP30 specific bus reset*/
1775         val |= UHSIC_DISABLE_BUSRESET;
1776         writel(val, base + UHSIC_MISC_CFG0);
1777
1778         val = readl(base + UHSIC_MISC_CFG1);
1779         val |= UHSIC_PLLU_STABLE_COUNT(phy->freq->stable_count);
1780         writel(val, base + UHSIC_MISC_CFG1);
1781
1782         val = readl(base + UHSIC_PLL_CFG1);
1783         val |= UHSIC_PLLU_ENABLE_DLY_COUNT(phy->freq->enable_delay);
1784         val |= UHSIC_XTAL_FREQ_COUNT(phy->freq->xtal_freq_count);
1785         writel(val, base + UHSIC_PLL_CFG1);
1786
1787         val = readl(base + USB_SUSP_CTRL);
1788         val &= ~(UHSIC_RESET);
1789         writel(val, base + USB_SUSP_CTRL);
1790         udelay(2);
1791
1792         val = readl(base + USB_USBMODE);
1793         val |= USB_USBMODE_HOST;
1794         writel(val, base + USB_USBMODE);
1795
1796         /* Change the USB controller PHY type to HSIC */
1797         val = readl(base + HOSTPC1_DEVLC);
1798         val &= ~HOSTPC1_DEVLC_PTS(HOSTPC1_DEVLC_PTS_MASK);
1799         val |= HOSTPC1_DEVLC_PTS(HOSTPC1_DEVLC_PTS_HSIC);
1800         val &= ~HOSTPC1_DEVLC_PSPD(HOSTPC1_DEVLC_PSPD_MASK);
1801         val |= HOSTPC1_DEVLC_PSPD(HOSTPC1_DEVLC_PSPD_HIGH_SPEED);
1802         writel(val, base + HOSTPC1_DEVLC);
1803
1804         val = readl(base + USB_TXFILLTUNING);
1805         if ((val & USB_FIFO_TXFILL_MASK) != USB_FIFO_TXFILL_THRES(0x10)) {
1806                 val = USB_FIFO_TXFILL_THRES(0x10);
1807                 writel(val, base + USB_TXFILLTUNING);
1808         }
1809
1810         val = readl(base + USB_PORTSC);
1811         val &= ~(USB_PORTSC_WKOC | USB_PORTSC_WKDS | USB_PORTSC_WKCN);
1812         writel(val, base + USB_PORTSC);
1813
1814         val = readl(base + UHSIC_PADS_CFG0);
1815         val &= ~(UHSIC_TX_RTUNEN);
1816         /* set Rtune impedance to 50 ohm */
1817         val |= UHSIC_TX_RTUNE(8);
1818         writel(val, base + UHSIC_PADS_CFG0);
1819
1820         if (usb_phy_reg_status_wait(base + USB_SUSP_CTRL,
1821                                 USB_PHY_CLK_VALID, USB_PHY_CLK_VALID, 2500)) {
1822                 pr_err("%s: timeout waiting for phy to stabilize\n", __func__);
1823                 return -ETIMEDOUT;
1824         }
1825
1826         phy->phy_clk_on = true;
1827         phy->hw_accessible = true;
1828
1829         return 0;
1830 }
1831
1832 static int uhsic_phy_power_off(struct tegra_usb_phy *phy)
1833 {
1834         unsigned long val;
1835         void __iomem *base = phy->regs;
1836
1837         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1838         if (!phy->phy_clk_on) {
1839                 DBG("%s(%d) inst:[%d] phy clk is already off\n",
1840                                         __func__, __LINE__, phy->inst);
1841                 return 0;
1842         }
1843
1844         val = readl(base + UHSIC_PADS_CFG1);
1845         val &= ~UHSIC_RPU_STROBE;
1846         val |= UHSIC_RPD_STROBE;
1847         writel(val, base + UHSIC_PADS_CFG1);
1848
1849         val = readl(base + USB_SUSP_CTRL);
1850         val |= UHSIC_RESET;
1851         writel(val, base + USB_SUSP_CTRL);
1852         udelay(30);
1853
1854         utmip_powerdown_pmc_wake_detect(phy);
1855
1856         phy->phy_clk_on = false;
1857         phy->hw_accessible = false;
1858
1859         return 0;
1860 }
1861
1862 static int uhsic_phy_bus_port_power(struct tegra_usb_phy *phy)
1863 {
1864         unsigned long val;
1865         void __iomem *base = phy->regs;
1866
1867         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1868         val = readl(base + UHSIC_STAT_CFG0);
1869         val &= ~UHSIC_CONNECT_DETECT;
1870         writel(val, base + UHSIC_STAT_CFG0);
1871
1872         val = readl(base + USB_USBMODE);
1873         val |= USB_USBMODE_HOST;
1874         writel(val, base + USB_USBMODE);
1875
1876         /* Change the USB controller PHY type to HSIC */
1877         val = readl(base + HOSTPC1_DEVLC);
1878         val &= ~(HOSTPC1_DEVLC_PTS(HOSTPC1_DEVLC_PTS_MASK));
1879         val |= HOSTPC1_DEVLC_PTS(HOSTPC1_DEVLC_PTS_HSIC);
1880         val &= ~(HOSTPC1_DEVLC_PSPD(HOSTPC1_DEVLC_PSPD_MASK));
1881         val |= HOSTPC1_DEVLC_PSPD(HOSTPC1_DEVLC_PSPD_HIGH_SPEED);
1882         writel(val, base + HOSTPC1_DEVLC);
1883
1884         val = readl(base + UHSIC_MISC_CFG0);
1885         val |= UHSIC_DETECT_SHORT_CONNECT;
1886         writel(val, base + UHSIC_MISC_CFG0);
1887         udelay(1);
1888
1889         val = readl(base + UHSIC_MISC_CFG0);
1890         val |= UHSIC_FORCE_XCVR_MODE;
1891         writel(val, base + UHSIC_MISC_CFG0);
1892
1893         val = readl(base + UHSIC_PADS_CFG1);
1894         val &= ~UHSIC_RPD_STROBE;
1895         /* safe to enable RPU on STROBE at all times during idle */
1896         val |= UHSIC_RPU_STROBE;
1897         writel(val, base + UHSIC_PADS_CFG1);
1898
1899         val = readl(base + USB_USBCMD);
1900         val &= ~USB_USBCMD_RS;
1901         writel(val, base + USB_USBCMD);
1902
1903         if (usb_phy_reg_status_wait(base + UHSIC_STAT_CFG0,
1904                         UHSIC_CONNECT_DETECT, UHSIC_CONNECT_DETECT, 25000)) {
1905                 pr_err("%s: timeout waiting for UHSIC_CONNECT_DETECT\n",
1906                                                                 __func__);
1907                 return -ETIMEDOUT;
1908         }
1909
1910         return 0;
1911 }
1912
1913 static int uhsic_phy_bus_reset(struct tegra_usb_phy *phy)
1914 {
1915         unsigned long val;
1916         void __iomem *base = phy->regs;
1917
1918         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1919
1920         /* Change the USB controller PHY type to HSIC */
1921         val = readl(base + HOSTPC1_DEVLC);
1922         val &= ~HOSTPC1_DEVLC_PTS(HOSTPC1_DEVLC_PTS_MASK);
1923         val |= HOSTPC1_DEVLC_PTS(HOSTPC1_DEVLC_PTS_HSIC);
1924         val &= ~HOSTPC1_DEVLC_PSPD(HOSTPC1_DEVLC_PSPD_MASK);
1925         val |= HOSTPC1_DEVLC_PSPD(HOSTPC1_DEVLC_PSPD_HIGH_SPEED);
1926         writel(val, base + HOSTPC1_DEVLC);
1927         /* wait here, otherwise HOSTPC1_DEVLC_PSPD will timeout */
1928         mdelay(5);
1929
1930         val = readl(base + USB_PORTSC);
1931         val |= USB_PORTSC_PTC(5);
1932         writel(val, base + USB_PORTSC);
1933         udelay(2);
1934
1935         val = readl(base + USB_PORTSC);
1936         val &= ~(USB_PORTSC_PTC(~0));
1937         writel(val, base + USB_PORTSC);
1938         udelay(2);
1939
1940         if (usb_phy_reg_status_wait(base + USB_PORTSC, USB_PORTSC_LS(0),
1941                                                  0, 2000)) {
1942                 pr_err("%s: timeout waiting for USB_PORTSC_LS\n", __func__);
1943                 return -ETIMEDOUT;
1944         }
1945
1946         /* Poll until CCS is enabled */
1947         if (usb_phy_reg_status_wait(base + USB_PORTSC, USB_PORTSC_CCS,
1948                                                  USB_PORTSC_CCS, 2000)) {
1949                 pr_err("%s: timeout waiting for USB_PORTSC_CCS\n", __func__);
1950                 return -ETIMEDOUT;
1951         }
1952
1953         if (usb_phy_reg_status_wait(base + HOSTPC1_DEVLC,
1954                         HOSTPC1_DEVLC_PSPD(2),
1955                         HOSTPC1_DEVLC_PSPD(2), 2000) < 0) {
1956                 pr_err("%s: timeout waiting hsic high speed configuration\n",
1957                                                 __func__);
1958                         return -ETIMEDOUT;
1959         }
1960
1961         val = readl(base + USB_USBCMD);
1962         val &= ~USB_USBCMD_RS;
1963         writel(val, base + USB_USBCMD);
1964
1965         if (usb_phy_reg_status_wait(base + USB_USBSTS, USB_USBSTS_HCH,
1966                                                  USB_USBSTS_HCH, 2000)) {
1967                 pr_err("%s: timeout waiting for USB_USBSTS_HCH\n", __func__);
1968                 return -ETIMEDOUT;
1969         }
1970
1971         val = readl(base + UHSIC_PADS_CFG1);
1972         val &= ~UHSIC_RPU_STROBE;
1973         val |= UHSIC_RPD_STROBE;
1974         writel(val, base + UHSIC_PADS_CFG1);
1975
1976         mdelay(50);
1977
1978         val = readl(base + UHSIC_PADS_CFG1);
1979         val &= ~UHSIC_RPD_STROBE;
1980         val |= UHSIC_RPU_STROBE;
1981         writel(val, base + UHSIC_PADS_CFG1);
1982
1983         val = readl(base + USB_USBCMD);
1984         val |= USB_USBCMD_RS;
1985         writel(val, base + USB_USBCMD);
1986
1987         val = readl(base + UHSIC_PADS_CFG1);
1988         val &= ~UHSIC_RPU_STROBE;
1989         writel(val, base + UHSIC_PADS_CFG1);
1990
1991         if (usb_phy_reg_status_wait(base + USB_USBCMD, USB_USBCMD_RS,
1992                                                  USB_USBCMD_RS, 2000)) {
1993                 pr_err("%s: timeout waiting for USB_USBCMD_RS\n", __func__);
1994                 return -ETIMEDOUT;
1995         }
1996
1997         return 0;
1998 }
1999
2000
2001 static int uhsic_phy_pre_resume(struct tegra_usb_phy *phy, bool remote_wakeup)
2002 {
2003         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2004
2005         usb_phy_wait_for_sof(phy);
2006
2007         return 0;
2008 }
2009
2010 static int uhsic_phy_resume(struct tegra_usb_phy *phy)
2011 {
2012         void __iomem *base = phy->regs;
2013         unsigned long val;
2014
2015         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2016
2017         /* Check if the phy resume from LP0. When the phy resume from LP0
2018          * USB register will be reset.to zero */
2019         if (!readl(base + USB_ASYNCLISTADDR)) {
2020
2021                 val = readl(base + USB_USBCMD);
2022                 val |= USB_CMD_RESET;
2023                 writel(val, base + USB_USBCMD);
2024
2025                 if (usb_phy_reg_status_wait(base + USB_USBCMD,
2026                         USB_CMD_RESET, 0, 2500) < 0) {
2027                         pr_err("%s: timeout waiting for reset\n", __func__);
2028                 }
2029
2030                 val = readl(base + USB_USBMODE);
2031                 val &= ~USB_USBMODE_MASK;
2032                 val |= USB_USBMODE_HOST;
2033                 writel(val, base + USB_USBMODE);
2034
2035                 /* Enable Port Power */
2036                 val = readl(base + USB_PORTSC);
2037                 val |= USB_PORTSC_PP;
2038                 writel(val, base + USB_PORTSC);
2039                 udelay(10);
2040
2041                 DBG("USB_USBSTS[0x%x] USB_PORTSC[0x%x]\n",
2042                 readl(base + USB_USBSTS), readl(base + USB_PORTSC));
2043
2044                 uhsic_phy_bus_port_power(phy);
2045         }
2046
2047         return 0;
2048 }
2049
2050 static int uhsic_phy_post_resume(struct tegra_usb_phy *phy)
2051 {
2052         unsigned long val;
2053         void __iomem *base = phy->regs;
2054
2055         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2056         val = readl(base + USB_TXFILLTUNING);
2057         if ((val & USB_FIFO_TXFILL_MASK) != USB_FIFO_TXFILL_THRES(0x10)) {
2058                 val = USB_FIFO_TXFILL_THRES(0x10);
2059                 writel(val, base + USB_TXFILLTUNING);
2060         }
2061
2062         return 0;
2063 }
2064
2065 static void ulpi_set_trimmer(struct tegra_usb_phy *phy)
2066 {
2067         struct tegra_ulpi_config *config = &phy->pdata->u_cfg.ulpi;
2068         void __iomem *base = phy->regs;
2069         unsigned long val;
2070
2071         val = ULPI_DATA_TRIMMER_SEL(config->data_trimmer);
2072         val |= ULPI_STPDIRNXT_TRIMMER_SEL(config->stpdirnxt_trimmer);
2073         val |= ULPI_DIR_TRIMMER_SEL(config->dir_trimmer);
2074         writel(val, base + ULPI_TIMING_CTRL_1);
2075         udelay(10);
2076
2077         val |= ULPI_DATA_TRIMMER_LOAD;
2078         val |= ULPI_STPDIRNXT_TRIMMER_LOAD;
2079         val |= ULPI_DIR_TRIMMER_LOAD;
2080         writel(val, base + ULPI_TIMING_CTRL_1);
2081 }
2082
2083 static void reset_utmip_uhsic(void __iomem *base)
2084 {
2085         unsigned long val;
2086
2087         val = readl(base + USB_SUSP_CTRL);
2088         val |= UHSIC_RESET;
2089         writel(val, base + USB_SUSP_CTRL);
2090
2091         val = readl(base + USB_SUSP_CTRL);
2092         val |= UTMIP_RESET;
2093         writel(val, base + USB_SUSP_CTRL);
2094 }
2095
2096 static void ulpi_set_host(void __iomem *base)
2097 {
2098         unsigned long val;
2099
2100         val = readl(base + USB_USBMODE);
2101         val |= USB_USBMODE_HOST;
2102         writel(val, base + USB_USBMODE);
2103
2104         val = readl(base + HOSTPC1_DEVLC);
2105         val |= HOSTPC1_DEVLC_PTS(2);
2106         writel(val, base + HOSTPC1_DEVLC);
2107 }
2108
2109
2110
2111 static inline void null_phy_set_tristate(bool enable)
2112 {
2113 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
2114         int tristate = (enable) ? TEGRA_TRI_TRISTATE : TEGRA_TRI_NORMAL;
2115         DBG("%s(%d) inst:[%s] FIXME enable pin group +++\n", __func__,
2116                                 __LINE__, enable ? "TRISTATE" : "NORMAL");
2117
2118         tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_DATA0, tristate);
2119         tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_DATA1, tristate);
2120         tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_DATA2, tristate);
2121         tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_DATA3, tristate);
2122         tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_DATA4, tristate);
2123         tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_DATA5, tristate);
2124         tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_DATA6, tristate);
2125         tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_DATA7, tristate);
2126         tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_NXT, tristate);
2127
2128         if (enable)
2129                 tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_DIR, tristate);
2130 #endif
2131
2132 }
2133
2134
2135 static int ulpi_null_phy_power_off(struct tegra_usb_phy *phy)
2136 {
2137         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2138
2139         if (!phy->phy_clk_on) {
2140                 DBG("%s(%d) inst:[%d] phy clk is already off\n", __func__,
2141                                                         __LINE__, phy->inst);
2142                 return 0;
2143         }
2144
2145         null_phy_set_tristate(true);
2146
2147         phy->phy_clk_on = false;
2148         phy->hw_accessible = false;
2149
2150         return 0;
2151 }
2152
2153 static int ulpi_null_phy_init(struct tegra_usb_phy *phy)
2154 {
2155         unsigned long val;
2156         void __iomem *base = phy->regs;
2157
2158         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2159         usb_phy_init(phy);
2160         val = readl(base + ULPIS2S_CTRL);
2161         val |=  ULPIS2S_SLV0_CLAMP_XMIT;
2162         writel(val, base + ULPIS2S_CTRL);
2163
2164         val = readl(base + USB_SUSP_CTRL);
2165         val |= ULPIS2S_SLV0_RESET;
2166         writel(val, base + USB_SUSP_CTRL);
2167         udelay(10);
2168
2169         return 0;
2170 }
2171
2172 static int ulpi_null_phy_irq(struct tegra_usb_phy *phy)
2173 {
2174         usb_phy_fence_read(phy);
2175         return IRQ_HANDLED;
2176 }
2177
2178 static int ulpi_null_phy_cmd_reset(struct tegra_usb_phy *phy)
2179 {
2180         unsigned long val;
2181         void __iomem *base = phy->regs;
2182
2183         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2184         ulpi_set_host(base);
2185
2186         /* remove slave0 reset */
2187         val = readl(base + USB_SUSP_CTRL);
2188         val &= ~ULPIS2S_SLV0_RESET;
2189         writel(val, base + USB_SUSP_CTRL);
2190
2191         val = readl(base + ULPIS2S_CTRL);
2192         val &=  ~ULPIS2S_SLV0_CLAMP_XMIT;
2193         writel(val, base + ULPIS2S_CTRL);
2194         udelay(10);
2195
2196         return 0;
2197 }
2198
2199 static int ulpi_null_phy_power_on(struct tegra_usb_phy *phy)
2200 {
2201         unsigned long val;
2202         void __iomem *base = phy->regs;
2203         struct tegra_ulpi_config *config = &phy->pdata->u_cfg.ulpi;
2204         static bool cold_boot = true;
2205
2206         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2207         if (phy->phy_clk_on) {
2208                 DBG("%s(%d) inst:[%d] phy clk is already On\n", __func__,
2209                                                         __LINE__, phy->inst);
2210                 return 0;
2211         }
2212         reset_utmip_uhsic(base);
2213
2214         /* remove ULPI PADS CLKEN reset */
2215         val = readl(base + USB_SUSP_CTRL);
2216         val &= ~ULPI_PADS_CLKEN_RESET;
2217         writel(val, base + USB_SUSP_CTRL);
2218         udelay(10);
2219
2220         val = readl(base + ULPI_TIMING_CTRL_0);
2221         val |= ULPI_OUTPUT_PINMUX_BYP | ULPI_CLKOUT_PINMUX_BYP;
2222         writel(val, base + ULPI_TIMING_CTRL_0);
2223
2224         val = readl(base + USB_SUSP_CTRL);
2225         val |= ULPI_PHY_ENABLE;
2226         writel(val, base + USB_SUSP_CTRL);
2227         udelay(10);
2228
2229         /* set timming parameters */
2230         val = readl(base + ULPI_TIMING_CTRL_0);
2231         val |= ULPI_SHADOW_CLK_LOOPBACK_EN;
2232         val &= ~ULPI_SHADOW_CLK_SEL;
2233         val &= ~ULPI_LBK_PAD_EN;
2234         val |= ULPI_SHADOW_CLK_DELAY(config->shadow_clk_delay);
2235         val |= ULPI_CLOCK_OUT_DELAY(config->clock_out_delay);
2236         val |= ULPI_LBK_PAD_E_INPUT_OR;
2237         writel(val, base + ULPI_TIMING_CTRL_0);
2238
2239         writel(0, base + ULPI_TIMING_CTRL_1);
2240         udelay(10);
2241
2242         /* start internal 60MHz clock */
2243         val = readl(base + ULPIS2S_CTRL);
2244         val |= ULPIS2S_ENA;
2245         val |= ULPIS2S_SUPPORT_DISCONNECT;
2246         val |= ULPIS2S_SPARE((phy->pdata->op_mode == TEGRA_USB_OPMODE_HOST) ? 3 : 1);
2247         val |= ULPIS2S_PLLU_MASTER_BLASTER60;
2248         writel(val, base + ULPIS2S_CTRL);
2249
2250         /* select ULPI_CORE_CLK_SEL to SHADOW_CLK */
2251         val = readl(base + ULPI_TIMING_CTRL_0);
2252         val |= ULPI_CORE_CLK_SEL;
2253         writel(val, base + ULPI_TIMING_CTRL_0);
2254         udelay(10);
2255
2256         /* enable ULPI null phy clock - can't set the trimmers before this */
2257         val = readl(base + ULPI_TIMING_CTRL_0);
2258         val |= ULPI_CLK_OUT_ENA;
2259         writel(val, base + ULPI_TIMING_CTRL_0);
2260         udelay(10);
2261
2262         if (usb_phy_reg_status_wait(base + USB_SUSP_CTRL, USB_PHY_CLK_VALID,
2263                                                  USB_PHY_CLK_VALID, 2500)) {
2264                 pr_err("%s: timeout waiting for phy to stabilize\n", __func__);
2265                 return -ETIMEDOUT;
2266         }
2267
2268         /* set ULPI trimmers */
2269         ulpi_set_trimmer(phy);
2270
2271         ulpi_set_host(base);
2272
2273         /* remove slave0 reset */
2274         val = readl(base + USB_SUSP_CTRL);
2275         val &= ~ULPIS2S_SLV0_RESET;
2276         writel(val, base + USB_SUSP_CTRL);
2277
2278         /* remove slave1 and line reset */
2279         val = readl(base + USB_SUSP_CTRL);
2280         val &= ~ULPIS2S_SLV1_RESET;
2281         val &= ~ULPIS2S_LINE_RESET;
2282
2283         /* remove ULPI PADS reset */
2284         val &= ~ULPI_PADS_RESET;
2285         writel(val, base + USB_SUSP_CTRL);
2286
2287         if (cold_boot) {
2288                 val = readl(base + ULPI_TIMING_CTRL_0);
2289                 val |= ULPI_CLK_PADOUT_ENA;
2290                 writel(val, base + ULPI_TIMING_CTRL_0);
2291                 cold_boot = false;
2292         }
2293         udelay(10);
2294
2295         phy->phy_clk_on = true;
2296         phy->hw_accessible = true;
2297
2298         return 0;
2299 }
2300
2301
2302 static int ulpi_null_phy_pre_resume(struct tegra_usb_phy *phy, bool remote_wakeup)
2303 {
2304         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2305
2306         usb_phy_wait_for_sof(phy);
2307         return 0;
2308 }
2309
2310 static struct tegra_usb_phy_ops utmi_phy_ops = {
2311         .init           = usb_phy_init,
2312         .open           = utmi_phy_open,
2313         .close          = utmi_phy_close,
2314         .irq            = utmi_phy_irq,
2315         .power_on       = utmi_phy_power_on,
2316         .power_off      = utmi_phy_power_off,
2317         .pre_resume = utmi_phy_pre_resume,
2318         .resume = utmi_phy_resume,
2319         .post_resume    = utmi_phy_post_resume,
2320         .charger_detect = utmi_phy_charger_detect,
2321 };
2322
2323 static struct tegra_usb_phy_ops uhsic_phy_ops = {
2324         .init           = usb_phy_init,
2325         .open           = uhsic_phy_open,
2326         .irq            = uhsic_phy_irq,
2327         .power_on       = uhsic_phy_power_on,
2328         .power_off      = uhsic_phy_power_off,
2329         .pre_resume = uhsic_phy_pre_resume,
2330         .resume = uhsic_phy_resume,
2331         .post_resume = uhsic_phy_post_resume,
2332         .port_power = uhsic_phy_bus_port_power,
2333         .bus_reset      = uhsic_phy_bus_reset,
2334 };
2335
2336 static struct tegra_usb_phy_ops ulpi_null_phy_ops = {
2337         .init           = ulpi_null_phy_init,
2338         .irq            = ulpi_null_phy_irq,
2339         .power_on       = ulpi_null_phy_power_on,
2340         .power_off      = ulpi_null_phy_power_off,
2341         .pre_resume = ulpi_null_phy_pre_resume,
2342         .reset          = ulpi_null_phy_cmd_reset,
2343 };
2344
2345 static struct tegra_usb_phy_ops ulpi_link_phy_ops;
2346 static struct tegra_usb_phy_ops icusb_phy_ops;
2347
2348 static struct tegra_usb_phy_ops *phy_ops[] = {
2349         [TEGRA_USB_PHY_INTF_UTMI] = &utmi_phy_ops,
2350         [TEGRA_USB_PHY_INTF_ULPI_LINK] = &ulpi_link_phy_ops,
2351         [TEGRA_USB_PHY_INTF_ULPI_NULL] = &ulpi_null_phy_ops,
2352         [TEGRA_USB_PHY_INTF_HSIC] = &uhsic_phy_ops,
2353         [TEGRA_USB_PHY_INTF_ICUSB] = &icusb_phy_ops,
2354 };
2355
2356 int tegra11x_usb_phy_init_ops(struct tegra_usb_phy *phy)
2357 {
2358         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2359
2360         phy->ops = phy_ops[phy->pdata->phy_intf];
2361
2362         /* FIXME: uncommenting below line to make USB host mode fail*/
2363         /* usb_phy_power_down_pmc(); */
2364
2365         return 0;
2366 }