ARM: tegra: pcie: Remove dock detect variable
[linux-3.10.git] / arch / arm / mach-tegra / tegra11_soctherm.c
1 /*
2  * arch/arm/mach-tegra/tegra11_soctherm.c
3  *
4  * Copyright (c) 2011-2013, NVIDIA CORPORATION. All rights reserved.
5  *
6  * This program is free software; you can redistribute it and/or modify it
7  * under the terms and conditions of the GNU General Public License,
8  * version 2, as published by the Free Software Foundation.
9  *
10  * This program is distributed in the hope it will be useful, but WITHOUT
11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13  * more details.
14  *
15  * You should have received a copy of the GNU General Public License
16  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
17  */
18
19 #include <linux/debugfs.h>
20 #include <linux/kernel.h>
21 #include <linux/module.h>
22 #include <linux/list.h>
23 #include <linux/mutex.h>
24 #include <linux/delay.h>
25 #include <linux/err.h>
26 #include <linux/gpio.h>
27 #include <linux/io.h>
28 #include <linux/clk.h>
29 #include <linux/cpufreq.h>
30 #include <linux/seq_file.h>
31 #include <linux/irq.h>
32 #include <linux/interrupt.h>
33 #include <linux/irqdomain.h>
34 #include <linux/slab.h>
35 #include <linux/suspend.h>
36 #include <linux/uaccess.h>
37 #include <linux/thermal.h>
38 #include <linux/platform_data/thermal_sensors.h>
39 #include <linux/bug.h>
40 #include <linux/tegra-fuse.h>
41
42
43 #include "iomap.h"
44 #include "tegra3_tsensor.h"
45 #include "tegra11_soctherm.h"
46 #include "gpio-names.h"
47 #include "common.h"
48
49 static const int MAX_HIGH_TEMP = 128000;
50
51 /* Min temp granularity specified as X in 2^X.
52  * -1: Hi precision option: 2^-1 = 0.5C (T12x onwards)
53  *  0: Lo precision option: 2^0  = 1.0C
54  */
55 #ifdef CONFIG_ARCH_TEGRA_12x_SOC
56 static const int precision = -1; /* Use high precision on T12x */
57 #else
58 static const int precision; /* default 0 -> low precision */
59 #endif
60
61 #define LOWER_PRECISION_FOR_CONV(val)   ((!precision) ? ((val)*2) : (val))
62 #define LOWER_PRECISION_FOR_TEMP(val)   ((!precision) ? ((val)/2) : (val))
63 #define PRECISION_IS_LOWER()            ((!precision))
64 #define PRECISION_TO_STR()              ((!precision) ? "Lo" : "Hi")
65
66 #define TS_TSENSE_REGS_SIZE             0x20
67 #define TS_TSENSE_REG_OFFSET(reg, ts)   ((reg) + ((ts) * TS_TSENSE_REGS_SIZE))
68
69 #define TS_THERM_LVL_REGS_SIZE          0x20
70 #define TS_THERM_GRP_REGS_SIZE          0x04
71 #define TS_THERM_REG_OFFSET(rg, lv, gr) ((rg) + ((lv) * TS_THERM_LVL_REGS_SIZE)\
72                                         + ((gr) * TS_THERM_GRP_REGS_SIZE))
73
74 #define CTL_LVL0_CPU0                   0x0
75 #define CTL_LVL0_CPU0_UP_THRESH_SHIFT   17
76 #define CTL_LVL0_CPU0_UP_THRESH_MASK    0xff
77 #define CTL_LVL0_CPU0_DN_THRESH_SHIFT   9
78 #define CTL_LVL0_CPU0_DN_THRESH_MASK    0xff
79 #define CTL_LVL0_CPU0_EN_SHIFT          8
80 #define CTL_LVL0_CPU0_EN_MASK           0x1
81 #define CTL_LVL0_CPU0_CPU_THROT_SHIFT   5
82 #define CTL_LVL0_CPU0_CPU_THROT_MASK    0x3
83 #define CTL_LVL0_CPU0_CPU_THROT_LIGHT   0x1
84 #define CTL_LVL0_CPU0_CPU_THROT_HEAVY   0x2
85 #define CTL_LVL0_CPU0_GPU_THROT_SHIFT   3
86 #define CTL_LVL0_CPU0_GPU_THROT_MASK    0x3
87 #define CTL_LVL0_CPU0_GPU_THROT_LIGHT   0x1
88 #define CTL_LVL0_CPU0_GPU_THROT_HEAVY   0x2
89 #define CTL_LVL0_CPU0_MEM_THROT_SHIFT   2
90 #define CTL_LVL0_CPU0_MEM_THROT_MASK    0x1
91 #define CTL_LVL0_CPU0_STATUS_SHIFT      0
92 #define CTL_LVL0_CPU0_STATUS_MASK       0x3
93
94 #define THERMTRIP                       0x80
95 #define THERMTRIP_ANY_EN_SHIFT          28
96 #define THERMTRIP_ANY_EN_MASK           0x1
97 #define THERMTRIP_MEM_EN_SHIFT          27
98 #define THERMTRIP_MEM_EN_MASK           0x1
99 #define THERMTRIP_GPU_EN_SHIFT          26
100 #define THERMTRIP_GPU_EN_MASK           0x1
101 #define THERMTRIP_CPU_EN_SHIFT          25
102 #define THERMTRIP_CPU_EN_MASK           0x1
103 #define THERMTRIP_TSENSE_EN_SHIFT       24
104 #define THERMTRIP_TSENSE_EN_MASK        0x1
105 #define THERMTRIP_GPUMEM_THRESH_SHIFT   16
106 #define THERMTRIP_GPUMEM_THRESH_MASK    0xff
107 #define THERMTRIP_CPU_THRESH_SHIFT      8
108 #define THERMTRIP_CPU_THRESH_MASK       0xff
109 #define THERMTRIP_TSENSE_THRESH_SHIFT   0
110 #define THERMTRIP_TSENSE_THRESH_MASK    0xff
111
112 #define TS_CPU0_CONFIG0                         0xc0
113 #define TS_CPU0_CONFIG0_TALL_SHIFT              8
114 #define TS_CPU0_CONFIG0_TALL_MASK               0xfffff
115 #define TS_CPU0_CONFIG0_TCALC_OVER_SHIFT        4
116 #define TS_CPU0_CONFIG0_TCALC_OVER_MASK         0x1
117 #define TS_CPU0_CONFIG0_OVER_SHIFT              3
118 #define TS_CPU0_CONFIG0_OVER_MASK               0x1
119 #define TS_CPU0_CONFIG0_CPTR_OVER_SHIFT         2
120 #define TS_CPU0_CONFIG0_CPTR_OVER_MASK          0x1
121 #define TS_CPU0_CONFIG0_STOP_SHIFT              0
122 #define TS_CPU0_CONFIG0_STOP_MASK               0x1
123
124 #define TS_CPU0_CONFIG1                 0xc4
125 #define TS_CPU0_CONFIG1_EN_SHIFT        31
126 #define TS_CPU0_CONFIG1_EN_MASK         0x1
127 #define TS_CPU0_CONFIG1_TIDDQ_SHIFT     15
128 #define TS_CPU0_CONFIG1_TIDDQ_MASK      0x3f
129 #define TS_CPU0_CONFIG1_TEN_COUNT_SHIFT 24
130 #define TS_CPU0_CONFIG1_TEN_COUNT_MASK  0x3f
131 #define TS_CPU0_CONFIG1_TSAMPLE_SHIFT   0
132 #define TS_CPU0_CONFIG1_TSAMPLE_MASK    0x3ff
133
134 #define TS_CPU0_CONFIG2                 0xc8
135 #define TS_CPU0_CONFIG2_THERM_A_SHIFT   16
136 #define TS_CPU0_CONFIG2_THERM_A_MASK    0xffff
137 #define TS_CPU0_CONFIG2_THERM_B_SHIFT   0
138 #define TS_CPU0_CONFIG2_THERM_B_MASK    0xffff
139
140 #define TS_CPU0_STATUS0                 0xcc
141 #define TS_CPU0_STATUS0_VALID_SHIFT     31
142 #define TS_CPU0_STATUS0_VALID_MASK      0x1
143 #define TS_CPU0_STATUS0_CAPTURE_SHIFT   0
144 #define TS_CPU0_STATUS0_CAPTURE_MASK    0xffff
145
146 #define TS_CPU0_STATUS1                         0xd0
147 #define TS_CPU0_STATUS1_TEMP_VALID_SHIFT        31
148 #define TS_CPU0_STATUS1_TEMP_VALID_MASK         0x1
149 #define TS_CPU0_STATUS1_TEMP_SHIFT              0
150 #define TS_CPU0_STATUS1_TEMP_MASK               0xffff
151
152 #define TS_CPU0_STATUS2                 0xd4
153
154 #define TS_PDIV                         0x1c0
155 #define TS_PDIV_CPU_SHIFT               12
156 #define TS_PDIV_CPU_MASK                0xf
157 #define TS_PDIV_GPU_SHIFT               8
158 #define TS_PDIV_GPU_MASK                0xf
159 #define TS_PDIV_MEM_SHIFT               4
160 #define TS_PDIV_MEM_MASK                0xf
161 #define TS_PDIV_PLLX_SHIFT              0
162 #define TS_PDIV_PLLX_MASK               0xf
163
164 #define TS_HOTSPOT_OFF                  0x1c4
165 #define TS_HOTSPOT_OFF_CPU_SHIFT        16
166 #define TS_HOTSPOT_OFF_CPU_MASK         0xff
167 #define TS_HOTSPOT_OFF_GPU_SHIFT        8
168 #define TS_HOTSPOT_OFF_GPU_MASK         0xff
169 #define TS_HOTSPOT_OFF_MEM_SHIFT        0
170 #define TS_HOTSPOT_OFF_MEM_MASK         0xff
171
172 #define TS_TEMP1                        0x1c8
173 #define TS_TEMP1_CPU_TEMP_SHIFT         16
174 #define TS_TEMP1_CPU_TEMP_MASK          0xffff
175 #define TS_TEMP1_GPU_TEMP_SHIFT         0
176 #define TS_TEMP1_GPU_TEMP_MASK          0xffff
177
178 #define TS_TEMP2                        0x1cc
179 #define TS_TEMP2_MEM_TEMP_SHIFT         16
180 #define TS_TEMP2_MEM_TEMP_MASK          0xffff
181 #define TS_TEMP2_PLLX_TEMP_SHIFT        0
182 #define TS_TEMP2_PLLX_TEMP_MASK         0xffff
183
184 #define TS_TEMP_SW_OVERRIDE             0x1d8
185
186 #define TH_INTR_STATUS                  0x84
187 #define TH_INTR_ENABLE                  0x88
188 #define TH_INTR_DISABLE                 0x8c
189
190 #define LOCK_CTL                        0x90
191
192 #define TH_INTR_POS_MD3_SHIFT           31
193 #define TH_INTR_POS_MD3_MASK            0x1
194 #define TH_INTR_POS_MU3_SHIFT           30
195 #define TH_INTR_POS_MU3_MASK            0x1
196 #define TH_INTR_POS_MD2_SHIFT           29
197 #define TH_INTR_POS_MD2_MASK            0x1
198 #define TH_INTR_POS_MU2_SHIFT           28
199 #define TH_INTR_POS_MU2_MASK            0x1
200 #define TH_INTR_POS_MD1_SHIFT           27
201 #define TH_INTR_POS_MD1_MASK            0x1
202 #define TH_INTR_POS_MU1_SHIFT           26
203 #define TH_INTR_POS_MU1_MASK            0x1
204 #define TH_INTR_POS_MD0_SHIFT           25
205 #define TH_INTR_POS_MD0_MASK            0x1
206 #define TH_INTR_POS_MU0_SHIFT           24
207 #define TH_INTR_POS_MU0_MASK            0x1
208 #define TH_INTR_POS_GD3_SHIFT           23
209 #define TH_INTR_POS_GD3_MASK            0x1
210 #define TH_INTR_POS_GU3_SHIFT           22
211 #define TH_INTR_POS_GU3_MASK            0x1
212 #define TH_INTR_POS_GD2_SHIFT           21
213 #define TH_INTR_POS_GD2_MASK            0x1
214 #define TH_INTR_POS_GU2_SHIFT           20
215 #define TH_INTR_POS_GU2_MASK            0x1
216 #define TH_INTR_POS_GD1_SHIFT           19
217 #define TH_INTR_POS_GD1_MASK            0x1
218 #define TH_INTR_POS_GU1_SHIFT           18
219 #define TH_INTR_POS_GU1_MASK            0x1
220 #define TH_INTR_POS_GD0_SHIFT           17
221 #define TH_INTR_POS_GD0_MASK            0x1
222 #define TH_INTR_POS_GU0_SHIFT           16
223 #define TH_INTR_POS_GU0_MASK            0x1
224 #define TH_INTR_POS_CD3_SHIFT           15
225 #define TH_INTR_POS_CD3_MASK            0x1
226 #define TH_INTR_POS_CU3_SHIFT           14
227 #define TH_INTR_POS_CU3_MASK            0x1
228 #define TH_INTR_POS_CD2_SHIFT           13
229 #define TH_INTR_POS_CD2_MASK            0x1
230 #define TH_INTR_POS_CU2_SHIFT           12
231 #define TH_INTR_POS_CU2_MASK            0x1
232 #define TH_INTR_POS_CD1_SHIFT           11
233 #define TH_INTR_POS_CD1_MASK            0x1
234 #define TH_INTR_POS_CU1_SHIFT           10
235 #define TH_INTR_POS_CU1_MASK            0x1
236 #define TH_INTR_POS_CD0_SHIFT           9
237 #define TH_INTR_POS_CD0_MASK            0x1
238 #define TH_INTR_POS_CU0_SHIFT           8
239 #define TH_INTR_POS_CU0_MASK            0x1
240 #define TH_INTR_POS_PD3_SHIFT           7
241 #define TH_INTR_POS_PD3_MASK            0x1
242 #define TH_INTR_POS_PU3_SHIFT           6
243 #define TH_INTR_POS_PU3_MASK            0x1
244 #define TH_INTR_POS_PD2_SHIFT           5
245 #define TH_INTR_POS_PD2_MASK            0x1
246 #define TH_INTR_POS_PU2_SHIFT           4
247 #define TH_INTR_POS_PU2_MASK            0x1
248 #define TH_INTR_POS_PD1_SHIFT           3
249 #define TH_INTR_POS_PD1_MASK            0x1
250 #define TH_INTR_POS_PU1_SHIFT           2
251 #define TH_INTR_POS_PU1_MASK            0x1
252 #define TH_INTR_POS_PD0_SHIFT           1
253 #define TH_INTR_POS_PD0_MASK            0x1
254 #define TH_INTR_POS_PU0_SHIFT           0
255 #define TH_INTR_POS_PU0_MASK            0x1
256
257
258 #define UP_STATS_L0             0x10
259 #define DN_STATS_L0             0x14
260
261 #define STATS_CTL               0x94
262 #define STATS_CTL_CLR_DN        0x8
263 #define STATS_CTL_EN_DN         0x4
264 #define STATS_CTL_CLR_UP        0x2
265 #define STATS_CTL_EN_UP         0x1
266
267 #define THROT_GLOBAL_CFG        0x400
268
269 #define OC1_CFG                         0x310
270 #define OC1_CFG_LONG_LATENCY_SHIFT      6
271 #define OC1_CFG_LONG_LATENCY_MASK       0x1
272 #define OC1_CFG_HW_RESTORE_SHIFT        5
273 #define OC1_CFG_HW_RESTORE_MASK         0x1
274 #define OC1_CFG_PWR_GOOD_MASK_SHIFT     4
275 #define OC1_CFG_PWR_GOOD_MASK_MASK      0x1
276 #define OC1_CFG_THROTTLE_MODE_SHIFT     2
277 #define OC1_CFG_THROTTLE_MODE_MASK      0x3
278 #define OC1_CFG_ALARM_POLARITY_SHIFT    1
279 #define OC1_CFG_ALARM_POLARITY_MASK     0x1
280 #define OC1_CFG_EN_THROTTLE_SHIFT       0
281 #define OC1_CFG_EN_THROTTLE_MASK        0x1
282
283 #define OC1_CNT_THRESHOLD               0x314
284 #define OC1_THRESHOLD_PERIOD            0x318
285 #define OC1_ALARM_COUNT                 0x31c
286 #define OC1_FILTER                      0x320
287
288 #define OC1_STATS                       0x3a8
289
290 #define OC_INTR_STATUS                  0x39c
291 #define OC_INTR_ENABLE                  0x3a0
292 #define OC_INTR_DISABLE                 0x3a4
293 #define OC_INTR_POS_OC1_SHIFT           0
294 #define OC_INTR_POS_OC1_MASK            0x1
295 #define OC_INTR_POS_OC2_SHIFT           1
296 #define OC_INTR_POS_OC2_MASK            0x1
297 #define OC_INTR_POS_OC3_SHIFT           2
298 #define OC_INTR_POS_OC3_MASK            0x1
299 #define OC_INTR_POS_OC4_SHIFT           3
300 #define OC_INTR_POS_OC4_MASK            0x1
301 #define OC_INTR_POS_OC5_SHIFT           4
302 #define OC_INTR_POS_OC5_MASK            0x1
303
304 #define OC_STATS_CTL                    0x3c4
305 #define OC_STATS_CTL_CLR_ALL            0x2
306 #define OC_STATS_CTL_EN_ALL             0x1
307
308 #define CPU_PSKIP_STATUS                        0x418
309 #define GPU_PSKIP_STATUS                        0x41c
310 #define XPU_PSKIP_STATUS_M_SHIFT                12
311 #define XPU_PSKIP_STATUS_M_MASK                 0xff
312 #define XPU_PSKIP_STATUS_N_SHIFT                4
313 #define XPU_PSKIP_STATUS_N_MASK                 0xff
314 #define XPU_PSKIP_STATUS_ENABLED_SHIFT          0
315 #define XPU_PSKIP_STATUS_ENABLED_MASK           0x1
316
317 #define THROT_PRIORITY_LOCK                     0x424
318 #define THROT_PRIORITY_LOCK_PRIORITY_SHIFT      0
319 #define THROT_PRIORITY_LOCK_PRIORITY_MASK       0xff
320
321 #define THROT_STATUS                            0x428
322 #define THROT_STATUS_BREACH_SHIFT               12
323 #define THROT_STATUS_BREACH_MASK                0x1
324 #define THROT_STATUS_STATE_SHIFT                4
325 #define THROT_STATUS_STATE_MASK                 0xff
326 #define THROT_STATUS_ENABLED_SHIFT              0
327 #define THROT_STATUS_ENABLED_MASK               0x1
328
329 #define THROT_PSKIP_CTRL_LITE_CPU               0x430
330 #define THROT_PSKIP_CTRL_ENABLE_SHIFT           31
331 #define THROT_PSKIP_CTRL_ENABLE_MASK            0x1
332 #define THROT_PSKIP_CTRL_DIVIDEND_SHIFT         8
333 #define THROT_PSKIP_CTRL_DIVIDEND_MASK          0xff
334 #define THROT_PSKIP_CTRL_DIVISOR_SHIFT          0
335 #define THROT_PSKIP_CTRL_DIVISOR_MASK           0xff
336
337 #define THROT_PSKIP_RAMP_LITE_CPU               0x434
338 #define THROT_PSKIP_RAMP_DURATION_SHIFT         8
339 #define THROT_PSKIP_RAMP_DURATION_MASK          0xffff
340 #define THROT_PSKIP_RAMP_STEP_SHIFT             0
341 #define THROT_PSKIP_RAMP_STEP_MASK              0xff
342
343 #define THROT_PSKIP_CTRL_LITE_GPU       0x438
344 #define THROT_PSKIP_CTRL_THROT_DEPTH_SHIFT              16
345 #define THROT_PSKIP_CTRL_THROT_DEPTH_MASK               0x7
346 #define THROT_DEPTH_NONE        0x0
347 #define THROT_DEPTH_LOW         0x1
348 #define THROT_DEPTH_MED         0x2
349 #define THROT_DEPTH_HIG         0x4
350
351 #define THROT_PRIORITY_LITE                     0x444
352 #define THROT_PRIORITY_LITE_PRIO_SHIFT          0
353 #define THROT_PRIORITY_LITE_PRIO_MASK           0xff
354
355 #define THROT_DELAY_LITE                        0x448
356 #define THROT_DELAY_LITE_DELAY_SHIFT            0
357 #define THROT_DELAY_LITE_DELAY_MASK             0xff
358
359 #define THROT_OFFSET                            0x30
360 #define ALARM_OFFSET                            0x14
361
362 #define FUSE_TSENSOR_CALIB_FT_SHIFT     13
363 #define FUSE_TSENSOR_CALIB_FT_MASK      0x1fff
364 #define FUSE_TSENSOR_CALIB_CP_SHIFT     0
365 #define FUSE_TSENSOR_CALIB_CP_MASK      0x1fff
366 #define FUSE_TSENSOR_CALIB_BITS         13
367
368 /* car register offsets needed for enabling HW throttling */
369 #define CAR_SUPER_CCLKG_DIVIDER         0x36c
370 #define CDIVG_USE_THERM_CONTROLS_SHIFT  30
371 #define CDIVG_USE_THERM_CONTROLS_MASK   0x1
372
373 /* pmc register offsets needed for powering off PMU */
374 #define PMC_SCRATCH_WRITE_SHIFT                 2
375 #define PMC_SCRATCH_WRITE_MASK                  0x1
376 #define PMC_ENABLE_RST_SHIFT                    1
377 #define PMC_ENABLE_RST_MASK                     0x1
378 #define PMC_SENSOR_CTRL                         0x1B0
379 #define PMC_SCRATCH54                           0x258
380 #define PMC_SCRATCH55                           0x25C
381
382 /* scratch54 register bit fields */
383 #define PMU_OFF_DATA_SHIFT                      8
384 #define PMU_OFF_DATA_MASK                       0xff
385 #define PMU_OFF_ADDR_SHIFT                      0
386 #define PMU_OFF_ADDR_MASK                       0xff
387
388 /* scratch55 register bit fields */
389 #define RESET_TEGRA_SHIFT                       31
390 #define RESET_TEGRA_MASK                        0x1
391 #define CONTROLLER_TYPE_SHIFT                   30
392 #define CONTROLLER_TYPE_MASK                    0x1
393 #define I2C_CONTROLLER_ID_SHIFT                 27
394 #define I2C_CONTROLLER_ID_MASK                  0x7
395 #define PINMUX_SHIFT                            24
396 #define PINMUX_MASK                             0x7
397 #define CHECKSUM_SHIFT                          16
398 #define CHECKSUM_MASK                           0xff
399 #define PMU_16BIT_SUPPORT_SHIFT                 15
400 #define PMU_16BIT_SUPPORT_MASK                  0x1
401 #define PMU_I2C_ADDRESS_SHIFT                   0
402 #define PMU_I2C_ADDRESS_MASK                    0x7f
403
404 #define THROT_PSKIP_CTRL(throt, dev)            (THROT_PSKIP_CTRL_LITE_CPU + \
405                                                 (THROT_OFFSET * throt) + \
406                                                 (8 * dev))
407 #define THROT_PSKIP_RAMP(throt, dev)            (THROT_PSKIP_RAMP_LITE_CPU + \
408                                                 (THROT_OFFSET * throt) + \
409                                                 (8 * dev))
410 #define THROT_PRIORITY_CTRL(throt)              (THROT_PRIORITY_LITE + \
411                                                 (THROT_OFFSET * throt))
412 #define THROT_DELAY_CTRL(throt)                 (THROT_DELAY_LITE + \
413                                                 (THROT_OFFSET * throt))
414 #define ALARM_CFG(throt)                        (OC1_CFG + \
415                                                 (ALARM_OFFSET * (throt - \
416                                                                 THROTTLE_OC1)))
417 #define ALARM_CNT_THRESHOLD(throt)              (OC1_CNT_THRESHOLD + \
418                                                 (ALARM_OFFSET * (throt - \
419                                                                 THROTTLE_OC1)))
420 #define ALARM_THRESHOLD_PERIOD(throt)           (OC1_THRESHOLD_PERIOD + \
421                                                 (ALARM_OFFSET * (throt - \
422                                                                 THROTTLE_OC1)))
423 #define ALARM_ALARM_COUNT(throt)                (OC1_ALARM_COUNT + \
424                                                 (ALARM_OFFSET * (throt - \
425                                                                 THROTTLE_OC1)))
426 #define ALARM_FILTER(throt)                     (OC1_FILTER + \
427                                                 (ALARM_OFFSET * (throt - \
428                                                                 THROTTLE_OC1)))
429 #define ALARM_STATS(throt)                      (OC1_STATS + \
430                                                 (4 * (throt - THROTTLE_OC1)))
431
432 #define THROT_DEPTH_DIVIDEND(depth)     ((256 * (100 - (depth)) / 100) - 1)
433 #define THROT_DEPTH_DEFAULT             (80)
434 #define THROT_DEPTH(th, dp)             {                       \
435                 (th)->depth    = (dp);                          \
436                 (th)->dividend = THROT_DEPTH_DIVIDEND(dp);      \
437                 (th)->divisor  = 255;                           \
438                 (th)->duration = 0xff;                          \
439                 (th)->step     = 0xf;                           \
440         }
441
442 #define REG_SET(r, _name, val)  (((r) & ~(_name##_MASK << _name##_SHIFT)) | \
443                                  (((val) & _name##_MASK) << _name##_SHIFT))
444 #define REG_GET_BIT(r, _name)   ((r) & (_name##_MASK << _name##_SHIFT))
445 #define REG_GET(r, _name)       (REG_GET_BIT(r, _name) >> _name##_SHIFT)
446 #define MAKE_SIGNED32(val, nb)  ((s32)(val) << (32 - (nb)) >> (32 - (nb)))
447
448 static void __iomem *reg_soctherm_base = IO_ADDRESS(TEGRA_SOCTHERM_BASE);
449 static void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
450 static void __iomem *clk_reset_base = IO_ADDRESS(TEGRA_CLK_RESET_BASE);
451
452 static DEFINE_MUTEX(soctherm_suspend_resume_lock);
453
454 static int soctherm_suspend(void);
455 static int soctherm_resume(void);
456
457 static struct soctherm_platform_data plat_data;
458
459 /*
460  * Remove this flag once this "driver" is structured as a platform driver and
461  * the board files calls platform_device_register instead of directly calling
462  * tegra11_soctherm_init(). See nvbug 1206311.
463  */
464 static bool soctherm_init_platform_done;
465 static bool read_hw_temp = true;
466 static bool soctherm_suspended;
467 static bool soctherm_high_voltage_range = true;
468 static u32 tegra_chip_id;
469
470 static struct clk *soctherm_clk;
471 static struct clk *tsensor_clk;
472
473 static inline void soctherm_writel(u32 value, u32 reg)
474 {
475         if (!soctherm_suspended)
476                 __raw_writel(value, (void *)
477                         (reg_soctherm_base + reg));
478 }
479
480 static inline u32 soctherm_readl(u32 reg)
481 {
482         if (soctherm_suspended)
483                 return 0;
484         return __raw_readl(reg_soctherm_base + reg);
485 }
486
487 static inline void pmc_writel(u32 value, u32 reg)
488 {
489         __raw_writel(value, (void *)
490                 (pmc_base + reg));
491 }
492
493 static inline u32 pmc_readl(u32 reg)
494 {
495         return __raw_readl(pmc_base + reg);
496 }
497
498 static inline void clk_reset_writel(u32 value, u32 reg)
499 {
500         __raw_writel(value, (void *)
501                 (clk_reset_base + reg));
502 }
503
504 static inline u32 clk_reset_readl(u32 reg)
505 {
506         return __raw_readl(clk_reset_base + reg);
507 }
508
509 static inline long temp_convert(int cap, int a, int b)
510 {
511         cap *= a;
512         cap >>= 10;
513         cap += (b << 3);
514         cap *= LOWER_PRECISION_FOR_CONV(500);
515         cap /= 8;
516         return cap;
517 }
518
519 static inline u32 temp_translate_rev(long temp)
520 {
521         int sign;
522         int low_bit;
523
524         u32 lsb = 0;
525         u32 abs = 0;
526         u32 reg = 0;
527         sign = (temp > 0 ? 1 : -1);
528         low_bit = (sign > 0 ? 0 : 1);
529         temp *= sign;
530         /* high precision only */
531         if (!PRECISION_IS_LOWER()) {
532                 lsb = ((temp % 1000) > 0) ? 1 : 0;
533                 abs = (temp - 500 * lsb) / 1000;
534                 abs &= 0xff;
535                 reg = ((abs << 8) | (lsb << 7) | low_bit);
536         }
537         return reg;
538 }
539
540 #ifdef CONFIG_THERMAL
541 static struct thermal_zone_device *thz[THERM_SIZE];
542 #endif
543 struct soctherm_oc_irq_chip_data {
544         int                     irq_base;
545         struct mutex            irq_lock;
546         struct irq_chip         irq_chip;
547         struct irq_domain       *domain;
548         int                     irq_enable;
549 };
550 static struct soctherm_oc_irq_chip_data soc_irq_cdata;
551
552 static u32 fuse_calib_base_cp;
553 static u32 fuse_calib_base_ft;
554 static s32 actual_temp_cp;
555 static s32 actual_temp_ft;
556
557 static const char *const therm_names[] = {
558         [THERM_CPU] = "CPU",
559         [THERM_MEM] = "MEM",
560         [THERM_GPU] = "GPU",
561         [THERM_PLL] = "PLL",
562 };
563
564 static const char *const throt_names[] = {
565         [THROTTLE_LIGHT]   = "light",
566         [THROTTLE_HEAVY]   = "heavy",
567         [THROTTLE_OC1]     = "oc1",
568         [THROTTLE_OC2]     = "oc2",
569         [THROTTLE_OC3]     = "oc3",
570         [THROTTLE_OC4]     = "oc4",
571         [THROTTLE_OC5]     = "oc5", /* reserved */
572 };
573
574 static const char *const throt_dev_names[] = {
575         [THROTTLE_DEV_CPU] = "CPU",
576         [THROTTLE_DEV_GPU] = "GPU",
577 };
578
579 static const char *const sensor_names[] = {
580         [TSENSE_CPU0] = "cpu0",
581         [TSENSE_CPU1] = "cpu1",
582         [TSENSE_CPU2] = "cpu2",
583         [TSENSE_CPU3] = "cpu3",
584         [TSENSE_MEM0] = "mem0",
585         [TSENSE_MEM1] = "mem1",
586         [TSENSE_GPU]  = "gpu0",
587         [TSENSE_PLLX] = "pllx",
588 };
589
590 static const int sensor2tsensorcalib[] = {
591         [TSENSE_CPU0] = 0,
592         [TSENSE_CPU1] = 1,
593         [TSENSE_CPU2] = 2,
594         [TSENSE_CPU3] = 3,
595         [TSENSE_MEM0] = 5,
596         [TSENSE_MEM1] = 6,
597         [TSENSE_GPU]  = 4,
598         [TSENSE_PLLX] = 7,
599 };
600
601 static const int tsensor2therm_map[] = {
602         [TSENSE_CPU0] = THERM_CPU,
603         [TSENSE_CPU1] = THERM_CPU,
604         [TSENSE_CPU2] = THERM_CPU,
605         [TSENSE_CPU3] = THERM_CPU,
606         [TSENSE_GPU]  = THERM_GPU,
607         [TSENSE_MEM0] = THERM_MEM,
608         [TSENSE_MEM1] = THERM_MEM,
609         [TSENSE_PLLX] = THERM_PLL,
610 };
611
612 static const enum soctherm_throttle_dev_id therm2dev[] = {
613         [THERM_CPU] = THROTTLE_DEV_CPU,
614         [THERM_MEM] = THROTTLE_DEV_NONE,
615         [THERM_GPU] = THROTTLE_DEV_GPU,
616         [THERM_PLL] = THROTTLE_DEV_NONE,
617 };
618
619 static const struct soctherm_sensor default_t11x_sensor_params = {
620         .tall      = 16300,
621         .tiddq     = 1,
622         .ten_count = 1,
623         .tsample   = 163,
624         .tsamp_ATE = 655,
625         .pdiv      = 10,
626         .pdiv_ATE  = 10,
627 };
628 static const struct soctherm_sensor default_t14x_sensor_params = {
629         .tall      = 16300,
630         .tiddq     = 1,
631         .ten_count = 1,
632         .tsample   = 120,
633         .tsamp_ATE = 481,
634         .pdiv      = 8,
635         .pdiv_ATE  = 8,
636 };
637
638 /* TODO: not the final sensor data for T124 */
639 static const struct soctherm_sensor default_t12x_sensor_params = {
640         .tall      = 16300,
641         .tiddq     = 1,
642         .ten_count = 1,
643         .tsample   = 120,
644         .tsamp_ATE = 481,
645         .pdiv      = 8,
646         .pdiv_ATE  = 8,
647 };
648
649 static const unsigned long default_t11x_soctherm_clk_rate = 51000000;
650 static const unsigned long default_t11x_tsensor_clk_rate = 500000;
651 static const unsigned long default_t14x_soctherm_clk_rate = 51000000;
652 static const unsigned long default_t14x_tsensor_clk_rate = 400000;
653 /* TODO : finalize the default clk rate */
654 static const unsigned long default_t12x_soctherm_clk_rate = 51000000;
655 static const unsigned long default_t12x_tsensor_clk_rate = 400000;
656
657 /* SOC- OCx to theirt GPIO which is wakeup capable. This is T114 specific */
658 static int soctherm_ocx_to_wake_gpio[TEGRA_SOC_OC_IRQ_MAX] = {
659         TEGRA_GPIO_PEE3,        /* TEGRA_SOC_OC_IRQ_1 */
660         TEGRA_GPIO_INVALID,     /* TEGRA_SOC_OC_IRQ_2 */
661         TEGRA_GPIO_INVALID,     /* TEGRA_SOC_OC_IRQ_3 */
662         TEGRA_GPIO_PJ2,         /* TEGRA_SOC_OC_IRQ_4 */
663         TEGRA_GPIO_INVALID,     /* TEGRA_SOC_OC_IRQ_5 */
664 };
665
666 static int sensor2therm_a[TSENSE_SIZE];
667 static int sensor2therm_b[TSENSE_SIZE];
668
669 static inline s64 div64_s64_precise(s64 a, s32 b)
670 {
671         s64 r, al;
672
673         /* scale up for increased precision in division */
674         al = a << 16;
675
676         r = div64_s64((al * 2) + 1, 2 * b);
677         return r >> 16;
678 }
679
680 static inline long temp_translate(int readback)
681 {
682         int abs = readback >> 8;
683         int lsb = (readback & 0x80) >> 7;
684         int sign = readback & 0x01 ? -1 : 1;
685
686         return (abs * LOWER_PRECISION_FOR_CONV(1000) +
687                 lsb * LOWER_PRECISION_FOR_CONV(500)) * sign;
688 }
689
690 #ifdef CONFIG_THERMAL
691 static inline void prog_hw_shutdown(struct thermal_trip_info *trip_state,
692                                     int therm)
693 {
694         int trip_temp;
695         u32 r;
696
697         trip_temp = LOWER_PRECISION_FOR_TEMP(trip_state->trip_temp / 1000);
698
699         r = soctherm_readl(THERMTRIP);
700         if (therm == THERM_CPU) {
701                 r = REG_SET(r, THERMTRIP_CPU_EN, 1);
702                 r = REG_SET(r, THERMTRIP_CPU_THRESH, trip_temp);
703         } else if (therm == THERM_GPU) {
704                 r = REG_SET(r, THERMTRIP_GPU_EN, 1);
705                 r = REG_SET(r, THERMTRIP_GPUMEM_THRESH, trip_temp);
706         } else if (therm == THERM_PLL) {
707                 r = REG_SET(r, THERMTRIP_TSENSE_EN, 1);
708                 r = REG_SET(r, THERMTRIP_TSENSE_THRESH, trip_temp);
709         } else if (therm == THERM_MEM) {
710                 r = REG_SET(r, THERMTRIP_MEM_EN, 1);
711                 r = REG_SET(r, THERMTRIP_GPUMEM_THRESH, trip_temp);
712         }
713         r = REG_SET(r, THERMTRIP_ANY_EN, 0);
714         soctherm_writel(r, THERMTRIP);
715 }
716
717 static inline void prog_hw_threshold(struct thermal_trip_info *trip_state,
718                                      int therm, int throt)
719 {
720         int trip_temp;
721         u32 r, reg_off;
722
723         trip_temp = LOWER_PRECISION_FOR_TEMP(trip_state->trip_temp / 1000);
724
725         /* Hardcode LITE on level-1 and HEAVY on level-2 */
726         reg_off = TS_THERM_REG_OFFSET(CTL_LVL0_CPU0, throt + 1, therm);
727
728         r = soctherm_readl(reg_off);
729         r = REG_SET(r, CTL_LVL0_CPU0_UP_THRESH, trip_temp);
730         r = REG_SET(r, CTL_LVL0_CPU0_DN_THRESH, trip_temp);
731         r = REG_SET(r, CTL_LVL0_CPU0_EN, 1);
732
733         r = REG_SET(r, CTL_LVL0_CPU0_CPU_THROT,
734                     throt == THROTTLE_HEAVY ?
735                     CTL_LVL0_CPU0_CPU_THROT_HEAVY :
736                     CTL_LVL0_CPU0_CPU_THROT_LIGHT);
737         r = REG_SET(r, CTL_LVL0_CPU0_GPU_THROT,
738                     throt == THROTTLE_HEAVY ?
739                     CTL_LVL0_CPU0_GPU_THROT_HEAVY :
740                     CTL_LVL0_CPU0_GPU_THROT_LIGHT);
741
742         soctherm_writel(r, reg_off);
743 }
744
745 static void soctherm_set_limits(enum soctherm_therm_id therm,
746                                 long lo_limit, long hi_limit)
747 {
748         u32 r, reg_off;
749
750         reg_off = TS_THERM_REG_OFFSET(CTL_LVL0_CPU0, 0, therm);
751         r = soctherm_readl(reg_off);
752
753         lo_limit = LOWER_PRECISION_FOR_TEMP(lo_limit);
754         hi_limit = LOWER_PRECISION_FOR_TEMP(hi_limit);
755
756         r = REG_SET(r, CTL_LVL0_CPU0_DN_THRESH, lo_limit);
757         r = REG_SET(r, CTL_LVL0_CPU0_UP_THRESH, hi_limit);
758         r = REG_SET(r, CTL_LVL0_CPU0_EN, 1);
759         soctherm_writel(r, reg_off);
760
761         switch (therm) {
762         case THERM_CPU:
763                 r = REG_SET(0, TH_INTR_POS_CD0, 1);
764                 r = REG_SET(r, TH_INTR_POS_CU0, 1);
765                 break;
766         case THERM_GPU:
767                 r = REG_SET(0, TH_INTR_POS_GD0, 1);
768                 r = REG_SET(r, TH_INTR_POS_GU0, 1);
769                 break;
770         case THERM_PLL:
771                 r = REG_SET(0, TH_INTR_POS_PD0, 1);
772                 r = REG_SET(r, TH_INTR_POS_PU0, 1);
773                 break;
774         case THERM_MEM:
775                 r = REG_SET(0, TH_INTR_POS_MD0, 1);
776                 r = REG_SET(r, TH_INTR_POS_MU0, 1);
777                 break;
778         default:
779                 r = 0;
780                 break;
781         }
782         soctherm_writel(r, TH_INTR_ENABLE);
783 }
784
785 static void soctherm_update_zone(int zn)
786 {
787         long low_temp = 0, high_temp = MAX_HIGH_TEMP;
788         long trip_temp, passive_low_temp = MAX_HIGH_TEMP, zone_temp;
789         enum thermal_trip_type trip_type;
790         struct thermal_trip_info *trip_state;
791         struct thermal_zone_device *cur_thz = thz[zn];
792         int count, trips;
793
794         thermal_zone_device_update(cur_thz);
795
796         trips = cur_thz->trips;
797         for (count = 0; count < trips; count++) {
798                 cur_thz->ops->get_trip_type(cur_thz, count, &trip_type);
799                 if ((trip_type == THERMAL_TRIP_HOT) ||
800                     (trip_type == THERMAL_TRIP_CRITICAL))
801                         continue; /* handled in HW */
802
803                 cur_thz->ops->get_trip_temp(cur_thz, count, &trip_temp);
804
805                 trip_state = &plat_data.therm[zn].trips[count];
806                 zone_temp = cur_thz->temperature;
807
808                 if (!trip_state->tripped) { /* not tripped? update high */
809                         if (trip_temp < high_temp)
810                                 high_temp = trip_temp;
811                 } else { /* tripped? update low */
812                         if (trip_type != THERMAL_TRIP_PASSIVE) {
813                                 /* get highest ACTIVE */
814                                 if (trip_temp > low_temp)
815                                         low_temp = trip_temp;
816                         } else {
817                                 /* get lowest PASSIVE */
818                                 if (trip_temp < passive_low_temp)
819                                         passive_low_temp = trip_temp;
820                         }
821                 }
822         }
823
824         if (passive_low_temp != MAX_HIGH_TEMP)
825                 low_temp = max(low_temp, passive_low_temp);
826
827         soctherm_set_limits(zn, low_temp/1000, high_temp/1000);
828 }
829
830 static void soctherm_update(void)
831 {
832         int i;
833
834         if (!soctherm_init_platform_done)
835                 return;
836
837         for (i = 0; i < THERM_SIZE; i++) {
838                 if (thz[i] && thz[i]->trips)
839                         soctherm_update_zone(i);
840         }
841 }
842
843 static int soctherm_hw_action_get_max_state(struct thermal_cooling_device *cdev,
844                                             unsigned long *max_state)
845 {
846         struct thermal_trip_info *trip_state = cdev->devdata;
847
848         if (!trip_state)
849                 return 0;
850
851         *max_state = 3; /* bit 1: CPU  bit 2: GPU */
852         return 0;
853 }
854
855 static int soctherm_hw_action_get_cur_state(struct thermal_cooling_device *cdev,
856                                             unsigned long *cur_state)
857 {
858         struct thermal_trip_info *trip_state = cdev->devdata;
859         struct soctherm_throttle_dev *devs;
860         u32 r, m, n;
861         int i;
862
863         if (!trip_state)
864                 return 0;
865
866         *cur_state = 0;
867         if (trip_state->trip_type != THERMAL_TRIP_HOT)
868                 return 0;
869
870         for (i = THROTTLE_LIGHT; i <= THROTTLE_HEAVY; i++) {
871                 if (!strnstr(trip_state->cdev_type, throt_names[i],
872                                                 THERMAL_NAME_LENGTH))
873                         continue;
874
875                 r = soctherm_readl(CPU_PSKIP_STATUS);
876                 devs = &plat_data.throttle[i].devs[THROTTLE_DEV_CPU];
877                 if (REG_GET(r, XPU_PSKIP_STATUS_ENABLED) && devs->enable) {
878                         m = REG_GET(r, XPU_PSKIP_STATUS_M);
879                         n = REG_GET(r, XPU_PSKIP_STATUS_N);
880                         if (m == devs->dividend && n == devs->divisor)
881                                 *cur_state |= (1 << THROTTLE_DEV_CPU);
882                 }
883
884                 r = soctherm_readl(GPU_PSKIP_STATUS);
885                 devs = &plat_data.throttle[i].devs[THROTTLE_DEV_GPU];
886                 if (REG_GET(r, XPU_PSKIP_STATUS_ENABLED) && devs->enable) {
887                         m = REG_GET(r, XPU_PSKIP_STATUS_M);
888                         n = REG_GET(r, XPU_PSKIP_STATUS_N);
889                                 /*
890                                  * On Tegra12x OC5 is a reserved alarm. Hence
891                                  * GPU 'PSKIP' state always shows ON. The real
892                                  * status register 'NV_THERM_CLK_STATUS' can't
893                                  * be read safely. So we mirror the CPU status.
894                                  */
895                         *cur_state |=
896                                 (tegra_chip_id == TEGRA_CHIPID_TEGRA12) ?
897                                 ((*cur_state & (1 << THROTTLE_DEV_CPU)) ?
898                                  (1 << THROTTLE_DEV_GPU) : 0) :
899                                 ((m == devs->dividend && n == devs->divisor) ?
900                                  (1 << THROTTLE_DEV_GPU) : 0);
901                 }
902         }
903         return 0;
904 }
905
906 static int soctherm_hw_action_set_cur_state(struct thermal_cooling_device *cdev,
907                                             unsigned long cur_state)
908 {
909         return 0; /* hw sets this state */
910 }
911
912 static struct thermal_cooling_device *soctherm_hw_critical_cdev;
913 static struct thermal_cooling_device *soctherm_hw_heavy_cdev;
914 static struct thermal_cooling_device *soctherm_hw_light_cdev;
915 static struct thermal_cooling_device_ops soctherm_hw_action_ops = {
916         .get_max_state = soctherm_hw_action_get_max_state,
917         .get_cur_state = soctherm_hw_action_get_cur_state,
918         .set_cur_state = soctherm_hw_action_set_cur_state,
919 };
920
921 static int soctherm_suspend_get_max_state(struct thermal_cooling_device *cdev,
922                                           unsigned long *max_state)
923 {
924         *max_state = 1;
925         return 0;
926 }
927
928 static int soctherm_suspend_get_cur_state(struct thermal_cooling_device *cdev,
929                                           unsigned long *cur_state)
930 {
931         *cur_state = !soctherm_suspended;
932         return 0;
933 }
934
935 static int soctherm_suspend_set_cur_state(struct thermal_cooling_device *cdev,
936                                           unsigned long cur_state)
937 {
938         if (!cur_state != soctherm_suspended) {
939                 if (cur_state)
940                         soctherm_resume();
941                 else
942                         soctherm_suspend();
943         }
944         return 0;
945 }
946
947 static struct thermal_cooling_device_ops soctherm_suspend_ops = {
948         .get_max_state = soctherm_suspend_get_max_state,
949         .get_cur_state = soctherm_suspend_get_cur_state,
950         .set_cur_state = soctherm_suspend_set_cur_state,
951 };
952
953 static int soctherm_bind(struct thermal_zone_device *thz,
954                                 struct thermal_cooling_device *cdev)
955 {
956         int i, index = ((int)thz->devdata) - TSENSE_SIZE;
957         struct thermal_trip_info *trip_state;
958         u32 base_cp, base_ft;
959         s32 shft_cp, shft_ft;
960
961         if (index < 0)
962                 return 0;
963
964         /* skip binding cooling devices on improperly fused soctherm */
965         if (tegra_fuse_calib_base_get_cp(&base_cp, &shft_cp) < 0 ||
966             tegra_fuse_calib_base_get_ft(&base_ft, &shft_ft) < 0)
967                 return 0;
968
969         for (i = 0; i < plat_data.therm[index].num_trips; i++) {
970                 trip_state = &plat_data.therm[index].trips[i];
971                 if (trip_state->bound)
972                         continue;
973                 if (trip_state->cdev_type &&
974                     !strncmp(trip_state->cdev_type, cdev->type,
975                                                 THERMAL_NAME_LENGTH)) {
976                         thermal_zone_bind_cooling_device(thz, i, cdev,
977                                                          trip_state->upper,
978                                                          trip_state->lower);
979                         trip_state->bound = true;
980                 }
981         }
982
983         return 0;
984 }
985
986 static int soctherm_unbind(struct thermal_zone_device *thz,
987                                 struct thermal_cooling_device *cdev)
988 {
989         int i, index = ((int)thz->devdata) - TSENSE_SIZE;
990         struct thermal_trip_info *trip_state;
991
992         if (index < 0)
993                 return 0;
994
995         for (i = 0; i < plat_data.therm[index].num_trips; i++) {
996                 trip_state = &plat_data.therm[index].trips[i];
997                 if (!trip_state->bound)
998                         continue;
999                 if (trip_state->cdev_type &&
1000                     !strncmp(trip_state->cdev_type, cdev->type,
1001                                                 THERMAL_NAME_LENGTH)) {
1002                         thermal_zone_unbind_cooling_device(thz, 0, cdev);
1003                         trip_state->bound = false;
1004                 }
1005         }
1006
1007         return 0;
1008 }
1009
1010 static int soctherm_get_temp(struct thermal_zone_device *thz,
1011                                         unsigned long *temp)
1012 {
1013         int index = (int)thz->devdata;
1014         u32 r, regv, shft, mask;
1015         enum soctherm_sense i, j;
1016         int tt, ti;
1017
1018         if (index < TSENSE_SIZE) { /* 'TSENSE_XXX' thermal zone */
1019                 regv = TS_CPU0_STATUS1;
1020                 shft = TS_CPU0_STATUS1_TEMP_SHIFT;
1021                 mask = TS_CPU0_STATUS1_TEMP_MASK;
1022                 i = j = index;
1023         } else {
1024                 index -= TSENSE_SIZE; /* 'THERM_XXX' thermal zone */
1025
1026                 switch (index) {
1027                 case THERM_CPU:
1028                         regv = TS_TEMP1;
1029                         shft = TS_TEMP1_CPU_TEMP_SHIFT;
1030                         mask = TS_TEMP1_CPU_TEMP_MASK;
1031                         i = TSENSE_CPU0;
1032                         j = TSENSE_CPU3;
1033                         break;
1034
1035                 case THERM_GPU:
1036                         regv = TS_TEMP1;
1037                         shft = TS_TEMP1_GPU_TEMP_SHIFT;
1038                         mask = TS_TEMP1_GPU_TEMP_MASK;
1039                         i = j = TSENSE_GPU;
1040                         break;
1041
1042                 case THERM_PLL:
1043                         regv = TS_TEMP2;
1044                         shft = TS_TEMP2_PLLX_TEMP_SHIFT;
1045                         mask = TS_TEMP2_PLLX_TEMP_MASK;
1046                         i = j = TSENSE_PLLX;
1047                         break;
1048
1049                 case THERM_MEM:
1050                         regv = TS_TEMP2;
1051                         shft = TS_TEMP2_MEM_TEMP_SHIFT;
1052                         mask = TS_TEMP2_MEM_TEMP_MASK;
1053                         i = TSENSE_MEM0;
1054                         j = TSENSE_MEM1;
1055                         break;
1056
1057                 default:
1058                         return 0; /* error really */
1059                 }
1060         }
1061
1062         if (read_hw_temp) {
1063                 r = soctherm_readl(regv);
1064                 *temp = temp_translate((r & (mask << shft)) >> shft);
1065         } else {
1066                 for (tt = 0; i <= j; i++) {
1067                         r = soctherm_readl(TS_TSENSE_REG_OFFSET(
1068                                                 TS_CPU0_STATUS0, i));
1069                         ti = temp_convert(REG_GET(r, TS_CPU0_STATUS0_CAPTURE),
1070                                                 sensor2therm_a[i],
1071                                                 sensor2therm_b[i]);
1072                         *temp = tt = max(tt, ti);
1073                 }
1074         }
1075         return 0;
1076 }
1077
1078 static int soctherm_get_trip_type(struct thermal_zone_device *thz,
1079                                 int trip, enum thermal_trip_type *type)
1080 {
1081         int index = ((int)thz->devdata) - TSENSE_SIZE;
1082         struct thermal_trip_info *trip_state;
1083
1084         if (index < 0)
1085                 return -EINVAL;
1086
1087         trip_state = &plat_data.therm[index].trips[trip];
1088         *type = trip_state->trip_type;
1089         return 0;
1090 }
1091
1092 static int soctherm_get_trip_temp(struct thermal_zone_device *thz,
1093                                 int trip, unsigned long *temp)
1094 {
1095         int index = ((int)thz->devdata) - TSENSE_SIZE;
1096         struct thermal_trip_info *trip_state;
1097         unsigned long trip_temp, zone_temp;
1098
1099         if (index < 0)
1100                 return -EINVAL;
1101
1102         trip_state = &plat_data.therm[index].trips[trip];
1103         trip_temp = trip_state->trip_temp;
1104         zone_temp = thz->temperature;
1105
1106         if (zone_temp >= trip_temp) {
1107                 trip_temp -= trip_state->hysteresis;
1108                 trip_state->tripped = true;
1109         } else if (trip_state->tripped) {
1110                 trip_temp -= trip_state->hysteresis;
1111                 if (zone_temp < trip_temp)
1112                         trip_state->tripped = false;
1113         }
1114
1115         *temp = trip_temp;
1116
1117         return 0;
1118 }
1119
1120 static int soctherm_set_trip_temp(struct thermal_zone_device *thz,
1121                                 int trip, unsigned long temp)
1122 {
1123         int index = ((int)thz->devdata) - TSENSE_SIZE;
1124         struct thermal_trip_info *trip_state;
1125         long rem;
1126
1127         if (index < 0)
1128                 return -EINVAL;
1129
1130         trip_state = &plat_data.therm[index].trips[trip];
1131
1132         trip_state->trip_temp = temp;
1133
1134         rem = trip_state->trip_temp % LOWER_PRECISION_FOR_CONV(1000);
1135         if (rem) {
1136                 pr_warn("soctherm: zone%d/trip_point%d %ld mC rounded down\n",
1137                         index, trip, trip_state->trip_temp);
1138                 trip_state->trip_temp -= rem;
1139         }
1140
1141         if (trip_state->trip_type == THERMAL_TRIP_HOT) {
1142                 if (strnstr(trip_state->cdev_type,
1143                                 "heavy", THERMAL_NAME_LENGTH))
1144                         prog_hw_threshold(trip_state, index, THROTTLE_HEAVY);
1145                 else if (strnstr(trip_state->cdev_type,
1146                                 "light", THERMAL_NAME_LENGTH))
1147                         prog_hw_threshold(trip_state, index, THROTTLE_LIGHT);
1148         }
1149
1150         /* Allow SW to shutdown at 'Critical temperature reached' */
1151         soctherm_update_zone(index);
1152
1153         /* Reprogram HW thermtrip */
1154         if (trip_state->trip_type == THERMAL_TRIP_CRITICAL)
1155                 prog_hw_shutdown(trip_state, index);
1156
1157         return 0;
1158 }
1159
1160 static int soctherm_get_crit_temp(struct thermal_zone_device *thz,
1161                                   unsigned long *temp)
1162 {
1163         int i, index = ((int)thz->devdata) - TSENSE_SIZE;
1164         struct thermal_trip_info *trip_state;
1165
1166         if (index < 0)
1167                 return -EINVAL;
1168
1169         for (i = 0; i < plat_data.therm[index].num_trips; i++) {
1170                 trip_state = &plat_data.therm[index].trips[i];
1171                 if (trip_state->trip_type != THERMAL_TRIP_CRITICAL)
1172                         continue;
1173                 *temp = trip_state->trip_temp;
1174                 return 0;
1175         }
1176
1177         return -EINVAL;
1178 }
1179
1180 static int soctherm_get_trend(struct thermal_zone_device *thz,
1181                                 int trip,
1182                                 enum thermal_trend *trend)
1183 {
1184         int index = ((int)thz->devdata) - TSENSE_SIZE;
1185         struct thermal_trip_info *trip_state;
1186         long trip_temp;
1187
1188         if (index < 0)
1189                 return -EINVAL;
1190
1191         trip_state = &plat_data.therm[index].trips[trip];
1192         thz->ops->get_trip_temp(thz, trip, &trip_temp);
1193
1194         switch (trip_state->trip_type) {
1195         case THERMAL_TRIP_ACTIVE:
1196                 /* aggressive active cooling */
1197                 *trend = THERMAL_TREND_RAISING;
1198                 break;
1199         case THERMAL_TRIP_PASSIVE:
1200                 if (thz->temperature > trip_state->trip_temp)
1201                         *trend = THERMAL_TREND_RAISING;
1202                 else if (thz->temperature < trip_temp)
1203                         *trend = THERMAL_TREND_DROPPING;
1204                 else
1205                         *trend = THERMAL_TREND_STABLE;
1206                 break;
1207         default:
1208                 return -EINVAL;
1209         }
1210         return 0;
1211 }
1212
1213 static struct thermal_zone_device_ops soctherm_ops = {
1214         .bind = soctherm_bind,
1215         .unbind = soctherm_unbind,
1216         .get_temp = soctherm_get_temp,
1217         .get_trip_type = soctherm_get_trip_type,
1218         .get_trip_temp = soctherm_get_trip_temp,
1219         .set_trip_temp = soctherm_set_trip_temp,
1220         .get_crit_temp = soctherm_get_crit_temp,
1221         .get_trend = soctherm_get_trend,
1222 };
1223
1224 static void __init soctherm_hot_cdev_register(int i, int trip)
1225 {
1226         struct soctherm_therm *therm;
1227         int k;
1228
1229         therm = &plat_data.therm[i];
1230
1231         for (k = 0; k < THROTTLE_SIZE; k++) {
1232                 if ((therm2dev[i] == THROTTLE_DEV_NONE)
1233                     || (!plat_data.throttle[k].
1234                         devs[therm2dev[i]].enable))
1235                         continue;
1236
1237                 if ((strnstr(therm->trips[trip].cdev_type,
1238                              "oc1",
1239                              THERMAL_NAME_LENGTH)
1240                      && k == THROTTLE_OC1) ||
1241                     (strnstr(therm->trips[trip].cdev_type,
1242                              "oc2",
1243                              THERMAL_NAME_LENGTH)
1244                      && k == THROTTLE_OC2) ||
1245                     (strnstr(therm->trips[trip].cdev_type,
1246                              "oc3",
1247                              THERMAL_NAME_LENGTH)
1248                      && k == THROTTLE_OC3) ||
1249                     (strnstr(therm->trips[trip].cdev_type,
1250                              "oc4",
1251                              THERMAL_NAME_LENGTH)
1252                      && k == THROTTLE_OC4))
1253                         continue;
1254
1255                 if (strnstr(therm->trips[trip].cdev_type,
1256                             "heavy",
1257                             THERMAL_NAME_LENGTH) &&
1258                     k == THROTTLE_HEAVY &&
1259                     !soctherm_hw_heavy_cdev) {
1260                         soctherm_hw_heavy_cdev =
1261                                 thermal_cooling_device_register(
1262                                         therm->trips[trip].cdev_type,
1263                                         &therm->trips[trip],
1264                                         &soctherm_hw_action_ops);
1265                         continue;
1266                 }
1267
1268                 if (strnstr(therm->trips[trip].cdev_type,
1269                             "light",
1270                             THERMAL_NAME_LENGTH) &&
1271                     k == THROTTLE_LIGHT &&
1272                     !soctherm_hw_light_cdev) {
1273                         soctherm_hw_light_cdev =
1274                                 thermal_cooling_device_register(
1275                                         therm->trips[trip].cdev_type,
1276                                         &therm->trips[trip],
1277                                         &soctherm_hw_action_ops);
1278                         continue;
1279                 }
1280         }
1281 }
1282
1283 static int __init soctherm_thermal_sys_init(void)
1284 {
1285         char name[THERMAL_NAME_LENGTH];
1286         struct soctherm_therm *therm;
1287         bool oc_en = false;
1288         int i, j;
1289
1290         if (!soctherm_init_platform_done)
1291                 return 0;
1292
1293         for (i = 0; i < TSENSE_SIZE; i++) {
1294                 if (plat_data.sensor_data[i].zone_enable) {
1295                         snprintf(name, THERMAL_NAME_LENGTH,
1296                                  "%s-tsensor", sensor_names[i]);
1297                         /* Create a thermal zone device for each sensor */
1298                         thermal_zone_device_register(
1299                                         name,
1300                                         0,
1301                                         0,
1302                                         (void *)i,
1303                                         &soctherm_ops,
1304                                         NULL,
1305                                         0,
1306                                         0);
1307                 }
1308         }
1309
1310         for (i = 0; i < THERM_SIZE; i++) {
1311                 therm = &plat_data.therm[i];
1312                 if (!therm->zone_enable)
1313                         continue;
1314
1315                 for (j = 0; j < therm->num_trips; j++) {
1316                         switch (therm->trips[j].trip_type) {
1317                         case THERMAL_TRIP_CRITICAL:
1318                                 if (soctherm_hw_critical_cdev)
1319                                         break;
1320                                 soctherm_hw_critical_cdev =
1321                                         thermal_cooling_device_register(
1322                                                 therm->trips[j].cdev_type,
1323                                                 &therm->trips[j],
1324                                                 &soctherm_hw_action_ops);
1325                                 break;
1326
1327                         case THERMAL_TRIP_HOT:
1328                                 soctherm_hot_cdev_register(i, j);
1329                                 break;
1330
1331                         case THERMAL_TRIP_PASSIVE:
1332                         case THERMAL_TRIP_ACTIVE:
1333                                 break; /* done elsewhere */
1334                         }
1335                 }
1336
1337                 snprintf(name, THERMAL_NAME_LENGTH,
1338                          "%s-therm", therm_names[i]);
1339                 thz[i] = thermal_zone_device_register(
1340                                         name,
1341                                         therm->num_trips,
1342                                         (1ULL << therm->num_trips) - 1,
1343                                         (void *)TSENSE_SIZE + i,
1344                                         &soctherm_ops,
1345                                         therm->tzp,
1346                                         therm->passive_delay,
1347                                         0);
1348
1349                 for (j = THROTTLE_OC1; !oc_en && j < THROTTLE_SIZE; j++)
1350                         if ((therm2dev[i] != THROTTLE_DEV_NONE) &&
1351                             (plat_data.throttle[j].devs[therm2dev[i]].enable))
1352                                 oc_en = true;
1353         }
1354
1355         /* do not enable suspend feature if any OC alarms are enabled */
1356         if (!oc_en)
1357                 thermal_cooling_device_register("suspend_soctherm", 0,
1358                                                 &soctherm_suspend_ops);
1359         else
1360                 pr_warn("soctherm: Suspend feature CANNOT be enabled %s\n",
1361                         "when any OC alarm is enabled");
1362
1363         soctherm_update();
1364         return 0;
1365 }
1366 module_init(soctherm_thermal_sys_init);
1367
1368 #else
1369 static void soctherm_update_zone(int zn)
1370 {
1371 }
1372 static void soctherm_update(void)
1373 {
1374 }
1375 #endif
1376
1377 static irqreturn_t soctherm_thermal_thread_func(int irq, void *arg)
1378 {
1379         u32 st, ex = 0, cp = 0, gp = 0, pl = 0;
1380
1381         st = soctherm_readl(TH_INTR_STATUS);
1382
1383         /* deliberately clear expected interrupts handled in SW */
1384         cp |= REG_GET_BIT(st, TH_INTR_POS_CD0);
1385         cp |= REG_GET_BIT(st, TH_INTR_POS_CU0);
1386         ex |= cp;
1387
1388         gp |= REG_GET_BIT(st, TH_INTR_POS_GD0);
1389         gp |= REG_GET_BIT(st, TH_INTR_POS_GU0);
1390         ex |= gp;
1391
1392         pl |= REG_GET_BIT(st, TH_INTR_POS_PD0);
1393         pl |= REG_GET_BIT(st, TH_INTR_POS_PU0);
1394         ex |= pl;
1395
1396         if (ex) {
1397                 soctherm_writel(ex, TH_INTR_STATUS);
1398                 st &= ~ex;
1399                 if (cp)
1400                         soctherm_update_zone(THERM_CPU);
1401                 if (gp)
1402                         soctherm_update_zone(THERM_GPU);
1403                 if (pl)
1404                         soctherm_update_zone(THERM_PLL);
1405         }
1406
1407         /* deliberately ignore expected interrupts NOT handled in SW */
1408         ex |= REG_GET_BIT(st, TH_INTR_POS_MD0);
1409         ex |= REG_GET_BIT(st, TH_INTR_POS_MU0);
1410
1411         ex |= REG_GET_BIT(st, TH_INTR_POS_CD1);
1412         ex |= REG_GET_BIT(st, TH_INTR_POS_CU1);
1413         ex |= REG_GET_BIT(st, TH_INTR_POS_CD2);
1414         ex |= REG_GET_BIT(st, TH_INTR_POS_CU2);
1415         ex |= REG_GET_BIT(st, TH_INTR_POS_CD3);
1416         ex |= REG_GET_BIT(st, TH_INTR_POS_CU3);
1417
1418         ex |= REG_GET_BIT(st, TH_INTR_POS_GD1);
1419         ex |= REG_GET_BIT(st, TH_INTR_POS_GU1);
1420         ex |= REG_GET_BIT(st, TH_INTR_POS_GD2);
1421         ex |= REG_GET_BIT(st, TH_INTR_POS_GU2);
1422         ex |= REG_GET_BIT(st, TH_INTR_POS_GD3);
1423         ex |= REG_GET_BIT(st, TH_INTR_POS_GU3);
1424
1425         ex |= REG_GET_BIT(st, TH_INTR_POS_PD1);
1426         ex |= REG_GET_BIT(st, TH_INTR_POS_PU1);
1427         ex |= REG_GET_BIT(st, TH_INTR_POS_PD2);
1428         ex |= REG_GET_BIT(st, TH_INTR_POS_PU2);
1429         ex |= REG_GET_BIT(st, TH_INTR_POS_PD3);
1430         ex |= REG_GET_BIT(st, TH_INTR_POS_PU3);
1431
1432         ex |= REG_GET_BIT(st, TH_INTR_POS_MD1);
1433         ex |= REG_GET_BIT(st, TH_INTR_POS_MU1);
1434         ex |= REG_GET_BIT(st, TH_INTR_POS_MD2);
1435         ex |= REG_GET_BIT(st, TH_INTR_POS_MU2);
1436         ex |= REG_GET_BIT(st, TH_INTR_POS_MD3);
1437         ex |= REG_GET_BIT(st, TH_INTR_POS_MU3);
1438         st &= ~ex;
1439
1440         if (st) {
1441                 /* Whine about any other unexpected INTR bits still set */
1442                 pr_err("soctherm: Ignored unexpected INTRs 0x%08x\n", st);
1443                 soctherm_writel(st, TH_INTR_STATUS);
1444         }
1445
1446         return IRQ_HANDLED;
1447 }
1448
1449 static inline void soctherm_oc_intr_enable(enum soctherm_throttle_id alarm,
1450                                            bool enable)
1451 {
1452         u32 r;
1453
1454         if (!enable)
1455                 return;
1456
1457         r = soctherm_readl(OC_INTR_ENABLE);
1458         switch (alarm) {
1459         case THROTTLE_OC1:
1460                 r = REG_SET(r, OC_INTR_POS_OC1, 1);
1461                 break;
1462         case THROTTLE_OC2:
1463                 r = REG_SET(r, OC_INTR_POS_OC2, 1);
1464                 break;
1465         case THROTTLE_OC3:
1466                 r = REG_SET(r, OC_INTR_POS_OC3, 1);
1467                 break;
1468         case THROTTLE_OC4:
1469                 r = REG_SET(r, OC_INTR_POS_OC4, 1);
1470                 break;
1471         default:
1472                 r = 0;
1473                 break;
1474         }
1475         soctherm_writel(r, OC_INTR_ENABLE);
1476 }
1477
1478 /* Return 0 (success) if you want to  reenable OC alarm intr. */
1479 static int soctherm_handle_alarm(enum soctherm_throttle_id alarm)
1480 {
1481         int rv = -EINVAL;
1482
1483         switch (alarm) {
1484         case THROTTLE_OC1:
1485                 pr_warn("soctherm: Unexpected OC1 alarm\n");
1486                 /* add OC1 alarm handling code here */
1487                 break;
1488
1489         case THROTTLE_OC2:
1490                 pr_info("soctherm: Successfully handled OC2 alarm\n");
1491                 /* TODO: add OC2 alarm handling code here */
1492                 rv = 0;
1493                 break;
1494
1495         case THROTTLE_OC3:
1496                 pr_warn("soctherm: Unexpected OC3 alarm\n");
1497                 /* add OC3 alarm handling code here */
1498                 break;
1499
1500         case THROTTLE_OC4:
1501                 pr_info("soctherm: Successfully handled OC4 alarm\n");
1502                 /* TODO: add OC4 alarm handling code here */
1503                 rv = 0;
1504                 break;
1505
1506         default:
1507                 break;
1508         }
1509
1510         if (rv)
1511                 pr_err("soctherm: ERROR in handling %s alarm\n",
1512                         throt_names[alarm]);
1513
1514         return rv;
1515 }
1516
1517 static irqreturn_t soctherm_edp_thread_func(int irq, void *arg)
1518 {
1519         u32 st, ex, oc1, oc2, oc3, oc4;
1520
1521         st = soctherm_readl(OC_INTR_STATUS);
1522
1523         /* deliberately clear expected interrupts handled in SW */
1524         oc1 = REG_GET_BIT(st, OC_INTR_POS_OC1);
1525         oc2 = REG_GET_BIT(st, OC_INTR_POS_OC2);
1526         oc3 = REG_GET_BIT(st, OC_INTR_POS_OC3);
1527         oc4 = REG_GET_BIT(st, OC_INTR_POS_OC4);
1528         ex = oc1 | oc2 | oc3 | oc4;
1529
1530         if (ex) {
1531                 soctherm_writel(st, OC_INTR_STATUS);
1532                 st &= ~ex;
1533
1534                 if (oc1 && !soctherm_handle_alarm(THROTTLE_OC1))
1535                         soctherm_oc_intr_enable(THROTTLE_OC1, true);
1536
1537                 if (oc2 && !soctherm_handle_alarm(THROTTLE_OC2))
1538                         soctherm_oc_intr_enable(THROTTLE_OC2, true);
1539
1540                 if (oc3 && !soctherm_handle_alarm(THROTTLE_OC3))
1541                         soctherm_oc_intr_enable(THROTTLE_OC3, true);
1542
1543                 if (oc4 && !soctherm_handle_alarm(THROTTLE_OC4))
1544                         soctherm_oc_intr_enable(THROTTLE_OC4, true);
1545
1546                 if (oc1 && soc_irq_cdata.irq_enable & BIT(0))
1547                         handle_nested_irq(
1548                                 irq_find_mapping(soc_irq_cdata.domain, 0));
1549
1550                 if (oc2 && soc_irq_cdata.irq_enable & BIT(1))
1551                         handle_nested_irq(
1552                                 irq_find_mapping(soc_irq_cdata.domain, 1));
1553
1554                 if (oc3 && soc_irq_cdata.irq_enable & BIT(2))
1555                         handle_nested_irq(
1556                                 irq_find_mapping(soc_irq_cdata.domain, 2));
1557
1558                 if (oc4 && soc_irq_cdata.irq_enable & BIT(3))
1559                         handle_nested_irq(
1560                                 irq_find_mapping(soc_irq_cdata.domain, 3));
1561         }
1562
1563         if (st) {
1564                 pr_err("soctherm: Ignored unexpected OC ALARM 0x%08x\n", st);
1565                 soctherm_writel(st, OC_INTR_STATUS);
1566         }
1567
1568         return IRQ_HANDLED;
1569 }
1570
1571 static irqreturn_t soctherm_thermal_isr(int irq, void *arg)
1572 {
1573         u32 r;
1574
1575         r = soctherm_readl(TH_INTR_STATUS);
1576         soctherm_writel(r, TH_INTR_DISABLE);
1577
1578         return IRQ_WAKE_THREAD;
1579 }
1580
1581 static irqreturn_t soctherm_edp_isr(int irq, void *arg)
1582 {
1583         u32 r;
1584
1585         r = soctherm_readl(OC_INTR_STATUS);
1586         soctherm_writel(r, OC_INTR_DISABLE);
1587
1588         return IRQ_WAKE_THREAD;
1589 }
1590
1591 static void soctherm_throttle_program(enum soctherm_throttle_id throt)
1592 {
1593         u32 r;
1594         int i;
1595         u8 gk20a_throt;
1596         bool throt_enable = false;
1597         struct soctherm_throttle_dev *dev;
1598         struct soctherm_throttle *data = &plat_data.throttle[throt];
1599
1600         for (i = 0; i < THROTTLE_DEV_SIZE; i++) {
1601                 dev = &data->devs[i];
1602                 if (!dev->enable)
1603                         continue;
1604                 throt_enable = true;
1605
1606                 if (i == THROTTLE_DEV_GPU && tegra_chip_id ==
1607                                 TEGRA_CHIPID_TEGRA12) {
1608                         /* gk20a interface N:3 Mapping */
1609                         if (!strcmp(dev->throttling_depth,
1610                                 "heavy_throttling"))
1611                                 gk20a_throt = THROT_DEPTH_HIG;
1612                         else if (!strcmp(dev->throttling_depth,
1613                                 "medium_throttling"))
1614                                 gk20a_throt = THROT_DEPTH_MED;
1615                         else
1616                                 gk20a_throt = THROT_DEPTH_LOW;
1617
1618                         r = soctherm_readl(THROT_PSKIP_CTRL(throt, i));
1619                         r = REG_SET(r, THROT_PSKIP_CTRL_ENABLE, dev->enable);
1620
1621                         r = REG_SET(r, THROT_PSKIP_CTRL_THROT_DEPTH,
1622                                 gk20a_throt);
1623
1624                         soctherm_writel(r, THROT_PSKIP_CTRL(throt, i));
1625                         continue;
1626                 }
1627                 if (dev->depth) {
1628                         THROT_DEPTH(dev, dev->depth);
1629                 } else if (!dev->dividend || !dev->divisor
1630                         || !dev->duration || !dev->step) {
1631                         THROT_DEPTH(dev, THROT_DEPTH_DEFAULT);
1632                 }
1633
1634                 r = soctherm_readl(THROT_PSKIP_CTRL(throt, i));
1635                 r = REG_SET(r, THROT_PSKIP_CTRL_ENABLE, dev->enable);
1636
1637                 r = REG_SET(r, THROT_PSKIP_CTRL_DIVIDEND, dev->dividend);
1638                 r = REG_SET(r, THROT_PSKIP_CTRL_DIVISOR, dev->divisor);
1639                 soctherm_writel(r, THROT_PSKIP_CTRL(throt, i));
1640
1641                 r = soctherm_readl(THROT_PSKIP_RAMP(throt, i));
1642                 r = REG_SET(r, THROT_PSKIP_RAMP_DURATION, dev->duration);
1643                 r = REG_SET(r, THROT_PSKIP_RAMP_STEP, dev->step);
1644                 soctherm_writel(r, THROT_PSKIP_RAMP(throt, i));
1645         }
1646
1647         r = REG_SET(0, THROT_PRIORITY_LITE_PRIO, data->priority);
1648         soctherm_writel(r, THROT_PRIORITY_CTRL(throt));
1649
1650         r = REG_SET(0, THROT_DELAY_LITE_DELAY, 0);
1651         soctherm_writel(r, THROT_DELAY_CTRL(throt));
1652
1653         r = soctherm_readl(THROT_PRIORITY_LOCK);
1654         if (r < data->priority) {
1655                 r = REG_SET(0, THROT_PRIORITY_LOCK_PRIORITY, data->priority);
1656                 soctherm_writel(r, THROT_PRIORITY_LOCK);
1657         }
1658
1659         /* ----- configure reserved OC5 alarm ----- */
1660         if (throt == THROTTLE_OC5) {
1661                 r = soctherm_readl(ALARM_CFG(throt));
1662                 r = REG_SET(r, OC1_CFG_THROTTLE_MODE, BRIEF);
1663                 r = REG_SET(r, OC1_CFG_ALARM_POLARITY, 0);
1664                 r = REG_SET(r, OC1_CFG_EN_THROTTLE, 1);
1665                 soctherm_writel(r, ALARM_CFG(throt));
1666
1667                 r = REG_SET(r, OC1_CFG_ALARM_POLARITY, 1);
1668                 soctherm_writel(r, ALARM_CFG(throt));
1669
1670                 r = REG_SET(r, OC1_CFG_ALARM_POLARITY, 0);
1671                 soctherm_writel(r, ALARM_CFG(throt));
1672
1673                 r = REG_SET(r, THROT_PSKIP_CTRL_DIVIDEND, 0);
1674                 r = REG_SET(r, THROT_PSKIP_CTRL_DIVISOR, 0);
1675                 r = REG_SET(r, THROT_PSKIP_CTRL_ENABLE, 1);
1676                 soctherm_writel(r, THROT_PSKIP_CTRL(throt, THROTTLE_DEV_CPU));
1677
1678                 r = soctherm_readl(THROT_PSKIP_RAMP(throt, THROTTLE_DEV_CPU));
1679                 r = REG_SET(r, THROT_PSKIP_RAMP_DURATION, 0xff);
1680                 r = REG_SET(r, THROT_PSKIP_RAMP_STEP, 0xf);
1681                 soctherm_writel(r, THROT_PSKIP_RAMP(throt, THROTTLE_DEV_CPU));
1682
1683                 r = soctherm_readl(THROT_PSKIP_CTRL(throt, THROTTLE_DEV_GPU));
1684                 r = REG_SET(r, THROT_PSKIP_CTRL_ENABLE, 1);
1685                 soctherm_writel(r, THROT_PSKIP_CTRL(throt, THROTTLE_DEV_GPU));
1686
1687                 r = REG_SET(0, THROT_PRIORITY_LITE_PRIO, 1);
1688                 soctherm_writel(r, THROT_PRIORITY_CTRL(throt));
1689                 return;
1690         }
1691
1692         if (!throt_enable || (throt < THROTTLE_OC1))
1693                 return;
1694
1695         /* ----- configure other OC alarms ----- */
1696         if (!(data->throt_mode == BRIEF || data->throt_mode == STICKY))
1697                 pr_warn("soctherm: Invalid throt_mode in %s\n",
1698                         throt_names[throt]);
1699
1700         r = soctherm_readl(ALARM_CFG(throt));
1701         r = REG_SET(r, OC1_CFG_HW_RESTORE, 1);
1702         r = REG_SET(r, OC1_CFG_PWR_GOOD_MASK, data->pgmask);
1703         r = REG_SET(r, OC1_CFG_THROTTLE_MODE, data->throt_mode);
1704         r = REG_SET(r, OC1_CFG_ALARM_POLARITY, data->polarity);
1705         r = REG_SET(r, OC1_CFG_EN_THROTTLE, 1);
1706         soctherm_writel(r, ALARM_CFG(throt));
1707
1708         soctherm_oc_intr_enable(throt, data->intr);
1709
1710         soctherm_writel(data->period, ALARM_THRESHOLD_PERIOD(throt)); /* usec */
1711         soctherm_writel(0xffffffff, ALARM_FILTER(throt));
1712 }
1713
1714 static void soctherm_tsense_program(enum soctherm_sense sensor,
1715                                                 struct soctherm_sensor *data)
1716 {
1717         u32 r;
1718
1719         r = REG_SET(0, TS_CPU0_CONFIG0_TALL, data->tall);
1720         soctherm_writel(r, TS_TSENSE_REG_OFFSET(TS_CPU0_CONFIG0, sensor));
1721
1722         r = REG_SET(0, TS_CPU0_CONFIG1_TIDDQ, data->tiddq);
1723         r = REG_SET(r, TS_CPU0_CONFIG1_EN, 1);
1724         r = REG_SET(r, TS_CPU0_CONFIG1_TEN_COUNT, data->ten_count);
1725         r = REG_SET(r, TS_CPU0_CONFIG1_TSAMPLE, data->tsample - 1);
1726         soctherm_writel(r, TS_TSENSE_REG_OFFSET(TS_CPU0_CONFIG1, sensor));
1727 }
1728
1729 static int __init soctherm_clk_init(void)
1730 {
1731         unsigned long default_soctherm_clk_rate;
1732         unsigned long default_tsensor_clk_rate;
1733
1734         soctherm_clk = clk_get_sys("soc_therm", NULL);
1735         tsensor_clk = clk_get_sys("tegra-tsensor", NULL);
1736
1737         if (IS_ERR(tsensor_clk) || IS_ERR(soctherm_clk)) {
1738                 clk_put(soctherm_clk);
1739                 clk_put(tsensor_clk);
1740                 soctherm_clk = tsensor_clk = NULL;
1741                 return -EINVAL;
1742         }
1743
1744         /* initialize default clock rates */
1745         if (tegra_chip_id == TEGRA_CHIPID_TEGRA11) {
1746                 default_soctherm_clk_rate =
1747                         default_t11x_soctherm_clk_rate;
1748                 default_tsensor_clk_rate =
1749                         default_t11x_tsensor_clk_rate;
1750         } else if (tegra_chip_id == TEGRA_CHIPID_TEGRA14) {
1751                 default_soctherm_clk_rate =
1752                         default_t14x_soctherm_clk_rate;
1753                 default_tsensor_clk_rate =
1754                         default_t14x_tsensor_clk_rate;
1755         } else if (tegra_chip_id == TEGRA_CHIPID_TEGRA12) {
1756                 default_soctherm_clk_rate =
1757                         default_t12x_soctherm_clk_rate;
1758                 default_tsensor_clk_rate =
1759                         default_t12x_tsensor_clk_rate;
1760         } else {
1761                 BUG();
1762         }
1763
1764         plat_data.soctherm_clk_rate =
1765                 plat_data.soctherm_clk_rate ?: default_soctherm_clk_rate;
1766         plat_data.tsensor_clk_rate =
1767                 plat_data.tsensor_clk_rate ?: default_tsensor_clk_rate;
1768
1769         if (clk_get_rate(soctherm_clk) != plat_data.soctherm_clk_rate)
1770                 if (clk_set_rate(soctherm_clk, plat_data.soctherm_clk_rate))
1771                         return -EINVAL;
1772
1773         if (clk_get_rate(tsensor_clk) != plat_data.tsensor_clk_rate)
1774                 if (clk_set_rate(tsensor_clk, plat_data.tsensor_clk_rate))
1775                         return -EINVAL;
1776
1777         return 0;
1778 }
1779
1780 static int soctherm_clk_enable(bool enable)
1781 {
1782         if (soctherm_clk == NULL || tsensor_clk == NULL)
1783                 return -EINVAL;
1784
1785         if (enable) {
1786                 clk_enable(soctherm_clk);
1787                 clk_enable(tsensor_clk);
1788         } else {
1789                 clk_disable(soctherm_clk);
1790                 clk_disable(tsensor_clk);
1791         }
1792
1793         return 0;
1794 }
1795
1796 static int soctherm_fuse_read_calib_base(void)
1797 {
1798         s32 calib_cp, calib_ft;
1799         s32 nominal_calib_cp, nominal_calib_ft;
1800
1801         if (tegra_fuse_calib_base_get_cp(&fuse_calib_base_cp, &calib_cp) < 0 ||
1802             tegra_fuse_calib_base_get_ft(&fuse_calib_base_ft, &calib_ft) < 0) {
1803                 pr_err("soctherm: ERROR: Improper CP or FT calib fuse.\n");
1804                 return -EINVAL;
1805         }
1806
1807         nominal_calib_cp = 25;
1808         if (tegra_chip_id == TEGRA_CHIPID_TEGRA11)
1809                 nominal_calib_ft = 90;
1810         else if (tegra_chip_id == TEGRA_CHIPID_TEGRA14)
1811                 nominal_calib_ft = 105;
1812         else if (tegra_chip_id == TEGRA_CHIPID_TEGRA12)
1813                 nominal_calib_ft = 105;
1814         else
1815                 BUG();
1816
1817         /* use HI precision to calculate: use fuse_temp in 0.5C */
1818         actual_temp_cp = 2 * nominal_calib_cp + calib_cp;
1819         actual_temp_ft = 2 * nominal_calib_ft + calib_ft;
1820
1821         return 0;
1822 }
1823
1824 static int t11x_fuse_corr_alpha[] = { /* scaled *1000000 */
1825         [TSENSE_CPU0] = 1196400,
1826         [TSENSE_CPU1] = 1196400,
1827         [TSENSE_CPU2] = 1196400,
1828         [TSENSE_CPU3] = 1196400,
1829         [TSENSE_GPU]  = 1124500,
1830         [TSENSE_PLLX] = 1224200,
1831 };
1832
1833 static int t11x_fuse_corr_beta[] = { /* scaled *1000000 */
1834         [TSENSE_CPU0] = -13600000,
1835         [TSENSE_CPU1] = -13600000,
1836         [TSENSE_CPU2] = -13600000,
1837         [TSENSE_CPU3] = -13600000,
1838         [TSENSE_GPU]  =  -9793100,
1839         [TSENSE_PLLX] = -14665000,
1840 };
1841
1842 static int t14x_fuse_corr_alpha[] = { /* scaled *1000000 */
1843         [TSENSE_CPU0] = 1149000,
1844         [TSENSE_CPU1] = 1148800,
1845         [TSENSE_CPU2] = 1139100,
1846         [TSENSE_CPU3] = 1141800,
1847         [TSENSE_MEM0] = 1082300,
1848         [TSENSE_MEM1] = 1061800,
1849         [TSENSE_GPU]  = 1078900,
1850         [TSENSE_PLLX] = 1125900,
1851 };
1852
1853 static int t14x_fuse_corr_beta[] = { /* scaled *1000000 */
1854         [TSENSE_CPU0] = -16753000,
1855         [TSENSE_CPU1] = -16287000,
1856         [TSENSE_CPU2] = -12552000,
1857         [TSENSE_CPU3] = -11061000,
1858         [TSENSE_MEM0] = -11061000,
1859         [TSENSE_MEM1] =  -7596500,
1860         [TSENSE_GPU]  = -10480000,
1861         [TSENSE_PLLX] = -14736000,
1862 };
1863
1864 static int t12x_fuse_corr_alpha[] = { /* scaled *1000000 */
1865         [TSENSE_CPU0] = 1148300,
1866         [TSENSE_CPU1] = 1126100,
1867         [TSENSE_CPU2] = 1155800,
1868         [TSENSE_CPU3] = 1134900,
1869         [TSENSE_MEM0] = 1062700,
1870         [TSENSE_MEM1] = 1084700,
1871         [TSENSE_GPU]  = 1084300,
1872         [TSENSE_PLLX] = 1134500,
1873 };
1874
1875 static int t12x_fuse_corr_beta[] = { /* scaled *1000000 */
1876         [TSENSE_CPU0] =  -6572300,
1877         [TSENSE_CPU1] =  -5794600,
1878         [TSENSE_CPU2] =  -7462800,
1879         [TSENSE_CPU3] =  -6810800,
1880         [TSENSE_MEM0] =  -4463200,
1881         [TSENSE_MEM1] =  -5603400,
1882         [TSENSE_GPU]  =  -5111900,
1883         [TSENSE_PLLX] =  -7410700,
1884 };
1885
1886 static int t12x_fuse_corr_alpa2[] = { /* scaled *1000000 */
1887         [TSENSE_CPU0] = 1135400,
1888         [TSENSE_CPU1] = 1122220,
1889         [TSENSE_CPU2] = 1127000,
1890         [TSENSE_CPU3] = 1110900,
1891         [TSENSE_MEM0] = 1122300,
1892         [TSENSE_MEM1] = 1145700,
1893         [TSENSE_GPU]  = 1120100,
1894         [TSENSE_PLLX] = 1106500,
1895 };
1896
1897 static int t12x_fuse_corr_beta2[] = { /* scaled *1000000 */
1898         [TSENSE_CPU0] =  -6266900,
1899         [TSENSE_CPU1] =  -5700700,
1900         [TSENSE_CPU2] =  -6768200,
1901         [TSENSE_CPU3] =  -6232000,
1902         [TSENSE_MEM0] =  -5936400,
1903         [TSENSE_MEM1] =  -7124600,
1904         [TSENSE_GPU]  =  -6000500,
1905         [TSENSE_PLLX] =  -6729300,
1906 };
1907
1908 static int soctherm_fuse_read_tsensor(enum soctherm_sense sensor)
1909 {
1910         u32 r, value;
1911         s32 calib, delta_sens, delta_temp;
1912         s16 therm_a, therm_b;
1913         s32 div, mult, actual_tsensor_ft, actual_tsensor_cp;
1914         int fuse_rev;
1915         u32 base_cp;
1916         s32 shft_cp;
1917
1918         fuse_rev = tegra_fuse_calib_base_get_cp(&base_cp, &shft_cp);
1919         if (fuse_rev < 0)
1920                 return -EINVAL;
1921
1922         tegra_fuse_get_tsensor_calib(sensor2tsensorcalib[sensor], &value);
1923
1924         /* Extract bits and convert to signed 2's complement */
1925         calib = REG_GET(value, FUSE_TSENSOR_CALIB_FT);
1926         calib = MAKE_SIGNED32(calib, FUSE_TSENSOR_CALIB_BITS);
1927         actual_tsensor_ft = (fuse_calib_base_ft * 32) + calib;
1928
1929         calib = REG_GET(value, FUSE_TSENSOR_CALIB_CP);
1930         calib = MAKE_SIGNED32(calib, FUSE_TSENSOR_CALIB_BITS);
1931         actual_tsensor_cp = (fuse_calib_base_cp * 64) + calib;
1932
1933         mult = plat_data.sensor_data[sensor].pdiv *
1934                 plat_data.sensor_data[sensor].tsamp_ATE;
1935         div = plat_data.sensor_data[sensor].tsample *
1936                 plat_data.sensor_data[sensor].pdiv_ATE;
1937
1938         /* first calculate therm_a and therm_b in Hi precision */
1939         delta_sens = actual_tsensor_ft - actual_tsensor_cp;
1940         delta_temp = actual_temp_ft - actual_temp_cp;
1941
1942         therm_a = div64_s64_precise((s64)delta_temp * (1LL << 13) * mult,
1943                                     (s64)delta_sens * div);
1944
1945         therm_b = div64_s64_precise((((s64)actual_tsensor_ft * actual_temp_cp) -
1946                                      ((s64)actual_tsensor_cp * actual_temp_ft)),
1947                                     (s64)delta_sens);
1948
1949         /* FUSE corrections for Tegra when precision is set LOW */
1950         if (PRECISION_IS_LOWER()) {
1951                 if (tegra_chip_id == TEGRA_CHIPID_TEGRA11) {
1952                         t11x_fuse_corr_alpha[sensor] =
1953                                 t11x_fuse_corr_alpha[sensor] ?: 1000000;
1954                         therm_a = div64_s64_precise(
1955                                 (s64)therm_a * t11x_fuse_corr_alpha[sensor],
1956                                 (s64)1000000LL);
1957                         therm_b = div64_s64_precise(
1958                                 (s64)therm_b * t11x_fuse_corr_alpha[sensor] +
1959                                 t11x_fuse_corr_beta[sensor], (s64)1000000LL);
1960                 } else if (tegra_chip_id == TEGRA_CHIPID_TEGRA14) {
1961                         t14x_fuse_corr_alpha[sensor] =
1962                                 t14x_fuse_corr_alpha[sensor] ?: 1000000;
1963                         therm_a = div64_s64_precise(
1964                                 (s64)therm_a * t14x_fuse_corr_alpha[sensor],
1965                                 (s64)1000000LL);
1966                         therm_b = div64_s64_precise(
1967                                 (s64)therm_b * t14x_fuse_corr_alpha[sensor] +
1968                                 t14x_fuse_corr_beta[sensor], (s64)1000000LL);
1969                 }
1970         } else {
1971                 if (tegra_chip_id == TEGRA_CHIPID_TEGRA12) {
1972                         if (fuse_rev == 0) { /* new CP1/CP2 */
1973                                 t12x_fuse_corr_alpa2[sensor] =
1974                                         t12x_fuse_corr_alpa2[sensor] ?: 1000000;
1975                                 therm_a = div64_s64_precise(
1976                                   (s64)therm_a * t12x_fuse_corr_alpa2[sensor],
1977                                   (s64)1000000LL);
1978                                 therm_b = div64_s64_precise(
1979                                   (s64)therm_b * t12x_fuse_corr_alpa2[sensor] +
1980                                   t12x_fuse_corr_beta2[sensor], (s64)1000000LL);
1981                         } else { /* old CP/FT */
1982                                 t12x_fuse_corr_alpha[sensor] =
1983                                         t12x_fuse_corr_alpha[sensor] ?: 1000000;
1984                                 therm_a = div64_s64_precise(
1985                                   (s64)therm_a * t12x_fuse_corr_alpha[sensor],
1986                                   (s64)1000000LL);
1987                                 therm_b = div64_s64_precise(
1988                                   (s64)therm_b * t12x_fuse_corr_alpha[sensor] +
1989                                   t12x_fuse_corr_beta[sensor], (s64)1000000LL);
1990                         }
1991                 }
1992         }
1993
1994         therm_a = LOWER_PRECISION_FOR_TEMP(therm_a);
1995         therm_b = LOWER_PRECISION_FOR_TEMP(therm_b);
1996
1997         sensor2therm_a[sensor] = (s16)therm_a;
1998         sensor2therm_b[sensor] = (s16)therm_b;
1999
2000         r = REG_SET(0, TS_CPU0_CONFIG2_THERM_A, therm_a);
2001         r = REG_SET(r, TS_CPU0_CONFIG2_THERM_B, therm_b);
2002         soctherm_writel(r, TS_TSENSE_REG_OFFSET(TS_CPU0_CONFIG2, sensor));
2003
2004         return 0;
2005 }
2006
2007 static void soctherm_therm_trip_init(struct tegra_tsensor_pmu_data *data)
2008 {
2009         u32 val, checksum;
2010
2011         if (!data)
2012                 return;
2013
2014         /* enable therm trip at PMC */
2015         val = pmc_readl(PMC_SENSOR_CTRL);
2016         val = REG_SET(val, PMC_SCRATCH_WRITE, 1);
2017         val = REG_SET(val, PMC_ENABLE_RST, 1);
2018         pmc_writel(val, PMC_SENSOR_CTRL);
2019
2020         /* Fill scratch registers to shutdown device on therm TRIP */
2021         val = REG_SET(0, PMU_OFF_DATA, data->poweroff_reg_data);
2022         val = REG_SET(val, PMU_OFF_ADDR, data->poweroff_reg_addr);
2023         pmc_writel(val, PMC_SCRATCH54);
2024
2025         val = REG_SET(0, RESET_TEGRA, 1);
2026         val = REG_SET(val, CONTROLLER_TYPE, data->controller_type);
2027         val = REG_SET(val, I2C_CONTROLLER_ID, data->i2c_controller_id);
2028         val = REG_SET(val, PINMUX, data->pinmux);
2029         val = REG_SET(val, PMU_16BIT_SUPPORT, data->pmu_16bit_ops);
2030         val = REG_SET(val, PMU_I2C_ADDRESS, data->pmu_i2c_addr);
2031
2032         checksum = data->poweroff_reg_addr +
2033                 data->poweroff_reg_data +
2034                 (val & 0xFF) +
2035                 ((val >> 8) & 0xFF) +
2036                 ((val >> 24) & 0xFF);
2037         checksum &= 0xFF;
2038         checksum = 0x100 - checksum;
2039
2040         val = REG_SET(val, CHECKSUM, checksum);
2041         pmc_writel(val, PMC_SCRATCH55);
2042 }
2043
2044 static void soctherm_adjust_cpu_zone(void)
2045 {
2046         u32 r;
2047         int cpu;
2048         unsigned long cpu_temp, pll_temp, diff;
2049
2050         if (soctherm_suspended)
2051                 return;
2052
2053         if (!soctherm_high_voltage_range) {
2054                 r = soctherm_readl(TS_TEMP1);
2055                 cpu_temp = temp_translate(REG_GET(r, TS_TEMP1_CPU_TEMP));
2056
2057
2058                 r = soctherm_readl(TS_TEMP2);
2059                 pll_temp = temp_translate(REG_GET(r, TS_TEMP2_PLLX_TEMP));
2060
2061                 if (cpu_temp > pll_temp)
2062                         diff = cpu_temp - pll_temp;
2063                 else
2064                         diff = 0;
2065
2066                 /* Program hotspot offsets per CPU ~ PLL diff */
2067                 r = soctherm_readl(TS_HOTSPOT_OFF);
2068                 r = REG_SET(r, TS_HOTSPOT_OFF_CPU, diff / 1000);
2069                 soctherm_writel(r, TS_HOTSPOT_OFF);
2070
2071                 /* Stop CPUn TSOSCs */
2072                 for (cpu = 0; cpu <= TSENSE_CPU3; cpu++) {
2073                         r = soctherm_readl(TS_TSENSE_REG_OFFSET
2074                                                 (TS_CPU0_CONFIG0, cpu));
2075                         r = REG_SET(r, TS_CPU0_CONFIG0_STOP, 1);
2076                         soctherm_writel(r, TS_TSENSE_REG_OFFSET
2077                                                 (TS_CPU0_CONFIG0, cpu));
2078                 }
2079         } else {
2080                 /* UN-Stop CPUn TSOSCs */
2081                 for (cpu = 0; cpu <= TSENSE_CPU3; cpu++) {
2082                         r = soctherm_readl(TS_TSENSE_REG_OFFSET
2083                                                 (TS_CPU0_CONFIG0, cpu));
2084                         r = REG_SET(r, TS_CPU0_CONFIG0_STOP, 0);
2085                         soctherm_writel(r, TS_TSENSE_REG_OFFSET
2086                                                 (TS_CPU0_CONFIG0, cpu));
2087                 }
2088
2089                 /* Program hotspot offsets per config */
2090                 r = soctherm_readl(TS_HOTSPOT_OFF);
2091                 r = REG_SET(r, TS_HOTSPOT_OFF_CPU,
2092                         plat_data.therm[THERM_CPU].hotspot_offset / 1000);
2093
2094                 soctherm_writel(r, TS_HOTSPOT_OFF);
2095         }
2096 }
2097
2098 static int soctherm_init_platform_data(void)
2099 {
2100         struct soctherm_therm *therm;
2101         struct soctherm_sensor *s;
2102         struct soctherm_sensor sensor_defaults;
2103         int i, j, k;
2104         long rem;
2105         long gsh = MAX_HIGH_TEMP;
2106         u32 r;
2107
2108         if (tegra_chip_id == TEGRA_CHIPID_TEGRA11)
2109                 sensor_defaults = default_t11x_sensor_params;
2110         else if (tegra_chip_id == TEGRA_CHIPID_TEGRA14)
2111                 sensor_defaults = default_t14x_sensor_params;
2112         else if (tegra_chip_id == TEGRA_CHIPID_TEGRA12)
2113                 sensor_defaults = default_t12x_sensor_params;
2114         else
2115                 BUG();
2116
2117         /* initialize default values for unspecified params */
2118         for (i = 0; i < TSENSE_SIZE; i++) {
2119                 therm = &plat_data.therm[tsensor2therm_map[i]];
2120                 s = &plat_data.sensor_data[i];
2121                 s->sensor_enable = s->zone_enable;
2122                 s->sensor_enable = s->sensor_enable ?: therm->zone_enable;
2123                 s->tall      = s->tall      ?: sensor_defaults.tall;
2124                 s->tiddq     = s->tiddq     ?: sensor_defaults.tiddq;
2125                 s->ten_count = s->ten_count ?: sensor_defaults.ten_count;
2126                 s->tsample   = s->tsample   ?: sensor_defaults.tsample;
2127                 s->tsamp_ATE = s->tsamp_ATE ?: sensor_defaults.tsamp_ATE;
2128                 s->pdiv      = s->pdiv      ?: sensor_defaults.pdiv;
2129                 s->pdiv_ATE  = s->pdiv_ATE  ?: sensor_defaults.pdiv_ATE;
2130         }
2131
2132         /* Pdiv */
2133         r = soctherm_readl(TS_PDIV);
2134         r = REG_SET(r, TS_PDIV_CPU, plat_data.sensor_data[TSENSE_CPU0].pdiv);
2135         r = REG_SET(r, TS_PDIV_GPU, plat_data.sensor_data[TSENSE_GPU].pdiv);
2136         r = REG_SET(r, TS_PDIV_MEM, plat_data.sensor_data[TSENSE_MEM0].pdiv);
2137         r = REG_SET(r, TS_PDIV_PLLX, plat_data.sensor_data[TSENSE_PLLX].pdiv);
2138         soctherm_writel(r, TS_PDIV);
2139
2140         /* Thermal Sensing programming */
2141         if (soctherm_fuse_read_calib_base() < 0)
2142                 return -EINVAL;
2143         for (i = 0; i < TSENSE_SIZE; i++) {
2144                 if (plat_data.sensor_data[i].sensor_enable) {
2145                         soctherm_tsense_program(i, &plat_data.sensor_data[i]);
2146                         if (soctherm_fuse_read_tsensor(i) < 0)
2147                                 return -EINVAL;
2148                 }
2149         }
2150
2151         soctherm_adjust_cpu_zone();
2152
2153         /* Sanitize therm trips */
2154         for (i = 0; i < THERM_SIZE; i++) {
2155                 therm = &plat_data.therm[i];
2156                 if (!therm->zone_enable)
2157                         continue;
2158
2159                 for (j = 0; j < therm->num_trips; j++) {
2160                         rem = therm->trips[j].trip_temp %
2161                                 LOWER_PRECISION_FOR_CONV(1000);
2162                         if (rem) {
2163                                 pr_warn(
2164                         "soctherm: zone%d/trip_point%d %ld mC rounded down\n",
2165                                         i, j, therm->trips[j].trip_temp);
2166                                 therm->trips[j].trip_temp -= rem;
2167                         }
2168                 }
2169         }
2170
2171         /* Program hotspot offsets per THERM */
2172         r = REG_SET(0, TS_HOTSPOT_OFF_CPU,
2173                     plat_data.therm[THERM_CPU].hotspot_offset / 1000);
2174         r = REG_SET(r, TS_HOTSPOT_OFF_GPU,
2175                     plat_data.therm[THERM_GPU].hotspot_offset / 1000);
2176         r = REG_SET(r, TS_HOTSPOT_OFF_MEM,
2177                     plat_data.therm[THERM_MEM].hotspot_offset / 1000);
2178         soctherm_writel(r, TS_HOTSPOT_OFF);
2179
2180         /* Thermal HW throttle programming */
2181         for (i = 0; i < THROTTLE_SIZE; i++) {
2182                 /* Sanitize HW throttle priority for OC1 - OC4 (not OC5) */
2183                 if ((i != THROTTLE_OC5) && (!plat_data.throttle[i].priority))
2184                         plat_data.throttle[i].priority = 0xE + i;
2185
2186                 /* Setup PSKIP parameters */
2187                 soctherm_throttle_program(i);
2188
2189                 /* Setup throttle thresholds per THERM */
2190                 for (j = 0; j < THERM_SIZE; j++) {
2191                         if ((therm2dev[j] == THROTTLE_DEV_NONE) ||
2192                             (!plat_data.throttle[i].devs[therm2dev[j]].enable))
2193                                 continue;
2194
2195                         therm = &plat_data.therm[j];
2196                         for (k = 0; k < therm->num_trips; k++)
2197                                 if ((therm->trips[k].trip_type ==
2198                                      THERMAL_TRIP_HOT) &&
2199                                     strnstr(therm->trips[k].cdev_type,
2200                                             i == THROTTLE_HEAVY ? "heavy" :
2201                                             "light", THERMAL_NAME_LENGTH))
2202                                         break;
2203                         if (k < therm->num_trips && i <= THROTTLE_HEAVY)
2204                                 prog_hw_threshold(&therm->trips[k], j, i);
2205                 }
2206         }
2207
2208         if (plat_data.throttle[THROTTLE_HEAVY].priority <
2209             plat_data.throttle[THROTTLE_LIGHT].priority)
2210                 pr_err("soctherm: ERROR: Priority of HEAVY less than LIGHT\n");
2211
2212         /* initialize stats collection */
2213         r = STATS_CTL_CLR_DN | STATS_CTL_EN_DN |
2214                 STATS_CTL_CLR_UP | STATS_CTL_EN_UP;
2215         soctherm_writel(r, STATS_CTL);
2216         soctherm_writel(OC_STATS_CTL_EN_ALL, OC_STATS_CTL);
2217
2218         /* Enable PMC to shutdown */
2219         soctherm_therm_trip_init(plat_data.tshut_pmu_trip_data);
2220
2221         r = clk_reset_readl(CAR_SUPER_CCLKG_DIVIDER);
2222         r = REG_SET(r, CDIVG_USE_THERM_CONTROLS, 1);
2223         clk_reset_writel(r, CAR_SUPER_CCLKG_DIVIDER);
2224
2225         /* Thermtrip */
2226         for (i = 0; i < THERM_SIZE; i++) {
2227                 therm = &plat_data.therm[i];
2228                 if (!therm->zone_enable)
2229                         continue;
2230
2231                 for (j = 0; j < therm->num_trips; j++) {
2232                         if (therm->trips[j].trip_type != THERMAL_TRIP_CRITICAL)
2233                                 continue;
2234                         if (i == THERM_GPU) {
2235                                 gsh = therm->trips[j].trip_temp;
2236                         } else if ((i == THERM_MEM) &&
2237                                    (gsh != MAX_HIGH_TEMP) &&
2238                                    (therm->trips[j].trip_temp != gsh)) {
2239                                 pr_warn("soctherm: Force TRIP temp: MEM = GPU");
2240                                 therm->trips[j].trip_temp = gsh;
2241                         }
2242                         prog_hw_shutdown(&therm->trips[j], i);
2243                 }
2244         }
2245
2246         return 0;
2247 }
2248
2249 static void soctherm_suspend_locked(void)
2250 {
2251         if (!soctherm_suspended) {
2252                 soctherm_writel((u32)-1, TH_INTR_DISABLE);
2253                 soctherm_writel((u32)-1, OC_INTR_DISABLE);
2254                 disable_irq(INT_THERMAL);
2255                 disable_irq(INT_EDP);
2256                 soctherm_init_platform_done = false;
2257                 soctherm_suspended = true;
2258                 /* soctherm_clk_enable(false);*/
2259         }
2260 }
2261
2262 static int soctherm_suspend(void)
2263 {
2264         mutex_lock(&soctherm_suspend_resume_lock);
2265         soctherm_suspend_locked();
2266         mutex_unlock(&soctherm_suspend_resume_lock);
2267         return 0;
2268 }
2269
2270 static void soctherm_resume_locked(void)
2271 {
2272         if (soctherm_suspended) {
2273                 /* soctherm_clk_enable(true);*/
2274                 soctherm_suspended = false;
2275                 soctherm_init_platform_data();
2276                 soctherm_init_platform_done = true;
2277                 soctherm_update();
2278                 enable_irq(INT_THERMAL);
2279                 enable_irq(INT_EDP);
2280         }
2281 }
2282
2283 static int soctherm_resume(void)
2284 {
2285         mutex_lock(&soctherm_suspend_resume_lock);
2286         soctherm_resume_locked();
2287         mutex_unlock(&soctherm_suspend_resume_lock);
2288         return 0;
2289 }
2290
2291 static int soctherm_sync(void)
2292 {
2293         mutex_lock(&soctherm_suspend_resume_lock);
2294
2295         if (soctherm_suspended) {
2296                 soctherm_resume_locked();
2297                 soctherm_suspend_locked();
2298         } else {
2299                 soctherm_update();
2300         }
2301
2302         mutex_unlock(&soctherm_suspend_resume_lock);
2303         return 0;
2304 }
2305 late_initcall_sync(soctherm_sync);
2306
2307 static int soctherm_pm_notify(struct notifier_block *nb,
2308                                 unsigned long event, void *data)
2309 {
2310         switch (event) {
2311         case PM_SUSPEND_PREPARE:
2312                 soctherm_suspend();
2313                 break;
2314         case PM_POST_SUSPEND:
2315                 soctherm_resume();
2316                 break;
2317         }
2318
2319         return NOTIFY_OK;
2320 }
2321
2322 static struct notifier_block soctherm_nb = {
2323         .notifier_call = soctherm_pm_notify,
2324 };
2325
2326 static void soctherm_oc_irq_lock(struct irq_data *data)
2327 {
2328         struct soctherm_oc_irq_chip_data *d = irq_data_get_irq_chip_data(data);
2329
2330         mutex_lock(&d->irq_lock);
2331 }
2332 static void soctherm_oc_irq_sync_unlock(struct irq_data *data)
2333 {
2334         struct soctherm_oc_irq_chip_data *d = irq_data_get_irq_chip_data(data);
2335
2336         mutex_unlock(&d->irq_lock);
2337 }
2338 static void soctherm_oc_irq_enable(struct irq_data *data)
2339 {
2340         struct soctherm_oc_irq_chip_data *d = irq_data_get_irq_chip_data(data);
2341
2342         d->irq_enable |= BIT(data->hwirq);
2343 }
2344
2345 static void soctherm_oc_irq_disable(struct irq_data *data)
2346 {
2347         struct soctherm_oc_irq_chip_data *d = irq_data_get_irq_chip_data(data);
2348
2349         d->irq_enable &= ~BIT(data->hwirq);
2350 }
2351
2352 static int soctherm_oc_irq_set_type(struct irq_data *data, unsigned int type)
2353 {
2354         return 0;
2355 }
2356
2357 static int soctherm_oc_irq_set_wake(struct irq_data *data, unsigned int on)
2358 {
2359         int gpio;
2360         int gpio_irq;
2361
2362         gpio = soctherm_ocx_to_wake_gpio[data->hwirq];
2363         if (!gpio_is_valid(gpio)) {
2364                 pr_err("No wakeup supported for irq %lu\n", data->hwirq);
2365                 return -EINVAL;
2366         }
2367
2368         gpio_irq = gpio_to_irq(gpio);
2369         if (gpio_irq < 0) {
2370                 pr_err("No gpio_to_irq for gpio %d\n", gpio);
2371                 return gpio;
2372         }
2373
2374         irq_set_irq_wake(gpio_irq, on);
2375         return 0;
2376 }
2377
2378 static int soctherm_oc_irq_map(struct irq_domain *h, unsigned int virq,
2379                 irq_hw_number_t hw)
2380 {
2381         struct soctherm_oc_irq_chip_data *data = h->host_data;
2382
2383         irq_set_chip_data(virq, data);
2384         irq_set_chip(virq, &data->irq_chip);
2385         irq_set_nested_thread(virq, 1);
2386         set_irq_flags(virq, IRQF_VALID);
2387         return 0;
2388 }
2389
2390 static struct irq_domain_ops soctherm_oc_domain_ops = {
2391         .map    = soctherm_oc_irq_map,
2392         .xlate  = irq_domain_xlate_twocell,
2393 };
2394
2395 static int tegra11_soctherem_oc_int_init(int irq_base, int num_irqs)
2396 {
2397         if (irq_base <= 0 || !num_irqs) {
2398                 pr_info("%s(): OC interrupts are not enabled\n", __func__);
2399                 return 0;
2400         }
2401
2402         mutex_init(&soc_irq_cdata.irq_lock);
2403         soc_irq_cdata.irq_enable = 0;
2404
2405         soc_irq_cdata.irq_chip.name = "sco_therm_oc";
2406         soc_irq_cdata.irq_chip.irq_bus_lock = soctherm_oc_irq_lock,
2407         soc_irq_cdata.irq_chip.irq_bus_sync_unlock = soctherm_oc_irq_sync_unlock,
2408         soc_irq_cdata.irq_chip.irq_disable = soctherm_oc_irq_disable,
2409         soc_irq_cdata.irq_chip.irq_enable = soctherm_oc_irq_enable,
2410         soc_irq_cdata.irq_chip.irq_set_type = soctherm_oc_irq_set_type,
2411         soc_irq_cdata.irq_chip.irq_set_wake = soctherm_oc_irq_set_wake,
2412
2413         irq_base = irq_alloc_descs(irq_base, 0, num_irqs, 0);
2414         if (irq_base < 0) {
2415                 pr_err("%s: Failed to allocate IRQs: %d\n", __func__, irq_base);
2416                 return irq_base;
2417         }
2418
2419         soc_irq_cdata.domain = irq_domain_add_legacy(NULL, num_irqs,
2420                         irq_base, 0, &soctherm_oc_domain_ops, &soc_irq_cdata);
2421         if (!soc_irq_cdata.domain) {
2422                 pr_err("%s: Failed to create IRQ domain\n", __func__);
2423                 return -ENOMEM;
2424         }
2425         pr_info("%s(): OC interrupts enabled successful\n", __func__);
2426         return 0;
2427 }
2428
2429 int __init tegra11_soctherm_init(struct soctherm_platform_data *data)
2430 {
2431         int ret;
2432
2433         tegra_chip_id = tegra_get_chip_id();
2434         if (!(tegra_chip_id == TEGRA_CHIPID_TEGRA11 ||
2435               tegra_chip_id == TEGRA_CHIPID_TEGRA14 ||
2436               tegra_chip_id == TEGRA_CHIPID_TEGRA12)) {
2437                 pr_err("%s: Unknown chip_id %d", __func__, tegra_chip_id);
2438                 return -1;
2439         }
2440
2441         register_pm_notifier(&soctherm_nb);
2442
2443         if (!data)
2444                 return -1;
2445         plat_data = *data;
2446
2447         if (soctherm_clk_init() < 0)
2448                 return -1;
2449
2450         if (soctherm_clk_enable(true) < 0)
2451                 return -1;
2452
2453         if (soctherm_init_platform_data() < 0)
2454                 return -1;
2455
2456         soctherm_init_platform_done = true;
2457
2458         ret = tegra11_soctherem_oc_int_init(data->oc_irq_base,
2459                         data->num_oc_irqs);
2460         if (ret < 0) {
2461                 pr_err("soctherem_oc_int_init failed: %d\n", ret);
2462                 return ret;
2463         }
2464
2465         if (request_threaded_irq(INT_THERMAL, soctherm_thermal_isr,
2466                                  soctherm_thermal_thread_func, IRQF_ONESHOT,
2467                                  "soctherm_thermal", NULL) < 0)
2468                 return -1;
2469
2470         if (request_threaded_irq(INT_EDP, soctherm_edp_isr,
2471                                  soctherm_edp_thread_func, IRQF_ONESHOT,
2472                                  "soctherm_edp", NULL) < 0)
2473                 return -1;
2474
2475         return 0;
2476 }
2477
2478 void tegra_soctherm_adjust_cpu_zone(bool high_voltage_range)
2479 {
2480         if (soctherm_high_voltage_range != high_voltage_range) {
2481                 soctherm_high_voltage_range = high_voltage_range;
2482                 soctherm_adjust_cpu_zone();
2483         }
2484 }
2485
2486 #ifdef CONFIG_DEBUG_FS
2487
2488 static int regs_show(struct seq_file *s, void *data)
2489 {
2490         u32 r;
2491         u32 state;
2492         int tcpu[TSENSE_SIZE];
2493         int i, j, level;
2494         uint m, n, q;
2495
2496         if (soctherm_suspended) {
2497                 seq_printf(s, "SOC_THERM is SUSPENDED\n");
2498                 return 0;
2499         }
2500
2501         seq_printf(s, "-----TSENSE (precision %s  convert %s)-----\n",
2502                 PRECISION_TO_STR(), read_hw_temp ? "HW" : "SW");
2503         for (i = 0; i < TSENSE_SIZE; i++) {
2504                 r = soctherm_readl(TS_TSENSE_REG_OFFSET(TS_CPU0_CONFIG1, i));
2505                 state = REG_GET(r, TS_CPU0_CONFIG1_EN);
2506                 if (!state)
2507                         continue;
2508
2509                 seq_printf(s, "%s: ", sensor_names[i]);
2510
2511                 seq_printf(s, "En(%d) ", state);
2512                 state = REG_GET(r, TS_CPU0_CONFIG1_TIDDQ);
2513                 seq_printf(s, "tiddq(%d) ", state);
2514                 state = REG_GET(r, TS_CPU0_CONFIG1_TEN_COUNT);
2515                 seq_printf(s, "ten_count(%d) ", state);
2516                 state = REG_GET(r, TS_CPU0_CONFIG1_TSAMPLE);
2517                 seq_printf(s, "tsample(%d) ", state + 1);
2518
2519                 r = soctherm_readl(TS_TSENSE_REG_OFFSET(TS_CPU0_STATUS1, i));
2520                 state = REG_GET(r, TS_CPU0_STATUS1_TEMP_VALID);
2521                 seq_printf(s, "Temp(%d/", state);
2522                 state = REG_GET(r, TS_CPU0_STATUS1_TEMP);
2523                 seq_printf(s, "%d) ", tcpu[i] = temp_translate(state));
2524
2525                 r = soctherm_readl(TS_TSENSE_REG_OFFSET(TS_CPU0_STATUS0, i));
2526                 state = REG_GET(r, TS_CPU0_STATUS0_VALID);
2527                 seq_printf(s, "Capture(%d/", state);
2528                 state = REG_GET(r, TS_CPU0_STATUS0_CAPTURE);
2529                 seq_printf(s, "%d) (Converted-temp(%ld) ", state,
2530                            temp_convert(state, sensor2therm_a[i],
2531                                         sensor2therm_b[i]));
2532
2533                 r = soctherm_readl(TS_TSENSE_REG_OFFSET(TS_CPU0_CONFIG0, i));
2534                 state = REG_GET(r, TS_CPU0_CONFIG0_TALL);
2535                 seq_printf(s, "Tall(%d) ", state);
2536                 state = REG_GET(r, TS_CPU0_CONFIG0_TCALC_OVER);
2537                 seq_printf(s, "Over(%d/", state);
2538                 state = REG_GET(r, TS_CPU0_CONFIG0_OVER);
2539                 seq_printf(s, "%d/", state);
2540                 state = REG_GET(r, TS_CPU0_CONFIG0_CPTR_OVER);
2541                 seq_printf(s, "%d) ", state);
2542
2543                 r = soctherm_readl(TS_TSENSE_REG_OFFSET(TS_CPU0_CONFIG2, i));
2544                 state = REG_GET(r, TS_CPU0_CONFIG2_THERM_A);
2545                 seq_printf(s, "Therm_A/B(%d/", state);
2546                 state = REG_GET(r, TS_CPU0_CONFIG2_THERM_B);
2547                 seq_printf(s, "%d)\n", (s16)state);
2548         }
2549
2550         r = soctherm_readl(TS_PDIV);
2551         seq_printf(s, "PDIV: 0x%x\n", r);
2552
2553         seq_printf(s, "\n");
2554         seq_printf(s, "-----SOC_THERM-----\n");
2555
2556         r = soctherm_readl(TS_TEMP1);
2557         state = REG_GET(r, TS_TEMP1_CPU_TEMP);
2558         seq_printf(s, "Temperatures: CPU(%ld) ", temp_translate(state));
2559         state = REG_GET(r, TS_TEMP1_GPU_TEMP);
2560         seq_printf(s, " GPU(%ld) ", temp_translate(state));
2561         r = soctherm_readl(TS_TEMP2);
2562         state = REG_GET(r, TS_TEMP2_PLLX_TEMP);
2563         seq_printf(s, " PLLX(%ld) ", temp_translate(state));
2564         state = REG_GET(r, TS_TEMP2_MEM_TEMP);
2565         seq_printf(s, " MEM(%ld)\n", temp_translate(state));
2566
2567         for (i = 0; i < THERM_SIZE; i++) {
2568                 seq_printf(s, "%s:\n", therm_names[i]);
2569                 for (level = 0; level < 4; level++) {
2570                         r = soctherm_readl(TS_THERM_REG_OFFSET(CTL_LVL0_CPU0,
2571                                                                 level, i));
2572                         state = REG_GET(r, CTL_LVL0_CPU0_UP_THRESH);
2573                         seq_printf(s, "   %d: Up/Dn(%d/", level,
2574                                    LOWER_PRECISION_FOR_CONV(state));
2575                         state = REG_GET(r, CTL_LVL0_CPU0_DN_THRESH);
2576                         seq_printf(s, "%d) ", LOWER_PRECISION_FOR_CONV(state));
2577                         state = REG_GET(r, CTL_LVL0_CPU0_EN);
2578                         seq_printf(s, "En(%d) ", state);
2579
2580                         state = REG_GET(r, CTL_LVL0_CPU0_CPU_THROT);
2581                         seq_printf(s, "CPU Throt");
2582                         seq_printf(s, "(%s) ", state ?
2583                         state == CTL_LVL0_CPU0_CPU_THROT_LIGHT ? "L" :
2584                         state == CTL_LVL0_CPU0_CPU_THROT_HEAVY ? "H" :
2585                                 "H+L" : "none");
2586
2587                         state = REG_GET(r, CTL_LVL0_CPU0_GPU_THROT);
2588                         seq_printf(s, "GPU Throt");
2589                         seq_printf(s, "(%s) ", state ?
2590                         state == CTL_LVL0_CPU0_GPU_THROT_LIGHT ? "L" :
2591                         state == CTL_LVL0_CPU0_GPU_THROT_HEAVY ? "H" :
2592                                 "H+L" : "none");
2593
2594                         state = REG_GET(r, CTL_LVL0_CPU0_STATUS);
2595                         seq_printf(s, "Status(%s)\n",
2596                                    state == 0 ? "LO" :
2597                                    state == 1 ? "in" :
2598                                    state == 2 ? "??" : "HI");
2599                 }
2600         }
2601
2602         r = soctherm_readl(STATS_CTL);
2603         seq_printf(s, "STATS: Up(%s) Dn(%s)\n",
2604                    r & STATS_CTL_EN_UP ? "En" : "--",
2605                    r & STATS_CTL_EN_DN ? "En" : "--");
2606         for (level = 0; level < 4; level++) {
2607                 r = soctherm_readl(TS_TSENSE_REG_OFFSET(UP_STATS_L0, level));
2608                 seq_printf(s, "  Level_%d Up(%d) ", level, r);
2609                 r = soctherm_readl(TS_TSENSE_REG_OFFSET(DN_STATS_L0, level));
2610                 seq_printf(s, "Dn(%d)\n", r);
2611         }
2612
2613         r = soctherm_readl(THERMTRIP);
2614         state = REG_GET(r, THERMTRIP_ANY_EN);
2615         seq_printf(s, "ThermTRIP ANY En(%d)\n", state);
2616
2617         state = REG_GET(r, THERMTRIP_CPU_EN);
2618         seq_printf(s, "     CPU En(%d) ", state);
2619         state = REG_GET(r, THERMTRIP_CPU_THRESH);
2620         seq_printf(s, "Thresh(%d)\n", LOWER_PRECISION_FOR_CONV(state));
2621
2622         state = REG_GET(r, THERMTRIP_GPU_EN);
2623         seq_printf(s, "     GPU En(%d) ", state);
2624         state = REG_GET(r, THERMTRIP_GPUMEM_THRESH);
2625         seq_printf(s, "Thresh(%d)\n", LOWER_PRECISION_FOR_CONV(state));
2626
2627         state = REG_GET(r, THERMTRIP_MEM_EN);
2628         seq_printf(s, "     MEM En(%d) ", state);
2629         state = REG_GET(r, THERMTRIP_GPUMEM_THRESH);
2630         seq_printf(s, "Thresh(%d)\n", LOWER_PRECISION_FOR_CONV(state));
2631
2632         state = REG_GET(r, THERMTRIP_TSENSE_EN);
2633         seq_printf(s, "    PLLX En(%d) ", state);
2634         state = REG_GET(r, THERMTRIP_TSENSE_THRESH);
2635         seq_printf(s, "Thresh(%d)\n", LOWER_PRECISION_FOR_CONV(state));
2636
2637         r = soctherm_readl(THROT_GLOBAL_CFG);
2638         seq_printf(s, "GLOBAL THROTTLE CONFIG: 0x%08x\n", r);
2639
2640         seq_printf(s, "---------------------------------------------------\n");
2641         r = soctherm_readl(THROT_STATUS);
2642         state = REG_GET(r, THROT_STATUS_BREACH);
2643         seq_printf(s, "THROT STATUS: breach(%d) ", state);
2644         state = REG_GET(r, THROT_STATUS_STATE);
2645         seq_printf(s, "state(%d) ", state);
2646         state = REG_GET(r, THROT_STATUS_ENABLED);
2647         seq_printf(s, "enabled(%d)\n", state);
2648
2649         r = soctherm_readl(CPU_PSKIP_STATUS);
2650         state = REG_GET(r, XPU_PSKIP_STATUS_M);
2651         seq_printf(s, "%s PSKIP STATUS: M(%d) ",
2652                 throt_dev_names[THROTTLE_DEV_CPU], state);
2653
2654         state = REG_GET(r, XPU_PSKIP_STATUS_N);
2655         seq_printf(s, "N(%d) ", state);
2656         state = REG_GET(r, XPU_PSKIP_STATUS_ENABLED);
2657         seq_printf(s, "enabled(%d)\n", state);
2658
2659         r = soctherm_readl(GPU_PSKIP_STATUS);
2660         if (tegra_chip_id == TEGRA_CHIPID_TEGRA12) {
2661                 state = REG_GET(r, XPU_PSKIP_STATUS_ENABLED);
2662                 seq_printf(s, "%s PSKIP STATUS: ",
2663                 throt_dev_names[THROTTLE_DEV_GPU]);
2664                 seq_printf(s, "enabled(%d)\n", state);
2665         } else {
2666                 state = REG_GET(r, XPU_PSKIP_STATUS_M);
2667                 seq_printf(s, "%s PSKIP STATUS: M(%d) ",
2668                            throt_dev_names[THROTTLE_DEV_GPU], state);
2669                 state = REG_GET(r, XPU_PSKIP_STATUS_N);
2670                 seq_printf(s, "N(%d) ", state);
2671                 state = REG_GET(r, XPU_PSKIP_STATUS_ENABLED);
2672                 seq_printf(s, "enabled(%d)\n", state);
2673         }
2674
2675         seq_printf(s, "---------------------------------------------------\n");
2676         seq_printf(s, "THROTTLE control and PSKIP configuration:\n");
2677         seq_printf(s, "%5s  %3s  %2s  %6s  %8s  %7s  %8s  %4s  %4s  %5s  ",
2678                    "throt", "dev", "en", "depth", "dividend", "divisor",
2679                    "duration", "step", "prio", "delay");
2680         seq_printf(s, "%2s  %2s  %2s  %2s  %2s  %2s  ",
2681                    "LL", "HW", "PG", "MD", "01", "EN");
2682         seq_printf(s, "%8s  %8s  %8s  %8s  %8s\n",
2683                    "thresh", "period", "count", "filter", "stats");
2684
2685         /* display throttle_cfg's of all alarms including OC5 */
2686         for (i = 0; i < THROTTLE_SIZE; i++) {
2687                 for (j = 0; j < THROTTLE_DEV_SIZE; j++) {
2688                         r = soctherm_readl(THROT_PSKIP_CTRL(i, j));
2689                         state = REG_GET(r, THROT_PSKIP_CTRL_ENABLE);
2690                         seq_printf(s, "%5s  %3s  %2d  ",
2691                                    j ? "" : throt_names[i],
2692                                    throt_dev_names[j], state);
2693
2694                         if (j == THROTTLE_DEV_GPU) {
2695                                 if (tegra_chip_id == TEGRA_CHIPID_TEGRA12) {
2696                                         state = REG_GET(r,
2697                                                 THROT_PSKIP_CTRL_THROT_DEPTH);
2698                                         seq_printf(s, "%6s  ",
2699                                                 state == THROT_DEPTH_HIG ?
2700                                                 "heavy" :
2701                                                 state == THROT_DEPTH_MED ?
2702                                                 "medium" :
2703                                                 state == THROT_DEPTH_LOW ?
2704                                                 "light" : "none");
2705                                 }
2706                                 seq_printf(s, "\n");
2707                                 continue;
2708                         }
2709
2710                         m = REG_GET(r, THROT_PSKIP_CTRL_DIVIDEND);
2711                         n = REG_GET(r, THROT_PSKIP_CTRL_DIVISOR);
2712                         q = 100 - (((100 * (m + 1)) + ((n + 1) / 2)) / (n + 1));
2713                         seq_printf(s, "%5u%%  ", q);
2714                         seq_printf(s, "%7u  ", m);
2715                         seq_printf(s, "%8u  ", n);
2716
2717                         r = soctherm_readl(THROT_PSKIP_RAMP(i, j));
2718                         state = REG_GET(r, THROT_PSKIP_RAMP_DURATION);
2719                         seq_printf(s, "%8d  ", state);
2720                         state = REG_GET(r, THROT_PSKIP_RAMP_STEP);
2721                         seq_printf(s, "%4d  ", state);
2722
2723                         r = soctherm_readl(THROT_PRIORITY_CTRL(i));
2724                         state = REG_GET(r, THROT_PRIORITY_LITE_PRIO);
2725                         seq_printf(s, "%4d  ", state);
2726
2727                         r = soctherm_readl(THROT_DELAY_CTRL(i));
2728                         state = REG_GET(r, THROT_DELAY_LITE_DELAY);
2729                         seq_printf(s, "%5d  ", state);
2730
2731                         if (i >= THROTTLE_OC1) {
2732                                 r = soctherm_readl(ALARM_CFG(i));
2733                                 state = REG_GET(r, OC1_CFG_LONG_LATENCY);
2734                                 seq_printf(s, "%2d  ", state);
2735                                 state = REG_GET(r, OC1_CFG_HW_RESTORE);
2736                                 seq_printf(s, "%2d  ", state);
2737                                 state = REG_GET(r, OC1_CFG_PWR_GOOD_MASK);
2738                                 seq_printf(s, "%2d  ", state);
2739                                 state = REG_GET(r, OC1_CFG_THROTTLE_MODE);
2740                                 seq_printf(s, "%2d  ", state);
2741                                 state = REG_GET(r, OC1_CFG_ALARM_POLARITY);
2742                                 seq_printf(s, "%2d  ", state);
2743                                 state = REG_GET(r, OC1_CFG_EN_THROTTLE);
2744                                 seq_printf(s, "%2d  ", state);
2745
2746                                 r = soctherm_readl(ALARM_CNT_THRESHOLD(i));
2747                                 seq_printf(s, "%8d  ", r);
2748                                 r = soctherm_readl(ALARM_THRESHOLD_PERIOD(i));
2749                                 seq_printf(s, "%8d  ", r);
2750                                 r = soctherm_readl(ALARM_ALARM_COUNT(i));
2751                                 seq_printf(s, "%8d  ", r);
2752                                 r = soctherm_readl(ALARM_FILTER(i));
2753                                 seq_printf(s, "%8d  ", r);
2754                                 r = soctherm_readl(ALARM_STATS(i));
2755                                 seq_printf(s, "%8d  ", r);
2756                         }
2757                         seq_printf(s, "\n");
2758                 }
2759         }
2760         return 0;
2761 }
2762
2763 static int temp_log_show(struct seq_file *s, void *data)
2764 {
2765         u32 r, state;
2766         int i;
2767         u64 ts;
2768         u_long ns;
2769         bool was_suspended = false;
2770
2771         ts = cpu_clock(0);
2772         ns = do_div(ts, 1000000000);
2773         seq_printf(s, "%6lu.%06lu", (u_long) ts, ns / 1000);
2774
2775         if (soctherm_suspended) {
2776                 mutex_lock(&soctherm_suspend_resume_lock);
2777                 soctherm_resume_locked();
2778                 was_suspended = true;
2779         }
2780
2781         for (i = 0; i < TSENSE_SIZE; i++) {
2782                 r = soctherm_readl(TS_TSENSE_REG_OFFSET(
2783                                         TS_CPU0_CONFIG1, i));
2784                 state = REG_GET(r, TS_CPU0_CONFIG1_EN);
2785                 if (!state)
2786                         continue;
2787
2788                 r = soctherm_readl(TS_TSENSE_REG_OFFSET(
2789                                         TS_CPU0_STATUS1, i));
2790                 if (!REG_GET(r, TS_CPU0_STATUS1_TEMP_VALID)) {
2791                         seq_printf(s, "\tINVALID");
2792                         continue;
2793                 }
2794
2795                 if (read_hw_temp) {
2796                         state = REG_GET(r, TS_CPU0_STATUS1_TEMP);
2797                         seq_printf(s, "\t%ld", temp_translate(state));
2798                 } else {
2799                         r = soctherm_readl(TS_TSENSE_REG_OFFSET(
2800                                                 TS_CPU0_STATUS0, i));
2801                         state = REG_GET(r, TS_CPU0_STATUS0_CAPTURE);
2802                         seq_printf(s, "\t%ld", temp_convert(state,
2803                                                 sensor2therm_a[i],
2804                                                 sensor2therm_b[i]));
2805                 }
2806         }
2807         seq_printf(s, "\n");
2808
2809         if (was_suspended) {
2810                 soctherm_suspend_locked();
2811                 mutex_unlock(&soctherm_suspend_resume_lock);
2812         }
2813         return 0;
2814 }
2815
2816 static int regs_open(struct inode *inode, struct file *file)
2817 {
2818         return single_open(file, regs_show, inode->i_private);
2819 }
2820
2821 static const struct file_operations regs_fops = {
2822         .open           = regs_open,
2823         .read           = seq_read,
2824         .llseek         = seq_lseek,
2825         .release        = single_release,
2826 };
2827
2828 static int convert_get(void *data, u64 *val)
2829 {
2830         *val = !read_hw_temp;
2831         return 0;
2832 }
2833 static int convert_set(void *data, u64 val)
2834 {
2835         read_hw_temp = !val;
2836         return 0;
2837 }
2838
2839 static int cputemp_get(void *data, u64 *val)
2840 {
2841         u32 reg;
2842         reg = soctherm_readl(TS_TEMP1);
2843         *val = (reg & 0xffff0000) >> 16;
2844         return 0;
2845 }
2846
2847 static int cputemp_set(void *data, u64 temp)
2848 {
2849         u32 reg_val = temp_translate_rev(temp);
2850         u32 reg_orig = soctherm_readl(TS_TEMP1);
2851         reg_val = (reg_val << 16) | (reg_orig & 0xffff);
2852         soctherm_writel(reg_val, TS_TEMP1);
2853         return 0;
2854 }
2855
2856 static int gputemp_get(void *data, u64 *val)
2857 {
2858         u32 reg;
2859         reg = soctherm_readl(TS_TEMP1);
2860         *val = (reg & 0x0000ffff);
2861         return 0;
2862 }
2863
2864 static int gputemp_set(void *data, u64 temp)
2865 {
2866         u32 reg_val = temp_translate_rev(temp);
2867         u32 reg_orig = soctherm_readl(TS_TEMP1);
2868         reg_val = reg_val | (reg_orig & 0xffff0000);
2869         soctherm_writel(reg_val, TS_TEMP1);
2870         return 0;
2871 }
2872
2873 static int memtemp_get(void *data, u64 *val)
2874 {
2875         u32 reg;
2876         reg = soctherm_readl(TS_TEMP2);
2877         *val = (reg & 0xffff0000) >> 16;
2878         return 0;
2879 }
2880
2881 static int memtemp_set(void *data, u64 temp)
2882 {
2883         u32 reg_val = temp_translate_rev(temp);
2884         u32 reg_orig = soctherm_readl(TS_TEMP2);
2885         reg_val = (reg_val << 16) | (reg_orig & 0xffff);
2886         soctherm_writel(reg_val, TS_TEMP2);
2887         return 0;
2888 }
2889
2890 static int plltemp_get(void *data, u64 *val)
2891 {
2892         u32 reg;
2893         reg = soctherm_readl(TS_TEMP2);
2894         *val = (reg & 0x0000ffff);
2895         return 0;
2896 }
2897
2898 static int plltemp_set(void *data, u64 temp)
2899 {
2900         u32 reg_val = temp_translate_rev(temp);
2901         u32 reg_orig = soctherm_readl(TS_TEMP2);
2902         reg_val = reg_val | (reg_orig & 0xffff0000);
2903         soctherm_writel(reg_val, TS_TEMP2);
2904         return 0;
2905 }
2906
2907 static int tempoverride_get(void *data, u64 *val)
2908 {
2909         *val = soctherm_readl(TS_TEMP_SW_OVERRIDE);
2910
2911         return 0;
2912 }
2913
2914 static int tempoverride_set(void *data, u64 val)
2915 {
2916         soctherm_writel(val, TS_TEMP_SW_OVERRIDE);
2917
2918         return 0;
2919 }
2920
2921 DEFINE_SIMPLE_ATTRIBUTE(convert_fops, convert_get, convert_set, "%llu\n");
2922
2923 DEFINE_SIMPLE_ATTRIBUTE(cputemp_fops, cputemp_get, cputemp_set, "%llu\n");
2924
2925 DEFINE_SIMPLE_ATTRIBUTE(gputemp_fops, gputemp_get, gputemp_set, "%llu\n");
2926
2927 DEFINE_SIMPLE_ATTRIBUTE(memtemp_fops, memtemp_get, memtemp_set, "%llu\n");
2928
2929 DEFINE_SIMPLE_ATTRIBUTE(plltemp_fops, plltemp_get, plltemp_set, "%llu\n");
2930
2931 DEFINE_SIMPLE_ATTRIBUTE(tempoverride_fops, tempoverride_get, tempoverride_set, "%llu\n");
2932
2933 static int temp_log_open(struct inode *inode, struct file *file)
2934 {
2935         return single_open(file, temp_log_show, inode->i_private);
2936 }
2937 static const struct file_operations temp_log_fops = {
2938         .open           = temp_log_open,
2939         .read           = seq_read,
2940         .llseek         = seq_lseek,
2941         .release        = single_release,
2942 };
2943
2944 static int __init soctherm_debug_init(void)
2945 {
2946         struct dentry *tegra_soctherm_root;
2947
2948         tegra_soctherm_root = debugfs_create_dir("tegra_soctherm", 0);
2949         debugfs_create_file("regs", 0644, tegra_soctherm_root,
2950                                 NULL, &regs_fops);
2951         debugfs_create_file("convert", 0644, tegra_soctherm_root,
2952                                 NULL, &convert_fops);
2953         debugfs_create_file("cputemp", 0644, tegra_soctherm_root,
2954                                 NULL, &cputemp_fops);
2955         debugfs_create_file("gputemp", 0644, tegra_soctherm_root,
2956                                 NULL, &gputemp_fops);
2957         debugfs_create_file("memtemp", 0644, tegra_soctherm_root,
2958                                 NULL, &memtemp_fops);
2959         debugfs_create_file("plltemp", 0644, tegra_soctherm_root,
2960                                 NULL, &plltemp_fops);
2961         debugfs_create_file("tempoverride", 0644, tegra_soctherm_root,
2962                                 NULL, &tempoverride_fops);
2963         debugfs_create_file("temp_log", 0644, tegra_soctherm_root,
2964                                 NULL, &temp_log_fops);
2965         return 0;
2966 }
2967 late_initcall(soctherm_debug_init);
2968 #endif