2 * arch/arm/mach-tegra/tegra11_emc.h
4 * Copyright (C) 2011-2013 NVIDIA Corporation
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * You should have received a copy of the GNU General Public License along
16 * with this program; if not, write to the Free Software Foundation, Inc.,
17 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
21 #ifndef _MACH_TEGRA_TEGRA11_EMC_H
22 #define _MACH_TEGRA_TEGRA11_EMC_H
24 #include "tegra_emc.h"
26 int tegra11_emc_init(void);
30 DRAM_DEV_SEL_0 = (2 << 30),
31 DRAM_DEV_SEL_1 = (1 << 30),
33 #define DRAM_BROADCAST(num) \
34 (((num) > 1) ? DRAM_DEV_SEL_ALL : DRAM_DEV_SEL_0)
36 #define EMC_INTSTATUS 0x0
37 #define EMC_INTSTATUS_CLKCHANGE_COMPLETE (0x1 << 4)
40 #define EMC_DBG_WRITE_MUX_ACTIVE (0x1 << 1)
43 #define EMC_CFG_DRAM_ACPD (0x1 << 29)
44 #define EMC_CFG_DYN_SREF_ENABLE (0x1 << 28)
45 #define EMC_CFG_PWR_MASK (0xF << 28)
46 #define EMC_CFG_PERIODIC_QRST (0x1 << 21)
47 #define EMC_CFG_EN_DYNAMIC_PUTERM (0x1 << 20)
48 #define EMC_CFG_DLY_WR_DQ_HALF_CLOCK (0x1 << 19)
49 #define EMC_CFG_DSR_VTTGEN_DRV_EN (0x1 << 18)
50 #define EMC_CFG_EMC2PMACRO_CFG_BYPASS_DATAPIPE2 (0x1 << 3)
51 #define EMC_CFG_EMC2PMACRO_CFG_BYPASS_DATAPIPE1 (0x1 << 2)
52 #define EMC_CFG_EMC2PMACRO_CFG_BYPASS_ADDRPIPE (0x1 << 1)
53 #define EMC_CFG_UPDATE_MASK \
54 (EMC_CFG_EMC2PMACRO_CFG_BYPASS_ADDRPIPE | \
55 EMC_CFG_EMC2PMACRO_CFG_BYPASS_DATAPIPE1 | \
56 EMC_CFG_EMC2PMACRO_CFG_BYPASS_DATAPIPE2 | \
57 EMC_CFG_DSR_VTTGEN_DRV_EN | \
58 EMC_CFG_DLY_WR_DQ_HALF_CLOCK | \
59 EMC_CFG_EN_DYNAMIC_PUTERM | \
60 EMC_CFG_PERIODIC_QRST | \
63 #define EMC_REFCTRL 0x20
64 #define EMC_REFCTRL_DEV_SEL_SHIFT 0
65 #define EMC_REFCTRL_DEV_SEL_MASK \
66 (0x3 << EMC_REFCTRL_DEV_SEL_SHIFT)
67 #define EMC_REFCTRL_ENABLE (0x1 << 31)
68 #define EMC_REFCTRL_ENABLE_ALL(num) \
69 (((((num) > 1) ? 0 : 2) << EMC_REFCTRL_DEV_SEL_SHIFT) \
71 #define EMC_REFCTRL_DISABLE_ALL(num) \
72 ((((num) > 1) ? 0 : 2) << EMC_REFCTRL_DEV_SEL_SHIFT)
74 #define EMC_TIMING_CONTROL 0x28
83 #define EMC_RD_RCD 0x4c
84 #define EMC_WR_RCD 0x50
90 #define EMC_QSAFE 0x68
92 #define EMC_REFRESH 0x70
93 #define EMC_BURST_REFRESH_NUM 0x74
94 #define EMC_PDEX2WR 0x78
95 #define EMC_PDEX2RD 0x7c
96 #define EMC_PCHG2PDEN 0x80
97 #define EMC_ACT2PDEN 0x84
98 #define EMC_AR2PDEN 0x88
99 #define EMC_RW2PDEN 0x8c
100 #define EMC_TXSR 0x90
101 #define EMC_TCKE 0x94
102 #define EMC_TFAW 0x98
103 #define EMC_TRPAB 0x9c
104 #define EMC_TCLKSTABLE 0xa0
105 #define EMC_TCLKSTOP 0xa4
106 #define EMC_TREFBW 0xa8
107 #define EMC_QUSE_EXTRA 0xac
108 #define EMC_ODT_WRITE 0xb0
109 #define EMC_ODT_READ 0xb4
110 #define EMC_WEXT 0xb8
112 #define EMC_RFC_SLR 0xc0
113 #define EMC_MRS_WAIT_CNT2 0xc4
115 #define EMC_MRS_WAIT_CNT 0xc8
116 #define EMC_MRS_WAIT_CNT 0xc8
117 #define EMC_MRS_WAIT_CNT_SHORT_WAIT_SHIFT 0
118 #define EMC_MRS_WAIT_CNT_SHORT_WAIT_MASK \
119 (0x3FF << EMC_MRS_WAIT_CNT_SHORT_WAIT_SHIFT)
120 #define EMC_MRS_WAIT_CNT_LONG_WAIT_SHIFT 16
121 #define EMC_MRS_WAIT_CNT_LONG_WAIT_MASK \
122 (0x3FF << EMC_MRS_WAIT_CNT_LONG_WAIT_SHIFT)
125 #define EMC_MODE_SET_DLL_RESET (0x1 << 8)
126 #define EMC_MODE_SET_LONG_CNT (0x1 << 26)
127 #define EMC_EMRS 0xd0
129 #define EMC_REF_FORCE_CMD 1
133 #define EMC_SELF_REF 0xe0
134 #define EMC_SELF_REF_CMD_ENABLED (0x1 << 0)
135 #define EMC_SELF_REF_DEV_SEL_SHIFT 30
136 #define EMC_SELF_REF_DEV_SEL_MASK \
137 (0x3 << EMC_SELF_REF_DEV_SEL_SHIFT)
143 #define EMC_MRR_DEV_SEL_SHIFT 30
144 #define EMC_MRR_DEV_SEL_MASK \
145 (0x3 << EMC_SELF_REF_DEV_SEL_SHIFT)
146 #define EMC_MRR_MA_SHIFT 16
147 #define EMC_MRR_MA_MASK (0xFF << EMC_MRR_MA_SHIFT)
148 #define EMC_MRR_DATA_MASK ((0x1 << EMC_MRR_MA_SHIFT) - 1)
149 #define LPDDR2_MR4_TEMP_SHIFT 0
150 #define LPDDR2_MR4_TEMP_MASK (0x7 << LPDDR2_MR4_TEMP_SHIFT)
152 #define EMC_CMDQ 0xf0
153 #define EMC_MC2EMCQ 0xf4
154 #define EMC_XM2DQSPADCTRL3 0xf8
155 #define EMC_XM2DQSPADCTRL3_VREF_ENABLE (0x1 << 5)
156 #define EMC_FBIO_SPARE 0x100
158 #define EMC_FBIO_CFG5 0x104
159 #define EMC_CFG5_TYPE_SHIFT 0x0
160 #define EMC_CFG5_TYPE_MASK (0x3 << EMC_CFG5_TYPE_SHIFT)
163 DRAM_TYPE_LPDDR2 = 2,
165 #define EMC_CFG5_QUSE_MODE_SHIFT 13
166 #define EMC_CFG5_QUSE_MODE_MASK \
167 (0x7 << EMC_CFG5_QUSE_MODE_SHIFT)
169 EMC_CFG5_QUSE_MODE_NORMAL = 0,
170 EMC_CFG5_QUSE_MODE_ALWAYS_ON,
171 EMC_CFG5_QUSE_MODE_INTERNAL_LPBK,
172 EMC_CFG5_QUSE_MODE_PULSE_INTERN,
173 EMC_CFG5_QUSE_MODE_PULSE_EXTERN,
174 EMC_CFG5_QUSE_MODE_DIRECT_QUSE,
177 #define EMC_FBIO_WRPTR_EQ_2 0x108
178 #define EMC_FBIO_CFG6 0x114
179 #define EMC_CFG_RSV 0x120
180 #define EMC_ACPD_CONTROL 0x124
181 #define EMC_EMRS2 0x12c
182 #define EMC_EMRS3 0x130
183 #define EMC_MRW2 0x134
184 #define EMC_MRW3 0x138
185 #define EMC_MRW4 0x13c
186 #define EMC_CLKEN_OVERRIDE 0x140
187 #define EMC_R2R 0x144
188 #define EMC_W2W 0x148
189 #define EMC_EINPUT 0x14c
190 #define EMC_EINPUT_DURATION 0x150
191 #define EMC_PUTERM_EXTRA 0x154
192 #define EMC_TCKESR 0x158
193 #define EMC_TPD 0x15c
195 #define EMC_AUTO_CAL_CONFIG 0x2a4
196 #define EMC_AUTO_CAL_INTERVAL 0x2a8
197 #define EMC_AUTO_CAL_STATUS 0x2ac
198 #define EMC_AUTO_CAL_STATUS_ACTIVE (0x1 << 31)
199 #define EMC_REQ_CTRL 0x2b0
200 #define EMC_STATUS 0x2b4
201 #define EMC_STATUS_TIMING_UPDATE_STALLED (0x1 << 23)
202 #define EMC_STATUS_MRR_DIVLD (0x1 << 20)
204 #define EMC_CFG_2 0x2b8
205 #define EMC_CFG_2_MODE_SHIFT 0
206 #define EMC_CFG_2_MODE_MASK (0x3 << EMC_CFG_2_MODE_SHIFT)
207 #define EMC_CFG_2_SREF_MODE 0x1
208 #define EMC_CFG_2_PD_MODE 0x3
210 #define EMC_CFG_DIG_DLL 0x2bc
211 #define EMC_CFG_DIG_DLL_PERIOD 0x2c0
212 #define EMC_DIG_DLL_STATUS 0x2c8
213 #define EMC_RDV_MASK 0x2cc
214 #define EMC_WDV_MASK 0x2d0
215 #define EMC_CTT_DURATION 0x2d8
216 #define EMC_CTT_TERM_CTRL 0x2dc
217 #define EMC_ZCAL_INTERVAL 0x2e0
218 #define EMC_ZCAL_WAIT_CNT 0x2e4
219 #define EMC_ZCAL_MRW_CMD 0x2e8
221 #define EMC_ZQ_CAL 0x2ec
222 #define EMC_ZQ_CAL_DEV_SEL_SHIFT 30
223 #define EMC_ZQ_CAL_DEV_SEL_MASK \
224 (0x3 << EMC_SELF_REF_DEV_SEL_SHIFT)
225 #define EMC_ZQ_CAL_CMD (0x1 << 0)
226 #define EMC_ZQ_CAL_LONG (0x1 << 4)
227 #define EMC_ZQ_CAL_LONG_CMD_DEV0 \
228 (DRAM_DEV_SEL_0 | EMC_ZQ_CAL_LONG | EMC_ZQ_CAL_CMD)
229 #define EMC_ZQ_CAL_LONG_CMD_DEV1 \
230 (DRAM_DEV_SEL_1 | EMC_ZQ_CAL_LONG | EMC_ZQ_CAL_CMD)
232 #define EMC_XM2CMDPADCTRL 0x2f0
233 #define EMC_XM2CMDPADCTRL2 0x2f4
234 #define EMC_XM2DQSPADCTRL 0x2f8
235 #define EMC_XM2DQSPADCTRL2 0x2fc
236 #define EMC_XM2DQSPADCTRL2_VREF_ENABLE (0x1 << 5)
237 #define EMC_XM2DQPADCTRL 0x300
238 #define EMC_XM2DQPADCTRL2 0x304
239 #define EMC_XM2CLKPADCTRL 0x308
240 #define EMC_XM2COMPPADCTRL 0x30c
241 #define EMC_XM2COMPPADCTRL_VREF_CAL_ENABLE (0x1 << 10)
242 #define EMC_XM2VTTGENPADCTRL 0x310
243 #define EMC_XM2VTTGENPADCTRL2 0x314
244 #define EMC_EMCPADEN 0x31c
245 #define EMC_XM2DQSPADCTRL4 0x320
246 #define EMC_SCRATCH0 0x324
247 #define EMC_DLL_XFORM_DQS0 0x328
248 #define EMC_DLL_XFORM_DQS1 0x32c
249 #define EMC_DLL_XFORM_DQS2 0x330
250 #define EMC_DLL_XFORM_DQS3 0x334
251 #define EMC_DLL_XFORM_DQS4 0x338
252 #define EMC_DLL_XFORM_DQS5 0x33c
253 #define EMC_DLL_XFORM_DQS6 0x340
254 #define EMC_DLL_XFORM_DQS7 0x344
255 #define EMC_DLL_XFORM_QUSE0 0x348
256 #define EMC_DLL_XFORM_QUSE1 0x34c
257 #define EMC_DLL_XFORM_QUSE2 0x350
258 #define EMC_DLL_XFORM_QUSE3 0x354
259 #define EMC_DLL_XFORM_QUSE4 0x358
260 #define EMC_DLL_XFORM_QUSE5 0x35c
261 #define EMC_DLL_XFORM_QUSE6 0x360
262 #define EMC_DLL_XFORM_QUSE7 0x364
263 #define EMC_DLL_XFORM_DQ0 0x368
264 #define EMC_DLL_XFORM_DQ1 0x36c
265 #define EMC_DLL_XFORM_DQ2 0x370
266 #define EMC_DLL_XFORM_DQ3 0x374
267 #define EMC_DLI_RX_TRIM0 0x378
268 #define EMC_DLI_RX_TRIM1 0x37c
269 #define EMC_DLI_RX_TRIM2 0x380
270 #define EMC_DLI_RX_TRIM3 0x384
271 #define EMC_DLI_RX_TRIM4 0x388
272 #define EMC_DLI_RX_TRIM5 0x38c
273 #define EMC_DLI_RX_TRIM6 0x390
274 #define EMC_DLI_RX_TRIM7 0x394
275 #define EMC_DLI_TX_TRIM0 0x398
276 #define EMC_DLI_TX_TRIM1 0x39c
277 #define EMC_DLI_TX_TRIM2 0x3a0
278 #define EMC_DLI_TX_TRIM3 0x3a4
279 #define EMC_DLI_TRIM_TXDQS0 0x3a8
280 #define EMC_DLI_TRIM_TXDQS1 0x3ac
281 #define EMC_DLI_TRIM_TXDQS2 0x3b0
282 #define EMC_DLI_TRIM_TXDQS3 0x3b4
283 #define EMC_DLI_TRIM_TXDQS4 0x3b8
284 #define EMC_DLI_TRIM_TXDQS5 0x3bc
285 #define EMC_DLI_TRIM_TXDQS6 0x3c0
286 #define EMC_DLI_TRIM_TXDQS7 0x3c4
287 #define EMC_STALL_THEN_EXE_AFTER_CLKCHANGE 0x3cc
288 #define EMC_AUTO_CAL_CLK_STATUS 0x3d4
289 #define EMC_SEL_DPD_CTRL 0x3d8
290 #define EMC_SEL_DPD_CTRL_QUSE_DPD_ENABLE (0x1 << 9)
291 #define EMC_PRE_REFRESH_REQ_CNT 0x3dc
292 #define EMC_DYN_SELF_REF_CONTROL 0x3e0
293 #define EMC_TXSRDLL 0x3e4
294 #define EMC_CCFIFO_ADDR 0x3e8
295 #define EMC_CCFIFO_DATA 0x3ec
296 #define EMC_CCFIFO_STATUS 0x3f0
297 #define EMC_CDB_CNTL_1 0x3f4
298 #define EMC_CDB_CNTL_2 0x3f8
299 #define EMC_XM2CLKPADCTRL2 0x3fc
300 #define EMC_SWIZZLE_RANK0_BYTE_CFG 0x400
301 #define EMC_SWIZZLE_RANK0_BYTE0 0x404
302 #define EMC_SWIZZLE_RANK0_BYTE1 0x408
303 #define EMC_SWIZZLE_RANK0_BYTE2 0x40c
304 #define EMC_SWIZZLE_RANK0_BYTE3 0x410
305 #define EMC_SWIZZLE_RANK1_BYTE_CFG 0x414
306 #define EMC_SWIZZLE_RANK1_BYTE0 0x418
307 #define EMC_SWIZZLE_RANK1_BYTE1 0x41c
308 #define EMC_SWIZZLE_RANK1_BYTE2 0x420
309 #define EMC_SWIZZLE_RANK1_BYTE3 0x424
310 #define EMC_CA_TRAINING_START 0x428
311 #define EMC_CA_TRAINING_BUSY 0x42c
312 #define EMC_CA_TRAINING_CFG 0x430
313 #define EMC_CA_TRAINING_TIMING_CNTL1 0x434
314 #define EMC_CA_TRAINING_TIMING_CNTL2 0x438
315 #define EMC_CA_TRAINING_CA_LEAD_IN 0x43c
316 #define EMC_CA_TRAINING_CA 0x440
317 #define EMC_CA_TRAINING_CA_LEAD_OUT 0x444
318 #define EMC_CA_TRAINING_RESULT1 0x448
319 #define EMC_CA_TRAINING_RESULT2 0x44c
320 #define EMC_CA_TRAINING_RESULT3 0x450
321 #define EMC_CA_TRAINING_RESULT4 0x454
322 #define EMC_AUTO_CAL_CONFIG2 0x458
323 #define EMC_AUTO_CAL_CONFIG3 0x45c
324 #define EMC_AUTO_CAL_STATUS2 0x460
325 #define EMC_XM2CMDPADCTRL3 0x464
326 #define EMC_IBDLY 0x468
327 #define EMC_DLL_XFORM_ADDR0 0x46c
328 #define EMC_DLL_XFORM_ADDR1 0x470
329 #define EMC_DLL_XFORM_ADDR2 0x474
330 #define EMC_DLI_ADDR_TRIM 0x478
331 #define EMC_DSR_VTTGEN_DRV 0x47c
332 #define EMC_TXDSRVTTGEN 0x480
333 #define EMC_XM2CMDPADCTRL4 0x484
334 #define EMC_ADDR_SWIZZLE_STACK1A 0x488
335 #define EMC_ADDR_SWIZZLE_STACK1B 0x48c
336 #define EMC_ADDR_SWIZZLE_STACK2A 0x490
337 #define EMC_ADDR_SWIZZLE_STACK2B 0x494
338 #define EMC_ADDR_SWIZZLE_STACK3 0x498
340 #define MC_EMEM_ADR_CFG 0x54
342 #define MC_EMEM_ARB_CFG 0x90
343 #define MC_EMEM_ARB_OUTSTANDING_REQ 0x94
344 #define MC_EMEM_ARB_TIMING_RCD 0x98
345 #define MC_EMEM_ARB_TIMING_RP 0x9c
346 #define MC_EMEM_ARB_TIMING_RC 0xa0
347 #define MC_EMEM_ARB_TIMING_RAS 0xa4
348 #define MC_EMEM_ARB_TIMING_FAW 0xa8
349 #define MC_EMEM_ARB_TIMING_RRD 0xac
350 #define MC_EMEM_ARB_TIMING_RAP2PRE 0xb0
351 #define MC_EMEM_ARB_TIMING_WAP2PRE 0xb4
352 #define MC_EMEM_ARB_TIMING_R2R 0xb8
353 #define MC_EMEM_ARB_TIMING_W2W 0xbc
354 #define MC_EMEM_ARB_TIMING_R2W 0xc0
355 #define MC_EMEM_ARB_TIMING_W2R 0xc4
356 #define MC_EMEM_ARB_DA_TURNS 0xd0
357 #define MC_EMEM_ARB_DA_COVERS 0xd4
358 #define MC_EMEM_ARB_MISC0 0xd8
359 #define MC_EMEM_ARB_MISC0_EMC_SAME_FREQ (0x1 << 27)
360 #define MC_EMEM_ARB_MISC1 0xdc
361 #define MC_EMEM_ARB_RING1_THROTTLE 0xe0
362 #define MC_EMEM_ARB_RING3_THROTTLE 0xe4
363 #define MC_EMEM_ARB_OVERRIDE 0xe8
364 #define MC_EMEM_ARB_RSV 0xec
366 #define MC_TIMING_CONTROL 0xfc
368 #define MC_LATENCY_ALLOWANCE_AVPC_0 0x2e4
369 #define MC_LATENCY_ALLOWANCE_DC_0 0x2e8
370 #define MC_LATENCY_ALLOWANCE_DC_1 0x2ec
371 #define MC_LATENCY_ALLOWANCE_DC_2 0x2f0
372 #define MC_LATENCY_ALLOWANCE_DCB_0 0x2f4
373 #define MC_LATENCY_ALLOWANCE_DCB_1 0x2f8
374 #define MC_LATENCY_ALLOWANCE_DCB_2 0x2fc
375 #define MC_LATENCY_ALLOWANCE_EPP_0 0x300
376 #define MC_LATENCY_ALLOWANCE_EPP_1 0x304
377 #define MC_LATENCY_ALLOWANCE_G2_0 0x308
378 #define MC_LATENCY_ALLOWANCE_G2_1 0x30c
379 #define MC_LATENCY_ALLOWANCE_HC_0 0x310
380 #define MC_LATENCY_ALLOWANCE_HC_1 0x314
381 #define MC_LATENCY_ALLOWANCE_HDA_0 0x318
382 #define MC_LATENCY_ALLOWANCE_ISP_0 0x31c
383 #define MC_LATENCY_ALLOWANCE_MPCORE_0 0x320
384 #define MC_LATENCY_ALLOWANCE_MPCORELP_0 0x324
385 #define MC_LATENCY_ALLOWANCE_MSENC_0 0x328
386 #define MC_LATENCY_ALLOWANCE_NV_0 0x334
387 #define MC_LATENCY_ALLOWANCE_NV_1 0x338
388 #define MC_LATENCY_ALLOWANCE_NV2_0 0x33c
389 #define MC_LATENCY_ALLOWANCE_NV2_1 0x340
390 #define MC_LATENCY_ALLOWANCE_PPCS_0 0x344
391 #define MC_LATENCY_ALLOWANCE_PPCS_1 0x348
392 #define MC_LATENCY_ALLOWANCE_PTC_0 0x34c
393 #define MC_LATENCY_ALLOWANCE_VDE_0 0x354
394 #define MC_LATENCY_ALLOWANCE_VDE_1 0x358
395 #define MC_LATENCY_ALLOWANCE_VDE_2 0x35c
396 #define MC_LATENCY_ALLOWANCE_VDE_3 0x360
397 #define MC_LATENCY_ALLOWANCE_VI_0 0x364
398 #define MC_LATENCY_ALLOWANCE_VI_1 0x368
399 #define MC_LATENCY_ALLOWANCE_VI_2 0x36c
400 #define MC_LATENCY_ALLOWANCE_XUSB_0 0x37c
401 #define MC_LATENCY_ALLOWANCE_XUSB_1 0x380
402 #define MC_LATENCY_ALLOWANCE_NV_2 0x384
403 #define MC_LATENCY_ALLOWANCE_NV_3 0x388
404 #define MC_LATENCY_ALLOWANCE_EMUCIF_0 0x38c
405 #define MC_LATENCY_ALLOWANCE_TSEC_0 0x390
407 #define MC_RESERVED_RSV 0x3fc
409 #define MC_PTSA_GRANT_DECREMENT 0x960