ARM: tegra11: power: Add T40T core edp tables
[linux-3.10.git] / arch / arm / mach-tegra / tegra11_edp.c
1 /*
2  * arch/arm/mach-tegra/tegra11_edp.c
3  *
4  * Copyright (c) 2012-2013, NVIDIA CORPORATION. All rights reserved.
5  *
6  * This program is free software; you can redistribute it and/or modify it
7  * under the terms and conditions of the GNU General Public License,
8  * version 2, as published by the Free Software Foundation.
9  *
10  * This program is distributed in the hope it will be useful, but WITHOUT
11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13  * more details.
14  *
15  * You should have received a copy of the GNU General Public License
16  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
17  */
18
19 #include <linux/kernel.h>
20 #include <linux/init.h>
21 #include <linux/string.h>
22 #include <linux/module.h>
23 #include <linux/clk.h>
24 #include <linux/kobject.h>
25 #include <linux/err.h>
26
27 #include <mach/edp.h>
28
29 #include "clock.h"
30 #include "fuse.h"
31
32 #define CORE_MODULES_STATES 1
33 #define TEMPERATURE_RANGES 4
34 #define CAP_CLKS_NUM 2
35 #define TOTAL_CAPS (CORE_EDP_PROFILES_NUM * CORE_MODULES_STATES *\
36                         TEMPERATURE_RANGES * CAP_CLKS_NUM)
37
38 struct core_edp_entry {
39         int sku;
40         int process_id;
41         unsigned int cap_mA;
42         int mult;
43         unsigned long cap_scpu_on[CORE_EDP_PROFILES_NUM][
44                 CORE_MODULES_STATES][TEMPERATURE_RANGES][CAP_CLKS_NUM];
45         unsigned long cap_scpu_off[CORE_EDP_PROFILES_NUM][
46                 CORE_MODULES_STATES][TEMPERATURE_RANGES][CAP_CLKS_NUM];
47 };
48
49 static int temperatures[] = { 50, 70, 90, 105 };
50
51 #ifdef CONFIG_TEGRA_DUAL_CBUS
52 static char *cap_clks_names[] = { "edp.emc", "edp.c2bus" };
53 #else
54 static char *cap_clks_names[] = { "edp.emc", "edp.cbus" };
55 #endif
56 static struct clk *cap_clks[CAP_CLKS_NUM];
57
58 static struct core_edp_entry core_edp_table[] = {
59         /* SKU 3 */
60         {
61                 .sku            = 0x3,          /* SKU = 3 */
62                 .process_id     = -1,           /* any process id */
63                 .cap_mA         = 6000,         /* 6A cap */
64                 .mult           = 1000000,      /* MHZ */
65                 .cap_scpu_on    = {
66                         /* favor emc */
67                         {       /* core modules power state 0 (all ON) */
68                                 {{ 924, 636 },
69                                  { 924, 612 },
70                                  { 924, 564 },
71                                  { 924, 384 },
72                                 },
73                         },
74                         /* balanced profile */
75                         {       /* core modules power state 0 (all ON) */
76                                 {{ 792, 636 },
77                                  { 792, 636 },
78                                  { 792, 636 },
79                                  { 792, 384 },
80                                 },
81                         },
82                         /* favor gpu */
83                         {       /* core modules power state 0 (all ON) */
84                                 {{ 624, 672 },
85                                  { 624, 672 },
86                                  { 528, 672 },
87                                  { 528, 384 },
88                                 }
89                         },
90                 },
91                 .cap_scpu_off   = {
92                         /* favor emc */
93                         {       /* core modules power state 0 (all ON) */
94                                 {{ 924, 672 },
95                                  { 924, 648 },
96                                  { 924, 636 },
97                                  { 924, 516 },
98                                 },
99                         },
100                         /* balanced profile */
101                         {       /* core modules power state 0 (all ON) */
102                                 {{ 924, 672 },
103                                  { 792, 672 },
104                                  { 792, 672 },
105                                  { 792, 516 },
106                                 },
107                         },
108                         /* favor gpu */
109                         {       /* core modules power state 0 (all ON) */
110                                 {{ 924, 672 },
111                                  { 792, 672 },
112                                  { 792, 672 },
113                                  { 792, 516 },
114                                 }
115                         },
116                 },
117         },
118         {
119                 .sku            = 0x3,          /* SKU = 3 */
120                 .process_id     = -1,           /* any process id */
121                 .cap_mA         = 8000,         /* 8A cap */
122                 .mult           = 1000000,      /* MHZ */
123                 .cap_scpu_on    = {
124                         /* favor emc */
125                         {       /* core modules power state 0 (all ON) */
126                                 {{ 924, 672 },
127                                  { 924, 672 },
128                                  { 924, 672 },
129                                  { 924, 588 },
130                                 },
131                         },
132                         /* balanced profile */
133                         {       /* core modules power state 0 (all ON) */
134                                 {{ 924, 672 },
135                                  { 924, 672 },
136                                  { 924, 672 },
137                                  { 924, 588 },
138                                 },
139                         },
140                         /* favor gpu */
141                         {       /* core modules power state 0 (all ON) */
142                                 {{ 924, 672 },
143                                  { 924, 672 },
144                                  { 924, 672 },
145                                  { 924, 588 },
146                                 }
147                         },
148                 },
149                 .cap_scpu_off   = {
150                         /* favor emc */
151                         {       /* core modules power state 0 (all ON) */
152                                 {{ 924, 672 },
153                                  { 924, 672 },
154                                  { 924, 672 },
155                                  { 924, 588 },
156                                 },
157                         },
158                         /* balanced profile */
159                         {       /* core modules power state 0 (all ON) */
160                                 {{ 924, 672 },
161                                  { 924, 672 },
162                                  { 924, 672 },
163                                  { 924, 588 },
164                                 },
165                         },
166                         /* favor gpu */
167                         {       /* core modules power state 0 (all ON) */
168                                 {{ 924, 672 },
169                                  { 924, 672 },
170                                  { 924, 672 },
171                                  { 924, 588 },
172                                 }
173                         },
174                 },
175         },
176         /* SKU 4 */
177         {
178                 .sku            = 0x4,          /* SKU = 4 */
179                 .process_id     = -1,           /* any process id */
180                 .cap_mA         = 6000,         /* 6A cap */
181                 .mult           = 1000000,      /* MHZ */
182                 .cap_scpu_on    = {
183                         /* favor emc */
184                         {       /* core modules power state 0 (all ON) */
185                                 {{ 924, 636 },
186                                  { 924, 624 },
187                                  { 924, 588 },
188                                  { 924, 526 },
189                                 },
190                         },
191                         /* balanced profile */
192                         {       /* core modules power state 0 (all ON) */
193                                 {{ 792, 672 },
194                                  { 792, 636 },
195                                  { 792, 636 },
196                                  { 792, 576 },
197                                 },
198                         },
199                         /* favor gpu */
200                         {       /* core modules power state 0 (all ON) */
201                                 {{ 792, 672 },
202                                  { 624, 672 },
203                                  { 624, 672 },
204                                  { 624, 636 },
205                                 }
206                         },
207                 },
208                 .cap_scpu_off   = {
209                         /* favor emc */
210                         {       /* core modules power state 0 (all ON) */
211                                 {{ 924, 672 },
212                                  { 924, 660 },
213                                  { 924, 636 },
214                                  { 924, 588 },
215                                 },
216                         },
217                         /* balanced profile */
218                         {       /* core modules power state 0 (all ON) */
219                                 {{ 924, 672 },
220                                  { 792, 672 },
221                                  { 792, 672 },
222                                  { 792, 648 },
223                                 },
224                         },
225                         /* favor gpu */
226                         {       /* core modules power state 0 (all ON) */
227                                 {{ 924, 672 },
228                                  { 792, 672 },
229                                  { 792, 672 },
230                                  { 792, 648 },
231                                 }
232                         },
233                 },
234         },
235         {
236                 .sku            = 0x4,          /* SKU = 4 */
237                 .process_id     = -1,           /* any process id */
238                 .cap_mA         = 8000,         /* 8A cap */
239                 .mult           = 1000000,      /* MHZ */
240                 .cap_scpu_on    = {
241                         /* favor emc */
242                         {       /* core modules power state 0 (all ON) */
243                                 {{ 924, 672 },
244                                  { 924, 672 },
245                                  { 924, 672 },
246                                  { 924, 648 },
247                                 },
248                         },
249                         /* balanced profile */
250                         {       /* core modules power state 0 (all ON) */
251                                 {{ 924, 672 },
252                                  { 924, 672 },
253                                  { 924, 672 },
254                                  { 924, 648 },
255                                 },
256                         },
257                         /* favor gpu */
258                         {       /* core modules power state 0 (all ON) */
259                                 {{ 924, 672 },
260                                  { 924, 672 },
261                                  { 924, 672 },
262                                  { 924, 648 },
263                                 }
264                         },
265                 },
266                 .cap_scpu_off   = {
267                         /* favor emc */
268                         {       /* core modules power state 0 (all ON) */
269                                 {{ 924, 672 },
270                                  { 924, 672 },
271                                  { 924, 672 },
272                                  { 924, 648 },
273                                 },
274                         },
275                         /* balanced profile */
276                         {       /* core modules power state 0 (all ON) */
277                                 {{ 924, 672 },
278                                  { 924, 672 },
279                                  { 924, 672 },
280                                  { 924, 648 },
281                                 },
282                         },
283                         /* favor gpu */
284                         {       /* core modules power state 0 (all ON) */
285                                 {{ 924, 816 },
286                                  { 924, 816 },
287                                  { 924, 816 },
288                                  { 924, 648 },
289                                 }
290                         },
291                 },
292         },
293         /* SKU 5 */
294         {
295                 .sku            = 0x5,          /* SKU = 5 */
296                 .process_id     = 0,            /* bin 0 */
297                 .cap_mA         = 4000,         /* 4A cap */
298                 .mult           = 1000000,      /* MHZ */
299                 .cap_scpu_on    = {
300                         /* favor emc */
301                         {       /* core modules power state 0 (all ON) */
302                                 {{ 792, 336 },
303                                  { 792, 336 },
304                                  { 792, 300 },
305                                  { 792, 240 },
306                                 },
307                         },
308                         /* balanced profile */
309                         {       /* core modules power state 0 (all ON) */
310                                 {{ 624, 396 },
311                                  { 660, 372 },
312                                  { 660, 324 },
313                                  { 660, 288 },
314                                 },
315                         },
316                         /* favor gpu */
317                         {       /* core modules power state 0 (all ON) */
318                                 {{ 408, 492 },
319                                  { 408, 396 },
320                                  { 408, 396 },
321                                  { 408, 396 },
322                                 }
323                         },
324                 },
325                 .cap_scpu_off   = {
326                         /* favor emc */
327                         {       /* core modules power state 0 (all ON) */
328                                 {{ 792, 432 },
329                                  { 792, 432 },
330                                  { 792, 396 },
331                                  { 792, 348 },
332                                 },
333                         },
334                         /* balanced profile */
335                         {       /* core modules power state 0 (all ON) */
336                                 {{ 624, 492 },
337                                  { 660, 492 },
338                                  { 660, 444 },
339                                  { 660, 384 },
340                                 },
341                         },
342                         /* favor gpu */
343                         {       /* core modules power state 0 (all ON) */
344                                 {{ 408, 516 },
345                                  { 408, 516 },
346                                  { 408, 516 },
347                                  { 408, 492 },
348                                 }
349                         },
350                 },
351         },
352         {
353                 .sku            = 0x5,          /* SKU = 5 */
354                 .process_id     = 1,            /* bin 1 */
355                 .cap_mA         = 4000,         /* 4A cap */
356                 .mult           = 1000000,      /* MHZ */
357                 .cap_scpu_on    = {
358                         /* favor emc */
359                         {       /* core modules power state 0 (all ON) */
360                                 {{ 792, 348 },
361                                  { 792, 336 },
362                                  { 792, 300 },
363                                  { 792, 240 },
364                                 },
365                         },
366                         /* balanced profile */
367                         {       /* core modules power state 0 (all ON) */
368                                 {{ 624, 420 },
369                                  { 660, 372 },
370                                  { 660, 324 },
371                                  { 660, 288 },
372                                 },
373                         },
374                         /* favor gpu */
375                         {       /* core modules power state 0 (all ON) */
376                                 {{ 408, 528 },
377                                  { 408, 492 },
378                                  { 408, 420 },
379                                  { 408, 420 },
380                                 }
381                         },
382                 },
383                 .cap_scpu_off   = {
384                         /* favor emc */
385                         {       /* core modules power state 0 (all ON) */
386                                 {{ 792, 432 },
387                                  { 792, 432 },
388                                  { 792, 396 },
389                                  { 792, 348 },
390                                 },
391                         },
392                         /* balanced profile */
393                         {       /* core modules power state 0 (all ON) */
394                                 {{ 624, 528 },
395                                  { 660, 492 },
396                                  { 660, 444 },
397                                  { 660, 384 },
398                                 },
399                         },
400                         /* favor gpu */
401                         {       /* core modules power state 0 (all ON) */
402                                 {{ 408, 564 },
403                                  { 408, 564 },
404                                  { 408, 528 },
405                                  { 408, 528 },
406                                 }
407                         },
408                 },
409         },
410         {
411                 .sku            = 0x5,          /* SKU = 5 */
412                 .process_id     = -1,           /* any process id */
413                 .cap_mA         = 6000,         /* 6A cap */
414                 .mult           = 1000000,      /* MHZ */
415                 .cap_scpu_on    = {
416                         /* favor emc */
417                         {       /* core modules power state 0 (all ON) */
418                                 {{ 792, 600 },
419                                  { 792, 600 },
420                                  { 792, 600 },
421                                  { 792, 516 },
422                                 },
423                         },
424                         /* balanced profile */
425                         {       /* core modules power state 0 (all ON) */
426                                 {{ 792, 600 },
427                                  { 792, 600 },
428                                  { 660, 600 },
429                                  { 660, 564 },
430                                 },
431                         },
432                         /* favor gpu */
433                         {       /* core modules power state 0 (all ON) */
434                                 {{ 792, 600 },
435                                  { 792, 600 },
436                                  { 660, 600 },
437                                  { 528, 600 },
438                                 }
439                         },
440                 },
441                 .cap_scpu_off   = {
442                         /* favor emc */
443                         {       /* core modules power state 0 (all ON) */
444                                 {{ 792, 600 },
445                                  { 792, 600 },
446                                  { 792, 600 },
447                                  { 792, 600 },
448                                 },
449                         },
450                         /* balanced profile */
451                         {       /* core modules power state 0 (all ON) */
452                                 {{ 792, 600 },
453                                  { 792, 600 },
454                                  { 792, 600 },
455                                  { 624, 600 },
456                                 },
457                         },
458                         /* favor gpu */
459                         {       /* core modules power state 0 (all ON) */
460                                 {{ 792, 600 },
461                                  { 792, 600 },
462                                  { 792, 600 },
463                                  { 624, 600 },
464                                 }
465                         },
466                 },
467         },
468         /* SKU 6 */
469         {
470                 .sku            = 0x6,          /* SKU = 6 */
471                 .process_id     = 0,            /* bin 0 */
472                 .cap_mA         = 4000,         /* 4A cap */
473                 .mult           = 1000000,      /* MHZ */
474                 .cap_scpu_on    = {
475                         /* favor emc */
476                         {       /* core modules power state 0 (all ON) */
477                                 {{ 792, 348 },
478                                  { 792, 348 },
479                                  { 792, 312 },
480                                  { 792, 264 },
481                                 },
482                         },
483                         /* balanced profile */
484                         {       /* core modules power state 0 (all ON) */
485                                 {{ 660, 372 },
486                                  { 660, 372 },
487                                  { 660, 336 },
488                                  { 660, 300 },
489                                 },
490                         },
491                         /* favor gpu */
492                         {       /* core modules power state 0 (all ON) */
493                                 {{ 408, 492 },
494                                  { 408, 396 },
495                                  { 408, 396 },
496                                  { 408, 396 },
497                                 }
498                         },
499                 },
500                 .cap_scpu_off   = {
501                         /* favor emc */
502                         {       /* core modules power state 0 (all ON) */
503                                 {{ 792, 444 },
504                                  { 792, 444 },
505                                  { 792, 408 },
506                                  { 792, 372 },
507                                 },
508                         },
509                         /* balanced profile */
510                         {       /* core modules power state 0 (all ON) */
511                                 {{ 660, 492 },
512                                  { 660, 492 },
513                                  { 660, 456 },
514                                  { 660, 408 },
515                                 },
516                         },
517                         /* favor gpu */
518                         {       /* core modules power state 0 (all ON) */
519                                 {{ 408, 552 },
520                                  { 408, 516 },
521                                  { 408, 516 },
522                                  { 408, 516 },
523                                 }
524                         },
525                 },
526         },
527         {
528                 .sku            = 0x6,          /* SKU = 6 */
529                 .process_id     = 1,            /* bin 1 */
530                 .cap_mA         = 4000,         /* 4A cap */
531                 .mult           = 1000000,      /* MHZ */
532                 .cap_scpu_on    = {
533                         /* favor emc */
534                         {       /* core modules power state 0 (all ON) */
535                                 {{ 792, 348 },
536                                  { 792, 348 },
537                                  { 792, 312 },
538                                  { 792, 264 },
539                                 },
540                         },
541                         /* balanced profile */
542                         {       /* core modules power state 0 (all ON) */
543                                 {{ 660, 420 },
544                                  { 660, 372 },
545                                  { 660, 336 },
546                                  { 660, 300 },
547                                 },
548                         },
549                         /* favor gpu */
550                         {       /* core modules power state 0 (all ON) */
551                                 {{ 408, 528 },
552                                  { 408, 492 },
553                                  { 408, 420 },
554                                  { 408, 420 },
555                                 }
556                         },
557                 },
558                 .cap_scpu_off   = {
559                         /* favor emc */
560                         {       /* core modules power state 0 (all ON) */
561                                 {{ 792, 444 },
562                                  { 792, 444 },
563                                  { 792, 408 },
564                                  { 792, 372 },
565                                 },
566                         },
567                         /* balanced profile */
568                         {       /* core modules power state 0 (all ON) */
569                                 {{ 660, 492 },
570                                  { 660, 492 },
571                                  { 660, 456 },
572                                  { 660, 408 },
573                                 },
574                         },
575                         /* favor gpu */
576                         {       /* core modules power state 0 (all ON) */
577                                 {{ 408, 564 },
578                                  { 408, 564 },
579                                  { 408, 564 },
580                                  { 408, 528 },
581                                 }
582                         },
583                 },
584         },
585         {
586                 .sku            = 0x6,          /* SKU = 6 */
587                 .process_id     = -1,           /* any process id */
588                 .cap_mA         = 6000,         /* 6A cap */
589                 .mult           = 1000000,      /* MHZ */
590                 .cap_scpu_on    = {
591                         /* favor emc */
592                         {       /* core modules power state 0 (all ON) */
593                                 {{ 792, 600 },
594                                  { 792, 600 },
595                                  { 792, 600 },
596                                  { 792, 516 },
597                                 },
598                         },
599                         /* balanced profile */
600                         {       /* core modules power state 0 (all ON) */
601                                 {{ 792, 600 },
602                                  { 792, 600 },
603                                  { 792, 600 },
604                                  { 660, 600 },
605                                 },
606                         },
607                         /* favor gpu */
608                         {       /* core modules power state 0 (all ON) */
609                                 {{ 792, 600 },
610                                  { 792, 600 },
611                                  { 792, 600 },
612                                  { 660, 600 },
613                                 }
614                         },
615                 },
616                 .cap_scpu_off   = {
617                         /* favor emc */
618                         {       /* core modules power state 0 (all ON) */
619                                 {{ 792, 600 },
620                                  { 792, 600 },
621                                  { 792, 600 },
622                                  { 792, 600 },
623                                 },
624                         },
625                         /* balanced profile */
626                         {       /* core modules power state 0 (all ON) */
627                                 {{ 792, 600 },
628                                  { 792, 600 },
629                                  { 792, 600 },
630                                  { 792, 600 },
631                                 },
632                         },
633                         /* favor gpu */
634                         {       /* core modules power state 0 (all ON) */
635                                 {{ 792, 600 },
636                                  { 792, 600 },
637                                  { 792, 600 },
638                                  { 792, 600 },
639                                 }
640                         },
641                 },
642         },
643 };
644
645 #ifdef CONFIG_TEGRA_EDP_LIMITS
646 #define LEAKAGE_CONSTS_IJK_COMMON                                       \
647         {                                                               \
648                 /* i = 0 */                                             \
649                 { {   13919916,  -28721837,   7560552,  -570495, },     \
650                   {  -39991855,   87294629, -22972570,  1734058, },     \
651                   {   36869935,  -86826110,  22833611, -1723750, },     \
652                   {  -10611796,   28192235,  -7407903,   559012, },     \
653                 },                                                      \
654                 /* i = 1 */                                             \
655                 { {  -37335213,   53397584, -16025243,  1341064, },     \
656                   {  111121782, -160756323,  48421377, -4049609, },     \
657                   { -107149149,  157911131, -47786861,  3994796, },     \
658                   {   32802647,  -49872380,  15236453, -1268662, },     \
659                 },                                                      \
660                 /* i = 2 */                                             \
661                 { {    3315214,  -21010655,   7718286,  -789185, },     \
662                   {   -4336249,   59786076, -22312653,  2313754, },     \
663                   {   -3346058,  -54529998,  20777469, -2198700, },     \
664                   {    4810027,   15417133,  -6086955,   665766, },     \
665                 },                                                      \
666                 /* i = 3 */                                             \
667                 { {    4681958,   -1470999,   -232691,    73384, },     \
668                   {  -15445149,    5487248,    422447,  -201475, },     \
669                   {   16983482,   -6716242,    -65917,   174128, },     \
670                   {   -6293336,    2756799,   -140100,   -44673, },     \
671                 },                                                      \
672         }
673
674 #define LEAKAGE_PARAMS_COMMON_PART                                      \
675         .temp_scaled        = 10,                                       \
676         .dyn_scaled         = 1000000,                                  \
677         .dyn_consts_n       = { 1410000, 2440000, 3450000, 4440000 },   \
678         .consts_scaled      = 1000000,                                  \
679         .leakage_consts_n   = {  400000,  650000,  850000, 1050000 },   \
680         .ijk_scaled         = 10000,                                    \
681         .leakage_min        = 30,                                       \
682         .volt_temp_cap      = { 70, 1300 },                             \
683         .leakage_consts_ijk = LEAKAGE_CONSTS_IJK_COMMON
684
685 static struct tegra_edp_cpu_leakage_params t11x_leakage_params[] = {
686         {
687                 .cpu_speedo_id      = 0, /* A01 CPU */
688                 .max_current_cap = { /* values are from tegra4 datasheet */
689                         { .max_cur = 9000, .max_temp = 60,
690                                 { 1900000, 1900000, 1600000, 1600000 }
691                         },
692                         { .max_cur = 9000, .max_temp = 75,
693                                 { 1900000, 1900000, 1530000, 1530000 }
694                         },
695                         { .max_cur = 9000, .max_temp = 90,
696                                 { 1900000, 1900000, 1500000, 1500000 }
697                         },
698                         { .max_cur = 12000, .max_temp = 90,
699                                 { 1900000, 1900000, 1700000, 1700000 }
700                         },
701                         { .max_cur = 15000, .max_temp = 90,
702                                 { 1900000, 1900000, 1900000, 1900000 }
703                         },
704                 },
705                 LEAKAGE_PARAMS_COMMON_PART,
706         },
707         {
708                 .cpu_speedo_id      = 1, /* A01P+ CPU */
709                 .safety_cap         = { 1810500, 1810500, 1606500, 1606500 },
710                 .max_current_cap = { /* values are from tegra4 datasheet */
711                         { .max_cur = 7500, .max_temp = 90,
712                                 { 1800000, 1700000, 1320000, 1320000 }
713                         },
714                         { .max_cur = 7500, .max_temp = 75,
715                                 { 1800000, 1700000, 1420000, 1420000 }
716                         },
717                         { .max_cur = 7500, .max_temp = 60,
718                                 { 1800000, 1800000, 1420000, 1420000 }
719                         },
720                         { .max_cur = 7500, .max_temp = 45,
721                                 { 1800000, 1800000, 1530000, 1530000 }
722                         },
723                         { .max_cur = 9000, .max_temp = 90,
724                                 { 1800000, 1800000, 1500000, 1500000 }
725                         },
726                         { .max_cur = 9000, .max_temp = 75,
727                                 { 1800000, 1800000, 1530000, 1530000 }
728                         },
729                         { .max_cur = 9000, .max_temp = 60,
730                                 { 1800000, 1800000, 1600000, 1600000 }
731                         },
732                         { .max_cur = 12000, .max_temp = 45,
733                                 { 1800000, 1800000, 1600000, 1600000 }
734                         },
735                 },
736                 LEAKAGE_PARAMS_COMMON_PART,
737         },
738         {
739                 .cpu_speedo_id      = 2, /* A01P+ fast CPU */
740                 .safety_cap         = { 1912500, 1912500, 1912500, 1912500 },
741                 .max_current_cap = { /* values are from tegra4 datasheet */
742                         { .max_cur = 9000, .max_temp = 90,
743                                 { 1900000, 1900000, 1500000, 1500000 }
744                         },
745                         { .max_cur = 9000, .max_temp = 75,
746                                 { 1900000, 1900000, 1530000, 1530000 }
747                         },
748                         { .max_cur = 9000, .max_temp = 60,
749                                 { 1900000, 1900000, 1600000, 1600000 }
750                         },
751                         { .max_cur = 12000, .max_temp = 90,
752                                 { 1900000, 1900000, 1700000, 1700000 }
753                         },
754                         { .max_cur = 15000, .max_temp = 90,
755                                 { 1900000, 1900000, 1900000, 1900000 }
756                         },
757                 },
758                 LEAKAGE_PARAMS_COMMON_PART,
759         },
760 };
761
762 struct tegra_edp_cpu_leakage_params *tegra11x_get_leakage_params(int index,
763                                                         unsigned int *sz)
764 {
765         BUG_ON(index >= ARRAY_SIZE(t11x_leakage_params));
766         if (sz)
767                 *sz = ARRAY_SIZE(t11x_leakage_params);
768         return &t11x_leakage_params[index];
769 }
770 #endif
771
772 static struct core_edp_entry *find_edp_entry(int sku, unsigned int regulator_mA)
773 {
774         int i;
775         int pid = tegra_core_process_id();
776
777         if ((sku == 0x5) || (sku == 0x6)) {
778                 if (regulator_mA >= 8000)
779                         return NULL;            /* no edp limits above 8A */
780         } else if ((sku == 0x3) || (sku == 0x4)) {
781                 if (regulator_mA >= 8000)
782                         regulator_mA = 8000;    /* apply 8A table above 8A */
783         } else {
784                 return NULL;                    /* no edp limits at all */
785         }
786
787         for (i = 0; i < ARRAY_SIZE(core_edp_table); i++) {
788                 struct core_edp_entry *entry = &core_edp_table[i];
789                 if ((entry->sku == sku) && (entry->cap_mA == regulator_mA) &&
790                     ((entry->process_id == -1) || (entry->process_id == pid)))
791                         return entry;
792         }
793         return ERR_PTR(-ENOENT);
794 }
795
796 static unsigned long clip_cap_rate(struct clk *cap_clk, unsigned long rate)
797 {
798         unsigned long floor, ceiling;
799         struct clk *p = clk_get_parent(cap_clk);
800
801         if (!p || !p->ops || !p->ops->shared_bus_update) {
802                 WARN(1, "%s: edp cap clk %s is not a shared bus user\n",
803                         __func__, cap_clk->name);
804                 return rate;
805         }
806
807         /*
808          * Clip cap rate to shared bus possible rates (going up via shared
809          * bus * ladder since bus clocks always rounds up with resolution of
810          * at least 2kHz)
811          */
812         ceiling = clk_round_rate(p, clk_get_min_rate(p));
813         do {
814                 floor = ceiling;
815                 ceiling = clk_round_rate(p, floor + 2000);
816                 if (IS_ERR_VALUE(ceiling)) {
817                         pr_err("%s: failed to clip %lu to %s possible rates\n",
818                                __func__, rate, p->name);
819                         return rate;
820                 }
821         } while ((floor < ceiling) && (ceiling <= rate));
822
823         if (floor > rate)
824                 WARN(1, "%s: %s cap rate %lu is below %s floor %lu\n",
825                         __func__, cap_clk->name, rate, p->name, floor);
826         return floor;
827 }
828
829 int __init tegra11x_select_core_edp_table(unsigned int regulator_mA,
830                                           struct tegra_core_edp_limits *limits)
831 {
832         int i;
833         int sku = tegra_sku_id;
834         unsigned long *cap_rates;
835         struct core_edp_entry *edp_entry;
836
837         BUG_ON(ARRAY_SIZE(temperatures) != TEMPERATURE_RANGES);
838         BUG_ON(ARRAY_SIZE(cap_clks_names) != CAP_CLKS_NUM);
839         for (i = 0; i < CAP_CLKS_NUM; i++) {
840                 struct clk *c = tegra_get_clock_by_name(cap_clks_names[i]);
841                 if (!c) {
842                         pr_err("%s: failed to find edp cap clock %s\n",
843                                __func__, cap_clks_names[i]);
844                         return -ENODEV;
845                 }
846                 cap_clks[i] = c;
847         }
848
849         edp_entry = find_edp_entry(sku, regulator_mA);
850         if (!edp_entry) {
851                 pr_info("%s: no core edp table for sku %d, %d mA\n",
852                        __func__, sku, regulator_mA);
853                 return -ENODATA;
854         } else if (IS_ERR(edp_entry)) {
855                 WARN(1, "%s: missing core edp table for sku %d, %d mA\n",
856                        __func__, sku, regulator_mA);
857                 return PTR_ERR(edp_entry);
858         }
859
860         limits->sku = sku;
861         limits->cap_clocks = cap_clks;
862         limits->cap_clocks_num = CAP_CLKS_NUM;
863         limits->temperatures = temperatures;
864         limits->temperature_ranges = TEMPERATURE_RANGES;
865         limits->core_modules_states = CORE_MODULES_STATES;
866
867         cap_rates = &edp_entry->cap_scpu_on[0][0][0][0];
868         limits->cap_rates_scpu_on = cap_rates;
869         for (i = 0; i < TOTAL_CAPS; i++, cap_rates++) {
870                 unsigned long rate = *cap_rates * edp_entry->mult;
871                 *cap_rates = clip_cap_rate(cap_clks[i % CAP_CLKS_NUM], rate);
872         }
873
874         cap_rates = &edp_entry->cap_scpu_off[0][0][0][0];
875         limits->cap_rates_scpu_off = cap_rates;
876         for (i = 0; i < TOTAL_CAPS; i++, cap_rates++) {
877                 unsigned long rate = *cap_rates * edp_entry->mult;
878                 *cap_rates = clip_cap_rate(cap_clks[i % CAP_CLKS_NUM], rate);
879         }
880
881         return 0;
882 }