arm: tegra: update edp parameters init for t11x
[linux-3.10.git] / arch / arm / mach-tegra / tegra11_edp.c
1 /*
2  * arch/arm/mach-tegra/tegra11_edp.c
3  *
4  * Copyright (c) 2012-2013, NVIDIA CORPORATION. All rights reserved.
5  *
6  * This program is free software; you can redistribute it and/or modify it
7  * under the terms and conditions of the GNU General Public License,
8  * version 2, as published by the Free Software Foundation.
9  *
10  * This program is distributed in the hope it will be useful, but WITHOUT
11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13  * more details.
14  *
15  * You should have received a copy of the GNU General Public License
16  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
17  */
18
19 #include <linux/kernel.h>
20 #include <linux/init.h>
21 #include <linux/string.h>
22 #include <linux/module.h>
23 #include <linux/clk.h>
24 #include <linux/kobject.h>
25 #include <linux/err.h>
26
27 #include <mach/edp.h>
28
29 #include "clock.h"
30 #include "fuse.h"
31
32 #define CORE_MODULES_STATES 1
33 #define TEMPERATURE_RANGES 4
34 #define CAP_CLKS_NUM 2
35 #define TOTAL_CAPS (CORE_EDP_PROFILES_NUM * CORE_MODULES_STATES *\
36                         TEMPERATURE_RANGES * CAP_CLKS_NUM)
37
38 struct core_edp_entry {
39         int sku;
40         unsigned int cap_mA;
41         int mult;
42         unsigned long cap_scpu_on[CORE_EDP_PROFILES_NUM][
43                 CORE_MODULES_STATES][TEMPERATURE_RANGES][CAP_CLKS_NUM];
44         unsigned long cap_scpu_off[CORE_EDP_PROFILES_NUM][
45                 CORE_MODULES_STATES][TEMPERATURE_RANGES][CAP_CLKS_NUM];
46 };
47
48 static int temperatures[] = { 50, 70, 90, 105 };
49
50 #ifdef CONFIG_TEGRA_DUAL_CBUS
51 static char *cap_clks_names[] = { "edp.emc", "edp.c2bus" };
52 #else
53 static char *cap_clks_names[] = { "edp.emc", "edp.cbus" };
54 #endif
55 static struct clk *cap_clks[CAP_CLKS_NUM];
56
57 static struct core_edp_entry core_edp_table[] = {
58         {
59                 .sku            = 0x3,          /* SKU = 4 - T40X */
60                 .cap_mA         = 6000,         /* 6A cap */
61                 .mult           = 1000000,      /* MHZ */
62                 .cap_scpu_on    = {
63                         /* favor emc */
64                         {       /* core modules power state 0 (all ON) */
65                                 {{ 924, 636 },
66                                  { 924, 612 },
67                                  { 924, 564 },
68                                  { 924, 480 },
69                                 },
70                         },
71                         /* balanced profile */
72                         {       /* core modules power state 0 (all ON) */
73                                 {{ 792, 636 },
74                                  { 792, 636 },
75                                  { 792, 636 },
76                                  { 792, 552 },
77                                 },
78                         },
79                         /* favor gpu */
80                         {       /* core modules power state 0 (all ON) */
81                                 {{ 624, 672 },
82                                  { 624, 672 },
83                                  { 528, 672 },
84                                  { 408, 672 },
85                                 }
86                         },
87                 },
88                 .cap_scpu_off   = {
89                         /* favor emc */
90                         {       /* core modules power state 0 (all ON) */
91                                 {{1066, 700 },
92                                  { 924, 648 },
93                                  { 924, 636 },
94                                  { 924, 588 },
95                                 },
96                         },
97                         /* balanced profile */
98                         {       /* core modules power state 0 (all ON) */
99                                 {{1066, 700 },
100                                  { 792, 672 },
101                                  { 792, 672 },
102                                  { 792, 624 },
103                                 },
104                         },
105                         /* favor gpu */
106                         {       /* core modules power state 0 (all ON) */
107                                 {{1066, 700 },
108                                  { 792, 672 },
109                                  { 792, 672 },
110                                  { 624, 672 },
111                                 }
112                         },
113                 },
114         },
115 };
116
117 #ifdef CONFIG_TEGRA_EDP_LIMITS
118 #define LEAKAGE_CONSTS_IJK_COMMON                                       \
119         {                                                               \
120                 /* i = 0 */                                             \
121                 { {   13919916,  -28721837,   7560552,  -570495, },     \
122                   {  -39991855,   87294629, -22972570,  1734058, },     \
123                   {   36869935,  -86826110,  22833611, -1723750, },     \
124                   {  -10611796,   28192235,  -7407903,   559012, },     \
125                 },                                                      \
126                 /* i = 1 */                                             \
127                 { {  -37335213,   53397584, -16025243,  1341064, },     \
128                   {  111121782, -160756323,  48421377, -4049609, },     \
129                   { -107149149,  157911131, -47786861,  3994796, },     \
130                   {   32802647,  -49872380,  15236453, -1268662, },     \
131                 },                                                      \
132                 /* i = 2 */                                             \
133                 { {    3315214,  -21010655,   7718286,  -789185, },     \
134                   {   -4336249,   59786076, -22312653,  2313754, },     \
135                   {   -3346058,  -54529998,  20777469, -2198700, },     \
136                   {    4810027,   15417133,  -6086955,   665766, },     \
137                 },                                                      \
138                 /* i = 3 */                                             \
139                 { {    4681958,   -1470999,   -232691,    73384, },     \
140                   {  -15445149,    5487248,    422447,  -201475, },     \
141                   {   16983482,   -6716242,    -65917,   174128, },     \
142                   {   -6293336,    2756799,   -140100,   -44673, },     \
143                 },                                                      \
144         }
145
146 #define LEAKAGE_PARAMS_COMMON_PART                                      \
147         .temp_scaled        = 10,                                       \
148         .dyn_scaled         = 1000000,                                  \
149         .dyn_consts_n       = { 1410000, 2440000, 3450000, 4440000 },   \
150         .consts_scaled      = 1000000,                                  \
151         .leakage_consts_n   = {  400000,  650000,  850000, 1050000 },   \
152         .ijk_scaled         = 10000,                                    \
153         .leakage_min        = 30,                                       \
154         .volt_temp_cap      = { 70, 1300 },                             \
155         .leakage_consts_ijk = LEAKAGE_CONSTS_IJK_COMMON
156
157 static struct tegra_edp_cpu_leakage_params t11x_leakage_params[] = {
158         {
159                 .cpu_speedo_id      = 0, /* A01 CPU */
160                 LEAKAGE_PARAMS_COMMON_PART,
161         },
162         {
163                 .cpu_speedo_id      = 1, /* A01P+ CPU */
164                 .safety_cap         = { 1810500, 1810500, 1606500, 1606500 },
165                 LEAKAGE_PARAMS_COMMON_PART,
166         },
167         {
168                 .cpu_speedo_id      = 2, /* A01P+ fast CPU */
169                 .safety_cap         = { 1912500, 1912500, 1912500, 1912500 },
170                 LEAKAGE_PARAMS_COMMON_PART,
171         },
172 };
173
174 struct tegra_edp_cpu_leakage_params *tegra11x_get_leakage_params(int index,
175                                                         unsigned int *sz)
176 {
177         BUG_ON(index >= ARRAY_SIZE(t11x_leakage_params));
178         if (sz)
179                 *sz = ARRAY_SIZE(t11x_leakage_params);
180         return &t11x_leakage_params[index];
181 }
182 #endif
183
184 static struct core_edp_entry *find_edp_entry(int sku, unsigned int regulator_mA)
185 {
186         int i;
187
188         for (i = 0; i < ARRAY_SIZE(core_edp_table); i++) {
189                 struct core_edp_entry *entry = &core_edp_table[i];
190                 if ((entry->sku == sku) && (entry->cap_mA == regulator_mA))
191                         return entry;
192         }
193         return NULL;
194 }
195
196 static unsigned long clip_cap_rate(struct clk *cap_clk, unsigned long rate)
197 {
198         unsigned long floor, ceiling;
199         struct clk *p = clk_get_parent(cap_clk);
200
201         if (!p || !p->ops || !p->ops->shared_bus_update) {
202                 WARN(1, "%s: edp cap clk %s is not a shared bus user\n",
203                         __func__, cap_clk->name);
204                 return rate;
205         }
206
207         /*
208          * Clip cap rate to shared bus possible rates (going up via shared
209          * bus * ladder since bus clocks always rounds up with resolution of
210          * at least 2kHz)
211          */
212         ceiling = clk_round_rate(p, clk_get_min_rate(p));
213         do {
214                 floor = ceiling;
215                 ceiling = clk_round_rate(p, floor + 2000);
216                 if (IS_ERR_VALUE(ceiling)) {
217                         pr_err("%s: failed to clip %lu to %s possible rates\n",
218                                __func__, rate, p->name);
219                         return rate;
220                 }
221         } while ((floor < ceiling) && (ceiling <= rate));
222
223         if (floor > rate)
224                 WARN(1, "%s: %s cap rate %lu is below %s floor %lu\n",
225                         __func__, cap_clk->name, rate, p->name, floor);
226         return floor;
227 }
228
229 int __init tegra11x_select_core_edp_table(unsigned int regulator_mA,
230                                           struct tegra_core_edp_limits *limits)
231 {
232         int i;
233         int sku = tegra_sku_id;
234         unsigned long *cap_rates;
235         struct core_edp_entry *edp_entry;
236
237         BUG_ON(ARRAY_SIZE(temperatures) != TEMPERATURE_RANGES);
238         BUG_ON(ARRAY_SIZE(cap_clks_names) != CAP_CLKS_NUM);
239         for (i = 0; i < CAP_CLKS_NUM; i++) {
240                 struct clk *c = tegra_get_clock_by_name(cap_clks_names[i]);
241                 if (!c) {
242                         pr_err("%s: failed to find edp cap clock %s\n",
243                                __func__, cap_clks_names[i]);
244                         return -ENODEV;
245                 }
246                 cap_clks[i] = c;
247         }
248
249         edp_entry = find_edp_entry(sku, regulator_mA);
250         if (!edp_entry) {
251                 pr_info("%s: no core edp table for sku %d, %d mA\n",
252                        __func__, sku, regulator_mA);
253                 return -ENODATA;
254         }
255
256         limits->sku = sku;
257         limits->cap_clocks = cap_clks;
258         limits->cap_clocks_num = CAP_CLKS_NUM;
259         limits->temperatures = temperatures;
260         limits->temperature_ranges = TEMPERATURE_RANGES;
261         limits->core_modules_states = CORE_MODULES_STATES;
262
263         cap_rates = &edp_entry->cap_scpu_on[0][0][0][0];
264         limits->cap_rates_scpu_on = cap_rates;
265         for (i = 0; i < TOTAL_CAPS; i++, cap_rates++) {
266                 unsigned long rate = *cap_rates * edp_entry->mult;
267                 *cap_rates = clip_cap_rate(cap_clks[i % CAP_CLKS_NUM], rate);
268         }
269
270         cap_rates = &edp_entry->cap_scpu_off[0][0][0][0];
271         limits->cap_rates_scpu_off = cap_rates;
272         for (i = 0; i < TOTAL_CAPS; i++, cap_rates++) {
273                 unsigned long rate = *cap_rates * edp_entry->mult;
274                 *cap_rates = clip_cap_rate(cap_clks[i % CAP_CLKS_NUM], rate);
275         }
276
277         return 0;
278 }