ARM: tegra11: power: Use process id to select core edp table
[linux-3.10.git] / arch / arm / mach-tegra / tegra11_edp.c
1 /*
2  * arch/arm/mach-tegra/tegra11_edp.c
3  *
4  * Copyright (c) 2012-2013, NVIDIA CORPORATION. All rights reserved.
5  *
6  * This program is free software; you can redistribute it and/or modify it
7  * under the terms and conditions of the GNU General Public License,
8  * version 2, as published by the Free Software Foundation.
9  *
10  * This program is distributed in the hope it will be useful, but WITHOUT
11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13  * more details.
14  *
15  * You should have received a copy of the GNU General Public License
16  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
17  */
18
19 #include <linux/kernel.h>
20 #include <linux/init.h>
21 #include <linux/string.h>
22 #include <linux/module.h>
23 #include <linux/clk.h>
24 #include <linux/kobject.h>
25 #include <linux/err.h>
26
27 #include <mach/edp.h>
28
29 #include "clock.h"
30 #include "fuse.h"
31
32 #define CORE_MODULES_STATES 1
33 #define TEMPERATURE_RANGES 4
34 #define CAP_CLKS_NUM 2
35 #define TOTAL_CAPS (CORE_EDP_PROFILES_NUM * CORE_MODULES_STATES *\
36                         TEMPERATURE_RANGES * CAP_CLKS_NUM)
37
38 struct core_edp_entry {
39         int sku;
40         int process_id;
41         unsigned int cap_mA;
42         int mult;
43         unsigned long cap_scpu_on[CORE_EDP_PROFILES_NUM][
44                 CORE_MODULES_STATES][TEMPERATURE_RANGES][CAP_CLKS_NUM];
45         unsigned long cap_scpu_off[CORE_EDP_PROFILES_NUM][
46                 CORE_MODULES_STATES][TEMPERATURE_RANGES][CAP_CLKS_NUM];
47 };
48
49 static int temperatures[] = { 50, 70, 90, 105 };
50
51 #ifdef CONFIG_TEGRA_DUAL_CBUS
52 static char *cap_clks_names[] = { "edp.emc", "edp.c2bus" };
53 #else
54 static char *cap_clks_names[] = { "edp.emc", "edp.cbus" };
55 #endif
56 static struct clk *cap_clks[CAP_CLKS_NUM];
57
58 static struct core_edp_entry core_edp_table[] = {
59         {
60                 .sku            = 0x3,          /* SKU = 3 - T40X */
61                 .process_id     = -1,           /* any process id */
62                 .cap_mA         = 6000,         /* 6A cap */
63                 .mult           = 1000000,      /* MHZ */
64                 .cap_scpu_on    = {
65                         /* favor emc */
66                         {       /* core modules power state 0 (all ON) */
67                                 {{ 924, 636 },
68                                  { 924, 612 },
69                                  { 924, 564 },
70                                  { 924, 480 },
71                                 },
72                         },
73                         /* balanced profile */
74                         {       /* core modules power state 0 (all ON) */
75                                 {{ 792, 636 },
76                                  { 792, 636 },
77                                  { 792, 636 },
78                                  { 792, 552 },
79                                 },
80                         },
81                         /* favor gpu */
82                         {       /* core modules power state 0 (all ON) */
83                                 {{ 624, 672 },
84                                  { 624, 672 },
85                                  { 528, 672 },
86                                  { 408, 672 },
87                                 }
88                         },
89                 },
90                 .cap_scpu_off   = {
91                         /* favor emc */
92                         {       /* core modules power state 0 (all ON) */
93                                 {{1066, 700 },
94                                  { 924, 648 },
95                                  { 924, 636 },
96                                  { 924, 588 },
97                                 },
98                         },
99                         /* balanced profile */
100                         {       /* core modules power state 0 (all ON) */
101                                 {{1066, 700 },
102                                  { 792, 672 },
103                                  { 792, 672 },
104                                  { 792, 624 },
105                                 },
106                         },
107                         /* favor gpu */
108                         {       /* core modules power state 0 (all ON) */
109                                 {{1066, 700 },
110                                  { 792, 672 },
111                                  { 792, 672 },
112                                  { 624, 672 },
113                                 }
114                         },
115                 },
116         },
117 };
118
119 #ifdef CONFIG_TEGRA_EDP_LIMITS
120 #define LEAKAGE_CONSTS_IJK_COMMON                                       \
121         {                                                               \
122                 /* i = 0 */                                             \
123                 { {   13919916,  -28721837,   7560552,  -570495, },     \
124                   {  -39991855,   87294629, -22972570,  1734058, },     \
125                   {   36869935,  -86826110,  22833611, -1723750, },     \
126                   {  -10611796,   28192235,  -7407903,   559012, },     \
127                 },                                                      \
128                 /* i = 1 */                                             \
129                 { {  -37335213,   53397584, -16025243,  1341064, },     \
130                   {  111121782, -160756323,  48421377, -4049609, },     \
131                   { -107149149,  157911131, -47786861,  3994796, },     \
132                   {   32802647,  -49872380,  15236453, -1268662, },     \
133                 },                                                      \
134                 /* i = 2 */                                             \
135                 { {    3315214,  -21010655,   7718286,  -789185, },     \
136                   {   -4336249,   59786076, -22312653,  2313754, },     \
137                   {   -3346058,  -54529998,  20777469, -2198700, },     \
138                   {    4810027,   15417133,  -6086955,   665766, },     \
139                 },                                                      \
140                 /* i = 3 */                                             \
141                 { {    4681958,   -1470999,   -232691,    73384, },     \
142                   {  -15445149,    5487248,    422447,  -201475, },     \
143                   {   16983482,   -6716242,    -65917,   174128, },     \
144                   {   -6293336,    2756799,   -140100,   -44673, },     \
145                 },                                                      \
146         }
147
148 #define LEAKAGE_PARAMS_COMMON_PART                                      \
149         .temp_scaled        = 10,                                       \
150         .dyn_scaled         = 1000000,                                  \
151         .dyn_consts_n       = { 1410000, 2440000, 3450000, 4440000 },   \
152         .consts_scaled      = 1000000,                                  \
153         .leakage_consts_n   = {  400000,  650000,  850000, 1050000 },   \
154         .ijk_scaled         = 10000,                                    \
155         .leakage_min        = 30,                                       \
156         .volt_temp_cap      = { 70, 1300 },                             \
157         .leakage_consts_ijk = LEAKAGE_CONSTS_IJK_COMMON
158
159 static struct tegra_edp_cpu_leakage_params t11x_leakage_params[] = {
160         {
161                 .cpu_speedo_id      = 0, /* A01 CPU */
162                 .max_current_cap = { /* values are from tegra4 datasheet */
163                         { .max_cur = 9000, .max_temp = 60,
164                                 { 1900000, 1900000, 1600000, 1600000 }
165                         },
166                         { .max_cur = 9000, .max_temp = 75,
167                                 { 1900000, 1900000, 1530000, 1530000 }
168                         },
169                         { .max_cur = 9000, .max_temp = 90,
170                                 { 1900000, 1900000, 1500000, 1500000 }
171                         },
172                         { .max_cur = 12000, .max_temp = 90,
173                                 { 1900000, 1900000, 1700000, 1700000 }
174                         },
175                         { .max_cur = 15000, .max_temp = 90,
176                                 { 1900000, 1900000, 1900000, 1900000 }
177                         },
178                 },
179                 LEAKAGE_PARAMS_COMMON_PART,
180         },
181         {
182                 .cpu_speedo_id      = 1, /* A01P+ CPU */
183                 .safety_cap         = { 1810500, 1810500, 1606500, 1606500 },
184                 .max_current_cap = { /* values are from tegra4 datasheet */
185                         { .max_cur = 7500, .max_temp = 90,
186                                 { 1800000, 1700000, 1320000, 1320000 }
187                         },
188                         { .max_cur = 7500, .max_temp = 75,
189                                 { 1800000, 1700000, 1420000, 1420000 }
190                         },
191                         { .max_cur = 7500, .max_temp = 60,
192                                 { 1800000, 1800000, 1420000, 1420000 }
193                         },
194                         { .max_cur = 7500, .max_temp = 45,
195                                 { 1800000, 1800000, 1530000, 1530000 }
196                         },
197                         { .max_cur = 9000, .max_temp = 90,
198                                 { 1800000, 1800000, 1500000, 1500000 }
199                         },
200                         { .max_cur = 9000, .max_temp = 75,
201                                 { 1800000, 1800000, 1530000, 1530000 }
202                         },
203                         { .max_cur = 9000, .max_temp = 60,
204                                 { 1800000, 1800000, 1600000, 1600000 }
205                         },
206                         { .max_cur = 12000, .max_temp = 45,
207                                 { 1800000, 1800000, 1600000, 1600000 }
208                         },
209                 },
210                 LEAKAGE_PARAMS_COMMON_PART,
211         },
212         {
213                 .cpu_speedo_id      = 2, /* A01P+ fast CPU */
214                 .safety_cap         = { 1912500, 1912500, 1912500, 1912500 },
215                 .max_current_cap = { /* values are from tegra4 datasheet */
216                         { .max_cur = 9000, .max_temp = 90,
217                                 { 1900000, 1900000, 1500000, 1500000 }
218                         },
219                         { .max_cur = 9000, .max_temp = 75,
220                                 { 1900000, 1900000, 1530000, 1530000 }
221                         },
222                         { .max_cur = 9000, .max_temp = 60,
223                                 { 1900000, 1900000, 1600000, 1600000 }
224                         },
225                         { .max_cur = 12000, .max_temp = 90,
226                                 { 1900000, 1900000, 1700000, 1700000 }
227                         },
228                         { .max_cur = 15000, .max_temp = 90,
229                                 { 1900000, 1900000, 1900000, 1900000 }
230                         },
231                 },
232                 LEAKAGE_PARAMS_COMMON_PART,
233         },
234 };
235
236 struct tegra_edp_cpu_leakage_params *tegra11x_get_leakage_params(int index,
237                                                         unsigned int *sz)
238 {
239         BUG_ON(index >= ARRAY_SIZE(t11x_leakage_params));
240         if (sz)
241                 *sz = ARRAY_SIZE(t11x_leakage_params);
242         return &t11x_leakage_params[index];
243 }
244 #endif
245
246 static struct core_edp_entry *find_edp_entry(int sku, unsigned int regulator_mA)
247 {
248         int i;
249         int pid = tegra_core_process_id();
250
251         for (i = 0; i < ARRAY_SIZE(core_edp_table); i++) {
252                 struct core_edp_entry *entry = &core_edp_table[i];
253                 if ((entry->sku == sku) && (entry->cap_mA == regulator_mA) &&
254                     ((entry->process_id == -1) || (entry->process_id == pid)))
255                         return entry;
256         }
257         return NULL;
258 }
259
260 static unsigned long clip_cap_rate(struct clk *cap_clk, unsigned long rate)
261 {
262         unsigned long floor, ceiling;
263         struct clk *p = clk_get_parent(cap_clk);
264
265         if (!p || !p->ops || !p->ops->shared_bus_update) {
266                 WARN(1, "%s: edp cap clk %s is not a shared bus user\n",
267                         __func__, cap_clk->name);
268                 return rate;
269         }
270
271         /*
272          * Clip cap rate to shared bus possible rates (going up via shared
273          * bus * ladder since bus clocks always rounds up with resolution of
274          * at least 2kHz)
275          */
276         ceiling = clk_round_rate(p, clk_get_min_rate(p));
277         do {
278                 floor = ceiling;
279                 ceiling = clk_round_rate(p, floor + 2000);
280                 if (IS_ERR_VALUE(ceiling)) {
281                         pr_err("%s: failed to clip %lu to %s possible rates\n",
282                                __func__, rate, p->name);
283                         return rate;
284                 }
285         } while ((floor < ceiling) && (ceiling <= rate));
286
287         if (floor > rate)
288                 WARN(1, "%s: %s cap rate %lu is below %s floor %lu\n",
289                         __func__, cap_clk->name, rate, p->name, floor);
290         return floor;
291 }
292
293 int __init tegra11x_select_core_edp_table(unsigned int regulator_mA,
294                                           struct tegra_core_edp_limits *limits)
295 {
296         int i;
297         int sku = tegra_sku_id;
298         unsigned long *cap_rates;
299         struct core_edp_entry *edp_entry;
300
301         BUG_ON(ARRAY_SIZE(temperatures) != TEMPERATURE_RANGES);
302         BUG_ON(ARRAY_SIZE(cap_clks_names) != CAP_CLKS_NUM);
303         for (i = 0; i < CAP_CLKS_NUM; i++) {
304                 struct clk *c = tegra_get_clock_by_name(cap_clks_names[i]);
305                 if (!c) {
306                         pr_err("%s: failed to find edp cap clock %s\n",
307                                __func__, cap_clks_names[i]);
308                         return -ENODEV;
309                 }
310                 cap_clks[i] = c;
311         }
312
313         edp_entry = find_edp_entry(sku, regulator_mA);
314         if (!edp_entry) {
315                 pr_info("%s: no core edp table for sku %d, %d mA\n",
316                        __func__, sku, regulator_mA);
317                 return -ENODATA;
318         }
319
320         limits->sku = sku;
321         limits->cap_clocks = cap_clks;
322         limits->cap_clocks_num = CAP_CLKS_NUM;
323         limits->temperatures = temperatures;
324         limits->temperature_ranges = TEMPERATURE_RANGES;
325         limits->core_modules_states = CORE_MODULES_STATES;
326
327         cap_rates = &edp_entry->cap_scpu_on[0][0][0][0];
328         limits->cap_rates_scpu_on = cap_rates;
329         for (i = 0; i < TOTAL_CAPS; i++, cap_rates++) {
330                 unsigned long rate = *cap_rates * edp_entry->mult;
331                 *cap_rates = clip_cap_rate(cap_clks[i % CAP_CLKS_NUM], rate);
332         }
333
334         cap_rates = &edp_entry->cap_scpu_off[0][0][0][0];
335         limits->cap_rates_scpu_off = cap_rates;
336         for (i = 0; i < TOTAL_CAPS; i++, cap_rates++) {
337                 unsigned long rate = *cap_rates * edp_entry->mult;
338                 *cap_rates = clip_cap_rate(cap_clks[i % CAP_CLKS_NUM], rate);
339         }
340
341         return 0;
342 }