ARM: tegra11: power: Add T40S core edp tables
[linux-3.10.git] / arch / arm / mach-tegra / tegra11_edp.c
1 /*
2  * arch/arm/mach-tegra/tegra11_edp.c
3  *
4  * Copyright (c) 2012-2013, NVIDIA CORPORATION. All rights reserved.
5  *
6  * This program is free software; you can redistribute it and/or modify it
7  * under the terms and conditions of the GNU General Public License,
8  * version 2, as published by the Free Software Foundation.
9  *
10  * This program is distributed in the hope it will be useful, but WITHOUT
11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13  * more details.
14  *
15  * You should have received a copy of the GNU General Public License
16  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
17  */
18
19 #include <linux/kernel.h>
20 #include <linux/init.h>
21 #include <linux/string.h>
22 #include <linux/module.h>
23 #include <linux/clk.h>
24 #include <linux/kobject.h>
25 #include <linux/err.h>
26
27 #include <mach/edp.h>
28
29 #include "clock.h"
30 #include "fuse.h"
31
32 #define CORE_MODULES_STATES 1
33 #define TEMPERATURE_RANGES 4
34 #define CAP_CLKS_NUM 2
35 #define TOTAL_CAPS (CORE_EDP_PROFILES_NUM * CORE_MODULES_STATES *\
36                         TEMPERATURE_RANGES * CAP_CLKS_NUM)
37
38 struct core_edp_entry {
39         int sku;
40         int process_id;
41         unsigned int cap_mA;
42         int mult;
43         unsigned long cap_scpu_on[CORE_EDP_PROFILES_NUM][
44                 CORE_MODULES_STATES][TEMPERATURE_RANGES][CAP_CLKS_NUM];
45         unsigned long cap_scpu_off[CORE_EDP_PROFILES_NUM][
46                 CORE_MODULES_STATES][TEMPERATURE_RANGES][CAP_CLKS_NUM];
47 };
48
49 static int temperatures[] = { 50, 70, 90, 105 };
50
51 #ifdef CONFIG_TEGRA_DUAL_CBUS
52 static char *cap_clks_names[] = { "edp.emc", "edp.c2bus" };
53 #else
54 static char *cap_clks_names[] = { "edp.emc", "edp.cbus" };
55 #endif
56 static struct clk *cap_clks[CAP_CLKS_NUM];
57
58 static struct core_edp_entry core_edp_table[] = {
59         /* SKU 3 */
60         {
61                 .sku            = 0x3,          /* SKU = 3 */
62                 .process_id     = -1,           /* any process id */
63                 .cap_mA         = 6000,         /* 6A cap */
64                 .mult           = 1000000,      /* MHZ */
65                 .cap_scpu_on    = {
66                         /* favor emc */
67                         {       /* core modules power state 0 (all ON) */
68                                 {{ 924, 636 },
69                                  { 924, 612 },
70                                  { 924, 564 },
71                                  { 924, 384 },
72                                 },
73                         },
74                         /* balanced profile */
75                         {       /* core modules power state 0 (all ON) */
76                                 {{ 792, 636 },
77                                  { 792, 636 },
78                                  { 792, 636 },
79                                  { 792, 384 },
80                                 },
81                         },
82                         /* favor gpu */
83                         {       /* core modules power state 0 (all ON) */
84                                 {{ 624, 672 },
85                                  { 624, 672 },
86                                  { 528, 672 },
87                                  { 528, 384 },
88                                 }
89                         },
90                 },
91                 .cap_scpu_off   = {
92                         /* favor emc */
93                         {       /* core modules power state 0 (all ON) */
94                                 {{ 924, 672 },
95                                  { 924, 648 },
96                                  { 924, 636 },
97                                  { 924, 516 },
98                                 },
99                         },
100                         /* balanced profile */
101                         {       /* core modules power state 0 (all ON) */
102                                 {{ 924, 672 },
103                                  { 792, 672 },
104                                  { 792, 672 },
105                                  { 792, 516 },
106                                 },
107                         },
108                         /* favor gpu */
109                         {       /* core modules power state 0 (all ON) */
110                                 {{ 924, 672 },
111                                  { 792, 672 },
112                                  { 792, 672 },
113                                  { 792, 516 },
114                                 }
115                         },
116                 },
117         },
118         {
119                 .sku            = 0x3,          /* SKU = 3 */
120                 .process_id     = -1,           /* any process id */
121                 .cap_mA         = 8000,         /* 8A cap */
122                 .mult           = 1000000,      /* MHZ */
123                 .cap_scpu_on    = {
124                         /* favor emc */
125                         {       /* core modules power state 0 (all ON) */
126                                 {{ 924, 672 },
127                                  { 924, 672 },
128                                  { 924, 672 },
129                                  { 924, 588 },
130                                 },
131                         },
132                         /* balanced profile */
133                         {       /* core modules power state 0 (all ON) */
134                                 {{ 924, 672 },
135                                  { 924, 672 },
136                                  { 924, 672 },
137                                  { 924, 588 },
138                                 },
139                         },
140                         /* favor gpu */
141                         {       /* core modules power state 0 (all ON) */
142                                 {{ 924, 672 },
143                                  { 924, 672 },
144                                  { 924, 672 },
145                                  { 924, 588 },
146                                 }
147                         },
148                 },
149                 .cap_scpu_off   = {
150                         /* favor emc */
151                         {       /* core modules power state 0 (all ON) */
152                                 {{ 924, 672 },
153                                  { 924, 672 },
154                                  { 924, 672 },
155                                  { 924, 588 },
156                                 },
157                         },
158                         /* balanced profile */
159                         {       /* core modules power state 0 (all ON) */
160                                 {{ 924, 672 },
161                                  { 924, 672 },
162                                  { 924, 672 },
163                                  { 924, 588 },
164                                 },
165                         },
166                         /* favor gpu */
167                         {       /* core modules power state 0 (all ON) */
168                                 {{ 924, 672 },
169                                  { 924, 672 },
170                                  { 924, 672 },
171                                  { 924, 588 },
172                                 }
173                         },
174                 },
175         },
176         /* SKU 5 */
177         {
178                 .sku            = 0x5,          /* SKU = 5 */
179                 .process_id     = 0,            /* bin 0 */
180                 .cap_mA         = 4000,         /* 4A cap */
181                 .mult           = 1000000,      /* MHZ */
182                 .cap_scpu_on    = {
183                         /* favor emc */
184                         {       /* core modules power state 0 (all ON) */
185                                 {{ 792, 336 },
186                                  { 792, 336 },
187                                  { 792, 300 },
188                                  { 792, 240 },
189                                 },
190                         },
191                         /* balanced profile */
192                         {       /* core modules power state 0 (all ON) */
193                                 {{ 624, 396 },
194                                  { 660, 372 },
195                                  { 660, 324 },
196                                  { 660, 288 },
197                                 },
198                         },
199                         /* favor gpu */
200                         {       /* core modules power state 0 (all ON) */
201                                 {{ 408, 492 },
202                                  { 408, 396 },
203                                  { 408, 396 },
204                                  { 408, 396 },
205                                 }
206                         },
207                 },
208                 .cap_scpu_off   = {
209                         /* favor emc */
210                         {       /* core modules power state 0 (all ON) */
211                                 {{ 792, 432 },
212                                  { 792, 432 },
213                                  { 792, 396 },
214                                  { 792, 348 },
215                                 },
216                         },
217                         /* balanced profile */
218                         {       /* core modules power state 0 (all ON) */
219                                 {{ 624, 492 },
220                                  { 660, 492 },
221                                  { 660, 444 },
222                                  { 660, 384 },
223                                 },
224                         },
225                         /* favor gpu */
226                         {       /* core modules power state 0 (all ON) */
227                                 {{ 408, 516 },
228                                  { 408, 516 },
229                                  { 408, 516 },
230                                  { 408, 492 },
231                                 }
232                         },
233                 },
234         },
235         {
236                 .sku            = 0x5,          /* SKU = 5 */
237                 .process_id     = 1,            /* bin 1 */
238                 .cap_mA         = 4000,         /* 4A cap */
239                 .mult           = 1000000,      /* MHZ */
240                 .cap_scpu_on    = {
241                         /* favor emc */
242                         {       /* core modules power state 0 (all ON) */
243                                 {{ 792, 348 },
244                                  { 792, 336 },
245                                  { 792, 300 },
246                                  { 792, 240 },
247                                 },
248                         },
249                         /* balanced profile */
250                         {       /* core modules power state 0 (all ON) */
251                                 {{ 624, 420 },
252                                  { 660, 372 },
253                                  { 660, 324 },
254                                  { 660, 288 },
255                                 },
256                         },
257                         /* favor gpu */
258                         {       /* core modules power state 0 (all ON) */
259                                 {{ 408, 528 },
260                                  { 408, 492 },
261                                  { 408, 420 },
262                                  { 408, 420 },
263                                 }
264                         },
265                 },
266                 .cap_scpu_off   = {
267                         /* favor emc */
268                         {       /* core modules power state 0 (all ON) */
269                                 {{ 792, 432 },
270                                  { 792, 432 },
271                                  { 792, 396 },
272                                  { 792, 348 },
273                                 },
274                         },
275                         /* balanced profile */
276                         {       /* core modules power state 0 (all ON) */
277                                 {{ 624, 528 },
278                                  { 660, 492 },
279                                  { 660, 444 },
280                                  { 660, 384 },
281                                 },
282                         },
283                         /* favor gpu */
284                         {       /* core modules power state 0 (all ON) */
285                                 {{ 408, 564 },
286                                  { 408, 564 },
287                                  { 408, 528 },
288                                  { 408, 528 },
289                                 }
290                         },
291                 },
292         },
293         {
294                 .sku            = 0x5,          /* SKU = 5 */
295                 .process_id     = -1,           /* any process id */
296                 .cap_mA         = 6000,         /* 6A cap */
297                 .mult           = 1000000,      /* MHZ */
298                 .cap_scpu_on    = {
299                         /* favor emc */
300                         {       /* core modules power state 0 (all ON) */
301                                 {{ 792, 600 },
302                                  { 792, 600 },
303                                  { 792, 600 },
304                                  { 792, 516 },
305                                 },
306                         },
307                         /* balanced profile */
308                         {       /* core modules power state 0 (all ON) */
309                                 {{ 792, 600 },
310                                  { 792, 600 },
311                                  { 660, 600 },
312                                  { 660, 564 },
313                                 },
314                         },
315                         /* favor gpu */
316                         {       /* core modules power state 0 (all ON) */
317                                 {{ 792, 600 },
318                                  { 792, 600 },
319                                  { 660, 600 },
320                                  { 528, 600 },
321                                 }
322                         },
323                 },
324                 .cap_scpu_off   = {
325                         /* favor emc */
326                         {       /* core modules power state 0 (all ON) */
327                                 {{ 792, 600 },
328                                  { 792, 600 },
329                                  { 792, 600 },
330                                  { 792, 600 },
331                                 },
332                         },
333                         /* balanced profile */
334                         {       /* core modules power state 0 (all ON) */
335                                 {{ 792, 600 },
336                                  { 792, 600 },
337                                  { 792, 600 },
338                                  { 624, 600 },
339                                 },
340                         },
341                         /* favor gpu */
342                         {       /* core modules power state 0 (all ON) */
343                                 {{ 792, 600 },
344                                  { 792, 600 },
345                                  { 792, 600 },
346                                  { 624, 600 },
347                                 }
348                         },
349                 },
350         },
351 };
352
353 #ifdef CONFIG_TEGRA_EDP_LIMITS
354 #define LEAKAGE_CONSTS_IJK_COMMON                                       \
355         {                                                               \
356                 /* i = 0 */                                             \
357                 { {   13919916,  -28721837,   7560552,  -570495, },     \
358                   {  -39991855,   87294629, -22972570,  1734058, },     \
359                   {   36869935,  -86826110,  22833611, -1723750, },     \
360                   {  -10611796,   28192235,  -7407903,   559012, },     \
361                 },                                                      \
362                 /* i = 1 */                                             \
363                 { {  -37335213,   53397584, -16025243,  1341064, },     \
364                   {  111121782, -160756323,  48421377, -4049609, },     \
365                   { -107149149,  157911131, -47786861,  3994796, },     \
366                   {   32802647,  -49872380,  15236453, -1268662, },     \
367                 },                                                      \
368                 /* i = 2 */                                             \
369                 { {    3315214,  -21010655,   7718286,  -789185, },     \
370                   {   -4336249,   59786076, -22312653,  2313754, },     \
371                   {   -3346058,  -54529998,  20777469, -2198700, },     \
372                   {    4810027,   15417133,  -6086955,   665766, },     \
373                 },                                                      \
374                 /* i = 3 */                                             \
375                 { {    4681958,   -1470999,   -232691,    73384, },     \
376                   {  -15445149,    5487248,    422447,  -201475, },     \
377                   {   16983482,   -6716242,    -65917,   174128, },     \
378                   {   -6293336,    2756799,   -140100,   -44673, },     \
379                 },                                                      \
380         }
381
382 #define LEAKAGE_PARAMS_COMMON_PART                                      \
383         .temp_scaled        = 10,                                       \
384         .dyn_scaled         = 1000000,                                  \
385         .dyn_consts_n       = { 1410000, 2440000, 3450000, 4440000 },   \
386         .consts_scaled      = 1000000,                                  \
387         .leakage_consts_n   = {  400000,  650000,  850000, 1050000 },   \
388         .ijk_scaled         = 10000,                                    \
389         .leakage_min        = 30,                                       \
390         .volt_temp_cap      = { 70, 1300 },                             \
391         .leakage_consts_ijk = LEAKAGE_CONSTS_IJK_COMMON
392
393 static struct tegra_edp_cpu_leakage_params t11x_leakage_params[] = {
394         {
395                 .cpu_speedo_id      = 0, /* A01 CPU */
396                 .max_current_cap = { /* values are from tegra4 datasheet */
397                         { .max_cur = 9000, .max_temp = 60,
398                                 { 1900000, 1900000, 1600000, 1600000 }
399                         },
400                         { .max_cur = 9000, .max_temp = 75,
401                                 { 1900000, 1900000, 1530000, 1530000 }
402                         },
403                         { .max_cur = 9000, .max_temp = 90,
404                                 { 1900000, 1900000, 1500000, 1500000 }
405                         },
406                         { .max_cur = 12000, .max_temp = 90,
407                                 { 1900000, 1900000, 1700000, 1700000 }
408                         },
409                         { .max_cur = 15000, .max_temp = 90,
410                                 { 1900000, 1900000, 1900000, 1900000 }
411                         },
412                 },
413                 LEAKAGE_PARAMS_COMMON_PART,
414         },
415         {
416                 .cpu_speedo_id      = 1, /* A01P+ CPU */
417                 .safety_cap         = { 1810500, 1810500, 1606500, 1606500 },
418                 .max_current_cap = { /* values are from tegra4 datasheet */
419                         { .max_cur = 7500, .max_temp = 90,
420                                 { 1800000, 1700000, 1320000, 1320000 }
421                         },
422                         { .max_cur = 7500, .max_temp = 75,
423                                 { 1800000, 1700000, 1420000, 1420000 }
424                         },
425                         { .max_cur = 7500, .max_temp = 60,
426                                 { 1800000, 1800000, 1420000, 1420000 }
427                         },
428                         { .max_cur = 7500, .max_temp = 45,
429                                 { 1800000, 1800000, 1530000, 1530000 }
430                         },
431                         { .max_cur = 9000, .max_temp = 90,
432                                 { 1800000, 1800000, 1500000, 1500000 }
433                         },
434                         { .max_cur = 9000, .max_temp = 75,
435                                 { 1800000, 1800000, 1530000, 1530000 }
436                         },
437                         { .max_cur = 9000, .max_temp = 60,
438                                 { 1800000, 1800000, 1600000, 1600000 }
439                         },
440                         { .max_cur = 12000, .max_temp = 45,
441                                 { 1800000, 1800000, 1600000, 1600000 }
442                         },
443                 },
444                 LEAKAGE_PARAMS_COMMON_PART,
445         },
446         {
447                 .cpu_speedo_id      = 2, /* A01P+ fast CPU */
448                 .safety_cap         = { 1912500, 1912500, 1912500, 1912500 },
449                 .max_current_cap = { /* values are from tegra4 datasheet */
450                         { .max_cur = 9000, .max_temp = 90,
451                                 { 1900000, 1900000, 1500000, 1500000 }
452                         },
453                         { .max_cur = 9000, .max_temp = 75,
454                                 { 1900000, 1900000, 1530000, 1530000 }
455                         },
456                         { .max_cur = 9000, .max_temp = 60,
457                                 { 1900000, 1900000, 1600000, 1600000 }
458                         },
459                         { .max_cur = 12000, .max_temp = 90,
460                                 { 1900000, 1900000, 1700000, 1700000 }
461                         },
462                         { .max_cur = 15000, .max_temp = 90,
463                                 { 1900000, 1900000, 1900000, 1900000 }
464                         },
465                 },
466                 LEAKAGE_PARAMS_COMMON_PART,
467         },
468 };
469
470 struct tegra_edp_cpu_leakage_params *tegra11x_get_leakage_params(int index,
471                                                         unsigned int *sz)
472 {
473         BUG_ON(index >= ARRAY_SIZE(t11x_leakage_params));
474         if (sz)
475                 *sz = ARRAY_SIZE(t11x_leakage_params);
476         return &t11x_leakage_params[index];
477 }
478 #endif
479
480 static struct core_edp_entry *find_edp_entry(int sku, unsigned int regulator_mA)
481 {
482         int i;
483         int pid = tegra_core_process_id();
484
485         for (i = 0; i < ARRAY_SIZE(core_edp_table); i++) {
486                 struct core_edp_entry *entry = &core_edp_table[i];
487                 if ((entry->sku == sku) && (entry->cap_mA == regulator_mA) &&
488                     ((entry->process_id == -1) || (entry->process_id == pid)))
489                         return entry;
490         }
491         return NULL;
492 }
493
494 static unsigned long clip_cap_rate(struct clk *cap_clk, unsigned long rate)
495 {
496         unsigned long floor, ceiling;
497         struct clk *p = clk_get_parent(cap_clk);
498
499         if (!p || !p->ops || !p->ops->shared_bus_update) {
500                 WARN(1, "%s: edp cap clk %s is not a shared bus user\n",
501                         __func__, cap_clk->name);
502                 return rate;
503         }
504
505         /*
506          * Clip cap rate to shared bus possible rates (going up via shared
507          * bus * ladder since bus clocks always rounds up with resolution of
508          * at least 2kHz)
509          */
510         ceiling = clk_round_rate(p, clk_get_min_rate(p));
511         do {
512                 floor = ceiling;
513                 ceiling = clk_round_rate(p, floor + 2000);
514                 if (IS_ERR_VALUE(ceiling)) {
515                         pr_err("%s: failed to clip %lu to %s possible rates\n",
516                                __func__, rate, p->name);
517                         return rate;
518                 }
519         } while ((floor < ceiling) && (ceiling <= rate));
520
521         if (floor > rate)
522                 WARN(1, "%s: %s cap rate %lu is below %s floor %lu\n",
523                         __func__, cap_clk->name, rate, p->name, floor);
524         return floor;
525 }
526
527 int __init tegra11x_select_core_edp_table(unsigned int regulator_mA,
528                                           struct tegra_core_edp_limits *limits)
529 {
530         int i;
531         int sku = tegra_sku_id;
532         unsigned long *cap_rates;
533         struct core_edp_entry *edp_entry;
534
535         BUG_ON(ARRAY_SIZE(temperatures) != TEMPERATURE_RANGES);
536         BUG_ON(ARRAY_SIZE(cap_clks_names) != CAP_CLKS_NUM);
537         for (i = 0; i < CAP_CLKS_NUM; i++) {
538                 struct clk *c = tegra_get_clock_by_name(cap_clks_names[i]);
539                 if (!c) {
540                         pr_err("%s: failed to find edp cap clock %s\n",
541                                __func__, cap_clks_names[i]);
542                         return -ENODEV;
543                 }
544                 cap_clks[i] = c;
545         }
546
547         edp_entry = find_edp_entry(sku, regulator_mA);
548         if (!edp_entry) {
549                 pr_info("%s: no core edp table for sku %d, %d mA\n",
550                        __func__, sku, regulator_mA);
551                 return -ENODATA;
552         }
553
554         limits->sku = sku;
555         limits->cap_clocks = cap_clks;
556         limits->cap_clocks_num = CAP_CLKS_NUM;
557         limits->temperatures = temperatures;
558         limits->temperature_ranges = TEMPERATURE_RANGES;
559         limits->core_modules_states = CORE_MODULES_STATES;
560
561         cap_rates = &edp_entry->cap_scpu_on[0][0][0][0];
562         limits->cap_rates_scpu_on = cap_rates;
563         for (i = 0; i < TOTAL_CAPS; i++, cap_rates++) {
564                 unsigned long rate = *cap_rates * edp_entry->mult;
565                 *cap_rates = clip_cap_rate(cap_clks[i % CAP_CLKS_NUM], rate);
566         }
567
568         cap_rates = &edp_entry->cap_scpu_off[0][0][0][0];
569         limits->cap_rates_scpu_off = cap_rates;
570         for (i = 0; i < TOTAL_CAPS; i++, cap_rates++) {
571                 unsigned long rate = *cap_rates * edp_entry->mult;
572                 *cap_rates = clip_cap_rate(cap_clks[i % CAP_CLKS_NUM], rate);
573         }
574
575         return 0;
576 }