2 * arch/arm/mach-tegra/tegra11_clocks.c
4 * Copyright (C) 2011-2012 NVIDIA Corporation
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * You should have received a copy of the GNU General Public License along
16 * with this program; if not, write to the Free Software Foundation, Inc.,
17 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
21 #include <linux/kernel.h>
22 #include <linux/module.h>
23 #include <linux/list.h>
24 #include <linux/spinlock.h>
25 #include <linux/delay.h>
26 #include <linux/err.h>
28 #include <linux/clk.h>
29 #include <linux/cpufreq.h>
30 #include <linux/syscore_ops.h>
31 #include <linux/platform_device.h>
33 #include <asm/clkdev.h>
35 #include <mach/iomap.h>
37 #include <mach/hardware.h>
46 #include "tegra11_emc.h"
47 #include "tegra_cl_dvfs.h"
49 #define RST_DEVICES_L 0x004
50 #define RST_DEVICES_H 0x008
51 #define RST_DEVICES_U 0x00C
52 #define RST_DEVICES_V 0x358
53 #define RST_DEVICES_W 0x35C
54 #define RST_DEVICES_X 0x28C
55 #define RST_DEVICES_SET_L 0x300
56 #define RST_DEVICES_CLR_L 0x304
57 #define RST_DEVICES_SET_V 0x430
58 #define RST_DEVICES_CLR_V 0x434
59 #define RST_DEVICES_SET_X 0x290
60 #define RST_DEVICES_CLR_X 0x294
61 #define RST_DEVICES_NUM 6
63 #define CLK_OUT_ENB_L 0x010
64 #define CLK_OUT_ENB_H 0x014
65 #define CLK_OUT_ENB_U 0x018
66 #define CLK_OUT_ENB_V 0x360
67 #define CLK_OUT_ENB_W 0x364
68 #define CLK_OUT_ENB_X 0x280
69 #define CLK_OUT_ENB_SET_L 0x320
70 #define CLK_OUT_ENB_CLR_L 0x324
71 #define CLK_OUT_ENB_SET_V 0x440
72 #define CLK_OUT_ENB_CLR_V 0x444
73 #define CLK_OUT_ENB_SET_X 0x284
74 #define CLK_OUT_ENB_CLR_X 0x288
75 #define CLK_OUT_ENB_NUM 6
77 #define RST_DEVICES_V_SWR_CPULP_RST_DIS (0x1 << 1) /* Reserved on Tegra11 */
78 #define CLK_OUT_ENB_V_CLK_ENB_CPULP_EN (0x1 << 1)
80 #define PERIPH_CLK_TO_BIT(c) (1 << (c->u.periph.clk_num % 32))
81 #define PERIPH_CLK_TO_RST_REG(c) \
82 periph_clk_to_reg((c), RST_DEVICES_L, RST_DEVICES_V, RST_DEVICES_X, 4)
83 #define PERIPH_CLK_TO_RST_SET_REG(c) \
84 periph_clk_to_reg((c), RST_DEVICES_SET_L, RST_DEVICES_SET_V, \
86 #define PERIPH_CLK_TO_RST_CLR_REG(c) \
87 periph_clk_to_reg((c), RST_DEVICES_CLR_L, RST_DEVICES_CLR_V, \
90 #define PERIPH_CLK_TO_ENB_REG(c) \
91 periph_clk_to_reg((c), CLK_OUT_ENB_L, CLK_OUT_ENB_V, CLK_OUT_ENB_X, 4)
92 #define PERIPH_CLK_TO_ENB_SET_REG(c) \
93 periph_clk_to_reg((c), CLK_OUT_ENB_SET_L, CLK_OUT_ENB_SET_V, \
95 #define PERIPH_CLK_TO_ENB_CLR_REG(c) \
96 periph_clk_to_reg((c), CLK_OUT_ENB_CLR_L, CLK_OUT_ENB_CLR_V, \
99 #define CLK_MASK_ARM 0x44
100 #define MISC_CLK_ENB 0x48
102 #define OSC_CTRL 0x50
103 #define OSC_CTRL_OSC_FREQ_MASK (0xF<<28)
104 #define OSC_CTRL_OSC_FREQ_13MHZ (0x0<<28)
105 #define OSC_CTRL_OSC_FREQ_19_2MHZ (0x4<<28)
106 #define OSC_CTRL_OSC_FREQ_12MHZ (0x8<<28)
107 #define OSC_CTRL_OSC_FREQ_26MHZ (0xC<<28)
108 #define OSC_CTRL_OSC_FREQ_16_8MHZ (0x1<<28)
109 #define OSC_CTRL_OSC_FREQ_38_4MHZ (0x5<<28)
110 #define OSC_CTRL_OSC_FREQ_48MHZ (0x9<<28)
111 #define OSC_CTRL_MASK (0x3f2 | OSC_CTRL_OSC_FREQ_MASK)
113 #define OSC_CTRL_PLL_REF_DIV_MASK (3<<26)
114 #define OSC_CTRL_PLL_REF_DIV_1 (0<<26)
115 #define OSC_CTRL_PLL_REF_DIV_2 (1<<26)
116 #define OSC_CTRL_PLL_REF_DIV_4 (2<<26)
118 #define PERIPH_CLK_SOURCE_I2S1 0x100
119 #define PERIPH_CLK_SOURCE_EMC 0x19c
120 #define PERIPH_CLK_SOURCE_OSC 0x1fc
121 #define PERIPH_CLK_SOURCE_NUM1 \
122 ((PERIPH_CLK_SOURCE_OSC - PERIPH_CLK_SOURCE_I2S1) / 4)
124 #define PERIPH_CLK_SOURCE_G3D2 0x3b0
125 #define PERIPH_CLK_SOURCE_SE 0x42c
126 #define PERIPH_CLK_SOURCE_NUM2 \
127 ((PERIPH_CLK_SOURCE_SE - PERIPH_CLK_SOURCE_G3D2) / 4 + 1)
129 #define AUDIO_DLY_CLK 0x49c
130 #define AUDIO_SYNC_CLK_SPDIF 0x4b4
131 #define PERIPH_CLK_SOURCE_NUM3 \
132 ((AUDIO_SYNC_CLK_SPDIF - AUDIO_DLY_CLK) / 4 + 1)
134 #define SPARE_REG 0x55c
135 #define PERIPH_CLK_SOURCE_XUSB_HOST 0x600
136 #define PERIPH_CLK_SOURCE_SOC_THERM 0x644
137 #define PERIPH_CLK_SOURCE_NUM4 \
138 ((PERIPH_CLK_SOURCE_SOC_THERM - PERIPH_CLK_SOURCE_XUSB_HOST) / 4 + 1)
140 #define PERIPH_CLK_SOURCE_NUM (PERIPH_CLK_SOURCE_NUM1 + \
141 PERIPH_CLK_SOURCE_NUM2 + \
142 PERIPH_CLK_SOURCE_NUM3 + \
143 PERIPH_CLK_SOURCE_NUM4)
145 #define CPU_SOFTRST_CTRL 0x380
146 #define CPU_SOFTRST_CTRL1 0x384
147 #define CPU_SOFTRST_CTRL2 0x388
149 #define PERIPH_CLK_SOURCE_DIVU71_MASK 0xFF
150 #define PERIPH_CLK_SOURCE_DIVU16_MASK 0xFFFF
151 #define PERIPH_CLK_SOURCE_DIV_SHIFT 0
152 #define PERIPH_CLK_SOURCE_DIVIDLE_SHIFT 8
153 #define PERIPH_CLK_SOURCE_DIVIDLE_VAL 50
154 #define PERIPH_CLK_UART_DIV_ENB (1<<24)
155 #define PERIPH_CLK_VI_SEL_EX_SHIFT 24
156 #define PERIPH_CLK_VI_SEL_EX_MASK (0x3<<PERIPH_CLK_VI_SEL_EX_SHIFT)
157 #define PERIPH_CLK_NAND_DIV_EX_ENB (1<<8)
158 #define PERIPH_CLK_DTV_POLARITY_INV (1<<25)
160 #define AUDIO_SYNC_SOURCE_MASK 0x0F
161 #define AUDIO_SYNC_DISABLE_BIT 0x10
162 #define AUDIO_SYNC_TAP_NIBBLE_SHIFT(c) ((c->reg_shift - 24) * 4)
166 #define PLL_BASE_BYPASS (1<<31)
167 #define PLL_BASE_ENABLE (1<<30)
168 #define PLL_BASE_REF_ENABLE (1<<29)
169 #define PLL_BASE_OVERRIDE (1<<28)
170 #define PLL_BASE_LOCK (1<<27)
171 #define PLL_BASE_DIVP_MASK (0x7<<20)
172 #define PLL_BASE_DIVP_SHIFT 20
173 #define PLL_BASE_DIVN_MASK (0x3FF<<8)
174 #define PLL_BASE_DIVN_SHIFT 8
175 #define PLL_BASE_DIVM_MASK (0x1F)
176 #define PLL_BASE_DIVM_SHIFT 0
178 #define PLL_BASE_PARSE(pll, cfg, b) \
180 (cfg).m = ((b) & pll##_BASE_DIVM_MASK) >> PLL_BASE_DIVM_SHIFT; \
181 (cfg).n = ((b) & pll##_BASE_DIVN_MASK) >> PLL_BASE_DIVN_SHIFT; \
182 (cfg).p = ((b) & pll##_BASE_DIVP_MASK) >> PLL_BASE_DIVP_SHIFT; \
185 #define PLL_OUT_RATIO_MASK (0xFF<<8)
186 #define PLL_OUT_RATIO_SHIFT 8
187 #define PLL_OUT_OVERRIDE (1<<2)
188 #define PLL_OUT_CLKEN (1<<1)
189 #define PLL_OUT_RESET_DISABLE (1<<0)
191 #define PLL_MISC(c) \
192 (((c)->flags & PLL_ALT_MISC_REG) ? 0x4 : 0xc)
193 #define PLL_MISCN(c, n) \
194 ((c)->u.pll.misc1 + ((n) - 1) * PLL_MISC(c))
195 #define PLL_MISC_LOCK_ENABLE(c) \
196 (((c)->flags & (PLLU | PLLD)) ? (1<<22) : (1<<18))
198 #define PLL_MISC_DCCON_SHIFT 20
199 #define PLL_MISC_CPCON_SHIFT 8
200 #define PLL_MISC_CPCON_MASK (0xF<<PLL_MISC_CPCON_SHIFT)
201 #define PLL_MISC_LFCON_SHIFT 4
202 #define PLL_MISC_LFCON_MASK (0xF<<PLL_MISC_LFCON_SHIFT)
203 #define PLL_MISC_VCOCON_SHIFT 0
204 #define PLL_MISC_VCOCON_MASK (0xF<<PLL_MISC_VCOCON_SHIFT)
206 #define PLL_FIXED_MDIV(c, ref) ((ref) > (c)->u.pll.cf_max ? 2 : 1)
209 #define PLLU_BASE_OVERRIDE (1<<24)
210 #define PLLU_BASE_POST_DIV (1<<20)
213 #define PLLD_BASE_CSI_CLKENABLE (1<<26)
214 #define PLLD_BASE_DSI_MUX_SHIFT 25
215 #define PLLD_BASE_DSI_MUX_MASK (1<<PLLD_BASE_DSI_MUX_SHIFT)
216 #define PLLD_BASE_CSI_CLKSOURCE (1<<24)
218 #define PLLD_MISC_DSI_CLKENABLE (1<<30)
219 #define PLLD_MISC_DIV_RST (1<<23)
220 #define PLLD_MISC_DCCON_SHIFT 12
222 #define PLLDU_LFCON 2
224 /* PLLC2 and PLLC3 (PLLCX) */
225 #define PLLCX_USE_DYN_RAMP 0
226 #define PLLCX_BASE_PHASE_LOCK (1<<26)
227 #define PLLCX_BASE_DIVP_MASK (0x7<<PLL_BASE_DIVP_SHIFT)
228 #define PLLCX_BASE_DIVN_MASK (0xFF<<PLL_BASE_DIVN_SHIFT)
229 #define PLLCX_BASE_DIVM_MASK (0x3<<PLL_BASE_DIVM_SHIFT)
230 #define PLLCX_PDIV_MAX ((PLLCX_BASE_DIVP_MASK >> PLL_BASE_DIVP_SHIFT))
231 #define PLLCX_IS_DYN(new_p, old_p) (((new_p) <= 8) && ((old_p) <= 8))
233 #define PLLCX_MISC_STROBE (1<<31)
234 #define PLLCX_MISC_RESET (1<<30)
235 #define PLLCX_MISC_SDM_DIV_SHIFT 28
236 #define PLLCX_MISC_SDM_DIV_MASK (0x3 << PLLCX_MISC_SDM_DIV_SHIFT)
237 #define PLLCX_MISC_FILT_DIV_SHIFT 26
238 #define PLLCX_MISC_FILT_DIV_MASK (0x3 << PLLCX_MISC_FILT_DIV_SHIFT)
239 #define PLLCX_MISC_ALPHA_SHIFT 18
240 #define PLLCX_MISC_ALPHA_MASK (0xFF << PLLCX_MISC_ALPHA_SHIFT)
241 #define PLLCX_MISC_KB_SHIFT 9
242 #define PLLCX_MISC_KB_MASK (0x1FF << PLLCX_MISC_KB_SHIFT)
243 #define PLLCX_MISC_KA_SHIFT 2
244 #define PLLCX_MISC_KA_MASK (0x7F << PLLCX_MISC_KA_SHIFT)
245 #define PLLCX_MISC_VCO_GAIN_SHIFT 0
246 #define PLLCX_MISC_VCO_GAIN_MASK (0x3 << PLLCX_MISC_VCO_GAIN_SHIFT)
248 #define PLLCX_MISC_KOEF_LOW_RANGE \
249 ((0x14 << PLLCX_MISC_KA_SHIFT) | (0x38 << PLLCX_MISC_KB_SHIFT))
251 #define PLLCX_MISC_DIV_LOW_RANGE \
252 ((0x2 << PLLCX_MISC_SDM_DIV_SHIFT) | (0x2 << PLLCX_MISC_FILT_DIV_SHIFT))
253 #define PLLCX_MISC_DIV_HIGH_RANGE \
254 ((0x1 << PLLCX_MISC_SDM_DIV_SHIFT) | (0x1 << PLLCX_MISC_FILT_DIV_SHIFT))
256 #define PLLCX_MISC_DEFAULT_VALUE ((0x0 << PLLCX_MISC_VCO_GAIN_SHIFT) | \
257 PLLCX_MISC_KOEF_LOW_RANGE | \
258 (0x19 << PLLCX_MISC_ALPHA_SHIFT) | \
259 PLLCX_MISC_DIV_LOW_RANGE | \
261 #define PLLCX_MISC1_DEFAULT_VALUE 0x000d2308
262 #define PLLCX_MISC2_DEFAULT_VALUE 0x30211200
263 #define PLLCX_MISC3_DEFAULT_VALUE 0x200
265 /* PLLX and PLLC (PLLXC)*/
266 #define PLLXC_USE_DYN_RAMP 0
267 #define PLLXC_BASE_DIVP_MASK (0xF<<PLL_BASE_DIVP_SHIFT)
268 #define PLLXC_BASE_DIVN_MASK (0xFF<<PLL_BASE_DIVN_SHIFT)
269 #define PLLXC_BASE_DIVM_MASK (0xFF<<PLL_BASE_DIVM_SHIFT)
271 /* PLLXC has 4-bit PDIV, but entry 15 is not allowed in h/w,
272 and s/w usage is limited to 5 */
273 #define PLLXC_PDIV_MAX 14
274 #define PLLXC_SW_PDIV_MAX 5
277 #define PLLX_MISC2_DYNRAMP_STEPB_SHIFT 24
278 #define PLLX_MISC2_DYNRAMP_STEPB_MASK (0xFF << PLLX_MISC2_DYNRAMP_STEPB_SHIFT)
279 #define PLLX_MISC2_DYNRAMP_STEPA_SHIFT 16
280 #define PLLX_MISC2_DYNRAMP_STEPA_MASK (0xFF << PLLX_MISC2_DYNRAMP_STEPA_SHIFT)
281 #define PLLX_MISC2_NDIV_NEW_SHIFT 8
282 #define PLLX_MISC2_NDIV_NEW_MASK (0xFF << PLLX_MISC2_NDIV_NEW_SHIFT)
283 #define PLLX_MISC2_LOCK_OVERRIDE (0x1 << 4)
284 #define PLLX_MISC2_DYNRAMP_DONE (0x1 << 2)
285 #define PLLX_MISC2_CLAMP_NDIV (0x1 << 1)
286 #define PLLX_MISC2_EN_DYNRAMP (0x1 << 0)
288 #define PLLX_MISC3_IDDQ (0x1 << 3)
290 #define PLLX_HW_CTRL_CFG 0x548
291 #define PLLX_HW_CTRL_CFG_SWCTRL (0x1 << 0)
294 #define PLLC_BASE_LOCK_OVERRIDE (1<<28)
296 #define PLLC_MISC_IDDQ (0x1 << 26)
297 #define PLLC_MISC_LOCK_ENABLE (0x1 << 24)
299 #define PLLC_MISC1_CLAMP_NDIV (0x1 << 26)
300 #define PLLC_MISC1_EN_DYNRAMP (0x1 << 25)
301 #define PLLC_MISC1_DYNRAMP_STEPA_SHIFT 17
302 #define PLLC_MISC1_DYNRAMP_STEPA_MASK (0xFF << PLLC_MISC1_DYNRAMP_STEPA_SHIFT)
303 #define PLLC_MISC1_DYNRAMP_STEPB_SHIFT 9
304 #define PLLC_MISC1_DYNRAMP_STEPB_MASK (0xFF << PLLC_MISC1_DYNRAMP_STEPB_SHIFT)
305 #define PLLC_MISC1_NDIV_NEW_SHIFT 1
306 #define PLLC_MISC1_NDIV_NEW_MASK (0xFF << PLLC_MISC1_NDIV_NEW_SHIFT)
307 #define PLLC_MISC1_DYNRAMP_DONE (0x1 << 0)
310 #define PLLM_BASE_DIVP_MASK (0x1 << PLL_BASE_DIVP_SHIFT)
311 #define PLLM_BASE_DIVN_MASK (0xFF << PLL_BASE_DIVN_SHIFT)
312 #define PLLM_BASE_DIVM_MASK (0xFF << PLL_BASE_DIVM_SHIFT)
313 #define PLLM_PDIV_MAX 1
315 #define PLLM_MISC_FSM_SW_OVERRIDE (0x1 << 10)
316 #define PLLM_MISC_IDDQ (0x1 << 5)
317 #define PLLM_MISC_LOCK_DISABLE (0x1 << 4)
318 #define PLLM_MISC_LOCK_OVERRIDE (0x1 << 3)
320 #define PMC_PLLP_WB0_OVERRIDE 0xf8
321 #define PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE (1 << 12)
322 #define PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE (1 << 11)
324 /* M, N layout for PLLM override and base registers are the same */
325 #define PMC_PLLM_WB0_OVERRIDE 0x1dc
327 #define PMC_PLLM_WB0_OVERRIDE_2 0x2b0
328 #define PMC_PLLM_WB0_OVERRIDE_2_DIVP_MASK (0x1 << 27)
331 #define PLLRE_BASE_DIVP_SHIFT 16
332 #define PLLRE_BASE_DIVP_MASK (0xF << PLLRE_BASE_DIVP_SHIFT)
333 #define PLLRE_BASE_DIVN_MASK (0xFF << PLL_BASE_DIVN_SHIFT)
334 #define PLLRE_BASE_DIVM_MASK (0xFF << PLL_BASE_DIVM_SHIFT)
336 /* PLLRE has 4-bit PDIV, but entry 15 is not allowed in h/w,
337 and s/w usage is limited to 5 */
338 #define PLLRE_PDIV_MAX 14
339 #define PLLRE_SW_PDIV_MAX 5
341 #define PLLRE_MISC_LOCK_ENABLE (0x1 << 30)
342 #define PLLRE_MISC_LOCK_OVERRIDE (0x1 << 29)
343 #define PLLRE_MISC_LOCK (0x1 << 24)
344 #define PLLRE_MISC_IDDQ (0x1 << 16)
346 #define OUT_OF_TABLE_CPCON 0x8
348 #define SUPER_CLK_MUX 0x00
349 #define SUPER_STATE_SHIFT 28
350 #define SUPER_STATE_MASK (0xF << SUPER_STATE_SHIFT)
351 #define SUPER_STATE_STANDBY (0x0 << SUPER_STATE_SHIFT)
352 #define SUPER_STATE_IDLE (0x1 << SUPER_STATE_SHIFT)
353 #define SUPER_STATE_RUN (0x2 << SUPER_STATE_SHIFT)
354 #define SUPER_STATE_IRQ (0x3 << SUPER_STATE_SHIFT)
355 #define SUPER_STATE_FIQ (0x4 << SUPER_STATE_SHIFT)
356 #define SUPER_LP_DIV2_BYPASS (0x1 << 16)
357 #define SUPER_SOURCE_MASK 0xF
358 #define SUPER_FIQ_SOURCE_SHIFT 12
359 #define SUPER_IRQ_SOURCE_SHIFT 8
360 #define SUPER_RUN_SOURCE_SHIFT 4
361 #define SUPER_IDLE_SOURCE_SHIFT 0
363 #define SUPER_CLK_DIVIDER 0x04
364 #define SUPER_CLOCK_DIV_U71_SHIFT 16
365 #define SUPER_CLOCK_DIV_U71_MASK (0xff << SUPER_CLOCK_DIV_U71_SHIFT)
367 #define BUS_CLK_DISABLE (1<<3)
368 #define BUS_CLK_DIV_MASK 0x3
371 #define PMC_CTRL_BLINK_ENB (1 << 7)
373 #define PMC_DPD_PADS_ORIDE 0x1c
374 #define PMC_DPD_PADS_ORIDE_BLINK_ENB (1 << 20)
376 #define PMC_BLINK_TIMER_DATA_ON_SHIFT 0
377 #define PMC_BLINK_TIMER_DATA_ON_MASK 0x7fff
378 #define PMC_BLINK_TIMER_ENB (1 << 15)
379 #define PMC_BLINK_TIMER_DATA_OFF_SHIFT 16
380 #define PMC_BLINK_TIMER_DATA_OFF_MASK 0xffff
382 #define UTMIP_PLL_CFG2 0x488
383 #define UTMIP_PLL_CFG2_STABLE_COUNT(x) (((x) & 0xfff) << 6)
384 #define UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(x) (((x) & 0x3f) << 18)
385 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN (1 << 0)
386 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN (1 << 2)
387 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN (1 << 4)
389 #define UTMIP_PLL_CFG1 0x484
390 #define UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(x) (((x) & 0x1f) << 27)
391 #define UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(x) (((x) & 0xfff) << 0)
392 #define UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERUP (1 << 15)
393 #define UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN (1 << 14)
394 #define UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN (1 << 12)
395 #define UTMIP_PLL_CFG1_FORCE_PLLU_POWERUP (1 << 17)
396 #define UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN (1 << 16)
399 #define PLLE_BASE_LOCK_OVERRIDE (0x1 << 29)
400 #define PLLE_BASE_DIVCML_SHIFT 24
401 #define PLLE_BASE_DIVCML_MASK (0xf<<PLLE_BASE_DIVCML_SHIFT)
402 #define PLLE_BASE_DIVN_MASK (0xFF<<PLL_BASE_DIVN_SHIFT)
403 #define PLLE_BASE_DIVM_MASK (0xFF<<PLL_BASE_DIVM_SHIFT)
405 /* PLLE has 4-bit CMLDIV, but entry 15 is not allowed in h/w */
406 #define PLLE_CMLDIV_MAX 14
408 #define PLLE_MISC_READY (1<<15)
409 #define PLLE_MISC_IDDQ_SW_CTRL (1<<14)
410 #define PLLE_MISC_IDDQ_SW_VALUE (1<<13)
411 #define PLLE_MISC_LOCK (1<<11)
412 #define PLLE_MISC_LOCK_ENABLE (1<<9)
413 #define PLLE_MISC_PLLE_PTS (1<<8)
414 #define PLLE_MISC_VREG_BG_CTRL_SHIFT 4
415 #define PLLE_MISC_VREG_BG_CTRL_MASK (0x3<<PLLE_MISC_VREG_BG_CTRL_SHIFT)
416 #define PLLE_MISC_VREG_CTRL_SHIFT 2
417 #define PLLE_MISC_VREG_CTRL_MASK (0x3<<PLLE_MISC_VREG_CTRL_SHIFT)
419 #define PLLE_SS_CTRL 0x68
420 #define PLLE_SS_CNTL_SSC_BYP (0x1 << 12)
421 #define PLLE_SS_CNTL_INTERP_RESET (0x1 << 11)
422 #define PLLE_SS_CNTL_BYPASS_SS (0x1 << 10)
423 #define PLLE_SS_DISABLE (PLLE_SS_CNTL_SSC_BYP |\
424 PLLE_SS_CNTL_INTERP_RESET | PLLE_SS_CNTL_BYPASS_SS)
425 #define PLLE_SS_COEFFICIENTS_MASK (~PLLE_SS_DISABLE)
427 #define PLLE_AUX 0x48c
428 #define PLLE_AUX_PLLRE_SEL (1<<28)
429 #define PLLE_AUX_SEQ_STATE_SHIFT 26
430 #define PLLE_AUX_SEQ_STATE_MASK (0x3<<PLLE_AUX_SEQ_STATE_SHIFT)
431 #define PLLE_AUX_SEQ_ENABLE (1<<24)
432 #define PLLE_AUX_ENABLE_SWCTL (1<<4)
433 #define PLLE_AUX_USE_LOCKDET (1<<3)
434 #define PLLE_AUX_PLLP_SEL (1<<2)
436 /* USB PLLs PD HW controls */
437 #define XUSBIO_PLL_CFG0 0x51c
438 #define XUSBIO_PLL_CFG0_SEQ_ENABLE (1<<24)
439 #define XUSBIO_PLL_CFG0_PADPLL_USE_LOCKDET (1<<6)
440 #define XUSBIO_PLL_CFG0_CLK_ENABLE_SWCTL (1<<2)
441 #define XUSBIO_PLL_CFG0_PADPLL_RESET_SWCTL (1<<0)
443 #define UTMIPLL_HW_PWRDN_CFG0 0x52c
444 #define UTMIPLL_HW_PWRDN_CFG0_SEQ_START_STATE (1<<25)
445 #define UTMIPLL_HW_PWRDN_CFG0_SEQ_ENABLE (1<<24)
446 #define UTMIPLL_HW_PWRDN_CFG0_USE_LOCKDET (1<<6)
447 #define UTMIPLL_HW_PWRDN_CFG0_SEQ_RESET_INPUT_VALUE (1<<5)
448 #define UTMIPLL_HW_PWRDN_CFG0_SEQ_IN_SWCTL (1<<4)
449 #define UTMIPLL_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL (1<<2)
450 #define UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE (1<<1)
451 #define UTMIPLL_HW_PWRDN_CFG0_IDDQ_SWCTL (1<<0)
453 #define PLLU_HW_PWRDN_CFG0 0x530
454 #define PLLU_HW_PWRDN_CFG0_SEQ_ENABLE (1<<24)
455 #define PLLU_HW_PWRDN_CFG0_USE_LOCKDET (1<<6)
456 #define PLLU_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL (1<<2)
457 #define PLLU_HW_PWRDN_CFG0_CLK_SWITCH_SWCTL (1<<0)
459 #define USB_PLLS_SEQ_START_STATE (1<<25)
460 #define USB_PLLS_SEQ_ENABLE (1<<24)
461 #define USB_PLLS_USE_LOCKDET (1<<6)
462 #define USB_PLLS_ENABLE_SWCTL ((1<<2) | (1<<0))
465 #define DFLL_BASE 0x2f4
466 #define DFLL_BASE_RESET (1<<0)
468 #define LVL2_CLK_GATE_OVRE 0x554
470 #define ROUND_DIVIDER_UP 0
471 #define ROUND_DIVIDER_DOWN 1
472 #define DIVIDER_1_5_ALLOWED 0
474 #define CPU_CLOCK(cpu) (0x1 << (8 + cpu))
475 #define CPU_RESET(cpu) (0x111001ul << (cpu))
477 /* PLLP default fixed rate in h/w controlled mode */
478 #define PLLP_DEFAULT_FIXED_RATE 216000000
480 static bool tegra11_is_dyn_ramp(struct clk *c,
481 unsigned long rate, bool from_vco_min);
482 static void tegra11_pllp_init_dependencies(unsigned long pllp_rate);
483 static unsigned long tegra11_clk_shared_bus_update(
484 struct clk *bus, struct clk **bus_top, struct clk **bus_slow);
486 static bool detach_shared_bus;
487 module_param(detach_shared_bus, bool, 0644);
492 * Structure defining the fields for USB UTMI clocks Parameters.
494 struct utmi_clk_param
496 /* Oscillator Frequency in KHz */
498 /* UTMIP PLL Enable Delay Count */
499 u8 enable_delay_count;
500 /* UTMIP PLL Stable count */
502 /* UTMIP PLL Active delay count */
503 u8 active_delay_count;
504 /* UTMIP PLL Xtal frequency count */
508 static const struct utmi_clk_param utmi_parameters[] =
510 /* OSC_FREQUENCY, ENABLE_DLY, STABLE_CNT, ACTIVE_DLY, XTAL_FREQ_CNT */
511 {13000000, 0x02, 0x33, 0x05, 0x7F},
512 {19200000, 0x03, 0x4B, 0x06, 0xBB},
513 {12000000, 0x02, 0x2F, 0x04, 0x76},
514 {26000000, 0x04, 0x66, 0x09, 0xFE},
515 {16800000, 0x03, 0x41, 0x0A, 0xA4},
518 static void __iomem *reg_clk_base = IO_ADDRESS(TEGRA_CLK_RESET_BASE);
519 static void __iomem *reg_pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
520 static void __iomem *misc_gp_base = IO_ADDRESS(TEGRA_APB_MISC_BASE);
522 #define MISC_GP_HIDREV 0x804
523 #define MISC_GP_TRANSACTOR_SCRATCH_0 0x864
524 #define MISC_GP_TRANSACTOR_SCRATCH_LA_ENABLE (0x1 << 1)
525 #define MISC_GP_TRANSACTOR_SCRATCH_DDS_ENABLE (0x1 << 2)
526 #define MISC_GP_TRANSACTOR_SCRATCH_DP2_ENABLE (0x1 << 3)
529 * Some peripheral clocks share an enable bit, so refcount the enable bits
530 * in registers CLK_ENABLE_L, ... CLK_ENABLE_W, and protect refcount updates
533 static DEFINE_SPINLOCK(periph_refcount_lock);
534 static int tegra_periph_clk_enable_refcount[CLK_OUT_ENB_NUM * 32];
536 #define clk_writel(value, reg) \
537 __raw_writel(value, (u32)reg_clk_base + (reg))
538 #define clk_readl(reg) \
539 __raw_readl((u32)reg_clk_base + (reg))
540 #define pmc_writel(value, reg) \
541 __raw_writel(value, (u32)reg_pmc_base + (reg))
542 #define pmc_readl(reg) \
543 __raw_readl((u32)reg_pmc_base + (reg))
544 #define chipid_readl() \
545 __raw_readl((u32)misc_gp_base + MISC_GP_HIDREV)
547 #define clk_writel_delay(value, reg) \
549 __raw_writel((value), (u32)reg_clk_base + (reg)); \
553 #define pll_writel_delay(value, reg) \
555 __raw_writel((value), reg_clk_base + (reg)); \
560 static inline int clk_set_div(struct clk *c, u32 n)
562 return clk_set_rate(c, (clk_get_rate(c->parent) + n-1) / n);
565 static inline u32 periph_clk_to_reg(
566 struct clk *c, u32 reg_L, u32 reg_V, u32 reg_X, int offs)
568 u32 reg = c->u.periph.clk_num / 32;
569 BUG_ON(reg >= RST_DEVICES_NUM);
571 reg = reg_L + (reg * offs);
573 reg = reg_V + ((reg - 3) * offs);
579 static int clk_div_x1_get_divider(unsigned long parent_rate, unsigned long rate,
581 u32 flags, u32 round_mode)
583 s64 divider_ux1 = parent_rate;
587 if (!(flags & DIV_U71_INT))
589 if (round_mode == ROUND_DIVIDER_UP)
590 divider_ux1 += rate - 1;
591 do_div(divider_ux1, rate);
592 if (flags & DIV_U71_INT)
595 if (divider_ux1 - 2 < 0)
598 if (divider_ux1 - 2 > max_x)
601 #if !DIVIDER_1_5_ALLOWED
602 if (divider_ux1 == 3)
603 divider_ux1 = (round_mode == ROUND_DIVIDER_UP) ? 4 : 2;
605 return divider_ux1 - 2;
608 static int clk_div71_get_divider(unsigned long parent_rate, unsigned long rate,
609 u32 flags, u32 round_mode)
611 return clk_div_x1_get_divider(parent_rate, rate, 0xFF,
615 static int clk_div151_get_divider(unsigned long parent_rate, unsigned long rate,
616 u32 flags, u32 round_mode)
618 return clk_div_x1_get_divider(parent_rate, rate, 0xFFFF,
622 static int clk_div16_get_divider(unsigned long parent_rate, unsigned long rate)
626 divider_u16 = parent_rate;
629 divider_u16 += rate - 1;
630 do_div(divider_u16, rate);
632 if (divider_u16 - 1 < 0)
635 if (divider_u16 - 1 > 0xFFFF)
638 return divider_u16 - 1;
641 static inline bool bus_user_is_slower(struct clk *a, struct clk *b)
643 return a->u.shared_bus_user.client->max_rate * a->div <
644 b->u.shared_bus_user.client->max_rate * b->div;
647 static inline bool bus_user_request_is_lower(struct clk *a, struct clk *b)
649 return a->u.shared_bus_user.rate * a->div <
650 b->u.shared_bus_user.rate * b->div;
653 /* clk_m functions */
654 static unsigned long tegra11_clk_m_autodetect_rate(struct clk *c)
656 u32 osc_ctrl = clk_readl(OSC_CTRL);
657 u32 auto_clock_control = osc_ctrl & ~OSC_CTRL_OSC_FREQ_MASK;
658 u32 pll_ref_div = osc_ctrl & OSC_CTRL_PLL_REF_DIV_MASK;
660 c->rate = tegra_clk_measure_input_freq();
663 auto_clock_control |= OSC_CTRL_OSC_FREQ_12MHZ;
664 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1);
667 auto_clock_control |= OSC_CTRL_OSC_FREQ_13MHZ;
668 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1);
671 auto_clock_control |= OSC_CTRL_OSC_FREQ_19_2MHZ;
672 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1);
675 auto_clock_control |= OSC_CTRL_OSC_FREQ_26MHZ;
676 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1);
679 auto_clock_control |= OSC_CTRL_OSC_FREQ_16_8MHZ;
680 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1);
683 auto_clock_control |= OSC_CTRL_OSC_FREQ_38_4MHZ;
684 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_2);
687 auto_clock_control |= OSC_CTRL_OSC_FREQ_48MHZ;
688 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_4);
690 case 115200: /* fake 13M for QT */
691 case 230400: /* fake 13M for QT */
692 auto_clock_control |= OSC_CTRL_OSC_FREQ_13MHZ;
694 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1);
697 pr_err("%s: Unexpected clock rate %ld", __func__, c->rate);
700 clk_writel(auto_clock_control, OSC_CTRL);
704 static void tegra11_clk_m_init(struct clk *c)
706 pr_debug("%s on clock %s\n", __func__, c->name);
707 tegra11_clk_m_autodetect_rate(c);
710 static int tegra11_clk_m_enable(struct clk *c)
712 pr_debug("%s on clock %s\n", __func__, c->name);
716 static void tegra11_clk_m_disable(struct clk *c)
718 pr_debug("%s on clock %s\n", __func__, c->name);
719 WARN(1, "Attempting to disable main SoC clock\n");
722 static struct clk_ops tegra_clk_m_ops = {
723 .init = tegra11_clk_m_init,
724 .enable = tegra11_clk_m_enable,
725 .disable = tegra11_clk_m_disable,
728 static struct clk_ops tegra_clk_m_div_ops = {
729 .enable = tegra11_clk_m_enable,
732 /* PLL reference divider functions */
733 static void tegra11_pll_ref_init(struct clk *c)
735 u32 pll_ref_div = clk_readl(OSC_CTRL) & OSC_CTRL_PLL_REF_DIV_MASK;
736 pr_debug("%s on clock %s\n", __func__, c->name);
738 switch (pll_ref_div) {
739 case OSC_CTRL_PLL_REF_DIV_1:
742 case OSC_CTRL_PLL_REF_DIV_2:
745 case OSC_CTRL_PLL_REF_DIV_4:
749 pr_err("%s: Invalid pll ref divider %d", __func__, pll_ref_div);
756 static struct clk_ops tegra_pll_ref_ops = {
757 .init = tegra11_pll_ref_init,
758 .enable = tegra11_clk_m_enable,
759 .disable = tegra11_clk_m_disable,
762 /* super clock functions */
763 /* "super clocks" on tegra11x have two-stage muxes, fractional 7.1 divider and
764 * clock skipping super divider. We will ignore the clock skipping divider,
765 * since we can't lower the voltage when using the clock skip, but we can if
766 * we lower the PLL frequency. Note that skipping divider can and will be used
767 * by thermal control h/w for automatic throttling. There is also a 7.1 divider
768 * that most CPU super-clock inputs can be routed through. We will not use it
769 * as well (keep default 1:1 state), to avoid high jitter on PLLX and DFLL path
770 * and possible concurrency access issues with thermal h/w (7.1 divider setting
771 * share register with clock skipping divider)
773 static void tegra11_super_clk_init(struct clk *c)
778 const struct clk_mux_sel *sel;
779 val = clk_readl(c->reg + SUPER_CLK_MUX);
781 BUG_ON(((val & SUPER_STATE_MASK) != SUPER_STATE_RUN) &&
782 ((val & SUPER_STATE_MASK) != SUPER_STATE_IDLE));
783 shift = ((val & SUPER_STATE_MASK) == SUPER_STATE_IDLE) ?
784 SUPER_IDLE_SOURCE_SHIFT : SUPER_RUN_SOURCE_SHIFT;
785 source = (val >> shift) & SUPER_SOURCE_MASK;
788 * Enforce PLLX DIV2 bypass setting as early as possible. It is always
789 * safe to do for both cclk_lp and cclk_g when booting on G CPU. (In
790 * case of booting on LP CPU, cclk_lp will be updated during the cpu
791 * rate change after boot, and cclk_g after the cluster switch.)
793 if ((c->flags & DIV_U71) && (!is_lp_cluster())) {
794 val |= SUPER_LP_DIV2_BYPASS;
795 clk_writel_delay(val, c->reg);
798 for (sel = c->inputs; sel->input != NULL; sel++) {
799 if (sel->value == source)
802 BUG_ON(sel->input == NULL);
803 c->parent = sel->input;
805 /* Update parent in case when LP CPU PLLX DIV2 bypassed */
806 if ((c->flags & DIV_2) && (c->parent->flags & PLLX) &&
807 (val & SUPER_LP_DIV2_BYPASS))
808 c->parent = c->parent->parent;
810 if (c->flags & DIV_U71) {
814 /* Make sure 7.1 divider is 1:1, clear s/w skipper control */
815 /* FIXME: set? preserve? thermal h/w skipper control */
816 val = clk_readl(c->reg + SUPER_CLK_DIVIDER);
817 BUG_ON(val & SUPER_CLOCK_DIV_U71_MASK);
819 clk_writel(val, c->reg + SUPER_CLK_DIVIDER);
822 clk_writel(0, c->reg + SUPER_CLK_DIVIDER);
825 static int tegra11_super_clk_enable(struct clk *c)
830 static void tegra11_super_clk_disable(struct clk *c)
832 /* since tegra 3 has 2 CPU super clocks - low power lp-mode clock and
833 geared up g-mode super clock - mode switch may request to disable
834 either of them; accept request with no affect on h/w */
837 static int tegra11_super_clk_set_parent(struct clk *c, struct clk *p)
840 const struct clk_mux_sel *sel;
843 val = clk_readl(c->reg + SUPER_CLK_MUX);
844 BUG_ON(((val & SUPER_STATE_MASK) != SUPER_STATE_RUN) &&
845 ((val & SUPER_STATE_MASK) != SUPER_STATE_IDLE));
846 shift = ((val & SUPER_STATE_MASK) == SUPER_STATE_IDLE) ?
847 SUPER_IDLE_SOURCE_SHIFT : SUPER_RUN_SOURCE_SHIFT;
848 for (sel = c->inputs; sel->input != NULL; sel++) {
849 if (sel->input == p) {
850 /* For LP mode super-clock switch between PLLX direct
851 and divided-by-2 outputs is allowed only when other
852 than PLLX clock source is current parent */
853 if ((c->flags & DIV_2) && (p->flags & PLLX) &&
854 ((sel->value ^ val) & SUPER_LP_DIV2_BYPASS)) {
855 if (c->parent->flags & PLLX)
857 val ^= SUPER_LP_DIV2_BYPASS;
858 clk_writel_delay(val, c->reg);
860 val &= ~(SUPER_SOURCE_MASK << shift);
861 val |= (sel->value & SUPER_SOURCE_MASK) << shift;
863 if (c->flags & DIV_U71) {
864 /* Make sure 7.1 divider is 1:1 */
865 u32 div = clk_readl(c->reg + SUPER_CLK_DIVIDER);
866 BUG_ON(div & SUPER_CLOCK_DIV_U71_MASK);
872 clk_writel_delay(val, c->reg);
874 if (c->refcnt && c->parent)
875 clk_disable(c->parent);
885 * Do not use super clocks "skippers", since dividing using a clock skipper
886 * does not allow the voltage to be scaled down. Instead adjust the rate of
887 * the parent clock. This requires that the parent of a super clock have no
888 * other children, otherwise the rate will change underneath the other
891 static int tegra11_super_clk_set_rate(struct clk *c, unsigned long rate)
893 /* In tegra11_cpu_clk_set_plls() and tegra11_sbus_cmplx_set_rate()
894 * this call is skipped by directly setting rate of source plls. If we
895 * ever use 7.1 divider at other than 1:1 setting, or exercise s/w
896 * skipper control, not only this function, but cpu and sbus set_rate
897 * APIs should be changed accordingly.
899 return clk_set_rate(c->parent, rate);
902 #ifdef CONFIG_PM_SLEEP
903 static void tegra11_super_clk_resume(struct clk *c, struct clk *backup,
907 const struct clk_mux_sel *sel;
910 /* For sclk and cclk_g super clock just restore saved value */
911 if (!(c->flags & DIV_2)) {
912 clk_writel_delay(setting, c->reg);
917 * For cclk_lp supper clock: switch to backup (= not PLLX) source,
918 * safely restore PLLX DIV2 bypass, and only then restore full
921 val = clk_readl(c->reg);
922 BUG_ON(((val & SUPER_STATE_MASK) != SUPER_STATE_RUN) &&
923 ((val & SUPER_STATE_MASK) != SUPER_STATE_IDLE));
924 shift = ((val & SUPER_STATE_MASK) == SUPER_STATE_IDLE) ?
925 SUPER_IDLE_SOURCE_SHIFT : SUPER_RUN_SOURCE_SHIFT;
926 for (sel = c->inputs; sel->input != NULL; sel++) {
927 if (sel->input == backup) {
928 val &= ~(SUPER_SOURCE_MASK << shift);
929 val |= (sel->value & SUPER_SOURCE_MASK) << shift;
931 BUG_ON(backup->flags & PLLX);
932 clk_writel_delay(val, c->reg);
934 val &= ~SUPER_LP_DIV2_BYPASS;
935 val |= (setting & SUPER_LP_DIV2_BYPASS);
936 clk_writel_delay(val, c->reg);
937 clk_writel_delay(setting, c->reg);
945 static struct clk_ops tegra_super_ops = {
946 .init = tegra11_super_clk_init,
947 .enable = tegra11_super_clk_enable,
948 .disable = tegra11_super_clk_disable,
949 .set_parent = tegra11_super_clk_set_parent,
950 .set_rate = tegra11_super_clk_set_rate,
953 /* virtual cpu clock functions */
954 /* some clocks can not be stopped (cpu, memory bus) while the SoC is running.
955 To change the frequency of these clocks, the parent pll may need to be
956 reprogrammed, so the clock must be moved off the pll, the pll reprogrammed,
957 and then the clock moved back to the pll. To hide this sequence, a virtual
960 static void tegra11_cpu_clk_init(struct clk *c)
962 c->state = (!is_lp_cluster() == (c->u.cpu.mode == MODE_G))? ON : OFF;
965 static int tegra11_cpu_clk_enable(struct clk *c)
970 static void tegra11_cpu_clk_disable(struct clk *c)
972 /* since tegra 3 has 2 virtual CPU clocks - low power lp-mode clock
973 and geared up g-mode clock - mode switch may request to disable
974 either of them; accept request with no affect on h/w */
977 static int tegra11_cpu_clk_set_plls(struct clk *c, unsigned long rate,
978 unsigned long old_rate)
981 bool on_main = false;
982 unsigned long backup_rate, main_rate;
983 unsigned long vco_min = c->u.cpu.main->u.pll.vco_min;
986 * Take an extra reference to the main pll so it doesn't turn off when
987 * we move the cpu off of it. If possible, use main pll dynamic ramp
988 * to reach target rate in one shot. Otherwise, use dynamic ramp to
989 * lower current rate to pll VCO minimum level before switching to
992 if (c->parent->parent == c->u.cpu.main) {
993 bool dramp = (rate > c->u.cpu.backup_rate) &&
994 tegra11_is_dyn_ramp(c->u.cpu.main, rate, false);
995 clk_enable(c->u.cpu.main);
999 ((old_rate > vco_min) &&
1000 tegra11_is_dyn_ramp(c->u.cpu.main, vco_min, false))) {
1001 main_rate = dramp ? rate : vco_min;
1002 ret = clk_set_rate(c->u.cpu.main, main_rate);
1004 pr_err("Failed to set cpu rate %lu on source"
1005 " %s\n", main_rate, c->u.cpu.main->name);
1010 } else if (old_rate > vco_min) {
1011 #if PLLXC_USE_DYN_RAMP
1012 pr_warn("No dynamic ramp down: %s: %lu to %lu\n",
1013 c->u.cpu.main->name, old_rate, vco_min);
1018 /* Switch to back-up source, and stay on it if target rate is below
1020 if (c->parent->parent != c->u.cpu.backup) {
1021 ret = clk_set_parent(c->parent, c->u.cpu.backup);
1023 pr_err("Failed to switch cpu to %s\n",
1024 c->u.cpu.backup->name);
1029 backup_rate = min(rate, c->u.cpu.backup_rate);
1030 if (backup_rate != clk_get_rate_locked(c)) {
1031 ret = clk_set_rate(c->u.cpu.backup, backup_rate);
1033 pr_err("Failed to set cpu rate %lu on backup source\n",
1038 if (rate == backup_rate)
1041 /* Switch from backup source to main at rate not exceeding pll VCO
1042 minimum. Use dynamic ramp to reach target rate if it is above VCO
1045 if (rate > vco_min) {
1046 if (tegra11_is_dyn_ramp(c->u.cpu.main, rate, true))
1047 main_rate = vco_min;
1048 #if PLLXC_USE_DYN_RAMP
1050 pr_warn("No dynamic ramp up: %s: %lu to %lu\n",
1051 c->u.cpu.main->name, vco_min, rate);
1055 ret = clk_set_rate(c->u.cpu.main, main_rate);
1057 pr_err("Failed to set cpu rate %lu on source"
1058 " %s\n", main_rate, c->u.cpu.main->name);
1061 ret = clk_set_parent(c->parent, c->u.cpu.main);
1063 pr_err("Failed to switch cpu to %s\n", c->u.cpu.main->name);
1066 if (rate != main_rate) {
1067 ret = clk_set_rate(c->u.cpu.main, rate);
1069 pr_err("Failed to set cpu rate %lu on source"
1070 " %s\n", rate, c->u.cpu.main->name);
1077 clk_disable(c->u.cpu.main);
1082 static int tegra11_cpu_clk_dfll_on(struct clk *c, unsigned long rate,
1083 unsigned long old_rate)
1086 struct clk *dfll = c->u.cpu.dynamic;
1087 unsigned long dfll_rate_min = c->dvfs->dfll_data.use_dfll_rate_min;
1089 /* dfll rate request */
1090 ret = clk_set_rate(dfll, rate);
1092 pr_err("Failed to set cpu rate %lu on source"
1093 " %s\n", rate, dfll->name);
1097 /* 1st time - switch to dfll */
1098 if (c->parent->parent != dfll) {
1099 if (max(old_rate, rate) < dfll_rate_min) {
1100 /* set interim cpu dvfs rate at dfll_rate_min to
1101 prevent voltage drop below dfll Vmin */
1102 ret = tegra_dvfs_set_rate(c, dfll_rate_min);
1104 pr_err("Failed to set cpu dvfs rate %lu\n",
1110 ret = clk_set_parent(c->parent, dfll);
1112 pr_err("Failed to switch cpu to %s\n", dfll->name);
1115 ret = tegra_clk_cfg_ex(dfll, TEGRA_CLK_DFLL_LOCK, 1);
1116 WARN(ret, "Failed to lock %s at rate %lu\n", dfll->name, rate);
1118 /* prevent legacy dvfs voltage scaling */
1119 tegra_dvfs_dfll_mode_set(c->dvfs, rate);
1124 static int tegra11_cpu_clk_dfll_off(struct clk *c, unsigned long rate,
1125 unsigned long old_rate)
1129 struct clk *dfll = c->u.cpu.dynamic;
1130 unsigned long dfll_rate_min = c->dvfs->dfll_data.use_dfll_rate_min;
1132 rate = min(rate, c->max_rate - c->dvfs->dfll_data.max_rate_boost);
1133 pll = (rate <= c->u.cpu.backup_rate) ? c->u.cpu.backup : c->u.cpu.main;
1135 ret = tegra_clk_cfg_ex(dfll, TEGRA_CLK_DFLL_LOCK, 0);
1137 pr_err("Failed to unlock %s\n", dfll->name);
1141 /* restore legacy dvfs operations and set appropriate voltage */
1142 ret = tegra_dvfs_dfll_mode_clear(c->dvfs, max(rate, dfll_rate_min));
1144 pr_err("Failed to set cpu rail for rate %lu\n", rate);
1148 /* set pll to target rate and return to pll source */
1149 ret = clk_set_rate(pll, rate);
1151 pr_err("Failed to set cpu rate %lu on source"
1152 " %s\n", rate, pll->name);
1155 ret = clk_set_parent(c->parent, pll);
1157 pr_err("Failed to switch cpu to %s\n", pll->name);
1161 /* If going up, adjust voltage here (down path is taken care of by the
1162 framework after set rate exit) */
1163 if (old_rate <= rate)
1164 tegra_dvfs_set_rate(c, rate);
1169 tegra_clk_cfg_ex(dfll, TEGRA_CLK_DFLL_LOCK, 1);
1170 tegra_dvfs_dfll_mode_set(c->dvfs, old_rate);
1174 static int tegra11_cpu_clk_set_rate(struct clk *c, unsigned long rate)
1176 unsigned long old_rate = clk_get_rate_locked(c);
1177 bool has_dfll = c->u.cpu.dynamic &&
1178 (c->u.cpu.dynamic->state != UNINITIALIZED);
1179 bool is_dfll = c->parent->parent == c->u.cpu.dynamic;
1181 /* On SILICON allow CPU rate change only if cpu regulator is connected.
1182 Ignore regulator connection on FPGA and SIMULATION platforms. */
1183 #ifdef CONFIG_TEGRA_SILICON_PLATFORM
1185 if (!c->dvfs->dvfs_rail)
1187 else if ((!c->dvfs->dvfs_rail->reg) && (old_rate < rate)) {
1188 WARN(1, "Increasing CPU rate while regulator is not"
1189 " ready is not allowed\n");
1194 if (has_dfll && c->dvfs && c->dvfs->dvfs_rail) {
1195 if (tegra_dvfs_is_dfll_range(c->dvfs, rate))
1196 return tegra11_cpu_clk_dfll_on(c, rate, old_rate);
1198 return tegra11_cpu_clk_dfll_off(c, rate, old_rate);
1200 return tegra11_cpu_clk_set_plls(c, rate, old_rate);
1203 static long tegra11_cpu_clk_round_rate(struct clk *c, unsigned long rate)
1205 unsigned long max_rate = c->max_rate;
1207 /* Remove dfll boost to maximum rate when running on PLL */
1208 if (!c->dvfs || !tegra_dvfs_is_dfll_scale(c->dvfs, rate))
1209 max_rate -= c->dvfs->dfll_data.max_rate_boost;
1211 if (rate > max_rate)
1213 else if (rate < c->min_rate)
1218 static struct clk_ops tegra_cpu_ops = {
1219 .init = tegra11_cpu_clk_init,
1220 .enable = tegra11_cpu_clk_enable,
1221 .disable = tegra11_cpu_clk_disable,
1222 .set_rate = tegra11_cpu_clk_set_rate,
1223 .round_rate = tegra11_cpu_clk_round_rate,
1227 static void tegra11_cpu_cmplx_clk_init(struct clk *c)
1229 int i = !!is_lp_cluster();
1231 BUG_ON(c->inputs[0].input->u.cpu.mode != MODE_G);
1232 BUG_ON(c->inputs[1].input->u.cpu.mode != MODE_LP);
1233 c->parent = c->inputs[i].input;
1236 /* cpu complex clock provides second level vitualization (on top of
1237 cpu virtual cpu rate control) in order to hide the CPU mode switch
1239 #if PARAMETERIZE_CLUSTER_SWITCH
1240 static unsigned int switch_delay;
1241 static unsigned int switch_flags;
1242 static DEFINE_SPINLOCK(parameters_lock);
1244 void tegra_cluster_switch_set_parameters(unsigned int us, unsigned int flags)
1246 spin_lock(¶meters_lock);
1248 switch_flags = flags;
1249 spin_unlock(¶meters_lock);
1253 static int tegra11_cpu_cmplx_clk_enable(struct clk *c)
1258 static void tegra11_cpu_cmplx_clk_disable(struct clk *c)
1260 pr_debug("%s on clock %s\n", __func__, c->name);
1262 /* oops - don't disable the CPU complex clock! */
1266 static int tegra11_cpu_cmplx_clk_set_rate(struct clk *c, unsigned long rate)
1268 unsigned long flags;
1270 struct clk *parent = c->parent;
1272 if (!parent->ops || !parent->ops->set_rate)
1275 clk_lock_save(parent, &flags);
1277 ret = clk_set_rate_locked(parent, rate);
1279 clk_unlock_restore(parent, &flags);
1284 static int tegra11_cpu_cmplx_clk_set_parent(struct clk *c, struct clk *p)
1287 unsigned int flags, delay;
1288 const struct clk_mux_sel *sel;
1289 unsigned long rate = clk_get_rate(c->parent);
1290 struct clk *dfll = c->parent->u.cpu.dynamic ? : p->u.cpu.dynamic;
1291 struct clk *p_source;
1293 pr_debug("%s: %s %s\n", __func__, c->name, p->name);
1294 BUG_ON(c->parent->u.cpu.mode != (is_lp_cluster() ? MODE_LP : MODE_G));
1296 for (sel = c->inputs; sel->input != NULL; sel++) {
1297 if (sel->input == p)
1303 #if PARAMETERIZE_CLUSTER_SWITCH
1304 spin_lock(¶meters_lock);
1305 flags = switch_flags;
1306 delay = switch_delay;
1308 spin_unlock(¶meters_lock);
1311 /* over/under-clocking after switch - allow, but update rate */
1312 if ((rate > p->max_rate) || (rate < p->min_rate)) {
1313 rate = rate > p->max_rate ? p->max_rate : p->min_rate;
1314 ret = clk_set_rate(c->parent, rate);
1316 pr_err("%s: Failed to set rate %lu for %s\n",
1317 __func__, rate, p->name);
1324 if (rate > p->max_rate) { /* over-clocking - no switch */
1325 pr_warn("%s: No %s mode switch to %s at rate %lu\n",
1326 __func__, c->name, p->name, rate);
1329 flags = TEGRA_POWER_CLUSTER_IMMEDIATE;
1330 flags |= TEGRA_POWER_CLUSTER_PART_DEFAULT;
1333 flags |= (p->u.cpu.mode == MODE_LP) ? TEGRA_POWER_CLUSTER_LP :
1334 TEGRA_POWER_CLUSTER_G;
1336 if (p == c->parent) {
1337 if (flags & TEGRA_POWER_CLUSTER_FORCE) {
1338 /* Allow parameterized switch to the same mode */
1339 ret = tegra_cluster_control(delay, flags);
1341 pr_err("%s: Failed to force %s mode to %s\n",
1342 __func__, c->name, p->name);
1345 return 0; /* already switched - exit */
1348 if (c->parent->parent->parent == dfll) {
1349 /* G (DFLL selected as clock source) => LP switch:
1350 * turn DFLL into open loop mode ("release" VDD_CPU rail)
1351 * select target p_source for LP, and get its rate ready
1353 ret = tegra_clk_cfg_ex(dfll, TEGRA_CLK_DFLL_LOCK, 0);
1357 p_source = rate <= p->u.cpu.backup_rate ?
1358 p->u.cpu.backup : p->u.cpu.main;
1359 ret = clk_set_rate(p_source, rate);
1362 } else if (p->parent->parent == dfll) {
1363 /* LP => G (DFLL selected as clock source) switch:
1364 * set DFLL rate ready (DFLL is still disabled)
1365 * (set target p_source as dfll, G source is already selected)
1368 ret = clk_set_rate(p_source, rate);
1372 /* DFLL is not selcted on either side of the switch:
1373 * set target p_source equal to current clock source
1375 p_source = c->parent->parent->parent;
1377 /* Switch new parent to target clock source if necessary */
1378 if (p->parent->parent != p_source) {
1379 ret = clk_set_parent(p->parent, p_source);
1381 pr_err("%s: Failed to set parent %s for %s\n",
1382 __func__, p_source->name, p->name);
1387 /* Enabling new parent scales new mode voltage rail in advanvce
1388 before the switch happens (if p_source is DFLL: open loop mode) */
1392 /* switch CPU mode */
1393 ret = tegra_cluster_control(delay, flags);
1397 pr_err("%s: Failed to switch %s mode to %s\n",
1398 __func__, c->name, p->name);
1402 /* Disabling old parent scales old mode voltage rail */
1403 if (c->refcnt && c->parent)
1404 clk_disable(c->parent);
1408 /* Lock DFLL now (resume closed loop VDD_CPU control) */
1409 if (p_source == dfll)
1410 tegra_clk_cfg_ex(dfll, TEGRA_CLK_DFLL_LOCK, 1);
1415 /* Re-lock DFLL if necessary after aborted switch */
1416 if (c->parent->parent->parent == dfll)
1417 tegra_clk_cfg_ex(dfll, TEGRA_CLK_DFLL_LOCK, 1);
1421 static long tegra11_cpu_cmplx_round_rate(struct clk *c,
1424 return clk_round_rate(c->parent, rate);
1427 static struct clk_ops tegra_cpu_cmplx_ops = {
1428 .init = tegra11_cpu_cmplx_clk_init,
1429 .enable = tegra11_cpu_cmplx_clk_enable,
1430 .disable = tegra11_cpu_cmplx_clk_disable,
1431 .set_rate = tegra11_cpu_cmplx_clk_set_rate,
1432 .set_parent = tegra11_cpu_cmplx_clk_set_parent,
1433 .round_rate = tegra11_cpu_cmplx_round_rate,
1436 /* virtual cop clock functions. Used to acquire the fake 'cop' clock to
1437 * reset the COP block (i.e. AVP) */
1438 static void tegra11_cop_clk_reset(struct clk *c, bool assert)
1440 unsigned long reg = assert ? RST_DEVICES_SET_L : RST_DEVICES_CLR_L;
1442 pr_debug("%s %s\n", __func__, assert ? "assert" : "deassert");
1443 clk_writel(1 << 1, reg);
1446 static struct clk_ops tegra_cop_ops = {
1447 .reset = tegra11_cop_clk_reset,
1450 /* bus clock functions */
1451 static void tegra11_bus_clk_init(struct clk *c)
1453 u32 val = clk_readl(c->reg);
1454 c->state = ((val >> c->reg_shift) & BUS_CLK_DISABLE) ? OFF : ON;
1455 c->div = ((val >> c->reg_shift) & BUS_CLK_DIV_MASK) + 1;
1459 static int tegra11_bus_clk_enable(struct clk *c)
1461 u32 val = clk_readl(c->reg);
1462 val &= ~(BUS_CLK_DISABLE << c->reg_shift);
1463 clk_writel(val, c->reg);
1467 static void tegra11_bus_clk_disable(struct clk *c)
1469 u32 val = clk_readl(c->reg);
1470 val |= BUS_CLK_DISABLE << c->reg_shift;
1471 clk_writel(val, c->reg);
1474 static int tegra11_bus_clk_set_rate(struct clk *c, unsigned long rate)
1476 u32 val = clk_readl(c->reg);
1477 unsigned long parent_rate = clk_get_rate(c->parent);
1479 for (i = 1; i <= 4; i++) {
1480 if (rate >= parent_rate / i) {
1481 val &= ~(BUS_CLK_DIV_MASK << c->reg_shift);
1482 val |= (i - 1) << c->reg_shift;
1483 clk_writel(val, c->reg);
1492 static struct clk_ops tegra_bus_ops = {
1493 .init = tegra11_bus_clk_init,
1494 .enable = tegra11_bus_clk_enable,
1495 .disable = tegra11_bus_clk_disable,
1496 .set_rate = tegra11_bus_clk_set_rate,
1499 /* Virtual system bus complex clock is used to hide the sequence of
1500 changing sclk/hclk/pclk parents and dividers to configure requested
1501 sclk target rate. */
1502 static void tegra11_sbus_cmplx_init(struct clk *c)
1506 c->max_rate = c->parent->max_rate;
1507 c->min_rate = c->parent->min_rate;
1509 /* Threshold must be an exact proper factor of low range parent,
1510 and both low/high range parents have 7.1 fractional dividers */
1511 rate = clk_get_rate(c->u.system.sclk_low->parent);
1512 if (c->u.system.threshold) {
1513 BUG_ON(c->u.system.threshold > rate) ;
1514 BUG_ON((rate % c->u.system.threshold) != 0);
1516 BUG_ON(!(c->u.system.sclk_low->flags & DIV_U71));
1517 BUG_ON(!(c->u.system.sclk_high->flags & DIV_U71));
1520 /* This special sbus round function is implemented because:
1522 * (a) sbus complex clock source is selected automatically based on rate
1524 * (b) since sbus is a shared bus, and its frequency is set to the highest
1525 * enabled shared_bus_user clock, the target rate should be rounded up divider
1526 * ladder (if max limit allows it) - for pll_div and peripheral_div common is
1527 * rounding down - special case again.
1529 * Note that final rate is trimmed (not rounded up) to avoid spiraling up in
1530 * recursive calls. Lost 1Hz is added in tegra11_sbus_cmplx_set_rate before
1531 * actually setting divider rate.
1533 static long tegra11_sbus_cmplx_round_rate(struct clk *c, unsigned long rate)
1536 unsigned long source_rate, round_rate;
1537 struct clk *new_parent;
1539 rate = max(rate, c->min_rate);
1541 new_parent = (rate <= c->u.system.threshold) ?
1542 c->u.system.sclk_low : c->u.system.sclk_high;
1543 source_rate = clk_get_rate(new_parent->parent);
1545 divider = clk_div71_get_divider(source_rate, rate,
1546 new_parent->flags, ROUND_DIVIDER_DOWN);
1553 round_rate = source_rate * 2 / (divider + 2);
1554 if (round_rate > c->max_rate) {
1555 divider = max(2, (divider + 1));
1556 round_rate = source_rate * 2 / (divider + 2);
1559 if (new_parent == c->u.system.sclk_high) {
1560 /* Prevent oscillation across threshold */
1561 if (round_rate <= c->u.system.threshold)
1562 round_rate = c->u.system.threshold;
1567 static int tegra11_sbus_cmplx_set_rate(struct clk *c, unsigned long rate)
1570 struct clk *new_parent;
1572 /* - select the appropriate sclk parent
1573 - keep hclk at the same rate as sclk
1574 - set pclk at 1:2 rate of hclk unless pclk minimum is violated,
1575 in the latter case switch to 1:1 ratio */
1577 if (rate >= c->u.system.pclk->min_rate * 2) {
1578 ret = clk_set_div(c->u.system.pclk, 2);
1580 pr_err("Failed to set 1 : 2 pclk divider\n");
1585 new_parent = (rate <= c->u.system.threshold) ?
1586 c->u.system.sclk_low : c->u.system.sclk_high;
1588 ret = clk_set_rate(new_parent, rate + 1);
1590 pr_err("Failed to set sclk source %s to %lu\n",
1591 new_parent->name, rate);
1595 if (new_parent != clk_get_parent(c->parent)) {
1596 ret = clk_set_parent(c->parent, new_parent);
1598 pr_err("Failed to switch sclk source to %s\n",
1604 if (rate < c->u.system.pclk->min_rate * 2) {
1605 ret = clk_set_div(c->u.system.pclk, 1);
1607 pr_err("Failed to set 1 : 1 pclk divider\n");
1615 static int tegra11_clk_sbus_update(struct clk *bus)
1617 unsigned long rate, old_rate;
1619 if (detach_shared_bus)
1622 rate = tegra11_clk_shared_bus_update(bus, NULL, NULL);
1623 rate = clk_round_rate_locked(bus, rate);
1625 old_rate = clk_get_rate_locked(bus);
1626 if (rate == old_rate)
1629 return clk_set_rate_locked(bus, rate);
1632 static struct clk_ops tegra_sbus_cmplx_ops = {
1633 .init = tegra11_sbus_cmplx_init,
1634 .set_rate = tegra11_sbus_cmplx_set_rate,
1635 .round_rate = tegra11_sbus_cmplx_round_rate,
1636 .shared_bus_update = tegra11_clk_sbus_update,
1639 /* Blink output functions */
1641 static void tegra11_blink_clk_init(struct clk *c)
1645 val = pmc_readl(PMC_CTRL);
1646 c->state = (val & PMC_CTRL_BLINK_ENB) ? ON : OFF;
1648 val = pmc_readl(c->reg);
1650 if (val & PMC_BLINK_TIMER_ENB) {
1651 unsigned int on_off;
1653 on_off = (val >> PMC_BLINK_TIMER_DATA_ON_SHIFT) &
1654 PMC_BLINK_TIMER_DATA_ON_MASK;
1655 val >>= PMC_BLINK_TIMER_DATA_OFF_SHIFT;
1656 val &= PMC_BLINK_TIMER_DATA_OFF_MASK;
1658 /* each tick in the blink timer is 4 32KHz clocks */
1659 c->div = on_off * 4;
1665 static int tegra11_blink_clk_enable(struct clk *c)
1669 val = pmc_readl(PMC_DPD_PADS_ORIDE);
1670 pmc_writel(val | PMC_DPD_PADS_ORIDE_BLINK_ENB, PMC_DPD_PADS_ORIDE);
1672 val = pmc_readl(PMC_CTRL);
1673 pmc_writel(val | PMC_CTRL_BLINK_ENB, PMC_CTRL);
1678 static void tegra11_blink_clk_disable(struct clk *c)
1682 val = pmc_readl(PMC_CTRL);
1683 pmc_writel(val & ~PMC_CTRL_BLINK_ENB, PMC_CTRL);
1685 val = pmc_readl(PMC_DPD_PADS_ORIDE);
1686 pmc_writel(val & ~PMC_DPD_PADS_ORIDE_BLINK_ENB, PMC_DPD_PADS_ORIDE);
1689 static int tegra11_blink_clk_set_rate(struct clk *c, unsigned long rate)
1691 unsigned long parent_rate = clk_get_rate(c->parent);
1692 if (rate >= parent_rate) {
1694 pmc_writel(0, c->reg);
1696 unsigned int on_off;
1699 on_off = DIV_ROUND_UP(parent_rate / 8, rate);
1700 c->div = on_off * 8;
1702 val = (on_off & PMC_BLINK_TIMER_DATA_ON_MASK) <<
1703 PMC_BLINK_TIMER_DATA_ON_SHIFT;
1704 on_off &= PMC_BLINK_TIMER_DATA_OFF_MASK;
1705 on_off <<= PMC_BLINK_TIMER_DATA_OFF_SHIFT;
1707 val |= PMC_BLINK_TIMER_ENB;
1708 pmc_writel(val, c->reg);
1714 static struct clk_ops tegra_blink_clk_ops = {
1715 .init = &tegra11_blink_clk_init,
1716 .enable = &tegra11_blink_clk_enable,
1717 .disable = &tegra11_blink_clk_disable,
1718 .set_rate = &tegra11_blink_clk_set_rate,
1722 static int tegra11_pll_clk_wait_for_lock(
1723 struct clk *c, u32 lock_reg, u32 lock_bits)
1725 #ifndef CONFIG_TEGRA_SIMULATION_PLATFORM
1726 #if USE_PLL_LOCK_BITS
1728 for (i = 0; i < (c->u.pll.lock_delay / PLL_PRE_LOCK_DELAY + 1); i++) {
1729 udelay(PLL_PRE_LOCK_DELAY);
1730 if ((clk_readl(lock_reg) & lock_bits) == lock_bits) {
1731 udelay(PLL_POST_LOCK_DELAY);
1735 pr_err("Timed out waiting for lock bit on pll %s\n", c->name);
1738 udelay(c->u.pll.lock_delay);
1743 static void usb_plls_hw_control_enable(u32 reg)
1745 u32 val = clk_readl(reg);
1746 val |= USB_PLLS_USE_LOCKDET;
1747 val &= ~USB_PLLS_ENABLE_SWCTL;
1748 val |= USB_PLLS_SEQ_START_STATE;
1749 pll_writel_delay(val, reg);
1751 val |= USB_PLLS_SEQ_ENABLE;
1752 pll_writel_delay(val, reg);
1755 static void tegra11_utmi_param_configure(struct clk *c)
1759 unsigned long main_rate =
1760 clk_get_rate(c->parent->parent);
1762 for (i = 0; i < ARRAY_SIZE(utmi_parameters); i++) {
1763 if (main_rate == utmi_parameters[i].osc_frequency) {
1768 if (i >= ARRAY_SIZE(utmi_parameters)) {
1769 pr_err("%s: Unexpected main rate %lu\n", __func__, main_rate);
1773 reg = clk_readl(UTMIP_PLL_CFG2);
1775 /* Program UTMIP PLL stable and active counts */
1776 /* [FIXME] arclk_rst.h says WRONG! This should be 1ms -> 0x50 Check! */
1777 reg &= ~UTMIP_PLL_CFG2_STABLE_COUNT(~0);
1778 reg |= UTMIP_PLL_CFG2_STABLE_COUNT(
1779 utmi_parameters[i].stable_count);
1781 reg &= ~UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(~0);
1783 reg |= UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(
1784 utmi_parameters[i].active_delay_count);
1786 /* Remove power downs from UTMIP PLL control bits */
1787 reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN;
1788 reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN;
1789 reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN;
1791 clk_writel(reg, UTMIP_PLL_CFG2);
1793 /* Program UTMIP PLL delay and oscillator frequency counts */
1794 reg = clk_readl(UTMIP_PLL_CFG1);
1795 reg &= ~UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(~0);
1797 reg |= UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(
1798 utmi_parameters[i].enable_delay_count);
1800 reg &= ~UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(~0);
1801 reg |= UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(
1802 utmi_parameters[i].xtal_freq_count);
1804 /* Remove power downs from UTMIP PLL control bits */
1805 reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN;
1806 reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN;
1807 reg &= ~UTMIP_PLL_CFG1_FORCE_PLLU_POWERUP;
1808 reg &= ~UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN;
1809 clk_writel(reg, UTMIP_PLL_CFG1);
1811 /* Setup HW control of UTMIPLL */
1812 reg = clk_readl(UTMIPLL_HW_PWRDN_CFG0);
1813 reg |= UTMIPLL_HW_PWRDN_CFG0_USE_LOCKDET;
1814 reg &= ~UTMIPLL_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL;
1815 reg |= UTMIPLL_HW_PWRDN_CFG0_SEQ_START_STATE;
1816 clk_writel(reg, UTMIPLL_HW_PWRDN_CFG0);
1818 reg = clk_readl(UTMIP_PLL_CFG1);
1819 reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERUP;
1820 reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN;
1821 clk_writel(reg, UTMIP_PLL_CFG1);
1825 /* Setup SW override of UTMIPLL assuming USB2.0
1826 ports are assigned to USB2 */
1827 reg = clk_readl(UTMIPLL_HW_PWRDN_CFG0);
1828 reg |= UTMIPLL_HW_PWRDN_CFG0_IDDQ_SWCTL;
1829 reg &= ~UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE;
1830 clk_writel(reg, UTMIPLL_HW_PWRDN_CFG0);
1834 /* Enable HW control UTMIPLL */
1835 reg = clk_readl(UTMIPLL_HW_PWRDN_CFG0);
1836 reg |= UTMIPLL_HW_PWRDN_CFG0_SEQ_ENABLE;
1837 clk_writel(reg, UTMIPLL_HW_PWRDN_CFG0);
1840 static void tegra11_pll_clk_init(struct clk *c)
1842 u32 val = clk_readl(c->reg + PLL_BASE);
1844 c->state = (val & PLL_BASE_ENABLE) ? ON : OFF;
1846 if (c->flags & PLL_FIXED && !(val & PLL_BASE_OVERRIDE)) {
1847 const struct clk_pll_freq_table *sel;
1848 unsigned long input_rate = clk_get_rate(c->parent);
1849 c->u.pll.fixed_rate = PLLP_DEFAULT_FIXED_RATE;
1851 for (sel = c->u.pll.freq_table; sel->input_rate != 0; sel++) {
1852 if (sel->input_rate == input_rate &&
1853 sel->output_rate == c->u.pll.fixed_rate) {
1855 c->div = sel->m * sel->p;
1859 pr_err("Clock %s has unknown fixed frequency\n", c->name);
1861 } else if (val & PLL_BASE_BYPASS) {
1865 c->mul = (val & PLL_BASE_DIVN_MASK) >> PLL_BASE_DIVN_SHIFT;
1866 c->div = (val & PLL_BASE_DIVM_MASK) >> PLL_BASE_DIVM_SHIFT;
1867 if (c->flags & PLLU)
1868 c->div *= (val & PLLU_BASE_POST_DIV) ? 1 : 2;
1870 c->div *= (0x1 << ((val & PLL_BASE_DIVP_MASK) >>
1871 PLL_BASE_DIVP_SHIFT));
1874 if (c->flags & PLL_FIXED) {
1875 c->u.pll.fixed_rate = clk_get_rate_locked(c);
1878 if (c->flags & PLLU) {
1879 /* Configure UTMI PLL power management */
1880 tegra11_utmi_param_configure(c);
1882 /* Put PLLU under h/w control */
1883 usb_plls_hw_control_enable(PLLU_HW_PWRDN_CFG0);
1885 val = clk_readl(c->reg + PLL_BASE);
1886 val &= ~PLLU_BASE_OVERRIDE;
1887 clk_writel(val, c->reg + PLL_BASE);
1891 static int tegra11_pll_clk_enable(struct clk *c)
1894 pr_debug("%s on clock %s\n", __func__, c->name);
1896 #if USE_PLL_LOCK_BITS
1897 val = clk_readl(c->reg + PLL_MISC(c));
1898 val |= PLL_MISC_LOCK_ENABLE(c);
1899 clk_writel(val, c->reg + PLL_MISC(c));
1901 val = clk_readl(c->reg + PLL_BASE);
1902 val &= ~PLL_BASE_BYPASS;
1903 val |= PLL_BASE_ENABLE;
1904 clk_writel(val, c->reg + PLL_BASE);
1906 tegra11_pll_clk_wait_for_lock(c, c->reg + PLL_BASE, PLL_BASE_LOCK);
1911 static void tegra11_pll_clk_disable(struct clk *c)
1914 pr_debug("%s on clock %s\n", __func__, c->name);
1916 val = clk_readl(c->reg);
1917 val &= ~(PLL_BASE_BYPASS | PLL_BASE_ENABLE);
1918 clk_writel(val, c->reg);
1921 static int tegra11_pll_clk_set_rate(struct clk *c, unsigned long rate)
1923 u32 val, p_div, old_base;
1924 unsigned long input_rate;
1925 const struct clk_pll_freq_table *sel;
1926 struct clk_pll_freq_table cfg;
1928 pr_debug("%s: %s %lu\n", __func__, c->name, rate);
1930 if (c->flags & PLL_FIXED) {
1932 if (rate != c->u.pll.fixed_rate) {
1933 pr_err("%s: Can not change %s fixed rate %lu to %lu\n",
1934 __func__, c->name, c->u.pll.fixed_rate, rate);
1941 input_rate = clk_get_rate(c->parent);
1943 /* Check if the target rate is tabulated */
1944 for (sel = c->u.pll.freq_table; sel->input_rate != 0; sel++) {
1945 if (sel->input_rate == input_rate && sel->output_rate == rate) {
1946 if (c->flags & PLLU) {
1947 BUG_ON(sel->p < 1 || sel->p > 2);
1949 p_div = PLLU_BASE_POST_DIV;
1952 for (val = sel->p; val > 1; val >>= 1, p_div++);
1953 p_div <<= PLL_BASE_DIVP_SHIFT;
1959 /* Configure out-of-table rate */
1960 if (sel->input_rate == 0) {
1961 unsigned long cfreq, vco;
1962 BUG_ON(c->flags & PLLU);
1965 switch (input_rate) {
1968 cfreq = (rate <= 1000000 * 1000) ? 1000000 : 2000000;
1971 cfreq = (rate <= 1000000 * 1000) ? 1000000 : 2600000;
1975 cfreq = (rate <= 1200000 * 1000) ? 1200000 : 2400000;
1978 if (c->parent->flags & DIV_U71_FIXED) {
1979 /* PLLP_OUT1 rate is not in PLLA table */
1980 pr_warn("%s: failed %s ref/out rates %lu/%lu\n",
1981 __func__, c->name, input_rate, rate);
1982 cfreq = input_rate/(input_rate/1000000);
1985 pr_err("%s: Unexpected reference rate %lu\n",
1986 __func__, input_rate);
1990 /* Raise VCO to guarantee 0.5% accuracy, and vco min boundary */
1991 vco = max(200 * cfreq, c->u.pll.vco_min);
1992 for (cfg.output_rate = rate; cfg.output_rate < vco; p_div++)
1993 cfg.output_rate <<= 1;
1995 cfg.p = 0x1 << p_div;
1996 cfg.m = input_rate / cfreq;
1997 cfg.n = cfg.output_rate / cfreq;
1998 cfg.cpcon = c->u.pll.cpcon_default ? : OUT_OF_TABLE_CPCON;
2000 if ((cfg.m > (PLL_BASE_DIVM_MASK >> PLL_BASE_DIVM_SHIFT)) ||
2001 (cfg.n > (PLL_BASE_DIVN_MASK >> PLL_BASE_DIVN_SHIFT)) ||
2002 (p_div > (PLL_BASE_DIVP_MASK >> PLL_BASE_DIVP_SHIFT)) ||
2003 (cfg.output_rate > c->u.pll.vco_max)) {
2004 pr_err("%s: Failed to set %s out-of-table rate %lu\n",
2005 __func__, c->name, rate);
2008 p_div <<= PLL_BASE_DIVP_SHIFT;
2012 c->div = sel->m * sel->p;
2014 old_base = val = clk_readl(c->reg + PLL_BASE);
2015 val &= ~(PLL_BASE_DIVM_MASK | PLL_BASE_DIVN_MASK |
2016 ((c->flags & PLLU) ? PLLU_BASE_POST_DIV : PLL_BASE_DIVP_MASK));
2017 val |= (sel->m << PLL_BASE_DIVM_SHIFT) |
2018 (sel->n << PLL_BASE_DIVN_SHIFT) | p_div;
2019 if (val == old_base)
2022 if (c->state == ON) {
2023 tegra11_pll_clk_disable(c);
2024 val &= ~(PLL_BASE_BYPASS | PLL_BASE_ENABLE);
2026 clk_writel(val, c->reg + PLL_BASE);
2028 if (c->flags & PLL_HAS_CPCON) {
2029 val = clk_readl(c->reg + PLL_MISC(c));
2030 val &= ~PLL_MISC_CPCON_MASK;
2031 val |= sel->cpcon << PLL_MISC_CPCON_SHIFT;
2032 if (c->flags & (PLLU | PLLD)) {
2033 val &= ~PLL_MISC_LFCON_MASK;
2034 val |= PLLDU_LFCON << PLL_MISC_LFCON_SHIFT;
2036 clk_writel(val, c->reg + PLL_MISC(c));
2040 tegra11_pll_clk_enable(c);
2045 static struct clk_ops tegra_pll_ops = {
2046 .init = tegra11_pll_clk_init,
2047 .enable = tegra11_pll_clk_enable,
2048 .disable = tegra11_pll_clk_disable,
2049 .set_rate = tegra11_pll_clk_set_rate,
2052 static void tegra11_pllp_clk_init(struct clk *c)
2054 tegra11_pll_clk_init(c);
2055 tegra11_pllp_init_dependencies(c->u.pll.fixed_rate);
2058 #ifdef CONFIG_PM_SLEEP
2059 static void tegra11_pllp_clk_resume(struct clk *c)
2061 unsigned long rate = c->u.pll.fixed_rate;
2062 tegra11_pll_clk_init(c);
2063 BUG_ON(rate != c->u.pll.fixed_rate);
2067 static struct clk_ops tegra_pllp_ops = {
2068 .init = tegra11_pllp_clk_init,
2069 .enable = tegra11_pll_clk_enable,
2070 .disable = tegra11_pll_clk_disable,
2071 .set_rate = tegra11_pll_clk_set_rate,
2075 tegra11_plld_clk_cfg_ex(struct clk *c, enum tegra_clk_ex_param p, u32 setting)
2080 case TEGRA_CLK_PLLD_CSI_OUT_ENB:
2081 mask = PLLD_BASE_CSI_CLKENABLE | PLLD_BASE_CSI_CLKSOURCE;
2082 reg = c->reg + PLL_BASE;
2084 case TEGRA_CLK_PLLD_DSI_OUT_ENB:
2085 mask = PLLD_MISC_DSI_CLKENABLE;
2086 reg = c->reg + PLL_MISC(c);
2088 case TEGRA_CLK_PLLD_MIPI_MUX_SEL:
2089 mask = PLLD_BASE_DSI_MUX_MASK;
2090 reg = c->reg + PLL_BASE;
2096 val = clk_readl(reg);
2101 clk_writel(val, reg);
2105 static struct clk_ops tegra_plld_ops = {
2106 .init = tegra11_pll_clk_init,
2107 .enable = tegra11_pll_clk_enable,
2108 .disable = tegra11_pll_clk_disable,
2109 .set_rate = tegra11_pll_clk_set_rate,
2110 .clk_cfg_ex = tegra11_plld_clk_cfg_ex,
2114 * Dynamic ramp PLLs:
2115 * PLLC2 and PLLC3 (PLLCX)
2116 * PLLX and PLLC (PLLXC)
2118 * When scaling PLLC and PLLX, dynamic ramp is allowed for any transition that
2119 * changes NDIV only. As a matter of policy we will make sure that switching
2120 * between output rates above VCO minimum is always dynamic. The pre-requisite
2121 * for the above guarantee is the following configuration convention:
2122 * - pll configured with fixed MDIV
2123 * - when output rate is above VCO minimum PDIV = 0 (p-value = 1)
2124 * Switching between output rates below VCO minimum may or may not be dynamic,
2125 * and switching across VCO minimum is never dynamic.
2127 * PLLC2 and PLLC3 in addition to dynamic ramp mechanism have also glitchless
2128 * output dividers. However dynamic ramp without overshoot is guaranteed only
2129 * when output divisor is less or equal 8.
2131 * Of course, dynamic ramp is applied provided PLL is already enabled.
2135 * Common configuration policy for dynamic ramp PLLs:
2136 * - always set fixed M-value based on the reference rate
2137 * - always set P-value value 1:1 for output rates above VCO minimum, and
2138 * choose minimum necessary P-value for output rates below VCO minimum
2139 * - calculate N-value based on selected M and P
2141 static int pll_dyn_ramp_cfg(struct clk *c, struct clk_pll_freq_table *cfg,
2142 unsigned long rate, unsigned long input_rate, u32 *pdiv)
2149 p = DIV_ROUND_UP(c->u.pll.vco_min, rate);
2150 p = c->u.pll.round_p_to_pdiv(p, pdiv);
2151 if (IS_ERR_VALUE(p))
2154 cfg->m = PLL_FIXED_MDIV(c, input_rate);
2156 cfg->output_rate = rate * cfg->p;
2157 cfg->n = cfg->output_rate * cfg->m / input_rate;
2159 /* can use PLLCX N-divider field layout for all dynamic ramp PLLs */
2160 if ((cfg->n > (PLLCX_BASE_DIVN_MASK >> PLL_BASE_DIVN_SHIFT)) ||
2161 (cfg->output_rate > c->u.pll.vco_max))
2167 static int pll_dyn_ramp_find_cfg(struct clk *c, struct clk_pll_freq_table *cfg,
2168 unsigned long rate, unsigned long input_rate, u32 *pdiv)
2170 const struct clk_pll_freq_table *sel;
2172 /* Check if the target rate is tabulated */
2173 for (sel = c->u.pll.freq_table; sel->input_rate != 0; sel++) {
2174 if (sel->input_rate == input_rate && sel->output_rate == rate) {
2175 u32 p = c->u.pll.round_p_to_pdiv(sel->p, pdiv);
2176 BUG_ON(IS_ERR_VALUE(p));
2177 BUG_ON(sel->m != PLL_FIXED_MDIV(c, input_rate));
2183 /* Configure out-of-table rate */
2184 if (pll_dyn_ramp_cfg(c, cfg, rate, input_rate, pdiv)) {
2185 pr_err("%s: Failed to set %s out-of-table rate %lu\n",
2186 __func__, c->name, rate);
2192 static inline void pll_do_iddq(struct clk *c, u32 offs, u32 iddq_bit, bool set)
2194 u32 val = clk_readl(c->reg + offs);
2199 clk_writel_delay(val, c->reg + offs);
2203 static u8 pllcx_p[PLLCX_PDIV_MAX + 1] = {
2204 /* PDIV: 0, 1, 2, 3, 4, 5, 6, 7 */
2205 /* p: */ 1, 2, 3, 4, 6, 8, 12, 16 };
2207 static u32 pllcx_round_p_to_pdiv(u32 p, u32 *pdiv)
2212 for (i = 0; i <= PLLCX_PDIV_MAX; i++) {
2213 /* Do not use DIV3 p values - mapped to even PDIV */
2214 if (i && ((i & 0x1) == 0))
2217 if (p <= pllcx_p[i]) {
2227 static void pllcx_update_dynamic_koef(struct clk *c, unsigned long input_rate,
2230 u32 val, n_threshold;
2232 switch (input_rate) {
2247 pr_err("%s: Unexpected reference rate %lu\n",
2248 __func__, input_rate);
2253 val = clk_readl(c->reg + PLL_MISC(c));
2254 val &= ~(PLLCX_MISC_SDM_DIV_MASK | PLLCX_MISC_FILT_DIV_MASK);
2255 val |= n <= n_threshold ?
2256 PLLCX_MISC_DIV_LOW_RANGE : PLLCX_MISC_DIV_HIGH_RANGE;
2257 clk_writel(val, c->reg + PLL_MISC(c));
2260 static void pllcx_strobe(struct clk *c)
2262 u32 reg = c->reg + PLL_MISC(c);
2263 u32 val = clk_readl(reg);
2265 val |= PLLCX_MISC_STROBE;
2266 pll_writel_delay(val, reg);
2268 val &= ~PLLCX_MISC_STROBE;
2269 clk_writel(val, reg);
2272 static void pllcx_set_defaults(struct clk *c, unsigned long input_rate, u32 n)
2274 clk_writel(PLLCX_MISC_DEFAULT_VALUE, c->reg + PLL_MISC(c));
2275 clk_writel(PLLCX_MISC1_DEFAULT_VALUE, c->reg + PLL_MISCN(c, 1));
2276 clk_writel(PLLCX_MISC2_DEFAULT_VALUE, c->reg + PLL_MISCN(c, 2));
2277 clk_writel(PLLCX_MISC3_DEFAULT_VALUE, c->reg + PLL_MISCN(c, 3));
2279 pllcx_update_dynamic_koef(c, input_rate, n);
2282 static void tegra11_pllcx_clk_init(struct clk *c)
2284 unsigned long input_rate = clk_get_rate(c->parent);
2287 /* clip vco_min to exact multiple of input rate to avoid crossover
2290 DIV_ROUND_UP(c->u.pll.vco_min, input_rate) * input_rate;
2291 c->min_rate = DIV_ROUND_UP(c->u.pll.vco_min, pllcx_p[PLLCX_PDIV_MAX]);
2293 val = clk_readl(c->reg + PLL_BASE);
2294 c->state = (val & PLL_BASE_ENABLE) ? ON : OFF;
2297 * PLLCX is not a boot PLL, it should be left disabled by boot-loader,
2298 * and no enabled module clocks should use it as a source during clock
2301 #ifndef CONFIG_TEGRA_SIMULATION_PLATFORM
2302 BUG_ON(c->state == ON);
2305 * Most of PLLCX register fields are shadowed, and can not be read
2306 * directly from PLL h/w. Hence, actual PLLCX boot state is unknown.
2307 * Initialize PLL to default state: disabled, reset; shadow registers
2308 * loaded with default parameters; dividers are preset for half of
2309 * minimum VCO rate (the latter assured that shadowed divider settings
2310 * are within supported range).
2312 m = PLL_FIXED_MDIV(c, input_rate);
2313 n = m * c->u.pll.vco_min / input_rate;
2315 val = (m << PLL_BASE_DIVM_SHIFT) | (n << PLL_BASE_DIVN_SHIFT) |
2316 (1 << PLL_BASE_DIVP_SHIFT);
2317 clk_writel(val, c->reg + PLL_BASE); /* PLL disabled */
2319 pllcx_set_defaults(c, input_rate, n);
2325 static int tegra11_pllcx_clk_enable(struct clk *c)
2328 pr_debug("%s on clock %s\n", __func__, c->name);
2330 val = clk_readl(c->reg + PLL_BASE);
2331 val &= ~PLL_BASE_BYPASS;
2332 val |= PLL_BASE_ENABLE;
2333 pll_writel_delay(val, c->reg + PLL_BASE);
2335 val = clk_readl(c->reg + PLL_MISC(c));
2336 val &= ~PLLCX_MISC_RESET;
2337 pll_writel_delay(val, c->reg + PLL_MISC(c));
2340 tegra11_pll_clk_wait_for_lock(c, c->reg + PLL_BASE,
2341 PLL_BASE_LOCK | PLLCX_BASE_PHASE_LOCK);
2345 static void tegra11_pllcx_clk_disable(struct clk *c)
2348 pr_debug("%s on clock %s\n", __func__, c->name);
2350 val = clk_readl(c->reg);
2351 val &= ~(PLL_BASE_BYPASS | PLL_BASE_ENABLE);
2352 clk_writel(val, c->reg);
2354 val = clk_readl(c->reg + PLL_MISC(c));
2355 val |= PLLCX_MISC_RESET;
2356 pll_writel_delay(val, c->reg + PLL_MISC(c));
2359 static int tegra11_pllcx_clk_set_rate(struct clk *c, unsigned long rate)
2362 unsigned long input_rate;
2363 struct clk_pll_freq_table cfg, old_cfg;
2364 const struct clk_pll_freq_table *sel = &cfg;
2366 pr_debug("%s: %s %lu\n", __func__, c->name, rate);
2368 input_rate = clk_get_rate(c->parent);
2370 if (pll_dyn_ramp_find_cfg(c, &cfg, rate, input_rate, &pdiv))
2374 c->div = sel->m * sel->p;
2376 val = clk_readl(c->reg + PLL_BASE);
2377 PLL_BASE_PARSE(PLLCX, old_cfg, val);
2378 old_cfg.p = pllcx_p[old_cfg.p];
2380 BUG_ON(old_cfg.m != sel->m);
2381 if ((sel->n == old_cfg.n) && (sel->p == old_cfg.p))
2384 #if PLLCX_USE_DYN_RAMP
2385 if (c->state == ON && ((sel->n == old_cfg.n) ||
2386 PLLCX_IS_DYN(sel->p, old_cfg.p))) {
2388 * Dynamic ramp if PLL is enabled, and M divider is unchanged:
2389 * - Change P divider 1st if intermediate rate is below either
2391 * - Change N divider with DFS strobe - target rate is either
2392 * final new rate or below old rate
2393 * - If divider has been changed, exit without waiting for lock.
2394 * Otherwise, wait for lock and change divider.
2396 if (sel->p > old_cfg.p) {
2397 val &= ~PLLCX_BASE_DIVP_MASK;
2398 val |= pdiv << PLL_BASE_DIVP_SHIFT;
2399 clk_writel(val, c->reg + PLL_BASE);
2402 if (sel->n != old_cfg.n) {
2403 pllcx_update_dynamic_koef(c, input_rate, sel->n);
2404 val &= ~PLLCX_BASE_DIVN_MASK;
2405 val |= sel->n << PLL_BASE_DIVN_SHIFT;
2406 pll_writel_delay(val, c->reg + PLL_BASE);
2409 tegra11_pll_clk_wait_for_lock(c, c->reg + PLL_BASE,
2410 PLL_BASE_LOCK | PLLCX_BASE_PHASE_LOCK);
2413 if (sel->p < old_cfg.p) {
2414 val &= ~PLLCX_BASE_DIVP_MASK;
2415 val |= pdiv << PLL_BASE_DIVP_SHIFT;
2416 clk_writel(val, c->reg + PLL_BASE);
2422 val &= ~(PLLCX_BASE_DIVN_MASK | PLLCX_BASE_DIVP_MASK);
2423 val |= (sel->n << PLL_BASE_DIVN_SHIFT) |
2424 (pdiv << PLL_BASE_DIVP_SHIFT);
2426 if (c->state == ON) {
2427 tegra11_pllcx_clk_disable(c);
2428 val &= ~(PLL_BASE_BYPASS | PLL_BASE_ENABLE);
2430 pllcx_update_dynamic_koef(c, input_rate, sel->n);
2431 clk_writel(val, c->reg + PLL_BASE);
2433 tegra11_pllcx_clk_enable(c);
2438 #ifdef CONFIG_PM_SLEEP
2439 static void tegra11_pllcx_clk_resume_enable(struct clk *c)
2441 unsigned long rate = clk_get_rate_all_locked(c->parent);
2442 u32 val = clk_readl(c->reg + PLL_BASE);
2443 enum clk_state state = c->state;
2445 if (val & PLL_BASE_ENABLE)
2446 return; /* already resumed */
2448 /* Restore input divider */
2449 val &= ~PLLCX_BASE_DIVM_MASK;
2450 val |= PLL_FIXED_MDIV(c, rate) << PLL_BASE_DIVM_SHIFT;
2451 clk_writel(val, c->reg + PLL_BASE);
2453 /* temporarily sync h/w and s/w states, final sync happens
2454 in tegra_clk_resume later */
2456 pllcx_set_defaults(c, rate, c->mul);
2458 rate = clk_get_rate_all_locked(c) + 1;
2459 tegra11_pllcx_clk_set_rate(c, rate);
2460 tegra11_pllcx_clk_enable(c);
2465 static struct clk_ops tegra_pllcx_ops = {
2466 .init = tegra11_pllcx_clk_init,
2467 .enable = tegra11_pllcx_clk_enable,
2468 .disable = tegra11_pllcx_clk_disable,
2469 .set_rate = tegra11_pllcx_clk_set_rate,
2473 /* non-monotonic mapping below is not a typo */
2474 static u8 pllxc_p[PLLXC_PDIV_MAX + 1] = {
2475 /* PDIV: 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 */
2476 /* p: */ 1, 2, 3, 4, 5, 6, 8, 10, 12, 16, 12, 16, 20, 24, 32 };
2478 static u32 pllxc_round_p_to_pdiv(u32 p, u32 *pdiv)
2480 if (!p || (p > PLLXC_SW_PDIV_MAX + 1))
2488 static void pllxc_get_dyn_steps(struct clk *c, unsigned long input_rate,
2489 u32 *step_a, u32 *step_b)
2491 switch (input_rate) {
2507 pr_err("%s: Unexpected reference rate %lu\n",
2508 __func__, input_rate);
2513 static void pllx_set_defaults(struct clk *c, unsigned long input_rate)
2518 /* Only s/w dyn ramp control is supported */
2519 val = clk_readl(PLLX_HW_CTRL_CFG);
2520 #ifndef CONFIG_TEGRA_SIMULATION_PLATFORM
2521 BUG_ON(!(val & PLLX_HW_CTRL_CFG_SWCTRL));
2524 pllxc_get_dyn_steps(c, input_rate, &step_a, &step_b);
2525 val = step_a << PLLX_MISC2_DYNRAMP_STEPA_SHIFT;
2526 val |= step_b << PLLX_MISC2_DYNRAMP_STEPB_SHIFT;
2528 /* Get ready dyn ramp state machine, disable lock override */
2529 clk_writel(val, c->reg + PLL_MISCN(c, 2));
2531 /* Enable outputs to CPUs and configure lock */
2533 #if USE_PLL_LOCK_BITS
2534 val |= PLL_MISC_LOCK_ENABLE(c);
2536 clk_writel(val, c->reg + PLL_MISC(c));
2538 /* Check/set IDDQ */
2539 val = clk_readl(c->reg + PLL_MISCN(c, 3));
2540 if (c->state == ON) {
2541 #ifndef CONFIG_TEGRA_SIMULATION_PLATFORM
2542 BUG_ON(val & PLLX_MISC3_IDDQ);
2545 val |= PLLX_MISC3_IDDQ;
2546 clk_writel(val, c->reg + PLL_MISCN(c, 3));
2550 static void pllc_set_defaults(struct clk *c, unsigned long input_rate)
2555 /* Get ready dyn ramp state machine */
2556 pllxc_get_dyn_steps(c, input_rate, &step_a, &step_b);
2557 val = step_a << PLLC_MISC1_DYNRAMP_STEPA_SHIFT;
2558 val |= step_b << PLLC_MISC1_DYNRAMP_STEPB_SHIFT;
2559 clk_writel(val, c->reg + PLL_MISCN(c, 1));
2561 /* Configure lock and check/set IDDQ */
2562 val = clk_readl(c->reg + PLL_BASE);
2563 val &= ~PLLC_BASE_LOCK_OVERRIDE;
2564 clk_writel(val, c->reg + PLL_BASE);
2566 val = clk_readl(c->reg + PLL_MISC(c));
2567 #if USE_PLL_LOCK_BITS
2568 val |= PLLC_MISC_LOCK_ENABLE;
2570 val &= ~PLLC_MISC_LOCK_ENABLE;
2572 clk_writel(val, c->reg + PLL_MISC(c));
2574 if (c->state == ON) {
2575 #ifndef CONFIG_TEGRA_SIMULATION_PLATFORM
2576 BUG_ON(val & PLLC_MISC_IDDQ);
2579 val |= PLLC_MISC_IDDQ;
2580 clk_writel(val, c->reg + PLL_MISC(c));
2584 static void tegra11_pllxc_clk_init(struct clk *c)
2586 unsigned long input_rate = clk_get_rate(c->parent);
2589 /* clip vco_min to exact multiple of input rate to avoid crossover
2592 DIV_ROUND_UP(c->u.pll.vco_min, input_rate) * input_rate;
2594 DIV_ROUND_UP(c->u.pll.vco_min, pllxc_p[PLLXC_SW_PDIV_MAX]);
2596 val = clk_readl(c->reg + PLL_BASE);
2597 c->state = (val & PLL_BASE_ENABLE) ? ON : OFF;
2599 m = (val & PLLXC_BASE_DIVM_MASK) >> PLL_BASE_DIVM_SHIFT;
2600 p = (val & PLLXC_BASE_DIVP_MASK) >> PLL_BASE_DIVP_SHIFT;
2601 BUG_ON(p > PLLXC_PDIV_MAX);
2605 c->mul = (val & PLLXC_BASE_DIVN_MASK) >> PLL_BASE_DIVN_SHIFT;
2607 if (c->flags & PLLX)
2608 pllx_set_defaults(c, input_rate);
2610 pllc_set_defaults(c, input_rate);
2613 static int tegra11_pllxc_clk_enable(struct clk *c)
2616 pr_debug("%s on clock %s\n", __func__, c->name);
2618 if (c->flags & PLLX)
2619 pll_do_iddq(c, PLL_MISCN(c, 3), PLLX_MISC3_IDDQ, false);
2621 pll_do_iddq(c, PLL_MISC(c), PLLC_MISC_IDDQ, false);
2623 val = clk_readl(c->reg + PLL_BASE);
2624 val |= PLL_BASE_ENABLE;
2625 clk_writel(val, c->reg + PLL_BASE);
2627 tegra11_pll_clk_wait_for_lock(c, c->reg + PLL_BASE, PLL_BASE_LOCK);
2632 static void tegra11_pllxc_clk_disable(struct clk *c)
2635 pr_debug("%s on clock %s\n", __func__, c->name);
2637 val = clk_readl(c->reg + PLL_BASE);
2638 val &= ~PLL_BASE_ENABLE;
2639 clk_writel(val, c->reg + PLL_BASE);
2641 if (c->flags & PLLX)
2642 pll_do_iddq(c, PLL_MISCN(c, 3), PLLX_MISC3_IDDQ, true);
2644 pll_do_iddq(c, PLL_MISC(c), PLLC_MISC_IDDQ, true);
2648 #define PLLXC_DYN_RAMP(pll_misc, reg) \
2650 u32 misc = clk_readl((reg)); \
2652 misc &= ~pll_misc##_NDIV_NEW_MASK; \
2653 misc |= sel->n << pll_misc##_NDIV_NEW_SHIFT; \
2654 pll_writel_delay(misc, (reg)); \
2656 misc |= pll_misc##_EN_DYNRAMP; \
2657 clk_writel(misc, (reg)); \
2658 tegra11_pll_clk_wait_for_lock(c, (reg), \
2659 pll_misc##_DYNRAMP_DONE); \
2661 val &= ~PLLXC_BASE_DIVN_MASK; \
2662 val |= sel->n << PLL_BASE_DIVN_SHIFT; \
2663 pll_writel_delay(val, c->reg + PLL_BASE); \
2665 misc &= ~pll_misc##_EN_DYNRAMP; \
2666 pll_writel_delay(misc, (reg)); \
2669 static int tegra11_pllxc_clk_set_rate(struct clk *c, unsigned long rate)
2672 unsigned long input_rate;
2673 struct clk_pll_freq_table cfg, old_cfg;
2674 const struct clk_pll_freq_table *sel = &cfg;
2676 pr_debug("%s: %s %lu\n", __func__, c->name, rate);
2678 input_rate = clk_get_rate(c->parent);
2680 if (pll_dyn_ramp_find_cfg(c, &cfg, rate, input_rate, &pdiv))
2684 c->div = sel->m * sel->p;
2686 val = clk_readl(c->reg + PLL_BASE);
2687 PLL_BASE_PARSE(PLLXC, old_cfg, val);
2688 old_cfg.p = pllxc_p[old_cfg.p];
2690 if ((sel->m == old_cfg.m) && (sel->n == old_cfg.n) &&
2691 (sel->p == old_cfg.p))
2694 #if PLLXC_USE_DYN_RAMP
2696 * Dynamic ramp can be used if M, P dividers are unchanged
2697 * (coveres superset of conventional dynamic ramps)
2699 if ((c->state == ON) && (sel->m == old_cfg.m) &&
2700 (sel->p == old_cfg.p)) {
2702 if (c->flags & PLLX) {
2703 u32 reg = c->reg + PLL_MISCN(c, 2);
2704 PLLXC_DYN_RAMP(PLLX_MISC2, reg);
2706 u32 reg = c->reg + PLL_MISCN(c, 1);
2707 PLLXC_DYN_RAMP(PLLC_MISC1, reg);
2713 if (c->state == ON) {
2714 /* Use "ENABLE" pulse without placing PLL into IDDQ */
2715 val &= ~PLL_BASE_ENABLE;
2716 pll_writel_delay(val, c->reg + PLL_BASE);
2719 val &= ~(PLLXC_BASE_DIVM_MASK |
2720 PLLXC_BASE_DIVN_MASK | PLLXC_BASE_DIVP_MASK);
2721 val |= (sel->m << PLL_BASE_DIVM_SHIFT) |
2722 (sel->n << PLL_BASE_DIVN_SHIFT) | (pdiv << PLL_BASE_DIVP_SHIFT);
2723 clk_writel(val, c->reg + PLL_BASE);
2725 if (c->state == ON) {
2726 val |= PLL_BASE_ENABLE;
2727 clk_writel(val, c->reg + PLL_BASE);
2728 tegra11_pll_clk_wait_for_lock(c, c->reg + PLL_BASE,
2734 #ifdef CONFIG_PM_SLEEP
2735 static void tegra11_pllxc_clk_resume_enable(struct clk *c)
2737 unsigned long rate = clk_get_rate_all_locked(c->parent);
2738 enum clk_state state = c->state;
2740 if (clk_readl(c->reg + PLL_BASE) & PLL_BASE_ENABLE)
2741 return; /* already resumed */
2743 /* temporarily sync h/w and s/w states, final sync happens
2744 in tegra_clk_resume later */
2746 if (c->flags & PLLX)
2747 pllx_set_defaults(c, rate);
2749 pllc_set_defaults(c, rate);
2751 rate = clk_get_rate_all_locked(c) + 1;
2752 tegra11_pllxc_clk_set_rate(c, rate);
2753 tegra11_pllxc_clk_enable(c);
2758 static struct clk_ops tegra_pllxc_ops = {
2759 .init = tegra11_pllxc_clk_init,
2760 .enable = tegra11_pllxc_clk_enable,
2761 .disable = tegra11_pllxc_clk_disable,
2762 .set_rate = tegra11_pllxc_clk_set_rate,
2766 /* FIXME: pllm suspend/resume */
2768 static u32 pllm_round_p_to_pdiv(u32 p, u32 *pdiv)
2778 static void pllm_set_defaults(struct clk *c, unsigned long input_rate)
2780 u32 val = clk_readl(c->reg + PLL_MISC(c));
2782 val &= ~PLLM_MISC_LOCK_OVERRIDE;
2783 #if USE_PLL_LOCK_BITS
2784 val &= ~PLLM_MISC_LOCK_DISABLE;
2786 val |= PLLM_MISC_LOCK_DISABLE;
2790 val |= PLLM_MISC_IDDQ;
2791 #ifndef CONFIG_TEGRA_SIMULATION_PLATFORM
2793 BUG_ON(val & PLLM_MISC_IDDQ);
2796 clk_writel(val, c->reg + PLL_MISC(c));
2799 static void tegra11_pllm_clk_init(struct clk *c)
2801 unsigned long input_rate = clk_get_rate(c->parent);
2804 /* clip vco_min to exact multiple of input rate to avoid crossover
2807 DIV_ROUND_UP(c->u.pll.vco_min, input_rate) * input_rate;
2809 DIV_ROUND_UP(c->u.pll.vco_min, 2);
2811 val = pmc_readl(PMC_PLLP_WB0_OVERRIDE);
2812 if (val & PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE) {
2813 c->state = (val & PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE) ? ON : OFF;
2814 val = pmc_readl(PMC_PLLM_WB0_OVERRIDE_2);
2815 p = (val & PMC_PLLM_WB0_OVERRIDE_2_DIVP_MASK) ? 2 : 1;
2817 val = pmc_readl(PMC_PLLM_WB0_OVERRIDE);
2819 val = clk_readl(c->reg + PLL_BASE);
2820 c->state = (val & PLL_BASE_ENABLE) ? ON : OFF;
2821 p = (val & PLLM_BASE_DIVP_MASK) ? 2 : 1;
2824 m = (val & PLLM_BASE_DIVM_MASK) >> PLL_BASE_DIVM_SHIFT;
2825 BUG_ON(m != PLL_FIXED_MDIV(c, input_rate));
2827 c->mul = (val & PLLM_BASE_DIVN_MASK) >> PLL_BASE_DIVN_SHIFT;
2829 pllm_set_defaults(c, input_rate);
2832 static int tegra11_pllm_clk_enable(struct clk *c)
2835 pr_debug("%s on clock %s\n", __func__, c->name);
2837 pll_do_iddq(c, PLL_MISC(c), PLLM_MISC_IDDQ, false);
2839 /* Just enable both base and override - one would work */
2840 val = clk_readl(c->reg + PLL_BASE);
2841 val |= PLL_BASE_ENABLE;
2842 clk_writel(val, c->reg + PLL_BASE);
2844 val = pmc_readl(PMC_PLLP_WB0_OVERRIDE);
2845 val |= PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE;
2846 pmc_writel(val, PMC_PLLP_WB0_OVERRIDE);
2847 val = pmc_readl(PMC_PLLP_WB0_OVERRIDE);
2849 tegra11_pll_clk_wait_for_lock(c, c->reg + PLL_BASE, PLL_BASE_LOCK);
2853 static void tegra11_pllm_clk_disable(struct clk *c)
2856 pr_debug("%s on clock %s\n", __func__, c->name);
2858 /* Just disable both base and override - one would work */
2859 val = pmc_readl(PMC_PLLP_WB0_OVERRIDE);
2860 val &= ~PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE;
2861 pmc_writel(val, PMC_PLLP_WB0_OVERRIDE);
2862 val = pmc_readl(PMC_PLLP_WB0_OVERRIDE);
2864 val = clk_readl(c->reg + PLL_BASE);
2865 val &= ~PLL_BASE_ENABLE;
2866 clk_writel(val, c->reg + PLL_BASE);
2868 pll_do_iddq(c, PLL_MISC(c), PLLM_MISC_IDDQ, true);
2871 static int tegra11_pllm_clk_set_rate(struct clk *c, unsigned long rate)
2874 unsigned long input_rate;
2875 struct clk_pll_freq_table cfg;
2876 const struct clk_pll_freq_table *sel = &cfg;
2878 pr_debug("%s: %s %lu\n", __func__, c->name, rate);
2880 if (c->state == ON) {
2881 if (rate != clk_get_rate_locked(c)) {
2882 pr_err("%s: Can not change memory %s rate in flight\n",
2889 input_rate = clk_get_rate(c->parent);
2891 if (pll_dyn_ramp_find_cfg(c, &cfg, rate, input_rate, &pdiv))
2895 c->div = sel->m * sel->p;
2897 val = pmc_readl(PMC_PLLP_WB0_OVERRIDE);
2898 if (val & PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE) {
2899 val = pmc_readl(PMC_PLLM_WB0_OVERRIDE_2);
2900 val = pdiv ? (val | PMC_PLLM_WB0_OVERRIDE_2_DIVP_MASK) :
2901 (val & ~PMC_PLLM_WB0_OVERRIDE_2_DIVP_MASK);
2902 pmc_writel(val, PMC_PLLM_WB0_OVERRIDE_2);
2904 val = pmc_readl(PMC_PLLM_WB0_OVERRIDE);
2905 val &= ~(PLLM_BASE_DIVM_MASK | PLLM_BASE_DIVN_MASK);
2906 val |= (sel->m << PLL_BASE_DIVM_SHIFT) |
2907 (sel->n << PLL_BASE_DIVN_SHIFT);
2908 pmc_writel(val, PMC_PLLM_WB0_OVERRIDE);
2910 val = clk_readl(c->reg + PLL_BASE);
2911 val &= ~(PLLM_BASE_DIVM_MASK | PLLM_BASE_DIVN_MASK |
2912 PLLM_BASE_DIVP_MASK);
2913 val |= (sel->m << PLL_BASE_DIVM_SHIFT) |
2914 (sel->n << PLL_BASE_DIVN_SHIFT) |
2915 (pdiv ? PLLM_BASE_DIVP_MASK : 0);
2916 clk_writel(val, c->reg + PLL_BASE);
2922 static struct clk_ops tegra_pllm_ops = {
2923 .init = tegra11_pllm_clk_init,
2924 .enable = tegra11_pllm_clk_enable,
2925 .disable = tegra11_pllm_clk_disable,
2926 .set_rate = tegra11_pllm_clk_set_rate,
2930 /* FIXME: pllre suspend/resume */
2931 /* non-monotonic mapping below is not a typo */
2932 static u8 pllre_p[PLLRE_PDIV_MAX + 1] = {
2933 /* PDIV: 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 */
2934 /* p: */ 1, 2, 3, 4, 5, 6, 8, 10, 12, 16, 12, 16, 20, 24, 32 };
2936 static u32 pllre_round_p_to_pdiv(u32 p, u32 *pdiv)
2938 if (!p || (p > PLLRE_SW_PDIV_MAX + 1))
2946 static void pllre_set_defaults(struct clk *c, unsigned long input_rate)
2948 u32 val = clk_readl(c->reg + PLL_MISC(c));
2950 val &= ~PLLRE_MISC_LOCK_OVERRIDE;
2951 #if USE_PLL_LOCK_BITS
2952 val |= PLLRE_MISC_LOCK_ENABLE;
2954 val &= ~PLLRE_MISC_LOCK_ENABLE;
2958 val |= PLLRE_MISC_IDDQ;
2959 #ifndef CONFIG_TEGRA_SIMULATION_PLATFORM
2961 BUG_ON(val & PLLRE_MISC_IDDQ);
2964 clk_writel(val, c->reg + PLL_MISC(c));
2967 static void tegra11_pllre_clk_init(struct clk *c)
2969 unsigned long input_rate = clk_get_rate(c->parent);
2972 /* clip vco_min to exact multiple of input rate to avoid crossover
2975 DIV_ROUND_UP(c->u.pll.vco_min, input_rate) * input_rate;
2976 c->min_rate = c->u.pll.vco_min;
2978 val = clk_readl(c->reg + PLL_BASE);
2979 c->state = (val & PLL_BASE_ENABLE) ? ON : OFF;
2982 /* overwrite h/w por state with min setting */
2983 m = PLL_FIXED_MDIV(c, input_rate);
2984 val = (m << PLL_BASE_DIVM_SHIFT) |
2985 (c->min_rate / input_rate << PLL_BASE_DIVN_SHIFT);
2986 clk_writel(val, c->reg + PLL_BASE);
2989 m = (val & PLLRE_BASE_DIVM_MASK) >> PLL_BASE_DIVM_SHIFT;
2990 BUG_ON(m != PLL_FIXED_MDIV(c, input_rate));
2993 c->mul = (val & PLLRE_BASE_DIVN_MASK) >> PLL_BASE_DIVN_SHIFT;
2995 pllre_set_defaults(c, input_rate);
2998 static int tegra11_pllre_clk_enable(struct clk *c)
3001 pr_debug("%s on clock %s\n", __func__, c->name);
3003 pll_do_iddq(c, PLL_MISC(c), PLLRE_MISC_IDDQ, false);
3005 val = clk_readl(c->reg + PLL_BASE);
3006 val |= PLL_BASE_ENABLE;
3007 clk_writel(val, c->reg + PLL_BASE);
3009 tegra11_pll_clk_wait_for_lock(c, c->reg + PLL_MISC(c), PLLRE_MISC_LOCK);
3013 static void tegra11_pllre_clk_disable(struct clk *c)
3016 pr_debug("%s on clock %s\n", __func__, c->name);
3018 val = clk_readl(c->reg + PLL_BASE);
3019 val &= ~PLL_BASE_ENABLE;
3020 clk_writel(val, c->reg + PLL_BASE);
3022 pll_do_iddq(c, PLL_MISC(c), PLLRE_MISC_IDDQ, true);
3025 static int tegra11_pllre_clk_set_rate(struct clk *c, unsigned long rate)
3028 unsigned long input_rate;
3029 struct clk_pll_freq_table cfg;
3031 pr_debug("%s: %s %lu\n", __func__, c->name, rate);
3033 if (rate < c->min_rate) {
3034 pr_err("%s: Failed to set %s rate %lu\n",
3035 __func__, c->name, rate);
3039 input_rate = clk_get_rate(c->parent);
3040 cfg.m = PLL_FIXED_MDIV(c, input_rate);
3041 cfg.n = rate * cfg.m / input_rate;
3046 val = old_base = clk_readl(c->reg + PLL_BASE);
3047 val &= ~(PLLRE_BASE_DIVM_MASK | PLLRE_BASE_DIVN_MASK);
3048 val |= (cfg.m << PLL_BASE_DIVM_SHIFT) | (cfg.n << PLL_BASE_DIVN_SHIFT);
3049 if (val == old_base)
3052 if (c->state == ON) {
3053 /* Use "ENABLE" pulse without placing PLL into IDDQ */
3054 val &= ~PLL_BASE_ENABLE;
3055 old_base &= ~PLL_BASE_ENABLE;
3056 pll_writel_delay(old_base, c->reg + PLL_BASE);
3059 clk_writel(val, c->reg + PLL_BASE);
3061 if (c->state == ON) {
3062 val |= PLL_BASE_ENABLE;
3063 clk_writel(val, c->reg + PLL_BASE);
3064 tegra11_pll_clk_wait_for_lock(
3065 c, c->reg + PLL_MISC(c), PLLRE_MISC_LOCK);
3070 static struct clk_ops tegra_pllre_ops = {
3071 .init = tegra11_pllre_clk_init,
3072 .enable = tegra11_pllre_clk_enable,
3073 .disable = tegra11_pllre_clk_disable,
3074 .set_rate = tegra11_pllre_clk_set_rate,
3077 static void tegra11_pllre_out_clk_init(struct clk *c)
3081 val = clk_readl(c->reg);
3082 p = (val & PLLRE_BASE_DIVP_MASK) >> PLLRE_BASE_DIVP_SHIFT;
3083 BUG_ON(p > PLLRE_PDIV_MAX);
3088 c->state = c->parent->state;
3091 static int tegra11_pllre_out_clk_enable(struct clk *c)
3096 static void tegra11_pllre_out_clk_disable(struct clk *c)
3100 static int tegra11_pllre_out_clk_set_rate(struct clk *c, unsigned long rate)
3103 unsigned long input_rate, flags;
3105 pr_debug("%s: %s %lu\n", __func__, c->name, rate);
3107 clk_lock_save(c->parent, &flags);
3108 input_rate = clk_get_rate_locked(c->parent);
3110 p = DIV_ROUND_UP(input_rate, rate);
3111 p = c->parent->u.pll.round_p_to_pdiv(p, &pdiv);
3112 if (IS_ERR_VALUE(p)) {
3113 pr_err("%s: Failed to set %s rate %lu\n",
3114 __func__, c->name, rate);
3115 clk_unlock_restore(c->parent, &flags);
3120 val = clk_readl(c->reg);
3121 val &= ~PLLRE_BASE_DIVP_MASK;
3122 val |= pdiv << PLLRE_BASE_DIVP_SHIFT;
3123 clk_writel(val, c->reg);
3125 clk_unlock_restore(c->parent, &flags);
3129 static struct clk_ops tegra_pllre_out_ops = {
3130 .init = tegra11_pllre_out_clk_init,
3131 .enable = tegra11_pllre_out_clk_enable,
3132 .disable = tegra11_pllre_out_clk_disable,
3133 .set_rate = tegra11_pllre_out_clk_set_rate,
3136 /* FIXME: plle suspend/resume */
3137 /* non-monotonic mapping below is not a typo */
3138 static u8 plle_p[PLLE_CMLDIV_MAX + 1] = {
3139 /* CMLDIV: 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 */
3140 /* p: */ 1, 2, 3, 4, 5, 6, 8, 10, 12, 16, 12, 16, 20, 24, 32 };
3142 static void tegra11_plle_clk_init(struct clk *c)
3145 struct clk *ref = tegra_get_clock_by_name("pll_re_vco");
3147 val = clk_readl(c->reg + PLL_BASE);
3148 c->state = (val & PLL_BASE_ENABLE) ? ON : OFF;
3149 c->mul = (val & PLLE_BASE_DIVN_MASK) >> PLL_BASE_DIVN_SHIFT;
3150 c->div = (val & PLLE_BASE_DIVM_MASK) >> PLL_BASE_DIVM_SHIFT;
3151 p = (val & PLLE_BASE_DIVCML_MASK) >> PLLE_BASE_DIVCML_SHIFT;
3152 c->div *= plle_p[p];
3154 val = clk_readl(PLLE_AUX);
3155 c->parent = (val & PLLE_AUX_PLLRE_SEL) ? ref :
3156 (val & PLLE_AUX_PLLP_SEL) ?
3157 tegra_get_clock_by_name("pll_p") :
3158 tegra_get_clock_by_name("pll_ref");
3159 if (c->parent != ref) {
3160 if (c->state == ON) {
3161 WARN(1, "%s: pll_e is left enabled with %s input\n",
3162 __func__, c->parent->name);
3165 val |= PLLE_AUX_PLLRE_SEL;
3166 clk_writel(val, PLLE_AUX);
3171 static void tegra11_plle_clk_disable(struct clk *c)
3174 pr_debug("%s on clock %s\n", __func__, c->name);
3176 /* FIXME: do we need to restore other s/w controls ? */
3177 val = clk_readl(c->reg + PLL_BASE);
3178 val &= ~PLL_BASE_ENABLE;
3179 clk_writel(val, c->reg + PLL_BASE);
3181 val = clk_readl(c->reg + PLL_MISC(c));
3182 val |= PLLE_MISC_IDDQ_SW_CTRL | PLLE_MISC_IDDQ_SW_VALUE;
3183 pll_writel_delay(val, c->reg + PLL_MISC(c));
3186 static int tegra11_plle_clk_enable(struct clk *c)
3189 const struct clk_pll_freq_table *sel;
3190 unsigned long rate = c->u.pll.fixed_rate;
3191 unsigned long input_rate = clk_get_rate(c->parent);
3193 if (c->state == ON) {
3194 /* BL left plle enabled - don't change configuartion */
3195 pr_warn("%s: pll_e is already enabled\n", __func__);
3199 for (sel = c->u.pll.freq_table; sel->input_rate != 0; sel++) {
3200 if (sel->input_rate == input_rate && sel->output_rate == rate)
3204 if (sel->input_rate == 0) {
3205 pr_err("%s: %s input rate %lu is out-of-table\n",
3206 __func__, c->name, input_rate);
3210 /* setup locking configuration, s/w control of IDDQ and enable modes,
3211 take pll out of IDDQ via s/w control, setup VREG */
3212 val = clk_readl(c->reg + PLL_BASE);
3213 val &= ~PLLE_BASE_LOCK_OVERRIDE;
3214 clk_writel(val, c->reg + PLL_BASE);
3216 val = clk_readl(PLLE_AUX);
3217 val |= PLLE_AUX_ENABLE_SWCTL;
3218 val &= ~PLLE_AUX_SEQ_ENABLE;
3219 pll_writel_delay(val, PLLE_AUX);
3221 val = clk_readl(c->reg + PLL_MISC(c));
3222 val |= PLLE_MISC_LOCK_ENABLE;
3223 val |= PLLE_MISC_IDDQ_SW_CTRL;
3224 val &= ~PLLE_MISC_IDDQ_SW_VALUE;
3225 val |= PLLE_MISC_PLLE_PTS;
3226 val |= PLLE_MISC_VREG_BG_CTRL_MASK | PLLE_MISC_VREG_CTRL_MASK;
3227 clk_writel(val, c->reg + PLL_MISC(c));
3230 /* configure dividers, disable SS */
3231 val = clk_readl(PLLE_SS_CTRL);
3232 val |= PLLE_SS_DISABLE;
3233 clk_writel(val, PLLE_SS_CTRL);
3235 val = clk_readl(c->reg + PLL_BASE);
3236 val &= ~(PLLE_BASE_DIVM_MASK | PLLE_BASE_DIVN_MASK |
3237 PLLE_BASE_DIVCML_MASK);
3238 val |= (sel->m << PLL_BASE_DIVM_SHIFT) |
3239 (sel->n << PLL_BASE_DIVN_SHIFT) |
3240 (sel->cpcon << PLLE_BASE_DIVCML_SHIFT);
3241 pll_writel_delay(val, c->reg + PLL_BASE);
3243 c->div = sel->m * sel->p;
3245 /* enable and lock pll */
3246 val |= PLL_BASE_ENABLE;
3247 clk_writel(val, c->reg + PLL_BASE);
3248 tegra11_pll_clk_wait_for_lock(
3249 c, c->reg + PLL_MISC(c), PLLE_MISC_LOCK);
3251 /* FIXME: enable SS if necessary */
3254 /* switch pll under h/w control */
3255 val = clk_readl(c->reg + PLL_MISC(c));
3256 val &= ~PLLE_MISC_IDDQ_SW_CTRL;
3257 clk_writel(val, c->reg + PLL_MISC(c));
3259 val = clk_readl(PLLE_AUX);
3260 val |= PLLE_AUX_USE_LOCKDET;
3261 val &= ~PLLE_AUX_ENABLE_SWCTL;
3262 pll_writel_delay(val, PLLE_AUX);
3263 val |= PLLE_AUX_SEQ_ENABLE;
3264 pll_writel_delay(val, PLLE_AUX);
3266 /* enable hw control of xusb brick pll */
3267 usb_plls_hw_control_enable(XUSBIO_PLL_CFG0);
3272 static struct clk_ops tegra_plle_ops = {
3273 .init = tegra11_plle_clk_init,
3274 .enable = tegra11_plle_clk_enable,
3275 .disable = tegra11_plle_clk_disable,
3279 * Tegra11 includes dynamic frequency lock loop (DFLL) with automatic voltage
3280 * control as possible CPU clock source. It is included in the Tegra11 clock
3281 * tree as "complex PLL" with standard Tegra clock framework APIs. However,
3282 * DFLL locking logic h/w access APIs are separated in the tegra_cl_dvfs.c
3283 * module. Hence, DFLL operations, with the exception of initialization, are
3284 * basically cl-dvfs wrappers.
3287 /* DFLL operations */
3288 static void __init tegra11_dfll_cpu_late_init(struct clk *c)
3290 #ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS
3292 struct clk *cpu = tegra_get_clock_by_name("cpu");
3294 #ifdef CONFIG_TEGRA_FPGA_PLATFORM
3295 u32 netlist, patchid;
3296 tegra_get_netlist_revision(&netlist, &patchid);
3298 pr_err("%s: CL-DVFS is not available on net %d\n",
3303 /* release dfll clock source reset, init cl_dvfs control logic, and
3304 move dfll to initialized state, so it can be used as CPU source */
3305 tegra_periph_reset_deassert(c);
3306 ret = tegra_init_cl_dvfs();
3309 c->u.dfll.cl_dvfs = platform_get_drvdata(&tegra_cl_dvfs_device);
3311 use_dfll = CONFIG_TEGRA_USE_DFLL_RANGE;
3312 tegra_dvfs_set_dfll_range(cpu->parent->dvfs, use_dfll);
3313 pr_info("Tegra CPU DFLL is initialized\n");
3318 static int tegra11_dfll_clk_enable(struct clk *c)
3320 return tegra_cl_dvfs_enable(c->u.dfll.cl_dvfs);
3323 static void tegra11_dfll_clk_disable(struct clk *c)
3325 tegra_cl_dvfs_disable(c->u.dfll.cl_dvfs);
3328 static int tegra11_dfll_clk_set_rate(struct clk *c, unsigned long rate)
3330 int ret = tegra_cl_dvfs_request_rate(c->u.dfll.cl_dvfs, rate);
3333 c->rate = tegra_cl_dvfs_request_get(c->u.dfll.cl_dvfs);
3338 static void tegra11_dfll_clk_reset(struct clk *c, bool assert)
3340 u32 val = assert ? DFLL_BASE_RESET : 0;
3341 clk_writel_delay(val, c->reg);
3345 tegra11_dfll_clk_cfg_ex(struct clk *c, enum tegra_clk_ex_param p, u32 setting)
3347 if (p == TEGRA_CLK_DFLL_LOCK)
3348 return setting ? tegra_cl_dvfs_lock(c->u.dfll.cl_dvfs) :
3349 tegra_cl_dvfs_unlock(c->u.dfll.cl_dvfs);
3353 #ifdef CONFIG_PM_SLEEP
3354 static void tegra11_dfll_clk_resume(struct clk *c)
3356 if (!(clk_readl(c->reg) & DFLL_BASE_RESET))
3357 return; /* already resumed */
3359 tegra_periph_reset_deassert(c);
3360 tegra_cl_dvfs_resume(c->u.dfll.cl_dvfs);
3364 static struct clk_ops tegra_dfll_ops = {
3365 .enable = tegra11_dfll_clk_enable,
3366 .disable = tegra11_dfll_clk_disable,
3367 .set_rate = tegra11_dfll_clk_set_rate,
3368 .reset = tegra11_dfll_clk_reset,
3369 .clk_cfg_ex = tegra11_dfll_clk_cfg_ex,
3372 /* DFLL sysfs interface */
3373 static int tegra11_use_dfll_cb(const char *arg, const struct kernel_param *kp)
3376 unsigned long c_flags, p_flags;
3377 unsigned int old_use_dfll;
3378 struct clk *c = tegra_get_clock_by_name("cpu");
3380 if (!c->parent || !c->parent->dvfs)
3383 clk_lock_save(c, &c_flags);
3384 if (c->parent->u.cpu.mode == MODE_LP) {
3385 pr_err("%s: DFLL is not used on LP CPU\n", __func__);
3386 clk_unlock_restore(c, &c_flags);
3390 clk_lock_save(c->parent, &p_flags);
3391 old_use_dfll = use_dfll;
3392 param_set_int(arg, kp);
3394 if (use_dfll != old_use_dfll) {
3395 ret = tegra_dvfs_set_dfll_range(c->parent->dvfs, use_dfll);
3397 use_dfll = old_use_dfll;
3399 ret = clk_set_rate_locked(c->parent,
3400 clk_get_rate_locked(c->parent));
3402 use_dfll = old_use_dfll;
3403 tegra_dvfs_set_dfll_range(
3404 c->parent->dvfs, use_dfll);
3408 clk_unlock_restore(c->parent, &p_flags);
3409 clk_unlock_restore(c, &c_flags);
3410 tegra_recalculate_cpu_edp_limits();
3414 static struct kernel_param_ops tegra11_use_dfll_ops = {
3415 .set = tegra11_use_dfll_cb,
3416 .get = param_get_int,
3418 module_param_cb(use_dfll, &tegra11_use_dfll_ops, &use_dfll, 0644);
3421 /* Clock divider ops (non-atomic shared register access) */
3422 static DEFINE_SPINLOCK(pll_div_lock);
3424 static int tegra11_pll_div_clk_set_rate(struct clk *c, unsigned long rate);
3425 static void tegra11_pll_div_clk_init(struct clk *c)
3427 if (c->flags & DIV_U71) {
3429 u32 val = clk_readl(c->reg);
3430 val >>= c->reg_shift;
3431 c->state = (val & PLL_OUT_CLKEN) ? ON : OFF;
3432 if (!(val & PLL_OUT_RESET_DISABLE))
3435 if (c->u.pll_div.default_rate) {
3436 int ret = tegra11_pll_div_clk_set_rate(
3437 c, c->u.pll_div.default_rate);
3441 divu71 = (val & PLL_OUT_RATIO_MASK) >> PLL_OUT_RATIO_SHIFT;
3442 c->div = (divu71 + 2);
3444 } else if (c->flags & DIV_2) {
3446 if (c->flags & (PLLD | PLLX)) {
3452 } else if (c->flags & PLLU) {
3453 u32 val = clk_readl(c->reg);
3454 c->state = val & (0x1 << c->reg_shift) ? ON : OFF;
3462 static int tegra11_pll_div_clk_enable(struct clk *c)
3466 unsigned long flags;
3468 pr_debug("%s: %s\n", __func__, c->name);
3469 if (c->flags & DIV_U71) {
3470 spin_lock_irqsave(&pll_div_lock, flags);
3471 val = clk_readl(c->reg);
3472 new_val = val >> c->reg_shift;
3475 new_val |= PLL_OUT_CLKEN | PLL_OUT_RESET_DISABLE;
3477 val &= ~(0xFFFF << c->reg_shift);
3478 val |= new_val << c->reg_shift;
3479 clk_writel_delay(val, c->reg);
3480 spin_unlock_irqrestore(&pll_div_lock, flags);
3482 } else if (c->flags & DIV_2) {
3484 } else if (c->flags & PLLU) {
3485 clk_lock_save(c->parent, &flags);
3486 val = clk_readl(c->reg) | (0x1 << c->reg_shift);
3487 clk_writel_delay(val, c->reg);
3488 clk_unlock_restore(c->parent, &flags);
3494 static void tegra11_pll_div_clk_disable(struct clk *c)
3498 unsigned long flags;
3500 pr_debug("%s: %s\n", __func__, c->name);
3501 if (c->flags & DIV_U71) {
3502 spin_lock_irqsave(&pll_div_lock, flags);
3503 val = clk_readl(c->reg);
3504 new_val = val >> c->reg_shift;
3507 new_val &= ~(PLL_OUT_CLKEN | PLL_OUT_RESET_DISABLE);
3509 val &= ~(0xFFFF << c->reg_shift);
3510 val |= new_val << c->reg_shift;
3511 clk_writel_delay(val, c->reg);
3512 spin_unlock_irqrestore(&pll_div_lock, flags);
3513 } else if (c->flags & PLLU) {
3514 clk_lock_save(c->parent, &flags);
3515 val = clk_readl(c->reg) & (~(0x1 << c->reg_shift));
3516 clk_writel_delay(val, c->reg);
3517 clk_unlock_restore(c->parent, &flags);
3521 static int tegra11_pll_div_clk_set_rate(struct clk *c, unsigned long rate)
3526 unsigned long parent_rate = clk_get_rate(c->parent);
3527 unsigned long flags;
3529 pr_debug("%s: %s %lu\n", __func__, c->name, rate);
3530 if (c->flags & DIV_U71) {
3531 divider_u71 = clk_div71_get_divider(
3532 parent_rate, rate, c->flags, ROUND_DIVIDER_UP);
3533 if (divider_u71 >= 0) {
3534 spin_lock_irqsave(&pll_div_lock, flags);
3535 val = clk_readl(c->reg);
3536 new_val = val >> c->reg_shift;
3538 if (c->flags & DIV_U71_FIXED)
3539 new_val |= PLL_OUT_OVERRIDE;
3540 new_val &= ~PLL_OUT_RATIO_MASK;
3541 new_val |= divider_u71 << PLL_OUT_RATIO_SHIFT;
3543 val &= ~(0xFFFF << c->reg_shift);
3544 val |= new_val << c->reg_shift;
3545 clk_writel_delay(val, c->reg);
3546 c->div = divider_u71 + 2;
3548 spin_unlock_irqrestore(&pll_div_lock, flags);
3551 } else if (c->flags & DIV_2)
3552 return clk_set_rate(c->parent, rate * 2);
3557 static long tegra11_pll_div_clk_round_rate(struct clk *c, unsigned long rate)
3560 unsigned long parent_rate = clk_get_rate(c->parent);
3561 pr_debug("%s: %s %lu\n", __func__, c->name, rate);
3563 if (c->flags & DIV_U71) {
3564 divider = clk_div71_get_divider(
3565 parent_rate, rate, c->flags, ROUND_DIVIDER_UP);
3568 return DIV_ROUND_UP(parent_rate * 2, divider + 2);
3569 } else if (c->flags & DIV_2)
3570 /* no rounding - fixed DIV_2 dividers pass rate to parent PLL */
3576 static struct clk_ops tegra_pll_div_ops = {
3577 .init = tegra11_pll_div_clk_init,
3578 .enable = tegra11_pll_div_clk_enable,
3579 .disable = tegra11_pll_div_clk_disable,
3580 .set_rate = tegra11_pll_div_clk_set_rate,
3581 .round_rate = tegra11_pll_div_clk_round_rate,
3584 /* Periph clk ops */
3585 static inline u32 periph_clk_source_mask(struct clk *c)
3587 if (c->u.periph.src_mask)
3588 return c->u.periph.src_mask;
3589 else if (c->flags & MUX8)
3591 else if (c->flags & MUX_PWM)
3593 else if (c->flags & MUX_CLK_OUT)
3594 return 3 << (c->u.periph.clk_num + 4);
3595 else if (c->flags & PLLD)
3596 return PLLD_BASE_DSI_MUX_MASK;
3601 static inline u32 periph_clk_source_shift(struct clk *c)
3603 if (c->u.periph.src_shift)
3604 return c->u.periph.src_shift;
3605 else if (c->flags & MUX8)
3607 else if (c->flags & MUX_PWM)
3609 else if (c->flags & MUX_CLK_OUT)
3610 return c->u.periph.clk_num + 4;
3611 else if (c->flags & PLLD)
3612 return PLLD_BASE_DSI_MUX_SHIFT;
3617 static void tegra11_periph_clk_init(struct clk *c)
3619 u32 val = clk_readl(c->reg);
3620 const struct clk_mux_sel *mux = 0;
3621 const struct clk_mux_sel *sel;
3622 if (c->flags & MUX) {
3623 for (sel = c->inputs; sel->input != NULL; sel++) {
3624 if (((val & periph_clk_source_mask(c)) >>
3625 periph_clk_source_shift(c)) == sel->value)
3630 c->parent = mux->input;
3632 if (c->flags & PLLU) {
3633 /* for xusb_hs clock enforce PLLU source during init */
3634 val &= periph_clk_source_mask(c);
3635 val |= c->inputs[0].value << periph_clk_source_shift(c);
3636 clk_writel_delay(val, c->reg);
3638 c->parent = c->inputs[0].input;
3641 if (c->flags & DIV_U71) {
3642 u32 divu71 = val & PERIPH_CLK_SOURCE_DIVU71_MASK;
3643 if (c->flags & DIV_U71_IDLE) {
3644 val &= ~(PERIPH_CLK_SOURCE_DIVU71_MASK <<
3645 PERIPH_CLK_SOURCE_DIVIDLE_SHIFT);
3646 val |= (PERIPH_CLK_SOURCE_DIVIDLE_VAL <<
3647 PERIPH_CLK_SOURCE_DIVIDLE_SHIFT);
3648 clk_writel(val, c->reg);
3650 c->div = divu71 + 2;
3652 } else if (c->flags & DIV_U151) {
3653 u32 divu151 = val & PERIPH_CLK_SOURCE_DIVU16_MASK;
3654 if ((c->flags & DIV_U151_UART) &&
3655 (!(val & PERIPH_CLK_UART_DIV_ENB))) {
3658 c->div = divu151 + 2;
3660 } else if (c->flags & DIV_U16) {
3661 u32 divu16 = val & PERIPH_CLK_SOURCE_DIVU16_MASK;
3662 c->div = divu16 + 1;
3669 if (c->flags & PERIPH_NO_ENB) {
3670 c->state = c->parent->state;
3676 if (!(clk_readl(PERIPH_CLK_TO_ENB_REG(c)) & PERIPH_CLK_TO_BIT(c)))
3678 if (!(c->flags & PERIPH_NO_RESET))
3679 if (clk_readl(PERIPH_CLK_TO_RST_REG(c)) & PERIPH_CLK_TO_BIT(c))
3683 static int tegra11_periph_clk_enable(struct clk *c)
3685 unsigned long flags;
3686 pr_debug("%s on clock %s\n", __func__, c->name);
3688 if (c->flags & PERIPH_NO_ENB)
3691 spin_lock_irqsave(&periph_refcount_lock, flags);
3693 tegra_periph_clk_enable_refcount[c->u.periph.clk_num]++;
3694 if (tegra_periph_clk_enable_refcount[c->u.periph.clk_num] > 1) {
3695 spin_unlock_irqrestore(&periph_refcount_lock, flags);
3699 clk_writel_delay(PERIPH_CLK_TO_BIT(c), PERIPH_CLK_TO_ENB_SET_REG(c));
3700 if (!(c->flags & PERIPH_NO_RESET) && !(c->flags & PERIPH_MANUAL_RESET)) {
3701 if (clk_readl(PERIPH_CLK_TO_RST_REG(c)) & PERIPH_CLK_TO_BIT(c)) {
3702 udelay(5); /* reset propagation delay */
3703 clk_writel(PERIPH_CLK_TO_BIT(c), PERIPH_CLK_TO_RST_CLR_REG(c));
3706 spin_unlock_irqrestore(&periph_refcount_lock, flags);
3710 static void tegra11_periph_clk_disable(struct clk *c)
3712 unsigned long val, flags;
3713 pr_debug("%s on clock %s\n", __func__, c->name);
3715 if (c->flags & PERIPH_NO_ENB)
3718 spin_lock_irqsave(&periph_refcount_lock, flags);
3721 tegra_periph_clk_enable_refcount[c->u.periph.clk_num]--;
3723 if (tegra_periph_clk_enable_refcount[c->u.periph.clk_num] == 0) {
3724 /* If peripheral is in the APB bus then read the APB bus to
3725 * flush the write operation in apb bus. This will avoid the
3726 * peripheral access after disabling clock*/
3727 if (c->flags & PERIPH_ON_APB)
3728 val = chipid_readl();
3731 PERIPH_CLK_TO_BIT(c), PERIPH_CLK_TO_ENB_CLR_REG(c));
3733 spin_unlock_irqrestore(&periph_refcount_lock, flags);
3736 static void tegra11_periph_clk_reset(struct clk *c, bool assert)
3739 pr_debug("%s %s on clock %s\n", __func__,
3740 assert ? "assert" : "deassert", c->name);
3742 if (c->flags & PERIPH_NO_ENB)
3745 if (!(c->flags & PERIPH_NO_RESET)) {
3747 /* If peripheral is in the APB bus then read the APB
3748 * bus to flush the write operation in apb bus. This
3749 * will avoid the peripheral access after disabling
3751 if (c->flags & PERIPH_ON_APB)
3752 val = chipid_readl();
3754 clk_writel(PERIPH_CLK_TO_BIT(c),
3755 PERIPH_CLK_TO_RST_SET_REG(c));
3757 clk_writel(PERIPH_CLK_TO_BIT(c),
3758 PERIPH_CLK_TO_RST_CLR_REG(c));
3762 static int tegra11_periph_clk_set_parent(struct clk *c, struct clk *p)
3765 const struct clk_mux_sel *sel;
3766 pr_debug("%s: %s %s\n", __func__, c->name, p->name);
3768 if (!(c->flags & MUX))
3769 return (p == c->parent) ? 0 : (-EINVAL);
3771 for (sel = c->inputs; sel->input != NULL; sel++) {
3772 if (sel->input == p) {
3773 val = clk_readl(c->reg);
3774 val &= ~periph_clk_source_mask(c);
3775 val |= (sel->value << periph_clk_source_shift(c));
3780 clk_writel_delay(val, c->reg);
3782 if (c->refcnt && c->parent)
3783 clk_disable(c->parent);
3793 static int tegra11_periph_clk_set_rate(struct clk *c, unsigned long rate)
3797 unsigned long parent_rate = clk_get_rate(c->parent);
3799 if (c->flags & DIV_U71) {
3800 divider = clk_div71_get_divider(
3801 parent_rate, rate, c->flags, ROUND_DIVIDER_UP);
3803 val = clk_readl(c->reg);
3804 val &= ~PERIPH_CLK_SOURCE_DIVU71_MASK;
3806 clk_writel_delay(val, c->reg);
3807 c->div = divider + 2;
3811 } else if (c->flags & DIV_U151) {
3812 divider = clk_div151_get_divider(
3813 parent_rate, rate, c->flags, ROUND_DIVIDER_UP);
3815 val = clk_readl(c->reg);
3816 val &= ~PERIPH_CLK_SOURCE_DIVU16_MASK;
3818 if (c->flags & DIV_U151_UART) {
3820 val |= PERIPH_CLK_UART_DIV_ENB;
3822 val &= ~PERIPH_CLK_UART_DIV_ENB;
3824 clk_writel_delay(val, c->reg);
3825 c->div = divider + 2;
3829 } else if (c->flags & DIV_U16) {
3830 divider = clk_div16_get_divider(parent_rate, rate);
3832 val = clk_readl(c->reg);
3833 val &= ~PERIPH_CLK_SOURCE_DIVU16_MASK;
3835 clk_writel_delay(val, c->reg);
3836 c->div = divider + 1;
3840 } else if (parent_rate <= rate) {
3848 static long tegra11_periph_clk_round_rate(struct clk *c,
3852 unsigned long parent_rate = clk_get_rate(c->parent);
3853 pr_debug("%s: %s %lu\n", __func__, c->name, rate);
3855 if (c->flags & DIV_U71) {
3856 divider = clk_div71_get_divider(
3857 parent_rate, rate, c->flags, ROUND_DIVIDER_UP);
3861 return DIV_ROUND_UP(parent_rate * 2, divider + 2);
3862 } else if (c->flags & DIV_U151) {
3863 divider = clk_div151_get_divider(
3864 parent_rate, rate, c->flags, ROUND_DIVIDER_UP);
3868 return DIV_ROUND_UP(parent_rate * 2, divider + 2);
3869 } else if (c->flags & DIV_U16) {
3870 divider = clk_div16_get_divider(parent_rate, rate);
3873 return DIV_ROUND_UP(parent_rate, divider + 1);
3878 static struct clk_ops tegra_periph_clk_ops = {
3879 .init = &tegra11_periph_clk_init,
3880 .enable = &tegra11_periph_clk_enable,
3881 .disable = &tegra11_periph_clk_disable,
3882 .set_parent = &tegra11_periph_clk_set_parent,
3883 .set_rate = &tegra11_periph_clk_set_rate,
3884 .round_rate = &tegra11_periph_clk_round_rate,
3885 .reset = &tegra11_periph_clk_reset,
3889 #if !defined(CONFIG_TEGRA_SIMULATION_PLATFORM)
3890 /* msenc clock propagation WAR for bug 1005168 */
3891 static int tegra11_msenc_clk_enable(struct clk *c)
3893 int ret = tegra11_periph_clk_enable(c);
3897 clk_writel(0, LVL2_CLK_GATE_OVRE);
3898 clk_writel(0x00400000, LVL2_CLK_GATE_OVRE);
3900 clk_writel(0, LVL2_CLK_GATE_OVRE);
3904 static struct clk_ops tegra_msenc_clk_ops = {
3905 .init = &tegra11_periph_clk_init,
3906 .enable = &tegra11_msenc_clk_enable,
3907 .disable = &tegra11_periph_clk_disable,
3908 .set_parent = &tegra11_periph_clk_set_parent,
3909 .set_rate = &tegra11_periph_clk_set_rate,
3910 .round_rate = &tegra11_periph_clk_round_rate,
3911 .reset = &tegra11_periph_clk_reset,
3914 /* Periph extended clock configuration ops */
3916 tegra11_vi_clk_cfg_ex(struct clk *c, enum tegra_clk_ex_param p, u32 setting)
3918 if (p == TEGRA_CLK_VI_INP_SEL) {
3919 u32 val = clk_readl(c->reg);
3920 val &= ~PERIPH_CLK_VI_SEL_EX_MASK;
3921 val |= (setting << PERIPH_CLK_VI_SEL_EX_SHIFT) &
3922 PERIPH_CLK_VI_SEL_EX_MASK;
3923 clk_writel(val, c->reg);
3929 static struct clk_ops tegra_vi_clk_ops = {
3930 .init = &tegra11_periph_clk_init,
3931 .enable = &tegra11_periph_clk_enable,
3932 .disable = &tegra11_periph_clk_disable,
3933 .set_parent = &tegra11_periph_clk_set_parent,
3934 .set_rate = &tegra11_periph_clk_set_rate,
3935 .round_rate = &tegra11_periph_clk_round_rate,
3936 .clk_cfg_ex = &tegra11_vi_clk_cfg_ex,
3937 .reset = &tegra11_periph_clk_reset,
3941 tegra11_nand_clk_cfg_ex(struct clk *c, enum tegra_clk_ex_param p, u32 setting)
3943 if (p == TEGRA_CLK_NAND_PAD_DIV2_ENB) {
3944 u32 val = clk_readl(c->reg);
3946 val |= PERIPH_CLK_NAND_DIV_EX_ENB;
3948 val &= ~PERIPH_CLK_NAND_DIV_EX_ENB;
3949 clk_writel(val, c->reg);
3955 static struct clk_ops tegra_nand_clk_ops = {
3956 .init = &tegra11_periph_clk_init,
3957 .enable = &tegra11_periph_clk_enable,
3958 .disable = &tegra11_periph_clk_disable,
3959 .set_parent = &tegra11_periph_clk_set_parent,
3960 .set_rate = &tegra11_periph_clk_set_rate,
3961 .round_rate = &tegra11_periph_clk_round_rate,
3962 .clk_cfg_ex = &tegra11_nand_clk_cfg_ex,
3963 .reset = &tegra11_periph_clk_reset,
3968 tegra11_dtv_clk_cfg_ex(struct clk *c, enum tegra_clk_ex_param p, u32 setting)
3970 if (p == TEGRA_CLK_DTV_INVERT) {
3971 u32 val = clk_readl(c->reg);
3973 val |= PERIPH_CLK_DTV_POLARITY_INV;
3975 val &= ~PERIPH_CLK_DTV_POLARITY_INV;
3976 clk_writel(val, c->reg);
3982 static struct clk_ops tegra_dtv_clk_ops = {
3983 .init = &tegra11_periph_clk_init,
3984 .enable = &tegra11_periph_clk_enable,
3985 .disable = &tegra11_periph_clk_disable,
3986 .set_parent = &tegra11_periph_clk_set_parent,
3987 .set_rate = &tegra11_periph_clk_set_rate,
3988 .round_rate = &tegra11_periph_clk_round_rate,
3989 .clk_cfg_ex = &tegra11_dtv_clk_cfg_ex,
3990 .reset = &tegra11_periph_clk_reset,
3993 static int tegra11_dsi_clk_set_parent(struct clk *c, struct clk *p)
3995 const struct clk_mux_sel *sel;
3996 struct clk *d = tegra_get_clock_by_name("pll_d");
3997 if (c->reg != d->reg)
3998 d = tegra_get_clock_by_name("pll_d2");
4000 pr_debug("%s: %s %s\n", __func__, c->name, p->name);
4002 for (sel = c->inputs; sel->input != NULL; sel++) {
4003 if (sel->input == p) {
4007 /* The DSI parent selection bit is in PLLD base
4008 register - can not do direct r-m-w, must be
4009 protected by PLLD lock */
4011 d, TEGRA_CLK_PLLD_MIPI_MUX_SEL, sel->value);
4013 if (c->refcnt && c->parent)
4014 clk_disable(c->parent);
4024 static struct clk_ops tegra_dsi_clk_ops = {
4025 .init = &tegra11_periph_clk_init,
4026 .enable = &tegra11_periph_clk_enable,
4027 .disable = &tegra11_periph_clk_disable,
4028 .set_parent = &tegra11_dsi_clk_set_parent,
4029 .set_rate = &tegra11_periph_clk_set_rate,
4030 .round_rate = &tegra11_periph_clk_round_rate,
4031 .reset = &tegra11_periph_clk_reset,
4034 /* pciex clock support only reset function */
4035 static struct clk_ops tegra_pciex_clk_ops = {
4036 .reset = tegra11_periph_clk_reset,
4039 /* Output clock ops */
4041 static DEFINE_SPINLOCK(clk_out_lock);
4043 static void tegra11_clk_out_init(struct clk *c)
4045 const struct clk_mux_sel *mux = 0;
4046 const struct clk_mux_sel *sel;
4047 u32 val = pmc_readl(c->reg);
4049 c->state = (val & (0x1 << c->u.periph.clk_num)) ? ON : OFF;
4053 for (sel = c->inputs; sel->input != NULL; sel++) {
4054 if (((val & periph_clk_source_mask(c)) >>
4055 periph_clk_source_shift(c)) == sel->value)
4059 c->parent = mux->input;
4062 static int tegra11_clk_out_enable(struct clk *c)
4065 unsigned long flags;
4067 pr_debug("%s on clock %s\n", __func__, c->name);
4069 spin_lock_irqsave(&clk_out_lock, flags);
4070 val = pmc_readl(c->reg);
4071 val |= (0x1 << c->u.periph.clk_num);
4072 pmc_writel(val, c->reg);
4073 spin_unlock_irqrestore(&clk_out_lock, flags);
4078 static void tegra11_clk_out_disable(struct clk *c)
4081 unsigned long flags;
4083 pr_debug("%s on clock %s\n", __func__, c->name);
4085 spin_lock_irqsave(&clk_out_lock, flags);
4086 val = pmc_readl(c->reg);
4087 val &= ~(0x1 << c->u.periph.clk_num);
4088 pmc_writel(val, c->reg);
4089 spin_unlock_irqrestore(&clk_out_lock, flags);
4092 static int tegra11_clk_out_set_parent(struct clk *c, struct clk *p)
4095 unsigned long flags;
4096 const struct clk_mux_sel *sel;
4098 pr_debug("%s: %s %s\n", __func__, c->name, p->name);
4100 for (sel = c->inputs; sel->input != NULL; sel++) {
4101 if (sel->input == p) {
4105 spin_lock_irqsave(&clk_out_lock, flags);
4106 val = pmc_readl(c->reg);
4107 val &= ~periph_clk_source_mask(c);
4108 val |= (sel->value << periph_clk_source_shift(c));
4109 pmc_writel(val, c->reg);
4110 spin_unlock_irqrestore(&clk_out_lock, flags);
4112 if (c->refcnt && c->parent)
4113 clk_disable(c->parent);
4122 static struct clk_ops tegra_clk_out_ops = {
4123 .init = &tegra11_clk_out_init,
4124 .enable = &tegra11_clk_out_enable,
4125 .disable = &tegra11_clk_out_disable,
4126 .set_parent = &tegra11_clk_out_set_parent,
4130 /* External memory controller clock ops */
4131 static void tegra11_emc_clk_init(struct clk *c)
4133 tegra11_periph_clk_init(c);
4134 tegra_emc_dram_type_init(c);
4135 c->max_rate = clk_get_rate(c->parent);
4138 static long tegra11_emc_clk_round_rate(struct clk *c, unsigned long rate)
4140 long new_rate = max(rate, c->min_rate);
4142 new_rate = tegra_emc_round_rate(new_rate);
4144 new_rate = c->max_rate;
4149 static int tegra11_emc_clk_set_rate(struct clk *c, unsigned long rate)
4155 /* The tegra11x memory controller has an interlock with the clock
4156 * block that allows memory shadowed registers to be updated,
4157 * and then transfer them to the main registers at the same
4158 * time as the clock update without glitches. During clock change
4159 * operation both clock parent and divider may change simultaneously
4160 * to achieve requested rate. */
4161 p = tegra_emc_predict_parent(rate, &div_value);
4162 div_value += 2; /* emc has fractional DIV_U71 divider */
4163 if (IS_ERR_OR_NULL(p)) {
4164 pr_err("%s: Failed to predict emc parent for rate %lu\n",
4169 if (p == c->parent) {
4170 if (div_value == c->div)
4172 } else if (c->refcnt)
4175 ret = tegra_emc_set_rate(rate);
4179 if (p != c->parent) {
4180 if(c->refcnt && c->parent)
4181 clk_disable(c->parent);
4189 static int tegra11_clk_emc_bus_update(struct clk *bus)
4191 struct clk *p = NULL;
4192 unsigned long rate, parent_rate, backup_rate;
4194 if (detach_shared_bus)
4197 rate = tegra11_clk_shared_bus_update(bus, NULL, NULL);
4198 rate = clk_round_rate_locked(bus, rate);
4200 if (rate == clk_get_rate_locked(bus))
4203 if (!tegra_emc_is_parent_ready(rate, &p, &parent_rate, &backup_rate)) {
4204 if (bus->parent == p) {
4205 /* need backup to re-lock current parent */
4206 if (IS_ERR_VALUE(backup_rate) ||
4207 clk_set_rate_locked(bus, backup_rate)) {
4208 pr_err("%s: Failed to backup %s for rate %lu\n",
4209 __func__, bus->name, rate);
4214 pr_err("%s: %s has other than emc child\n",
4219 if (clk_set_rate(p, parent_rate)) {
4220 pr_err("%s: Failed to set %s rate %lu\n",
4221 __func__, p->name, parent_rate);
4226 return clk_set_rate_locked(bus, rate);
4229 static struct clk_ops tegra_emc_clk_ops = {
4230 .init = &tegra11_emc_clk_init,
4231 .enable = &tegra11_periph_clk_enable,
4232 .disable = &tegra11_periph_clk_disable,
4233 .set_rate = &tegra11_emc_clk_set_rate,
4234 .round_rate = &tegra11_emc_clk_round_rate,
4235 .reset = &tegra11_periph_clk_reset,
4236 .shared_bus_update = &tegra11_clk_emc_bus_update,
4239 /* Clock doubler ops (non-atomic shared register access) */
4240 static DEFINE_SPINLOCK(doubler_lock);
4242 static void tegra11_clk_double_init(struct clk *c)
4244 u32 val = clk_readl(c->reg);
4245 c->mul = val & (0x1 << c->reg_shift) ? 1 : 2;
4248 if (!(clk_readl(PERIPH_CLK_TO_ENB_REG(c)) & PERIPH_CLK_TO_BIT(c)))
4252 static int tegra11_clk_double_set_rate(struct clk *c, unsigned long rate)
4255 unsigned long parent_rate = clk_get_rate(c->parent);
4256 unsigned long flags;
4258 if (rate == parent_rate) {
4259 spin_lock_irqsave(&doubler_lock, flags);
4260 val = clk_readl(c->reg) | (0x1 << c->reg_shift);
4261 clk_writel(val, c->reg);
4264 spin_unlock_irqrestore(&doubler_lock, flags);
4266 } else if (rate == 2 * parent_rate) {
4267 spin_lock_irqsave(&doubler_lock, flags);
4268 val = clk_readl(c->reg) & (~(0x1 << c->reg_shift));
4269 clk_writel(val, c->reg);
4272 spin_unlock_irqrestore(&doubler_lock, flags);
4278 static struct clk_ops tegra_clk_double_ops = {
4279 .init = &tegra11_clk_double_init,
4280 .enable = &tegra11_periph_clk_enable,
4281 .disable = &tegra11_periph_clk_disable,
4282 .set_rate = &tegra11_clk_double_set_rate,
4285 /* Audio sync clock ops */
4286 static int tegra11_sync_source_set_rate(struct clk *c, unsigned long rate)
4292 static struct clk_ops tegra_sync_source_ops = {
4293 .set_rate = &tegra11_sync_source_set_rate,
4296 static void tegra11_audio_sync_clk_init(struct clk *c)
4299 const struct clk_mux_sel *sel;
4300 u32 val = clk_readl(c->reg);
4301 c->state = (val & AUDIO_SYNC_DISABLE_BIT) ? OFF : ON;
4302 source = val & AUDIO_SYNC_SOURCE_MASK;
4303 for (sel = c->inputs; sel->input != NULL; sel++)
4304 if (sel->value == source)
4306 BUG_ON(sel->input == NULL);
4307 c->parent = sel->input;
4310 static int tegra11_audio_sync_clk_enable(struct clk *c)
4312 u32 val = clk_readl(c->reg);
4313 clk_writel((val & (~AUDIO_SYNC_DISABLE_BIT)), c->reg);
4317 static void tegra11_audio_sync_clk_disable(struct clk *c)
4319 u32 val = clk_readl(c->reg);
4320 clk_writel((val | AUDIO_SYNC_DISABLE_BIT), c->reg);
4323 static int tegra11_audio_sync_clk_set_parent(struct clk *c, struct clk *p)
4326 const struct clk_mux_sel *sel;
4327 for (sel = c->inputs; sel->input != NULL; sel++) {
4328 if (sel->input == p) {
4329 val = clk_readl(c->reg);
4330 val &= ~AUDIO_SYNC_SOURCE_MASK;
4336 clk_writel(val, c->reg);
4338 if (c->refcnt && c->parent)
4339 clk_disable(c->parent);
4349 static struct clk_ops tegra_audio_sync_clk_ops = {
4350 .init = tegra11_audio_sync_clk_init,
4351 .enable = tegra11_audio_sync_clk_enable,
4352 .disable = tegra11_audio_sync_clk_disable,
4353 .set_parent = tegra11_audio_sync_clk_set_parent,
4359 * Some clocks require dynamic re-locking of source PLL in order to
4360 * achieve frequency scaling granularity that matches characterized
4361 * core voltage steps. The cbus clock creates a shared bus that
4362 * provides a virtual root for such clocks to hide and synchronize
4363 * parent PLL re-locking as well as backup operations.
4366 static void tegra11_clk_cbus_init(struct clk *c)
4372 static int tegra11_clk_cbus_enable(struct clk *c)
4377 static long tegra11_clk_cbus_round_rate(struct clk *c, unsigned long rate)
4383 c->min_rate = c->parent->min_rate;
4384 rate = max(rate, c->min_rate);
4388 /* update min now, since no dvfs table was available during init
4389 (skip placeholder entries set to 1 kHz) */
4391 for (i = 0; i < (c->dvfs->num_freqs - 1); i++) {
4392 if (c->dvfs->freqs[i] > 1 * c->dvfs->freqs_mult) {
4393 c->min_rate = c->dvfs->freqs[i];
4397 BUG_ON(!c->min_rate);
4399 rate = max(rate, c->min_rate);
4401 for (i = 0; i < (c->dvfs->num_freqs - 1); i++) {
4402 unsigned long f = c->dvfs->freqs[i];
4403 int mv = c->dvfs->millivolts[i];
4404 if ((f >= rate) || (mv >= c->dvfs->max_millivolts))
4407 return c->dvfs->freqs[i];
4410 static int cbus_switch_one(struct clk *c, struct clk *p, u32 div, bool abort)
4414 /* set new divider if it is bigger than the current one */
4415 if (c->div < c->mul * div) {
4416 ret = clk_set_div(c, div);
4418 pr_err("%s: failed to set %s clock divider %u: %d\n",
4419 __func__, c->name, div, ret);
4425 if (c->parent != p) {
4426 ret = clk_set_parent(c, p);
4428 pr_err("%s: failed to set %s clock parent %s: %d\n",
4429 __func__, c->name, p->name, ret);
4435 /* set new divider if it is smaller than the current one */
4436 if (c->div > c->mul * div) {
4437 ret = clk_set_div(c, div);
4439 pr_err("%s: failed to set %s clock divider %u: %d\n",
4440 __func__, c->name, div, ret);
4446 static int cbus_backup(struct clk *c)
4451 list_for_each_entry(user, &c->shared_bus_list,
4452 u.shared_bus_user.node) {
4453 struct clk *client = user->u.shared_bus_user.client;
4454 if (client && (client->state == ON) &&
4455 (client->parent == c->parent)) {
4456 ret = cbus_switch_one(client,
4457 c->shared_bus_backup.input,
4458 c->shared_bus_backup.value *
4467 static int cbus_dvfs_set_rate(struct clk *c, unsigned long rate)
4472 list_for_each_entry(user, &c->shared_bus_list,
4473 u.shared_bus_user.node) {
4474 struct clk *client = user->u.shared_bus_user.client;
4475 if (client && client->refcnt && (client->parent == c->parent)) {
4476 ret = tegra_dvfs_set_rate(c, rate);
4484 static void cbus_restore(struct clk *c)
4488 list_for_each_entry(user, &c->shared_bus_list,
4489 u.shared_bus_user.node) {
4490 if (user->u.shared_bus_user.client)
4491 cbus_switch_one(user->u.shared_bus_user.client,
4492 c->parent, c->div * user->div, false);
4496 static int get_next_backup_div(struct clk *c, unsigned long rate)
4499 unsigned long backup_rate = clk_get_rate(c->shared_bus_backup.input);
4501 rate = max(rate, clk_get_rate_locked(c));
4502 rate = rate - (rate >> 2); /* 25% margin for backup rate */
4503 if ((u64)rate * div < backup_rate)
4504 div = DIV_ROUND_UP(backup_rate, rate);
4510 static int tegra11_clk_cbus_set_rate(struct clk *c, unsigned long rate)
4518 ret = clk_enable(c->parent);
4520 pr_err("%s: failed to enable %s clock: %d\n",
4521 __func__, c->name, ret);
4525 dramp = tegra11_is_dyn_ramp(c->parent, rate * c->div, false);
4527 c->shared_bus_backup.value = get_next_backup_div(c, rate);
4528 ret = cbus_backup(c);
4533 ret = clk_set_rate(c->parent, rate * c->div);
4535 pr_err("%s: failed to set %s clock rate %lu: %d\n",
4536 __func__, c->name, rate, ret);
4540 /* Safe voltage setting is taken care of by cbus clock dvfs; the call
4541 * below only records requirements for each enabled client.
4544 ret = cbus_dvfs_set_rate(c, rate);
4549 clk_disable(c->parent);
4553 static inline void cbus_move_enabled_user(
4554 struct clk *user, struct clk *dst, struct clk *src)
4557 list_move_tail(&user->u.shared_bus_user.node, &dst->shared_bus_list);
4559 clk_reparent(user, dst);
4562 #ifdef CONFIG_TEGRA_DYNAMIC_CBUS
4563 static int tegra11_clk_cbus_update(struct clk *bus)
4566 struct clk *slow = NULL;
4567 struct clk *top = NULL;
4569 unsigned long old_rate;
4571 if (detach_shared_bus)
4574 rate = tegra11_clk_shared_bus_update(bus, &top, &slow);
4576 /* use dvfs table of the slowest enabled client as cbus dvfs table */
4577 if (bus->dvfs && slow && (slow != bus->u.cbus.slow_user)) {
4579 unsigned long *dest = &bus->dvfs->freqs[0];
4580 unsigned long *src =
4581 &slow->u.shared_bus_user.client->dvfs->freqs[0];
4583 for (i = 0; i < bus->dvfs->num_freqs; i++)
4584 dest[i] = src[i] * slow->div;
4586 memcpy(dest, src, sizeof(*dest) * bus->dvfs->num_freqs);
4589 /* update bus state variables and rate */
4590 bus->u.cbus.slow_user = slow;
4591 bus->u.cbus.top_user = top;
4593 rate = bus->ops->round_rate(bus, rate);
4594 mv = tegra_dvfs_predict_millivolts(bus, rate);
4595 if (IS_ERR_VALUE(mv))
4599 mv -= bus->dvfs->cur_millivolts;
4600 if (bus->refcnt && (mv > 0)) {
4601 ret = tegra_dvfs_set_rate(bus, rate);
4607 old_rate = clk_get_rate_locked(bus);
4608 if (old_rate != rate) {
4609 ret = bus->ops->set_rate(bus, rate);
4615 if (bus->refcnt && (mv <= 0)) {
4616 ret = tegra_dvfs_set_rate(bus, rate);
4622 clk_rate_change_notify(bus, rate);
4626 static int tegra11_clk_cbus_update(struct clk *bus)
4628 unsigned long rate, old_rate;
4630 if (detach_shared_bus)
4633 rate = tegra11_clk_shared_bus_update(bus, NULL, NULL);
4634 rate = clk_round_rate_locked(bus, rate);
4636 old_rate = clk_get_rate_locked(bus);
4637 if (rate == old_rate)
4640 return clk_set_rate_locked(bus, rate);
4644 static int tegra11_clk_cbus_migrate_users(struct clk *user)
4646 #ifdef CONFIG_TEGRA_MIGRATE_CBUS_USERS
4647 struct clk *src_bus, *dst_bus, *top_user, *c;
4648 struct list_head *pos, *n;
4650 if (!user->u.shared_bus_user.client || !user->inputs)
4653 /* Dual cbus on Tegra11 */
4654 src_bus = user->inputs[0].input;
4655 dst_bus = user->inputs[1].input;
4657 if (!src_bus->u.cbus.top_user && !dst_bus->u.cbus.top_user)
4660 /* Make sure top user on the source bus is requesting highest rate */
4661 if (!src_bus->u.cbus.top_user || (dst_bus->u.cbus.top_user &&
4662 bus_user_request_is_lower(src_bus->u.cbus.top_user,
4663 dst_bus->u.cbus.top_user)))
4664 swap(src_bus, dst_bus);
4666 /* If top user is the slow one on its own (source) bus, do nothing */
4667 top_user = src_bus->u.cbus.top_user;
4668 BUG_ON(!top_user->u.shared_bus_user.client);
4669 if (!bus_user_is_slower(src_bus->u.cbus.slow_user, top_user))
4672 /* If source bus top user is slower than all users on destination bus,
4673 move top user; otherwise move all users slower than the top one */
4674 if (!dst_bus->u.cbus.slow_user ||
4675 !bus_user_is_slower(dst_bus->u.cbus.slow_user, top_user)) {
4676 cbus_move_enabled_user(top_user, dst_bus, src_bus);
4678 list_for_each_safe(pos, n, &src_bus->shared_bus_list) {
4679 c = list_entry(pos, struct clk, u.shared_bus_user.node);
4680 if (c->u.shared_bus_user.enabled &&
4681 c->u.shared_bus_user.client &&
4682 bus_user_is_slower(c, top_user))
4683 cbus_move_enabled_user(c, dst_bus, src_bus);
4687 /* Update destination bus 1st (move clients), then source */
4688 tegra_clk_shared_bus_update(dst_bus);
4689 tegra_clk_shared_bus_update(src_bus);
4694 static struct clk_ops tegra_clk_cbus_ops = {
4695 .init = tegra11_clk_cbus_init,
4696 .enable = tegra11_clk_cbus_enable,
4697 .set_rate = tegra11_clk_cbus_set_rate,
4698 .round_rate = tegra11_clk_cbus_round_rate,
4699 .shared_bus_update = tegra11_clk_cbus_update,
4702 /* shared bus ops */
4704 * Some clocks may have multiple downstream users that need to request a
4705 * higher clock rate. Shared bus clocks provide a unique shared_bus_user
4706 * clock to each user. The frequency of the bus is set to the highest
4707 * enabled shared_bus_user clock, with a minimum value set by the
4711 static unsigned long tegra11_clk_shared_bus_update(
4712 struct clk *bus, struct clk **bus_top, struct clk **bus_slow)
4715 struct clk *slow = NULL;
4716 struct clk *top = NULL;
4718 unsigned long override_rate = 0;
4719 unsigned long top_rate = 0;
4720 unsigned long rate = bus->min_rate;
4721 unsigned long bw = 0;
4722 unsigned long ceiling = bus->max_rate;
4723 u8 emc_bw_efficiency = tegra_emc_bw_efficiency;
4725 list_for_each_entry(c, &bus->shared_bus_list,
4726 u.shared_bus_user.node) {
4728 * Ignore requests from disabled floor and bw users, and from
4729 * auto-users riding the bus. Always honor ceiling users, even
4730 * if they are disabled - we do not want to keep enabled parent
4731 * bus just because ceiling is set.
4733 if (c->u.shared_bus_user.enabled ||
4734 (c->u.shared_bus_user.mode == SHARED_CEILING)) {
4735 unsigned long request_rate = c->u.shared_bus_user.rate *
4738 switch (c->u.shared_bus_user.mode) {
4741 if (bw > bus->max_rate)
4744 case SHARED_CEILING:
4745 ceiling = min(request_rate, ceiling);
4747 case SHARED_OVERRIDE:
4748 if (override_rate == 0)
4749 override_rate = request_rate;
4755 rate = max(request_rate, rate);
4756 if (c->u.shared_bus_user.client) {
4757 if (top_rate < request_rate) {
4758 top_rate = request_rate;
4760 } else if ((top_rate == request_rate) &&
4761 bus_user_is_slower(c, top)) {
4766 if (c->u.shared_bus_user.client &&
4767 (!slow || bus_user_is_slower(c, slow)))
4772 if ((bus->flags & PERIPH_EMC_ENB) && bw && (emc_bw_efficiency < 100)) {
4773 bw = emc_bw_efficiency ?
4774 (bw / emc_bw_efficiency) : bus->max_rate;
4775 bw = (bw < bus->max_rate / 100) ? (bw * 100) : bus->max_rate;
4778 rate = override_rate ? : min(max(rate, bw), ceiling);
4787 static int tegra_clk_shared_bus_migrate_users(struct clk *user)
4789 if (detach_shared_bus)
4792 /* Only cbus migration is supported */
4793 if (user->flags & PERIPH_ON_CBUS)
4794 return tegra11_clk_cbus_migrate_users(user);
4798 static void tegra_clk_shared_bus_user_init(struct clk *c)
4800 c->max_rate = c->parent->max_rate;
4801 c->u.shared_bus_user.rate = c->parent->max_rate;
4805 if (c->u.shared_bus_user.client_id) {
4806 c->u.shared_bus_user.client =
4807 tegra_get_clock_by_name(c->u.shared_bus_user.client_id);
4808 if (!c->u.shared_bus_user.client) {
4809 pr_err("%s: could not find clk %s\n", __func__,
4810 c->u.shared_bus_user.client_id);
4813 c->u.shared_bus_user.client->flags |=
4814 c->parent->flags & PERIPH_ON_CBUS;
4815 c->flags |= c->parent->flags & PERIPH_ON_CBUS;
4816 c->div = c->u.shared_bus_user.client_div ? : 1;
4820 list_add_tail(&c->u.shared_bus_user.node,
4821 &c->parent->shared_bus_list);
4825 * Shared bus and its children/users have reversed rate relations - user rates
4826 * determine bus rate. Hence switching user from one parent/bus to another may
4827 * change rates of both parents. Therefore we need a cross-bus lock on top of
4828 * individual user and bus locks. For now limit bus switch support to cansleep
4829 * users with cross-clock mutex only.
4831 static int tegra_clk_shared_bus_user_set_parent(struct clk *c, struct clk *p)
4833 const struct clk_mux_sel *sel;
4835 if (detach_shared_bus)
4841 if (!(c->inputs && c->cross_clk_mutex && clk_cansleep(c)))
4844 for (sel = c->inputs; sel->input != NULL; sel++) {
4845 if (sel->input == p)
4854 list_move_tail(&c->u.shared_bus_user.node, &p->shared_bus_list);
4855 tegra_clk_shared_bus_update(p);
4856 tegra_clk_shared_bus_update(c->parent);
4858 if (c->refcnt && c->parent)
4859 clk_disable(c->parent);
4866 static int tegra_clk_shared_bus_user_set_rate(struct clk *c, unsigned long rate)
4868 c->u.shared_bus_user.rate = rate;
4869 tegra_clk_shared_bus_update(c->parent);
4871 if (c->cross_clk_mutex && clk_cansleep(c))
4872 tegra_clk_shared_bus_migrate_users(c);
4877 static long tegra_clk_shared_bus_user_round_rate(
4878 struct clk *c, unsigned long rate)
4880 /* Defer rounding requests until aggregated. BW users must not be
4881 rounded at all, others just clipped to bus range (some clients
4882 may use round api to find limits) */
4883 if (c->u.shared_bus_user.mode != SHARED_BW) {
4887 if (rate > c->parent->max_rate)
4888 rate = c->parent->max_rate;
4889 else if (rate < c->parent->min_rate)
4890 rate = c->parent->min_rate;
4898 static int tegra_clk_shared_bus_user_enable(struct clk *c)
4902 c->u.shared_bus_user.enabled = true;
4903 tegra_clk_shared_bus_update(c->parent);
4904 if (c->u.shared_bus_user.client)
4905 ret = clk_enable(c->u.shared_bus_user.client);
4907 if (c->cross_clk_mutex && clk_cansleep(c))
4908 tegra_clk_shared_bus_migrate_users(c);
4913 static void tegra_clk_shared_bus_user_disable(struct clk *c)
4915 if (c->u.shared_bus_user.client)
4916 clk_disable(c->u.shared_bus_user.client);
4917 c->u.shared_bus_user.enabled = false;
4918 tegra_clk_shared_bus_update(c->parent);
4920 if (c->cross_clk_mutex && clk_cansleep(c))
4921 tegra_clk_shared_bus_migrate_users(c);
4924 static void tegra_clk_shared_bus_user_reset(struct clk *c, bool assert)
4926 if (c->u.shared_bus_user.client) {
4927 if (c->u.shared_bus_user.client->ops &&
4928 c->u.shared_bus_user.client->ops->reset)
4929 c->u.shared_bus_user.client->ops->reset(
4930 c->u.shared_bus_user.client, assert);
4934 static struct clk_ops tegra_clk_shared_bus_user_ops = {
4935 .init = tegra_clk_shared_bus_user_init,
4936 .enable = tegra_clk_shared_bus_user_enable,
4937 .disable = tegra_clk_shared_bus_user_disable,
4938 .set_parent = tegra_clk_shared_bus_user_set_parent,
4939 .set_rate = tegra_clk_shared_bus_user_set_rate,
4940 .round_rate = tegra_clk_shared_bus_user_round_rate,
4941 .reset = tegra_clk_shared_bus_user_reset,
4944 /* coupled gate ops */
4946 * Some clocks may have common enable/disable control, but run at different
4947 * rates, and have different dvfs tables. Coupled gate clock synchronize
4948 * enable/disable operations for such clocks.
4951 static int tegra11_clk_coupled_gate_enable(struct clk *c)
4954 const struct clk_mux_sel *sel;
4957 pr_debug("%s on clock %s\n", __func__, c->name);
4959 for (sel = c->inputs; sel->input != NULL; sel++) {
4960 if (sel->input == c->parent)
4963 ret = clk_enable(sel->input);
4965 while(sel != c->inputs) {
4967 if (sel->input == c->parent)
4969 clk_disable(sel->input);
4975 return tegra11_periph_clk_enable(c);
4978 static void tegra11_clk_coupled_gate_disable(struct clk *c)
4980 const struct clk_mux_sel *sel;
4983 pr_debug("%s on clock %s\n", __func__, c->name);
4985 tegra11_periph_clk_disable(c);
4987 for (sel = c->inputs; sel->input != NULL; sel++) {
4988 if (sel->input == c->parent)
4991 if (sel->input->set) /* enforce coupling after boot only */
4992 clk_disable(sel->input);
4996 static struct clk_ops tegra_clk_coupled_gate_ops = {
4997 .init = tegra11_periph_clk_init,
4998 .enable = tegra11_clk_coupled_gate_enable,
4999 .disable = tegra11_clk_coupled_gate_disable,
5000 .reset = &tegra11_periph_clk_reset,
5004 /* Clock definitions */
5005 static struct clk tegra_clk_32k = {
5012 static struct clk tegra_clk_m = {
5014 .flags = ENABLE_ON_INIT,
5015 .ops = &tegra_clk_m_ops,
5018 .max_rate = 48000000,
5021 static struct clk tegra_clk_m_div2 = {
5022 .name = "clk_m_div2",
5023 .ops = &tegra_clk_m_div_ops,
5024 .parent = &tegra_clk_m,
5028 .max_rate = 24000000,
5031 static struct clk tegra_clk_m_div4 = {
5032 .name = "clk_m_div4",
5033 .ops = &tegra_clk_m_div_ops,
5034 .parent = &tegra_clk_m,
5038 .max_rate = 12000000,
5041 static struct clk tegra_pll_ref = {
5043 .flags = ENABLE_ON_INIT,
5044 .ops = &tegra_pll_ref_ops,
5045 .parent = &tegra_clk_m,
5046 .max_rate = 26000000,
5049 static struct clk_pll_freq_table tegra_pll_c_freq_table[] = {
5050 { 12000000, 624000000, 104, 1, 2},
5051 { 12000000, 600000000, 100, 1, 2},
5052 { 13000000, 600000000, 92, 1, 2}, /* actual: 598.0 MHz */
5053 { 16800000, 600000000, 71, 1, 2}, /* actual: 596.4 MHz */
5054 { 19200000, 600000000, 62, 1, 2}, /* actual: 595.2 MHz */
5055 { 26000000, 600000000, 92, 2, 2}, /* actual: 598.0 MHz */
5056 { 0, 0, 0, 0, 0, 0 },
5059 static struct clk tegra_pll_c = {
5061 .ops = &tegra_pllxc_ops,
5063 .parent = &tegra_pll_ref,
5064 .max_rate = 1400000000,
5066 .input_min = 12000000,
5067 .input_max = 800000000,
5069 .cf_max = 19200000, /* s/w policy, h/w capability 50 MHz */
5070 .vco_min = 600000000,
5071 .vco_max = 1400000000,
5072 .freq_table = tegra_pll_c_freq_table,
5074 .misc1 = 0x88 - 0x80,
5075 .round_p_to_pdiv = pllxc_round_p_to_pdiv,
5079 static struct clk tegra_pll_c_out1 = {
5080 .name = "pll_c_out1",
5081 .ops = &tegra_pll_div_ops,
5082 .flags = DIV_U71 | PERIPH_ON_CBUS,
5083 .parent = &tegra_pll_c,
5086 .max_rate = 700000000,
5089 static struct clk_pll_freq_table tegra_pll_cx_freq_table[] = {
5090 { 12000000, 600000000, 100, 1, 2},
5091 { 13000000, 600000000, 92, 1, 2}, /* actual: 598.0 MHz */
5092 { 16800000, 600000000, 71, 1, 2}, /* actual: 596.4 MHz */
5093 { 19200000, 600000000, 62, 1, 2}, /* actual: 595.2 MHz */
5094 { 26000000, 600000000, 92, 2, 2}, /* actual: 598.0 MHz */
5095 { 0, 0, 0, 0, 0, 0 },
5098 static struct clk tegra_pll_c2 = {
5100 .ops = &tegra_pllcx_ops,
5101 .flags = PLL_ALT_MISC_REG,
5103 .parent = &tegra_pll_ref,
5104 .max_rate = 1200000000,
5106 .input_min = 12000000,
5107 .input_max = 48000000,
5110 .vco_min = 600000000,
5111 .vco_max = 1200000000,
5112 .freq_table = tegra_pll_cx_freq_table,
5114 .misc1 = 0x4f0 - 0x4e8,
5115 .round_p_to_pdiv = pllcx_round_p_to_pdiv,
5119 static struct clk tegra_pll_c3 = {
5121 .ops = &tegra_pllcx_ops,
5122 .flags = PLL_ALT_MISC_REG,
5124 .parent = &tegra_pll_ref,
5125 .max_rate = 1200000000,
5127 .input_min = 12000000,
5128 .input_max = 48000000,
5131 .vco_min = 600000000,
5132 .vco_max = 1200000000,
5133 .freq_table = tegra_pll_cx_freq_table,
5135 .misc1 = 0x504 - 0x4fc,
5136 .round_p_to_pdiv = pllcx_round_p_to_pdiv,
5140 static struct clk_pll_freq_table tegra_pll_m_freq_table[] = {
5141 { 12000000, 800000000, 66, 1, 1}, /* actual: 792.0 MHz */
5142 { 13000000, 800000000, 61, 1, 1}, /* actual: 793.0 MHz */
5143 { 16800000, 800000000, 47, 1, 1}, /* actual: 789.6 MHz */
5144 { 19200000, 800000000, 41, 1, 1}, /* actual: 787.2 MHz */
5145 { 26000000, 800000000, 61, 2, 1}, /* actual: 793.0 MHz */
5146 { 0, 0, 0, 0, 0, 0 },
5149 static struct clk tegra_pll_m = {
5152 .ops = &tegra_pllm_ops,
5154 .parent = &tegra_pll_ref,
5155 .max_rate = 1066000000,
5157 .input_min = 12000000,
5158 .input_max = 500000000,
5160 .cf_max = 19200000, /* s/w policy, h/w capability 50 MHz */
5161 .vco_min = 400000000,
5162 .vco_max = 1066000000,
5163 .freq_table = tegra_pll_m_freq_table,
5165 .misc1 = 0x98 - 0x90,
5166 .round_p_to_pdiv = pllm_round_p_to_pdiv,
5170 static struct clk tegra_pll_m_out1 = {
5171 .name = "pll_m_out1",
5172 .ops = &tegra_pll_div_ops,
5173 .flags = DIV_U71 | DIV_U71_INT,
5174 .parent = &tegra_pll_m,
5177 .max_rate = 600000000,
5180 static struct clk_pll_freq_table tegra_pll_p_freq_table[] = {
5181 { 12000000, 216000000, 432, 12, 2, 8},
5182 { 13000000, 216000000, 432, 13, 2, 8},
5183 { 16800000, 216000000, 360, 14, 2, 8},
5184 { 19200000, 216000000, 360, 16, 2, 8},
5185 { 26000000, 216000000, 432, 26, 2, 8},
5186 { 0, 0, 0, 0, 0, 0 },
5189 static struct clk tegra_pll_p = {
5191 .flags = ENABLE_ON_INIT | PLL_FIXED | PLL_HAS_CPCON,
5192 .ops = &tegra_pllp_ops,
5194 .parent = &tegra_pll_ref,
5195 .max_rate = 432000000,
5197 .input_min = 2000000,
5198 .input_max = 31000000,
5201 .vco_min = 200000000,
5202 .vco_max = 700000000,
5203 .freq_table = tegra_pll_p_freq_table,
5208 static struct clk tegra_pll_p_out1 = {
5209 .name = "pll_p_out1",
5210 .ops = &tegra_pll_div_ops,
5211 .flags = DIV_U71 | DIV_U71_FIXED,
5212 .parent = &tegra_pll_p,
5215 .max_rate = 432000000,
5218 static struct clk tegra_pll_p_out2 = {
5219 .name = "pll_p_out2",
5220 .ops = &tegra_pll_div_ops,
5221 .flags = DIV_U71 | DIV_U71_FIXED | DIV_U71_INT,
5222 .parent = &tegra_pll_p,
5225 .max_rate = 432000000,
5228 static struct clk tegra_pll_p_out3 = {
5229 .name = "pll_p_out3",
5230 .ops = &tegra_pll_div_ops,
5231 .flags = DIV_U71 | DIV_U71_FIXED,
5232 .parent = &tegra_pll_p,
5235 .max_rate = 432000000,
5238 static struct clk tegra_pll_p_out4 = {
5239 .name = "pll_p_out4",
5240 .ops = &tegra_pll_div_ops,
5241 .flags = DIV_U71 | DIV_U71_FIXED,
5242 .parent = &tegra_pll_p,
5245 .max_rate = 432000000,
5248 static struct clk_pll_freq_table tegra_pll_a_freq_table[] = {
5249 { 9600000, 282240000, 147, 5, 1, 4},
5250 { 9600000, 368640000, 192, 5, 1, 4},
5251 { 9600000, 240000000, 200, 8, 1, 8},
5253 { 28800000, 282240000, 245, 25, 1, 8},
5254 { 28800000, 368640000, 320, 25, 1, 8},
5255 { 28800000, 240000000, 200, 24, 1, 8},
5256 { 0, 0, 0, 0, 0, 0 },
5259 static struct clk tegra_pll_a = {
5261 .flags = PLL_HAS_CPCON,
5262 .ops = &tegra_pll_ops,
5264 .parent = &tegra_pll_p_out1,
5265 .max_rate = 700000000,
5267 .input_min = 2000000,
5268 .input_max = 31000000,
5271 .vco_min = 200000000,
5272 .vco_max = 700000000,
5273 .freq_table = tegra_pll_a_freq_table,
5278 static struct clk tegra_pll_a_out0 = {
5279 .name = "pll_a_out0",
5280 .ops = &tegra_pll_div_ops,
5282 .parent = &tegra_pll_a,
5285 .max_rate = 100000000,
5288 static struct clk_pll_freq_table tegra_pll_d_freq_table[] = {
5289 { 12000000, 216000000, 864, 12, 4, 12},
5290 { 13000000, 216000000, 864, 13, 4, 12},
5291 { 16800000, 216000000, 720, 14, 4, 12},
5292 { 19200000, 216000000, 720, 16, 4, 12},
5293 { 26000000, 216000000, 864, 26, 4, 12},
5295 { 12000000, 594000000, 594, 12, 1, 12},
5296 { 13000000, 594000000, 594, 13, 1, 12},
5297 { 16800000, 594000000, 495, 14, 1, 12},
5298 { 19200000, 594000000, 495, 16, 1, 12},
5299 { 26000000, 594000000, 594, 26, 1, 12},
5301 { 12000000, 1000000000, 1000, 12, 1, 12},
5302 { 13000000, 1000000000, 1000, 13, 1, 12},
5303 { 19200000, 1000000000, 625, 12, 1, 12},
5304 { 26000000, 1000000000, 1000, 26, 1, 12},
5306 { 0, 0, 0, 0, 0, 0 },
5309 static struct clk tegra_pll_d = {
5311 .flags = PLL_HAS_CPCON | PLLD,
5312 .ops = &tegra_plld_ops,
5314 .parent = &tegra_pll_ref,
5315 .max_rate = 1000000000,
5317 .input_min = 2000000,
5318 .input_max = 40000000,
5321 .vco_min = 500000000,
5322 .vco_max = 1000000000,
5323 .freq_table = tegra_pll_d_freq_table,
5329 static struct clk tegra_pll_d_out0 = {
5330 .name = "pll_d_out0",
5331 .ops = &tegra_pll_div_ops,
5332 .flags = DIV_2 | PLLD,
5333 .parent = &tegra_pll_d,
5334 .max_rate = 500000000,
5337 static struct clk tegra_pll_d2 = {
5339 .flags = PLL_HAS_CPCON | PLL_ALT_MISC_REG | PLLD,
5340 .ops = &tegra_plld_ops,
5342 .parent = &tegra_pll_ref,
5343 .max_rate = 1000000000,
5345 .input_min = 2000000,
5346 .input_max = 40000000,
5349 .vco_min = 500000000,
5350 .vco_max = 1000000000,
5351 .freq_table = tegra_pll_d_freq_table,
5353 .cpcon_default = 12,
5357 static struct clk tegra_pll_d2_out0 = {
5358 .name = "pll_d2_out0",
5359 .ops = &tegra_pll_div_ops,
5360 .flags = DIV_2 | PLLD,
5361 .parent = &tegra_pll_d2,
5362 .max_rate = 500000000,
5365 static struct clk_pll_freq_table tegra_pll_u_freq_table[] = {
5366 { 12000000, 480000000, 960, 12, 2, 12},
5367 { 13000000, 480000000, 960, 13, 2, 12},
5368 { 16800000, 480000000, 400, 7, 2, 5},
5369 { 19200000, 480000000, 200, 4, 2, 3},
5370 { 26000000, 480000000, 960, 26, 2, 12},
5371 { 0, 0, 0, 0, 0, 0 },
5374 static struct clk tegra_pll_u = {
5376 .flags = PLL_HAS_CPCON | PLLU,
5377 .ops = &tegra_pll_ops,
5379 .parent = &tegra_pll_ref,
5380 .max_rate = 480000000,
5382 .input_min = 2000000,
5383 .input_max = 40000000,
5386 .vco_min = 480000000,
5387 .vco_max = 960000000,
5388 .freq_table = tegra_pll_u_freq_table,
5390 .cpcon_default = 12,
5394 static struct clk tegra_pll_u_480M = {
5395 .name = "pll_u_480M",
5397 .ops = &tegra_pll_div_ops,
5400 .parent = &tegra_pll_u,
5403 .max_rate = 480000000,
5406 static struct clk tegra_pll_u_60M = {
5407 .name = "pll_u_60M",
5409 .ops = &tegra_pll_div_ops,
5412 .parent = &tegra_pll_u,
5415 .max_rate = 60000000,
5418 static struct clk tegra_pll_u_48M = {
5419 .name = "pll_u_48M",
5421 .ops = &tegra_pll_div_ops,
5424 .parent = &tegra_pll_u,
5427 .max_rate = 48000000,
5430 static struct clk tegra_pll_u_12M = {
5431 .name = "pll_u_12M",
5433 .ops = &tegra_pll_div_ops,
5436 .parent = &tegra_pll_u,
5439 .max_rate = 12000000,
5442 static struct clk_pll_freq_table tegra_pll_x_freq_table[] = {
5444 { 12000000, 1000000000, 83, 1, 1}, /* actual: 996.0 MHz */
5445 { 13000000, 1000000000, 76, 1, 1}, /* actual: 988.0 MHz */
5446 { 16800000, 1000000000, 59, 1, 1}, /* actual: 991.2 MHz */
5447 { 19200000, 1000000000, 52, 1, 1}, /* actual: 998.4 MHz */
5448 { 26000000, 1000000000, 76, 2, 1}, /* actual: 988.0 MHz */
5450 { 0, 0, 0, 0, 0, 0 },
5453 static struct clk tegra_pll_x = {
5455 .flags = PLL_ALT_MISC_REG | PLLX,
5456 .ops = &tegra_pllxc_ops,
5458 .parent = &tegra_pll_ref,
5459 .max_rate = 1800000000,
5461 .input_min = 12000000,
5462 .input_max = 800000000,
5464 .cf_max = 19200000, /* s/w policy, h/w capability 50 MHz */
5465 .vco_min = 700000000,
5466 .vco_max = 2400000000U,
5467 .freq_table = tegra_pll_x_freq_table,
5469 .misc1 = 0x510 - 0xe0,
5470 .round_p_to_pdiv = pllxc_round_p_to_pdiv,
5474 static struct clk tegra_pll_x_out0 = {
5475 .name = "pll_x_out0",
5476 .ops = &tegra_pll_div_ops,
5477 .flags = DIV_2 | PLLX,
5478 .parent = &tegra_pll_x,
5479 .max_rate = 700000000,
5482 /* FIXME: remove; for now, should be always checked-in as "0" */
5483 #define USE_LP_CPU_TO_TEST_DFLL 0
5485 static struct clk tegra_dfll_cpu = {
5488 .ops = &tegra_dfll_ops,
5490 .max_rate = 2000000000,
5493 static struct clk tegra_pll_re_vco = {
5494 .name = "pll_re_vco",
5495 .flags = PLL_ALT_MISC_REG,
5496 .ops = &tegra_pllre_ops,
5498 .parent = &tegra_pll_ref,
5499 .max_rate = 600000000,
5501 .input_min = 12000000,
5502 .input_max = 1000000000,
5504 .cf_max = 19200000, /* s/w policy, h/w capability 38 MHz */
5505 .vco_min = 300000000,
5506 .vco_max = 600000000,
5508 .round_p_to_pdiv = pllre_round_p_to_pdiv,
5512 static struct clk tegra_pll_re_out = {
5513 .name = "pll_re_out",
5514 .ops = &tegra_pllre_out_ops,
5515 .parent = &tegra_pll_re_vco,
5517 .max_rate = 600000000,
5520 static struct clk_pll_freq_table tegra_pll_e_freq_table[] = {
5521 /* PLLE special case: use cpcon field to store cml divider value */
5522 { 336000000, 100000000, 100, 21, 16, 11},
5523 { 312000000, 100000000, 200, 26, 24, 13},
5524 { 0, 0, 0, 0, 0, 0 },
5527 static struct clk tegra_pll_e = {
5529 .flags = PLL_ALT_MISC_REG,
5530 .ops = &tegra_plle_ops,
5532 .max_rate = 100000000,
5534 .input_min = 12000000,
5535 .input_max = 1000000000,
5538 .vco_min = 1600000000,
5539 .vco_max = 2400000000U,
5540 .freq_table = tegra_pll_e_freq_table,
5542 .fixed_rate = 100000000,
5546 static struct clk tegra_pciex_clk = {
5548 .parent = &tegra_pll_e,
5549 .ops = &tegra_pciex_clk_ops,
5550 .max_rate = 100000000,
5556 /* Audio sync clocks */
5557 #define SYNC_SOURCE(_id, _dev) \
5559 .name = #_id "_sync", \
5562 .con_id = "ext_audio_sync", \
5565 .max_rate = 24000000, \
5566 .ops = &tegra_sync_source_ops \
5568 static struct clk tegra_sync_source_list[] = {
5569 SYNC_SOURCE(spdif_in, tegra30-spdif),
5570 SYNC_SOURCE(i2s0, tegra30-i2s.0),
5571 SYNC_SOURCE(i2s1, tegra30-i2s.1),
5572 SYNC_SOURCE(i2s2, tegra30-i2s.2),
5573 SYNC_SOURCE(i2s3, tegra30-i2s.3),
5574 SYNC_SOURCE(i2s4, tegra30-i2s.4),
5575 SYNC_SOURCE(vimclk, vimclk),
5578 static struct clk_mux_sel mux_d_audio_clk[] = {
5579 { .input = &tegra_pll_a_out0, .value = 0},
5580 { .input = &tegra_pll_p, .value = 0x8000},
5581 { .input = &tegra_clk_m, .value = 0xc000},
5582 { .input = &tegra_sync_source_list[0], .value = 0xE000},
5583 { .input = &tegra_sync_source_list[1], .value = 0xE001},
5584 { .input = &tegra_sync_source_list[2], .value = 0xE002},
5585 { .input = &tegra_sync_source_list[3], .value = 0xE003},
5586 { .input = &tegra_sync_source_list[4], .value = 0xE004},
5587 { .input = &tegra_sync_source_list[5], .value = 0xE005},
5588 { .input = &tegra_pll_a_out0, .value = 0xE006},
5589 { .input = &tegra_sync_source_list[6], .value = 0xE007},
5593 static struct clk_mux_sel mux_audio_sync_clk[] =
5595 { .input = &tegra_sync_source_list[0], .value = 0},
5596 { .input = &tegra_sync_source_list[1], .value = 1},
5597 { .input = &tegra_sync_source_list[2], .value = 2},
5598 { .input = &tegra_sync_source_list[3], .value = 3},
5599 { .input = &tegra_sync_source_list[4], .value = 4},
5600 { .input = &tegra_sync_source_list[5], .value = 5},
5601 { .input = &tegra_pll_a_out0, .value = 6},
5602 { .input = &tegra_sync_source_list[6], .value = 7},
5606 #define AUDIO_SYNC_CLK(_id, _dev, _index) \
5611 .con_id = "audio_sync", \
5613 .inputs = mux_audio_sync_clk, \
5614 .reg = 0x4A0 + (_index) * 4, \
5615 .max_rate = 24000000, \
5616 .ops = &tegra_audio_sync_clk_ops \
5618 static struct clk tegra_clk_audio_list[] = {
5619 AUDIO_SYNC_CLK(audio0, tegra30-i2s.0, 0),
5620 AUDIO_SYNC_CLK(audio1, tegra30-i2s.1, 1),
5621 AUDIO_SYNC_CLK(audio2, tegra30-i2s.2, 2),
5622 AUDIO_SYNC_CLK(audio3, tegra30-i2s.3, 3),
5623 AUDIO_SYNC_CLK(audio4, tegra30-i2s.4, 4),
5624 AUDIO_SYNC_CLK(audio, tegra30-spdif, 5), /* SPDIF */
5627 #define AUDIO_SYNC_2X_CLK(_id, _dev, _index) \
5629 .name = #_id "_2x", \
5632 .con_id = "audio_sync_2x" \
5634 .flags = PERIPH_NO_RESET, \
5635 .max_rate = 48000000, \
5636 .ops = &tegra_clk_double_ops, \
5638 .reg_shift = 24 + (_index), \
5639 .parent = &tegra_clk_audio_list[(_index)], \
5641 .clk_num = 113 + (_index), \
5644 static struct clk tegra_clk_audio_2x_list[] = {
5645 AUDIO_SYNC_2X_CLK(audio0, tegra30-i2s.0, 0),
5646 AUDIO_SYNC_2X_CLK(audio1, tegra30-i2s.1, 1),
5647 AUDIO_SYNC_2X_CLK(audio2, tegra30-i2s.2, 2),
5648 AUDIO_SYNC_2X_CLK(audio3, tegra30-i2s.3, 3),
5649 AUDIO_SYNC_2X_CLK(audio4, tegra30-i2s.4, 4),
5650 AUDIO_SYNC_2X_CLK(audio, tegra30-spdif, 5), /* SPDIF */
5653 #define MUX_I2S_SPDIF(_id, _index) \
5654 static struct clk_mux_sel mux_pllaout0_##_id##_2x_pllp_clkm[] = { \
5655 {.input = &tegra_pll_a_out0, .value = 0}, \
5656 {.input = &tegra_clk_audio_2x_list[(_index)], .value = 1}, \
5657 {.input = &tegra_pll_p, .value = 2}, \
5658 {.input = &tegra_clk_m, .value = 3}, \
5661 MUX_I2S_SPDIF(audio0, 0);
5662 MUX_I2S_SPDIF(audio1, 1);
5663 MUX_I2S_SPDIF(audio2, 2);
5664 MUX_I2S_SPDIF(audio3, 3);
5665 MUX_I2S_SPDIF(audio4, 4);
5666 MUX_I2S_SPDIF(audio, 5); /* SPDIF */
5668 /* External clock outputs (through PMC) */
5669 #define MUX_EXTERN_OUT(_id) \
5670 static struct clk_mux_sel mux_clkm_clkm2_clkm4_extern##_id[] = { \
5671 {.input = &tegra_clk_m, .value = 0}, \
5672 {.input = &tegra_clk_m_div2, .value = 1}, \
5673 {.input = &tegra_clk_m_div4, .value = 2}, \
5674 {.input = NULL, .value = 3}, /* placeholder */ \
5681 static struct clk_mux_sel *mux_extern_out_list[] = {
5682 mux_clkm_clkm2_clkm4_extern1,
5683 mux_clkm_clkm2_clkm4_extern2,
5684 mux_clkm_clkm2_clkm4_extern3,
5687 #define CLK_OUT_CLK(_id, _max_rate) \
5689 .name = "clk_out_" #_id, \
5691 .dev_id = "clk_out_" #_id, \
5692 .con_id = "extern" #_id, \
5694 .ops = &tegra_clk_out_ops, \
5696 .inputs = mux_clkm_clkm2_clkm4_extern##_id, \
5697 .flags = MUX_CLK_OUT, \
5698 .max_rate = _max_rate, \
5700 .clk_num = (_id - 1) * 8 + 2, \
5703 static struct clk tegra_clk_out_list[] = {
5704 CLK_OUT_CLK(1, 12288000),
5705 CLK_OUT_CLK(2, 40800000),
5706 CLK_OUT_CLK(3, 12288000),
5709 /* called after peripheral external clocks are initialized */
5710 static void init_clk_out_mux(void)
5715 /* output clock con_id is the name of peripheral
5716 external clock connected to input 3 of the output mux */
5717 for (i = 0; i < ARRAY_SIZE(tegra_clk_out_list); i++) {
5718 c = tegra_get_clock_by_name(
5719 tegra_clk_out_list[i].lookup.con_id);
5721 pr_err("%s: could not find clk %s\n", __func__,
5722 tegra_clk_out_list[i].lookup.con_id);
5723 mux_extern_out_list[i][3].input = c;
5727 /* Peripheral muxes */
5728 static struct clk_mux_sel mux_cclk_g[] = {
5729 { .input = &tegra_clk_m, .value = 0},
5730 { .input = &tegra_pll_c, .value = 1},
5731 { .input = &tegra_clk_32k, .value = 2},
5732 { .input = &tegra_pll_m, .value = 3},
5733 { .input = &tegra_pll_p, .value = 4},
5734 { .input = &tegra_pll_p_out4, .value = 5},
5735 /* { .input = &tegra_pll_c2, .value = 6}, - no use on tegra11x */
5736 /* { .input = &tegra_clk_c3, .value = 7}, - no use on tegra11x */
5737 { .input = &tegra_pll_x, .value = 8},
5738 { .input = &tegra_dfll_cpu, .value = 15},
5742 static struct clk_mux_sel mux_cclk_lp[] = {
5743 { .input = &tegra_clk_m, .value = 0},
5744 { .input = &tegra_pll_c, .value = 1},
5745 { .input = &tegra_clk_32k, .value = 2},
5746 { .input = &tegra_pll_m, .value = 3},
5747 { .input = &tegra_pll_p, .value = 4},
5748 { .input = &tegra_pll_p_out4, .value = 5},
5749 /* { .input = &tegra_pll_c2, .value = 6}, - no use on tegra11x */
5750 /* { .input = &tegra_clk_c3, .value = 7}, - no use on tegra11x */
5751 { .input = &tegra_pll_x_out0, .value = 8},
5752 #if USE_LP_CPU_TO_TEST_DFLL
5753 { .input = &tegra_dfll_cpu, .value = 15},
5755 { .input = &tegra_pll_x, .value = 8 | SUPER_LP_DIV2_BYPASS},
5759 static struct clk_mux_sel mux_sclk[] = {
5760 { .input = &tegra_clk_m, .value = 0},
5761 { .input = &tegra_pll_c_out1, .value = 1},
5762 { .input = &tegra_pll_p_out4, .value = 2},
5763 { .input = &tegra_pll_p_out3, .value = 3},
5764 { .input = &tegra_pll_p_out2, .value = 4},
5765 /* { .input = &tegra_clk_d, .value = 5}, - no use on tegra11x */
5766 { .input = &tegra_clk_32k, .value = 6},
5767 { .input = &tegra_pll_m_out1, .value = 7},
5771 static struct clk tegra_clk_cclk_g = {
5773 .flags = DIV_U71 | DIV_U71_INT | MUX,
5774 .inputs = mux_cclk_g,
5776 .ops = &tegra_super_ops,
5777 .max_rate = 2000000000,
5780 static struct clk tegra_clk_cclk_lp = {
5782 .flags = DIV_2 | DIV_U71 | DIV_U71_INT | MUX,
5783 .inputs = mux_cclk_lp,
5785 .ops = &tegra_super_ops,
5786 .max_rate = 700000000,
5789 static struct clk tegra_clk_sclk = {
5793 .ops = &tegra_super_ops,
5794 .max_rate = 336000000,
5795 .min_rate = 24000000,
5798 static struct clk tegra_clk_virtual_cpu_g = {
5800 .parent = &tegra_clk_cclk_g,
5801 .ops = &tegra_cpu_ops,
5802 .max_rate = 2000000000,
5804 .main = &tegra_pll_x,
5805 .backup = &tegra_pll_p_out4,
5806 .dynamic = &tegra_dfll_cpu,
5811 static struct clk tegra_clk_virtual_cpu_lp = {
5813 .parent = &tegra_clk_cclk_lp,
5814 .ops = &tegra_cpu_ops,
5815 .max_rate = 700000000,
5817 .main = &tegra_pll_x,
5818 .backup = &tegra_pll_p_out4,
5819 #if USE_LP_CPU_TO_TEST_DFLL
5820 .dynamic = &tegra_dfll_cpu,
5826 static struct clk_mux_sel mux_cpu_cmplx[] = {
5827 { .input = &tegra_clk_virtual_cpu_g, .value = 0},
5828 { .input = &tegra_clk_virtual_cpu_lp, .value = 1},
5832 static struct clk tegra_clk_cpu_cmplx = {
5834 .inputs = mux_cpu_cmplx,
5835 .ops = &tegra_cpu_cmplx_ops,
5836 .max_rate = 2000000000,
5839 static struct clk tegra_clk_cop = {
5841 .parent = &tegra_clk_sclk,
5842 .ops = &tegra_cop_ops,
5843 .max_rate = 336000000,
5846 static struct clk tegra_clk_hclk = {
5849 .parent = &tegra_clk_sclk,
5852 .ops = &tegra_bus_ops,
5853 .max_rate = 336000000,
5854 .min_rate = 24000000,
5857 static struct clk tegra_clk_pclk = {
5860 .parent = &tegra_clk_hclk,
5863 .ops = &tegra_bus_ops,
5864 .max_rate = 168000000,
5865 .min_rate = 12000000,
5868 static struct raw_notifier_head sbus_rate_change_nh;
5870 static struct clk tegra_clk_sbus_cmplx = {
5872 .parent = &tegra_clk_sclk,
5873 .ops = &tegra_sbus_cmplx_ops,
5875 .pclk = &tegra_clk_pclk,
5876 .hclk = &tegra_clk_hclk,
5877 .sclk_low = &tegra_pll_p_out2,
5878 .sclk_high = &tegra_pll_m_out1,
5880 .rate_change_nh = &sbus_rate_change_nh,
5883 static struct clk tegra_clk_blink = {
5885 .parent = &tegra_clk_32k,
5887 .ops = &tegra_blink_clk_ops,
5892 /* Multimedia modules muxes */
5893 static struct clk_mux_sel mux_pllm_pllc2_c_c3_pllp_plla[] = {
5894 { .input = &tegra_pll_m, .value = 0},
5895 { .input = &tegra_pll_c2, .value = 1},
5896 { .input = &tegra_pll_c, .value = 2},
5897 { .input = &tegra_pll_c3, .value = 3},
5898 { .input = &tegra_pll_p, .value = 4},
5899 { .input = &tegra_pll_a_out0, .value = 6},
5903 static struct clk_mux_sel mux_pllm_pllc_pllp_plla[] = {
5904 { .input = &tegra_pll_m, .value = 0},
5905 { .input = &tegra_pll_c, .value = 1},
5906 { .input = &tegra_pll_p, .value = 2},
5907 { .input = &tegra_pll_a_out0, .value = 3},
5911 static struct clk_mux_sel mux_plla_pllc_pllp_clkm[] = {
5912 { .input = &tegra_pll_a_out0, .value = 0},
5913 { .input = &tegra_pll_c, .value = 1},
5914 { .input = &tegra_pll_p, .value = 2},
5915 { .input = &tegra_clk_m, .value = 3},
5920 /* FIXME: add EMC latency mux */
5921 static struct clk_mux_sel mux_pllm_pllc_pllp_clkm[] = {
5922 { .input = &tegra_pll_m, .value = 0},
5923 { .input = &tegra_pll_c, .value = 1},
5924 { .input = &tegra_pll_p, .value = 2},
5925 { .input = &tegra_clk_m, .value = 3},
5926 { .input = &tegra_pll_m, .value = 4}, /* low jitter PLLM input */
5931 /* Display subsystem muxes */
5932 static struct clk_mux_sel mux_pllp_pllm_plld_plla_pllc_plld2_clkm[] = {
5933 {.input = &tegra_pll_p, .value = 0},
5934 {.input = &tegra_pll_m, .value = 1},
5935 {.input = &tegra_pll_d_out0, .value = 2},
5936 {.input = &tegra_pll_a_out0, .value = 3},
5937 {.input = &tegra_pll_c, .value = 4},
5938 {.input = &tegra_pll_d2_out0, .value = 5},
5939 {.input = &tegra_clk_m, .value = 6},
5943 static struct clk_mux_sel mux_plld_out0_plld2_out0[] = {
5944 { .input = &tegra_pll_d_out0, .value = 0},
5945 { .input = &tegra_pll_d2_out0, .value = 1},
5949 static struct clk_mux_sel mux_pllp_pllc_clkm[] = {
5950 {.input = &tegra_pll_p, .value = 0},
5951 {.input = &tegra_pll_c, .value = 1},
5952 {.input = &tegra_clk_m, .value = 3},
5956 /* Peripheral muxes */
5957 static struct clk_mux_sel mux_pllp_pllc2_c_c3_pllm_clkm[] = {
5958 { .input = &tegra_pll_p, .value = 0},
5959 { .input = &tegra_pll_c2, .value = 1},
5960 { .input = &tegra_pll_c, .value = 2},
5961 { .input = &tegra_pll_c3, .value = 3},
5962 { .input = &tegra_pll_m, .value = 4},
5963 { .input = &tegra_clk_m, .value = 6},
5967 static struct clk_mux_sel mux_pllp_pllc_pllm_clkm[] = {
5968 { .input = &tegra_pll_p, .value = 0},
5969 { .input = &tegra_pll_c, .value = 1},
5970 { .input = &tegra_pll_m, .value = 2},
5971 { .input = &tegra_clk_m, .value = 3},
5975 static struct clk_mux_sel mux_pllp_pllc_pllm[] = {
5976 {.input = &tegra_pll_p, .value = 0},
5977 {.input = &tegra_pll_c, .value = 1},
5978 {.input = &tegra_pll_m, .value = 2},
5982 static struct clk_mux_sel mux_pllp_clkm[] = {
5983 { .input = &tegra_pll_p, .value = 0},
5984 { .input = &tegra_clk_m, .value = 3},
5988 static struct clk_mux_sel mux_pllp_pllc_clk32_clkm[] = {
5989 {.input = &tegra_pll_p, .value = 0},
5990 {.input = &tegra_pll_c, .value = 1},
5991 {.input = &tegra_clk_32k, .value = 2},
5992 {.input = &tegra_clk_m, .value = 3},
5996 static struct clk_mux_sel mux_pllp_pllc_clkm_clk32[] = {
5997 {.input = &tegra_pll_p, .value = 0},
5998 {.input = &tegra_pll_c, .value = 1},
5999 {.input = &tegra_clk_m, .value = 2},
6000 {.input = &tegra_clk_32k, .value = 3},
6004 static struct clk_mux_sel mux_plla_clk32_pllp_clkm_plle[] = {
6005 { .input = &tegra_pll_a_out0, .value = 0},
6006 { .input = &tegra_clk_32k, .value = 1},
6007 { .input = &tegra_pll_p, .value = 2},
6008 { .input = &tegra_clk_m, .value = 3},
6009 { .input = &tegra_pll_e, .value = 4},
6013 static struct clk_mux_sel mux_clkm_pllp_pllc_pllre[] = {
6014 { .input = &tegra_clk_m, .value = 0},
6015 { .input = &tegra_pll_p, .value = 1},
6016 { .input = &tegra_pll_c, .value = 3},
6017 { .input = &tegra_pll_re_out, .value = 5},
6021 static struct clk_mux_sel mux_clkm_48M_pllp_480M[] = {
6022 { .input = &tegra_clk_m, .value = 0},
6023 { .input = &tegra_pll_u_48M, .value = 1},
6024 { .input = &tegra_pll_p, .value = 2},
6025 { .input = &tegra_pll_u_480M, .value = 3},
6029 static struct clk_mux_sel mux_clkm_pllre_clk32_480M_pllc_ref[] = {
6030 { .input = &tegra_clk_m, .value = 0},
6031 { .input = &tegra_pll_re_out, .value = 1},
6032 { .input = &tegra_clk_32k, .value = 2},
6033 { .input = &tegra_pll_u_480M, .value = 3},
6034 { .input = &tegra_pll_c, .value = 4},
6035 { .input = &tegra_pll_ref, .value = 7},
6039 /* Single clock source ("fake") muxes */
6040 static struct clk_mux_sel mux_clk_m[] = {
6041 { .input = &tegra_clk_m, .value = 0},
6045 static struct clk_mux_sel mux_pllp_out3[] = {
6046 { .input = &tegra_pll_p_out3, .value = 0},
6050 static struct clk_mux_sel mux_clk_32k[] = {
6051 { .input = &tegra_clk_32k, .value = 0},
6055 /* xusb_hs has an alternative source, that is not used - therefore, xusb_hs
6056 is modeled as a single source mux */
6057 static struct clk_mux_sel mux_pllu_60M[] = {
6058 { .input = &tegra_pll_u_60M, .value = 1},
6062 static struct raw_notifier_head emc_rate_change_nh;
6064 static struct clk tegra_clk_emc = {
6066 .ops = &tegra_emc_clk_ops,
6068 .max_rate = 1066000000,
6069 .min_rate = 12750000,
6070 .inputs = mux_pllm_pllc_pllp_clkm,
6071 .flags = MUX | MUX8 | DIV_U71 | PERIPH_EMC_ENB,
6075 .rate_change_nh = &emc_rate_change_nh,
6078 #ifdef CONFIG_TEGRA_DUAL_CBUS
6080 static struct raw_notifier_head c2bus_rate_change_nh;
6081 static struct raw_notifier_head c3bus_rate_change_nh;
6083 static struct clk tegra_clk_c2bus = {
6085 .parent = &tegra_pll_c2,
6086 .ops = &tegra_clk_cbus_ops,
6087 .max_rate = 700000000,
6090 .flags = PERIPH_ON_CBUS,
6091 .shared_bus_backup = {
6092 .input = &tegra_pll_p,
6094 .rate_change_nh = &c2bus_rate_change_nh,
6096 static struct clk tegra_clk_c3bus = {
6098 .parent = &tegra_pll_c3,
6099 .ops = &tegra_clk_cbus_ops,
6100 .max_rate = 700000000,
6103 .flags = PERIPH_ON_CBUS,
6104 .shared_bus_backup = {
6105 .input = &tegra_pll_p,
6107 .rate_change_nh = &c3bus_rate_change_nh,
6110 static DEFINE_MUTEX(cbus_mutex);
6112 static struct clk_mux_sel mux_clk_cbus[] = {
6113 { .input = &tegra_clk_c2bus, .value = 0},
6114 { .input = &tegra_clk_c3bus, .value = 1},
6118 #define DUAL_CBUS_CLK(_name, _dev, _con, _parent, _id, _div, _mode)\
6125 .ops = &tegra_clk_shared_bus_user_ops, \
6126 .parent = _parent, \
6127 .inputs = mux_clk_cbus, \
6129 .u.shared_bus_user = { \
6131 .client_div = _div, \
6134 .cross_clk_mutex = &cbus_mutex, \
6139 static struct raw_notifier_head cbus_rate_change_nh;
6141 static struct clk tegra_clk_cbus = {
6143 .parent = &tegra_pll_c,
6144 .ops = &tegra_clk_cbus_ops,
6145 .max_rate = 700000000,
6148 .flags = PERIPH_ON_CBUS,
6149 .shared_bus_backup = {
6150 .input = &tegra_pll_p,
6152 .rate_change_nh = &cbus_rate_change_nh,
6156 #define PERIPH_CLK(_name, _dev, _con, _clk_num, _reg, _max, _inputs, _flags) \
6163 .ops = &tegra_periph_clk_ops, \
6165 .inputs = _inputs, \
6169 .clk_num = _clk_num, \
6173 #define PERIPH_CLK_EX(_name, _dev, _con, _clk_num, _reg, _max, _inputs, \
6183 .inputs = _inputs, \
6187 .clk_num = _clk_num, \
6191 #define D_AUDIO_CLK(_name, _dev, _con, _clk_num, _reg, _max, _inputs, _flags) \
6198 .ops = &tegra_periph_clk_ops, \
6200 .inputs = _inputs, \
6204 .clk_num = _clk_num, \
6205 .src_mask = 0xE01F << 16, \
6210 #define SHARED_CLK(_name, _dev, _con, _parent, _id, _div, _mode)\
6217 .ops = &tegra_clk_shared_bus_user_ops, \
6218 .parent = _parent, \
6219 .u.shared_bus_user = { \
6221 .client_div = _div, \
6225 struct clk tegra_list_clks[] = {
6226 PERIPH_CLK("apbdma", "tegra-dma", NULL, 34, 0, 26000000, mux_clk_m, 0),
6227 PERIPH_CLK("rtc", "rtc-tegra", NULL, 4, 0, 32768, mux_clk_32k, PERIPH_NO_RESET | PERIPH_ON_APB),
6228 PERIPH_CLK("kbc", "tegra-kbc", NULL, 36, 0, 32768, mux_clk_32k, PERIPH_NO_RESET | PERIPH_ON_APB),
6229 PERIPH_CLK("timer", "timer", NULL, 5, 0, 26000000, mux_clk_m, 0),
6230 PERIPH_CLK("kfuse", "kfuse-tegra", NULL, 40, 0, 26000000, mux_clk_m, PERIPH_ON_APB),
6231 PERIPH_CLK("fuse", "fuse-tegra", "fuse", 39, 0, 26000000, mux_clk_m, PERIPH_ON_APB),
6232 PERIPH_CLK("fuse_burn", "fuse-tegra", "fuse_burn", 39, 0, 26000000, mux_clk_m, PERIPH_ON_APB),
6233 PERIPH_CLK("apbif", "tegra30-ahub", "apbif", 107, 0, 26000000, mux_clk_m, PERIPH_ON_APB),
6234 PERIPH_CLK("i2s0", "tegra30-i2s.0", NULL, 30, 0x1d8, 24576000, mux_pllaout0_audio0_2x_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
6235 PERIPH_CLK("i2s1", "tegra30-i2s.1", NULL, 11, 0x100, 24576000, mux_pllaout0_audio1_2x_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
6236 PERIPH_CLK("i2s2", "tegra30-i2s.2", NULL, 18, 0x104, 24576000, mux_pllaout0_audio2_2x_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
6237 PERIPH_CLK("i2s3", "tegra30-i2s.3", NULL, 101, 0x3bc, 24576000, mux_pllaout0_audio3_2x_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
6238 PERIPH_CLK("i2s4", "tegra30-i2s.4", NULL, 102, 0x3c0, 24576000, mux_pllaout0_audio4_2x_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
6239 PERIPH_CLK("spdif_out", "tegra30-spdif", "spdif_out", 10, 0x108, 24576000, mux_pllaout0_audio_2x_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
6240 PERIPH_CLK("spdif_in", "tegra30-spdif", "spdif_in", 10, 0x10c, 100000000, mux_pllp_pllc_pllm, MUX | DIV_U71 | PERIPH_ON_APB),
6241 PERIPH_CLK("pwm", "pwm", NULL, 17, 0x110, 48000000, mux_pllp_pllc_clk32_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
6242 D_AUDIO_CLK("d_audio", "tegra30-ahub", "d_audio", 106, 0x3d0, 48000000, mux_d_audio_clk, MUX | DIV_U71 | PERIPH_ON_APB),
6243 D_AUDIO_CLK("dam0", "tegra30-dam.0", NULL, 108, 0x3d8, 19910000, mux_d_audio_clk, MUX | DIV_U71 | PERIPH_ON_APB),
6244 D_AUDIO_CLK("dam1", "tegra30-dam.1", NULL, 109, 0x3dc, 19910000, mux_d_audio_clk, MUX | DIV_U71 | PERIPH_ON_APB),
6245 D_AUDIO_CLK("dam2", "tegra30-dam.2", NULL, 110, 0x3e0, 19910000, mux_d_audio_clk, MUX | DIV_U71 | PERIPH_ON_APB),
6246 PERIPH_CLK("adx", "adx", NULL, 154, 0x638, 19910000, mux_plla_pllc_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
6247 PERIPH_CLK("amx", "amx", NULL, 153, 0x63c, 19910000, mux_plla_pllc_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
6248 PERIPH_CLK("hda", "tegra30-hda", "hda", 125, 0x428, 48000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
6249 PERIPH_CLK("hda2codec_2x", "tegra30-hda", "hda2codec", 111, 0x3e4, 48000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
6250 PERIPH_CLK("hda2hdmi", "tegra30-hda", "hda2hdmi", 128, 0, 48000000, mux_clk_m, PERIPH_ON_APB),
6251 PERIPH_CLK("sbc1", "tegra11-spi.0", NULL, 41, 0x134, 52000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
6252 PERIPH_CLK("sbc2", "tegra11-spi.1", NULL, 44, 0x118, 52000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
6253 PERIPH_CLK("sbc3", "tegra11-spi.2", NULL, 46, 0x11c, 52000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
6254 PERIPH_CLK("sbc4", "tegra11-spi.3", NULL, 68, 0x1b4, 52000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
6255 PERIPH_CLK("sbc5", "tegra11-spi.4", NULL, 104, 0x3c8, 52000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
6256 PERIPH_CLK("sbc6", "tegra11-spi.5", NULL, 105, 0x3cc, 52000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
6257 PERIPH_CLK("sata_oob", "tegra_sata_oob", NULL, 123, 0x420, 216000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
6258 PERIPH_CLK("sata", "tegra_sata", NULL, 124, 0x424, 216000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
6259 PERIPH_CLK("sata_cold", "tegra_sata_cold", NULL, 129, 0, 48000000, mux_clk_m, PERIPH_ON_APB),
6260 PERIPH_CLK_EX("ndflash", "tegra_nand", NULL, 13, 0x160, 240000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB, &tegra_nand_clk_ops),
6261 PERIPH_CLK("ndspeed", "tegra_nand_speed", NULL, 80, 0x3f8, 240000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
6262 PERIPH_CLK("vfir", "vfir", NULL, 7, 0x168, 72000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
6263 PERIPH_CLK("sdmmc1", "sdhci-tegra.0", NULL, 14, 0x150, 208000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
6264 PERIPH_CLK("sdmmc2", "sdhci-tegra.1", NULL, 9, 0x154, 102000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
6265 PERIPH_CLK("sdmmc3", "sdhci-tegra.2", NULL, 69, 0x1bc, 208000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
6266 PERIPH_CLK("sdmmc4", "sdhci-tegra.3", NULL, 15, 0x164, 200000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
6267 PERIPH_CLK("vcp", "tegra-avp", "vcp", 29, 0, 250000000, mux_clk_m, 0),
6268 PERIPH_CLK("bsea", "tegra-avp", "bsea", 62, 0, 250000000, mux_clk_m, 0),
6269 PERIPH_CLK("bsev", "tegra-aes", "bsev", 63, 0, 250000000, mux_clk_m, 0),
6270 PERIPH_CLK("vde", "vde", NULL, 61, 0x1c8, 600000000, mux_pllp_pllc2_c_c3_pllm_clkm, MUX | MUX8 | DIV_U71 | DIV_U71_INT),
6271 PERIPH_CLK("csite", "csite", NULL, 73, 0x1d4, 144000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
6272 PERIPH_CLK("la", "la", NULL, 76, 0x1f8, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
6273 PERIPH_CLK("trace", "trace", NULL, 77, 0x634, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
6274 PERIPH_CLK("owr", "tegra_w1", NULL, 71, 0x1cc, 12000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
6275 PERIPH_CLK("nor", "tegra-nor", NULL, 42, 0x1d0, 127000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
6276 PERIPH_CLK("mipi", "mipi", NULL, 50, 0x174, 60000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
6277 PERIPH_CLK("i2c1", "tegra11-i2c.0", "div-clk", 12, 0x124, 136000000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB),
6278 PERIPH_CLK("i2c2", "tegra11-i2c.1", "div-clk", 54, 0x198, 136000000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB),
6279 PERIPH_CLK("i2c3", "tegra11-i2c.2", "div-clk", 67, 0x1b8, 136000000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB),
6280 PERIPH_CLK("i2c4", "tegra11-i2c.3", "div-clk", 103, 0x3c4, 136000000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB),
6281 PERIPH_CLK("i2c5", "tegra11-i2c.4", "div-clk", 47, 0x128, 58300000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB),
6282 PERIPH_CLK("mipi-cal", "mipi-cal", NULL, 56, 0, 60000000, mux_clk_m, 0),
6283 PERIPH_CLK("uarta", "tegra_uart.0", NULL, 6, 0x178, 800000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U151 | DIV_U151_UART | PERIPH_ON_APB),
6284 PERIPH_CLK("uartb", "tegra_uart.1", NULL, 7, 0x17c, 800000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U151 | DIV_U151_UART | PERIPH_ON_APB),
6285 PERIPH_CLK("uartc", "tegra_uart.2", NULL, 55, 0x1a0, 800000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U151 | DIV_U151_UART | PERIPH_ON_APB),
6286 PERIPH_CLK("uartd", "tegra_uart.3", NULL, 65, 0x1c0, 800000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U151 | DIV_U151_UART | PERIPH_ON_APB),
6287 PERIPH_CLK("uarte", "tegra_uart.4", NULL, 66, 0x1c4, 800000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U151 | DIV_U151_UART | PERIPH_ON_APB),
6288 PERIPH_CLK("uarta_dbg", "serial8250.0", "uarta", 6, 0x178, 408000000, mux_pllp_clkm, MUX | DIV_U151 | DIV_U151_UART | PERIPH_ON_APB),
6289 PERIPH_CLK("uartb_dbg", "serial8250.0", "uartb", 7, 0x17c, 408000000, mux_pllp_clkm, MUX | DIV_U151 | DIV_U151_UART | PERIPH_ON_APB),
6290 PERIPH_CLK("uartc_dbg", "serial8250.0", "uartc", 55, 0x1a0, 408000000, mux_pllp_clkm, MUX | DIV_U151 | DIV_U151_UART | PERIPH_ON_APB),
6291 PERIPH_CLK("uartd_dbg", "serial8250.0", "uartd", 65, 0x1c0, 408000000, mux_pllp_clkm, MUX | DIV_U151 | DIV_U151_UART | PERIPH_ON_APB),
6292 PERIPH_CLK("uarte_dbg", "serial8250.0", "uarte", 66, 0x1c4, 408000000, mux_pllp_clkm, MUX | DIV_U151 | DIV_U151_UART | PERIPH_ON_APB),
6293 PERIPH_CLK("3d", "3d", NULL, 24, 0x158, 700000000, mux_pllm_pllc2_c_c3_pllp_plla, MUX | MUX8 | DIV_U71 | DIV_U71_INT | DIV_U71_IDLE | PERIPH_MANUAL_RESET),
6294 PERIPH_CLK("2d", "2d", NULL, 21, 0x15c, 700000000, mux_pllm_pllc2_c_c3_pllp_plla, MUX | MUX8 | DIV_U71 | DIV_U71_INT | DIV_U71_IDLE),
6295 PERIPH_CLK_EX("vi", "tegra_camera", "vi", 20, 0x148, 425000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | DIV_U71_INT, &tegra_vi_clk_ops),
6296 PERIPH_CLK("vi_sensor", "tegra_camera", "vi_sensor", 20, 0x1a8, 150000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | PERIPH_NO_RESET),
6297 PERIPH_CLK("epp", "epp", NULL, 19, 0x16c, 700000000, mux_pllm_pllc2_c_c3_pllp_plla, MUX | MUX8 | DIV_U71 | DIV_U71_INT),
6298 #ifdef CONFIG_TEGRA_SIMULATION_PLATFORM
6299 PERIPH_CLK("msenc", "msenc", NULL, 60, 0x170, 600000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | DIV_U71_INT),
6301 PERIPH_CLK_EX("msenc", "msenc", NULL, 91, 0x1f0, 600000000, mux_pllm_pllc2_c_c3_pllp_plla, MUX | MUX8 | DIV_U71 | DIV_U71_INT, &tegra_msenc_clk_ops),
6303 PERIPH_CLK("tsec", "tsec", NULL, 83, 0x1f4, 600000000, mux_pllp_pllc2_c_c3_pllm_clkm, MUX | MUX8 | DIV_U71 | DIV_U71_INT),
6304 PERIPH_CLK("host1x", "host1x", NULL, 28, 0x180, 336000000, mux_pllm_pllc2_c_c3_pllp_plla, MUX | MUX8 | DIV_U71 | DIV_U71_INT),
6305 PERIPH_CLK_EX("dtv", "dtv", NULL, 79, 0x1dc, 250000000, mux_clk_m, PERIPH_ON_APB, &tegra_dtv_clk_ops),
6306 PERIPH_CLK("hdmi", "hdmi", NULL, 51, 0x18c, 297000000, mux_pllp_pllm_plld_plla_pllc_plld2_clkm, MUX | MUX8 | DIV_U71),
6307 PERIPH_CLK("disp1", "tegradc.0", NULL, 27, 0x138, 600000000, mux_pllp_pllm_plld_plla_pllc_plld2_clkm, MUX | MUX8),
6308 PERIPH_CLK("disp2", "tegradc.1", NULL, 26, 0x13c, 600000000, mux_pllp_pllm_plld_plla_pllc_plld2_clkm, MUX | MUX8),
6309 PERIPH_CLK("usbd", "tegra-udc.0", NULL, 22, 0, 480000000, mux_clk_m, 0),
6310 PERIPH_CLK("usb2", "tegra-ehci.1", NULL, 58, 0, 480000000, mux_clk_m, 0),
6311 PERIPH_CLK("usb3", "tegra-ehci.2", NULL, 59, 0, 480000000, mux_clk_m, 0),
6312 PERIPH_CLK_EX("dsia", "tegradc.0", "dsia", 48, 0xd0, 500000000, mux_plld_out0_plld2_out0, MUX | PLLD, &tegra_dsi_clk_ops),
6313 PERIPH_CLK_EX("dsib", "tegradc.1", "dsib", 82, 0x4b8, 500000000, mux_plld_out0_plld2_out0, MUX | PLLD, &tegra_dsi_clk_ops),
6314 PERIPH_CLK("dsi1-fixed", "tegradc.0", "dsi-fixed", 0, 0, 108000000, mux_pllp_out3, PERIPH_NO_ENB),
6315 PERIPH_CLK("dsi2-fixed", "tegradc.1", "dsi-fixed", 0, 0, 108000000, mux_pllp_out3, PERIPH_NO_ENB),
6316 PERIPH_CLK("csi", "tegra_camera", "csi", 52, 0, 102000000, mux_pllp_out3, 0),
6317 PERIPH_CLK("isp", "tegra_camera", "isp", 23, 0, 150000000, mux_clk_m, 0), /* same frequency as VI */
6318 PERIPH_CLK("csus", "tegra_camera", "csus", 92, 0, 150000000, mux_clk_m, PERIPH_NO_RESET),
6319 PERIPH_CLK("cilab", "tegra_camera", "cilab", 144, 0x614, 102000000, mux_pllp_pllc_clkm, MUX | DIV_U71),
6320 PERIPH_CLK("cilcd", "tegra_camera", "cilcd", 145, 0x618, 102000000, mux_pllp_pllc_clkm, MUX | DIV_U71),
6321 PERIPH_CLK("cile", "tegra_camera", "cile", 146, 0x61c, 102000000, mux_pllp_pllc_clkm, MUX | DIV_U71),
6322 PERIPH_CLK("dsialp", "tegradc.0", "dsialp", 147, 0x620, 102000000, mux_pllp_pllc_clkm, MUX | DIV_U71),
6323 PERIPH_CLK("dsiblp", "tegradc.1", "dsiblp", 148, 0x624, 102000000, mux_pllp_pllc_clkm, MUX | DIV_U71),
6325 PERIPH_CLK("tsensor", "tegra-tsensor", NULL, 100, 0x3b8, 12000000, mux_pllp_pllc_clkm_clk32, MUX | DIV_U71 | PERIPH_ON_APB),
6326 PERIPH_CLK("actmon", "actmon", NULL, 119, 0x3e8, 216000000, mux_pllp_pllc_clk32_clkm, MUX | DIV_U71),
6327 PERIPH_CLK("extern1", "extern1", NULL, 120, 0x3ec, 216000000, mux_plla_clk32_pllp_clkm_plle, MUX | MUX8 | DIV_U71),
6328 PERIPH_CLK("extern2", "extern2", NULL, 121, 0x3f0, 216000000, mux_plla_clk32_pllp_clkm_plle, MUX | MUX8 | DIV_U71),
6329 PERIPH_CLK("extern3", "extern3", NULL, 122, 0x3f4, 216000000, mux_plla_clk32_pllp_clkm_plle, MUX | MUX8 | DIV_U71),
6330 PERIPH_CLK("i2cslow", "i2cslow", NULL, 81, 0x3fc, 26000000, mux_pllp_pllc_clk32_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
6331 PERIPH_CLK("pcie", "tegra-pcie", "pcie", 70, 0, 250000000, mux_clk_m, 0),
6332 PERIPH_CLK("afi", "tegra-pcie", "afi", 72, 0, 250000000, mux_clk_m, 0),
6333 PERIPH_CLK("se", "se", NULL, 127, 0x42c, 600000000, mux_pllp_pllc2_c_c3_pllm_clkm, MUX | MUX8 | DIV_U71 | DIV_U71_INT | PERIPH_ON_APB),
6334 PERIPH_CLK("mselect", "mselect", NULL, 99, 0x3b4, 102000000, mux_pllp_clkm, MUX | DIV_U71 | DIV_U71_INT),
6335 PERIPH_CLK("cl_dvfs_ref", "tegra_cl_dvfs", "ref", 155, 0x62c, 54000000, mux_pllp_clkm, MUX | DIV_U71 | DIV_U71_INT | PERIPH_ON_APB),
6336 PERIPH_CLK("cl_dvfs_soc", "tegra_cl_dvfs", "soc", 155, 0x630, 54000000, mux_pllp_clkm, MUX | DIV_U71 | DIV_U71_INT | PERIPH_ON_APB),
6337 PERIPH_CLK("soc_therm", "soc_therm", NULL, 78, 0x644, 136000000, mux_pllm_pllc_pllp_plla, MUX | MUX8 | DIV_U71 | PERIPH_ON_APB),
6339 PERIPH_CLK("dds", "dds", NULL, 150, 0, 26000000, mux_clk_m, PERIPH_ON_APB),
6340 PERIPH_CLK("dp2", "dp2", NULL, 152, 0, 26000000, mux_clk_m, PERIPH_ON_APB),
6342 SHARED_CLK("avp.sclk", "tegra-avp", "sclk", &tegra_clk_sbus_cmplx, NULL, 0, 0),
6343 SHARED_CLK("bsea.sclk", "tegra-aes", "sclk", &tegra_clk_sbus_cmplx, NULL, 0, 0),
6344 SHARED_CLK("usbd.sclk", "tegra-udc.0", "sclk", &tegra_clk_sbus_cmplx, NULL, 0, 0),
6345 SHARED_CLK("usb1.sclk", "tegra-ehci.0", "sclk", &tegra_clk_sbus_cmplx, NULL, 0, 0),
6346 SHARED_CLK("usb2.sclk", "tegra-ehci.1", "sclk", &tegra_clk_sbus_cmplx, NULL, 0, 0),
6347 SHARED_CLK("usb3.sclk", "tegra-ehci.2", "sclk", &tegra_clk_sbus_cmplx, NULL, 0, 0),
6348 SHARED_CLK("wake.sclk", "wake_sclk", "sclk", &tegra_clk_sbus_cmplx, NULL, 0, 0),
6349 SHARED_CLK("mon.avp", "tegra_actmon", "avp", &tegra_clk_sbus_cmplx, NULL, 0, 0),
6350 SHARED_CLK("cap.sclk", "cap_sclk", NULL, &tegra_clk_sbus_cmplx, NULL, 0, SHARED_CEILING),
6351 SHARED_CLK("floor.sclk", "floor_sclk", NULL, &tegra_clk_sbus_cmplx, NULL, 0, 0),
6352 SHARED_CLK("override.sclk", "override_sclk", NULL, &tegra_clk_sbus_cmplx, NULL, 0, SHARED_OVERRIDE),
6353 SHARED_CLK("sbc1.sclk", "tegra11-spi.0", "sclk", &tegra_clk_sbus_cmplx, NULL, 0, 0),
6354 SHARED_CLK("sbc2.sclk", "tegra11-spi.1", "sclk", &tegra_clk_sbus_cmplx, NULL, 0, 0),
6355 SHARED_CLK("sbc3.sclk", "tegra11-spi.2", "sclk", &tegra_clk_sbus_cmplx, NULL, 0, 0),
6356 SHARED_CLK("sbc4.sclk", "tegra11-spi.3", "sclk", &tegra_clk_sbus_cmplx, NULL, 0, 0),
6357 SHARED_CLK("sbc5.sclk", "tegra11-spi.4", "sclk", &tegra_clk_sbus_cmplx, NULL, 0, 0),
6358 SHARED_CLK("sbc6.sclk", "tegra11-spi.5", "sclk", &tegra_clk_sbus_cmplx, NULL, 0, 0),
6360 SHARED_CLK("avp.emc", "tegra-avp", "emc", &tegra_clk_emc, NULL, 0, 0),
6361 SHARED_CLK("cpu.emc", "cpu", "emc", &tegra_clk_emc, NULL, 0, 0),
6362 SHARED_CLK("disp1.emc", "tegradc.0", "emc", &tegra_clk_emc, NULL, 0, SHARED_BW),
6363 SHARED_CLK("disp2.emc", "tegradc.1", "emc", &tegra_clk_emc, NULL, 0, SHARED_BW),
6364 SHARED_CLK("hdmi.emc", "hdmi", "emc", &tegra_clk_emc, NULL, 0, 0),
6365 SHARED_CLK("usbd.emc", "tegra-udc.0", "emc", &tegra_clk_emc, NULL, 0, 0),
6366 SHARED_CLK("usb1.emc", "tegra-ehci.0", "emc", &tegra_clk_emc, NULL, 0, 0),
6367 SHARED_CLK("usb2.emc", "tegra-ehci.1", "emc", &tegra_clk_emc, NULL, 0, 0),
6368 SHARED_CLK("usb3.emc", "tegra-ehci.2", "emc", &tegra_clk_emc, NULL, 0, 0),
6369 SHARED_CLK("mon.emc", "tegra_actmon", "emc", &tegra_clk_emc, NULL, 0, 0),
6370 SHARED_CLK("cap.emc", "cap.emc", NULL, &tegra_clk_emc, NULL, 0, SHARED_CEILING),
6371 SHARED_CLK("3d.emc", "tegra_gr3d", "emc", &tegra_clk_emc, NULL, 0, 0),
6372 SHARED_CLK("2d.emc", "tegra_gr2d", "emc", &tegra_clk_emc, NULL, 0, 0),
6373 SHARED_CLK("msenc.emc", "tegra_msenc", "emc", &tegra_clk_emc, NULL, 0, 0),
6374 SHARED_CLK("tsec.emc", "tegra_tsec", "emc", &tegra_clk_emc, NULL, 0, 0),
6375 SHARED_CLK("sdmmc4.emc", "sdhci-tegra.3", "emc", &tegra_clk_emc, NULL, 0, 0),
6376 SHARED_CLK("camera.emc", "tegra_camera", "emc", &tegra_clk_emc, NULL, 0, SHARED_BW),
6377 SHARED_CLK("iso.emc", "iso", "emc", &tegra_clk_emc, NULL, 0, SHARED_BW),
6378 SHARED_CLK("floor.emc", "floor.emc", NULL, &tegra_clk_emc, NULL, 0, 0),
6379 SHARED_CLK("override.emc", "override.emc", NULL, &tegra_clk_emc, NULL, 0, SHARED_OVERRIDE),
6380 SHARED_CLK("edp.emc", "edp.emc", NULL, &tegra_clk_emc, NULL, 0, SHARED_CEILING),
6382 #ifdef CONFIG_TEGRA_DUAL_CBUS
6383 DUAL_CBUS_CLK("3d.cbus", "tegra_gr3d", "gr3d", &tegra_clk_c2bus, "3d", 0, 0),
6384 DUAL_CBUS_CLK("2d.cbus", "tegra_gr2d", "gr2d", &tegra_clk_c2bus, "2d", 0, 0),
6385 DUAL_CBUS_CLK("epp.cbus", "tegra_gr2d", "epp", &tegra_clk_c2bus, "epp", 0, 0),
6386 SHARED_CLK("cap.c2bus", "cap.c2bus", NULL, &tegra_clk_c2bus, NULL, 0, SHARED_CEILING),
6387 SHARED_CLK("floor.c2bus", "floor.c2bus", NULL, &tegra_clk_c2bus, NULL, 0, 0),
6388 SHARED_CLK("override.c2bus", "override.c2bus", NULL, &tegra_clk_c2bus, NULL, 0, SHARED_OVERRIDE),
6389 SHARED_CLK("edp.c2bus", "edp.c2bus", NULL, &tegra_clk_c2bus, NULL, 0, SHARED_CEILING),
6391 DUAL_CBUS_CLK("msenc.cbus", "tegra_msenc", "msenc", &tegra_clk_c3bus, "msenc", 0, 0),
6392 DUAL_CBUS_CLK("tsec.cbus", "tegra_tsec", "tsec", &tegra_clk_c3bus, "tsec", 0, 0),
6393 DUAL_CBUS_CLK("vde.cbus", "tegra-avp", "vde", &tegra_clk_c3bus, "vde", 0, 0),
6394 DUAL_CBUS_CLK("se.cbus", "tegra11-se", NULL, &tegra_clk_c3bus, "se", 0, 0),
6395 SHARED_CLK("cap.c3bus", "cap.c3bus", NULL, &tegra_clk_c3bus, NULL, 0, SHARED_CEILING),
6396 SHARED_CLK("floor.c3bus", "floor.c3bus", NULL, &tegra_clk_c3bus, NULL, 0, 0),
6397 SHARED_CLK("override.c3bus", "override.c3bus", NULL, &tegra_clk_c3bus, NULL, 0, SHARED_OVERRIDE),
6399 SHARED_CLK("3d.cbus", "tegra_gr3d", "gr3d", &tegra_clk_cbus, "3d", 0, 0),
6400 SHARED_CLK("2d.cbus", "tegra_gr2d", "gr2d", &tegra_clk_cbus, "2d", 0, 0),
6401 SHARED_CLK("epp.cbus", "tegra_gr2d", "epp", &tegra_clk_cbus, "epp", 0, 0),
6402 SHARED_CLK("msenc.cbus","tegra_msenc", "msenc",&tegra_clk_cbus, "msenc", 0, 0),
6403 SHARED_CLK("tsec.cbus", "tegra_tsec", "tsec", &tegra_clk_cbus, "tsec", 0, 0),
6404 SHARED_CLK("vde.cbus", "tegra-avp", "vde", &tegra_clk_cbus, "vde", 0, 0),
6405 SHARED_CLK("se.cbus", "tegra11-se", NULL, &tegra_clk_cbus, "se", 0, 0),
6406 SHARED_CLK("cap.cbus", "cap.cbus", NULL, &tegra_clk_cbus, NULL, 0, SHARED_CEILING),
6407 SHARED_CLK("floor.cbus", "floor.cbus", NULL, &tegra_clk_cbus, NULL, 0, 0),
6408 SHARED_CLK("override.cbus", "override.cbus", NULL, &tegra_clk_cbus, NULL, 0, SHARED_OVERRIDE),
6409 SHARED_CLK("edp.cbus", "edp.cbus", NULL, &tegra_clk_cbus, NULL, 0, SHARED_CEILING),
6415 #define XUSB_ID "tegra_xhci"
6417 static struct clk tegra_xusb_source_clks[] = {
6418 PERIPH_CLK("xusb_host_src", XUSB_ID, "host_src", 143, 0x600, 120000000, mux_clkm_pllp_pllc_pllre, MUX | MUX8 | DIV_U71 | DIV_U71_INT | PERIPH_NO_RESET | PERIPH_ON_APB),
6419 PERIPH_CLK("xusb_falcon_src", XUSB_ID, "falcon_src", 143, 0x604, 350000000, mux_clkm_pllp_pllc_pllre, MUX | MUX8 | DIV_U71 | DIV_U71_INT | PERIPH_NO_RESET),
6420 PERIPH_CLK("xusb_fs_src", XUSB_ID, "fs_src", 143, 0x608, 48000000, mux_clkm_48M_pllp_480M, MUX | DIV_U71 | DIV_U71_INT | PERIPH_NO_RESET),
6421 PERIPH_CLK("xusb_ss_src", XUSB_ID, "ss_src", 143, 0x610, 120000000, mux_clkm_pllre_clk32_480M_pllc_ref, MUX | MUX8 | DIV_U71 | DIV_U71_INT | PERIPH_NO_RESET),
6422 PERIPH_CLK("xusb_dev_src", XUSB_ID, "dev_src", 95, 0x60c, 120000000, mux_clkm_pllp_pllc_pllre, MUX | MUX8 | DIV_U71 | DIV_U71_INT | PERIPH_NO_RESET | PERIPH_ON_APB),
6424 .name = "xusb_hs_src",
6429 .ops = &tegra_periph_clk_ops,
6431 .inputs = mux_pllu_60M,
6432 .flags = PLLU | PERIPH_NO_ENB,
6433 .max_rate = 60000000,
6439 SHARED_CLK("xusb.emc", "XUSB_ID", "emc", &tegra_clk_emc, NULL, 0, SHARED_BW),
6442 static struct clk_mux_sel mux_xusb_host[] = {
6443 { .input = &tegra_xusb_source_clks[0], .value = 0},
6444 { .input = &tegra_xusb_source_clks[1], .value = 1},
6445 { .input = &tegra_xusb_source_clks[2], .value = 2},
6446 { .input = &tegra_xusb_source_clks[5], .value = 5},
6450 static struct clk_mux_sel mux_xusb_ss[] = {
6451 { .input = &tegra_xusb_source_clks[3], .value = 3},
6452 { .input = &tegra_xusb_source_clks[0], .value = 0},
6453 { .input = &tegra_xusb_source_clks[1], .value = 1},
6457 static struct clk_mux_sel mux_xusb_dev[] = {
6458 { .input = &tegra_xusb_source_clks[4], .value = 4},
6459 { .input = &tegra_xusb_source_clks[2], .value = 2},
6460 { .input = &tegra_xusb_source_clks[3], .value = 3},
6464 static struct clk tegra_xusb_coupled_clks[] = {
6465 PERIPH_CLK_EX("xusb_host", XUSB_ID, "host", 89, 0, 350000000, mux_xusb_host, 0, &tegra_clk_coupled_gate_ops),
6466 PERIPH_CLK_EX("xusb_ss", XUSB_ID, "ss", 156, 0, 350000000, mux_xusb_ss, 0, &tegra_clk_coupled_gate_ops),
6467 PERIPH_CLK_EX("xusb_dev", XUSB_ID, "dev", 95, 0, 120000000, mux_xusb_dev, 0, &tegra_clk_coupled_gate_ops),
6471 #define CLK_DUPLICATE(_name, _dev, _con) \
6480 /* Some clocks may be used by different drivers depending on the board
6481 * configuration. List those here to register them twice in the clock lookup
6482 * table under two names.
6484 struct clk_duplicate tegra_clk_duplicates[] = {
6485 CLK_DUPLICATE("usbd", "utmip-pad", NULL),
6486 CLK_DUPLICATE("usbd", "tegra-ehci.0", NULL),
6487 CLK_DUPLICATE("usbd", "tegra-otg", NULL),
6488 CLK_DUPLICATE("disp1", "tegra_dc_dsi_vs1.0", NULL),
6489 CLK_DUPLICATE("disp1.emc", "tegra_dc_dsi_vs1.0", "emc"),
6490 CLK_DUPLICATE("disp1", "tegra_dc_dsi_vs1.1", NULL),
6491 CLK_DUPLICATE("disp1.emc", "tegra_dc_dsi_vs1.1", "emc"),
6492 CLK_DUPLICATE("hdmi", "tegradc.0", "hdmi"),
6493 CLK_DUPLICATE("hdmi", "tegradc.1", "hdmi"),
6494 CLK_DUPLICATE("dsib", "tegradc.0", "dsib"),
6495 CLK_DUPLICATE("dsia", "tegradc.1", "dsia"),
6496 CLK_DUPLICATE("dsiblp", "tegradc.0", "dsiblp"),
6497 CLK_DUPLICATE("dsialp", "tegradc.1", "dsialp"),
6498 CLK_DUPLICATE("dsia", "tegra_dc_dsi_vs1.0", "dsia"),
6499 CLK_DUPLICATE("dsia", "tegra_dc_dsi_vs1.1", "dsia"),
6500 CLK_DUPLICATE("dsialp", "tegra_dc_dsi_vs1.0", "dsialp"),
6501 CLK_DUPLICATE("dsialp", "tegra_dc_dsi_vs1.1", "dsialp"),
6502 CLK_DUPLICATE("dsi1-fixed", "tegra_dc_dsi_vs1.0", "dsi-fixed"),
6503 CLK_DUPLICATE("dsi1-fixed", "tegra_dc_dsi_vs1.1", "dsi-fixed"),
6504 CLK_DUPLICATE("pwm", "tegra_pwm.0", NULL),
6505 CLK_DUPLICATE("pwm", "tegra_pwm.1", NULL),
6506 CLK_DUPLICATE("pwm", "tegra_pwm.2", NULL),
6507 CLK_DUPLICATE("pwm", "tegra_pwm.3", NULL),
6508 CLK_DUPLICATE("cop", "tegra-avp", "cop"),
6509 CLK_DUPLICATE("bsev", "tegra-avp", "bsev"),
6510 CLK_DUPLICATE("cop", "nvavp", "cop"),
6511 CLK_DUPLICATE("bsev", "nvavp", "bsev"),
6512 CLK_DUPLICATE("vde", "tegra-aes", "vde"),
6513 CLK_DUPLICATE("bsea", "tegra-aes", "bsea"),
6514 CLK_DUPLICATE("bsea", "nvavp", "bsea"),
6515 CLK_DUPLICATE("pciex", "tegra_pcie", "pciex"),
6516 CLK_DUPLICATE("i2c1", "tegra-i2c-slave.0", NULL),
6517 CLK_DUPLICATE("i2c2", "tegra-i2c-slave.1", NULL),
6518 CLK_DUPLICATE("i2c3", "tegra-i2c-slave.2", NULL),
6519 CLK_DUPLICATE("i2c4", "tegra-i2c-slave.3", NULL),
6520 CLK_DUPLICATE("i2c5", "tegra-i2c-slave.4", NULL),
6521 CLK_DUPLICATE("sbc1", "tegra11-spi-slave.0", NULL),
6522 CLK_DUPLICATE("sbc2", "tegra11-spi-slave.1", NULL),
6523 CLK_DUPLICATE("sbc3", "tegra11-spi-slave.2", NULL),
6524 CLK_DUPLICATE("sbc4", "tegra11-spi-slave.3", NULL),
6525 CLK_DUPLICATE("sbc5", "tegra11-spi-slave.4", NULL),
6526 CLK_DUPLICATE("sbc6", "tegra11-spi-slave.5", NULL),
6527 CLK_DUPLICATE("vcp", "nvavp", "vcp"),
6528 CLK_DUPLICATE("avp.sclk", "nvavp", "sclk"),
6529 CLK_DUPLICATE("avp.emc", "nvavp", "emc"),
6530 CLK_DUPLICATE("vde.cbus", "nvavp", "vde"),
6531 CLK_DUPLICATE("i2c5", "tegra_cl_dvfs", "i2c"),
6532 CLK_DUPLICATE("cpu_g", "tegra_cl_dvfs", "safe_dvfs"),
6533 CLK_DUPLICATE("host1x", "tegra_host1x", "host1x"),
6534 CLK_DUPLICATE("epp.cbus", "tegra_isp", "epp"),
6537 struct clk *tegra_ptr_clks[] = {
6577 &tegra_clk_virtual_cpu_g,
6578 &tegra_clk_virtual_cpu_lp,
6579 &tegra_clk_cpu_cmplx,
6582 &tegra_clk_sbus_cmplx,
6584 #ifdef CONFIG_TEGRA_DUAL_CBUS
6592 /* Return true from this function if the target rate can be locked without
6593 switching pll clients to back-up source */
6594 static bool tegra11_is_dyn_ramp(
6595 struct clk *c, unsigned long rate, bool from_vco_min)
6597 #if PLLCX_USE_DYN_RAMP
6598 /* PLLC2, PLLC3 support dynamic ramp only when output divider <= 8 */
6599 if ((c == &tegra_pll_c2) || (c == &tegra_pll_c3)) {
6600 struct clk_pll_freq_table cfg, old_cfg;
6601 unsigned long input_rate = clk_get_rate(c->parent);
6603 u32 val = clk_readl(c->reg + PLL_BASE);
6604 PLL_BASE_PARSE(PLLCX, old_cfg, val);
6605 old_cfg.p = pllcx_p[old_cfg.p];
6607 if (!pll_dyn_ramp_find_cfg(c, &cfg, rate, input_rate, NULL)) {
6608 if ((cfg.n == old_cfg.n) ||
6609 PLLCX_IS_DYN(cfg.p, old_cfg.p))
6615 #if PLLXC_USE_DYN_RAMP
6616 /* PPLX, PLLC support dynamic ramp when changing NDIV only */
6617 if ((c == &tegra_pll_x) || (c == &tegra_pll_c)) {
6618 struct clk_pll_freq_table cfg, old_cfg;
6619 unsigned long input_rate = clk_get_rate(c->parent);
6622 old_cfg.m = PLL_FIXED_MDIV(c, input_rate);
6625 u32 val = clk_readl(c->reg + PLL_BASE);
6626 PLL_BASE_PARSE(PLLXC, old_cfg, val);
6627 old_cfg.p = pllxc_p[old_cfg.p];
6630 if (!pll_dyn_ramp_find_cfg(c, &cfg, rate, input_rate, NULL)) {
6631 if ((cfg.m == old_cfg.m) && (cfg.p == old_cfg.p))
6640 * Backup pll is used as transitional CPU clock source while main pll is
6641 * relocking; in addition all CPU rates below backup level are sourced from
6642 * backup pll only. Target backup levels for each CPU mode are selected high
6643 * enough to avoid voltage droop when CPU clock is switched between backup and
6644 * main plls. Actual backup rates will be rounded to match backup source fixed
6645 * frequency. Backup rates are also used as stay-on-backup thresholds, and must
6646 * be kept the same in G and LP mode (will need to add a separate stay-on-backup
6647 * parameter to allow different backup rates if necessary).
6649 * Sbus threshold must be exact factor of pll_p rate.
6651 #define CPU_G_BACKUP_RATE_TARGET 200000000
6652 #define CPU_LP_BACKUP_RATE_TARGET 200000000
6654 static void tegra11_pllp_init_dependencies(unsigned long pllp_rate)
6657 unsigned long backup_rate;
6659 switch (pllp_rate) {
6661 tegra_pll_p_out1.u.pll_div.default_rate = 28800000;
6662 tegra_pll_p_out3.u.pll_div.default_rate = 72000000;
6663 tegra_clk_sbus_cmplx.u.system.threshold = 108000000;
6666 tegra_pll_p_out1.u.pll_div.default_rate = 9600000;
6667 tegra_pll_p_out3.u.pll_div.default_rate = 102000000;
6668 tegra_clk_sbus_cmplx.u.system.threshold = 204000000;
6671 tegra_pll_p_out1.u.pll_div.default_rate = 4800000;
6672 tegra_pll_p_out3.u.pll_div.default_rate = 102000000;
6673 tegra_clk_sbus_cmplx.u.system.threshold = 204000000;
6676 pr_err("tegra: PLLP rate: %lu is not supported\n", pllp_rate);
6679 pr_info("tegra: PLLP fixed rate: %lu\n", pllp_rate);
6681 div = pllp_rate / CPU_G_BACKUP_RATE_TARGET;
6682 backup_rate = pllp_rate / div;
6683 tegra_clk_virtual_cpu_g.u.cpu.backup_rate = backup_rate;
6685 div = pllp_rate / CPU_LP_BACKUP_RATE_TARGET;
6686 backup_rate = pllp_rate / div;
6687 tegra_clk_virtual_cpu_lp.u.cpu.backup_rate = backup_rate;
6690 static void tegra11_init_one_clock(struct clk *c)
6693 INIT_LIST_HEAD(&c->shared_bus_list);
6694 if (!c->lookup.dev_id && !c->lookup.con_id)
6695 c->lookup.con_id = c->name;
6697 clkdev_add(&c->lookup);
6700 void tegra_edp_throttle_cpu_now(u8 factor)
6702 /* empty definition for tegra11 */
6706 bool tegra_clk_is_parent_allowed(struct clk *c, struct clk *p)
6709 * Most of the Tegra11 multimedia and peripheral muxes include pll_c2
6710 * and pll_c3 as possible inputs. However, per clock policy these plls
6711 * are allowed to be used only by handful devices aggregated on cbus.
6712 * For all others, instead of enforcing policy at run-time in this
6713 * function, we simply stripped out pll_c2 and pll_c3 options from the
6714 * respective muxes statically.
6717 /* pll_c can be used as a clock source for EMC only on configuration
6718 with dual cbus, or as a clock source for single cbus */
6719 if (p == &tegra_pll_c) {
6720 #ifdef CONFIG_TEGRA_DUAL_CBUS
6721 return c->flags & PERIPH_EMC_ENB;
6723 return c->flags & PERIPH_ON_CBUS;
6729 /* Internal LA may request some clocks to be enabled on init via TRANSACTION
6730 SCRATCH register settings */
6731 void __init tegra11x_clk_init_la(void)
6734 u32 reg = readl(misc_gp_base + MISC_GP_TRANSACTOR_SCRATCH_0);
6736 if (!(reg & MISC_GP_TRANSACTOR_SCRATCH_LA_ENABLE))
6739 c = tegra_get_clock_by_name("la");
6740 if (WARN(!c, "%s: could not find la clk\n", __func__))
6744 if (reg & MISC_GP_TRANSACTOR_SCRATCH_DDS_ENABLE) {
6745 c = tegra_get_clock_by_name("dds");
6746 if (WARN(!c, "%s: could not find la clk\n", __func__))
6750 if (reg & MISC_GP_TRANSACTOR_SCRATCH_DP2_ENABLE) {
6751 c = tegra_get_clock_by_name("dp2");
6752 if (WARN(!c, "%s: could not find la clk\n", __func__))
6756 c = tegra_get_clock_by_name("hdmi");
6757 if (WARN(!c, "%s: could not find la clk\n", __func__))
6763 #ifdef CONFIG_CPU_FREQ
6766 * Frequency table index must be sequential starting at 0 and frequencies
6767 * must be ascending.
6769 #define CPU_FREQ_STEP 102000 /* 102MHz cpu_g table step */
6770 #define CPU_FREQ_TABLE_MAX_SIZE (2 * MAX_DVFS_FREQS + 1)
6772 static struct cpufreq_frequency_table freq_table[CPU_FREQ_TABLE_MAX_SIZE];
6773 static struct tegra_cpufreq_table_data freq_table_data;
6775 struct tegra_cpufreq_table_data *tegra_cpufreq_table_get(void)
6778 bool g_vmin_done = false;
6779 unsigned int freq, lp_backup_freq, g_vmin_freq, g_start_freq, max_freq;
6780 struct clk *cpu_clk_g = tegra_get_clock_by_name("cpu_g");
6781 struct clk *cpu_clk_lp = tegra_get_clock_by_name("cpu_lp");
6783 /* Initialize once */
6784 if (freq_table_data.freq_table)
6785 return &freq_table_data;
6788 for (i = 0; i < CPU_FREQ_TABLE_MAX_SIZE; i++) {
6789 freq_table[i].index = i;
6790 freq_table[i].frequency = CPUFREQ_TABLE_END;
6793 lp_backup_freq = cpu_clk_lp->u.cpu.backup_rate / 1000;
6794 if (!lp_backup_freq) {
6795 WARN(1, "%s: cannot make cpufreq table: no LP CPU backup rate\n",
6799 if (!cpu_clk_lp->dvfs) {
6800 WARN(1, "%s: cannot make cpufreq table: no LP CPU dvfs\n",
6804 if (!cpu_clk_g->dvfs) {
6805 WARN(1, "%s: cannot make cpufreq table: no G CPU dvfs\n",
6809 g_vmin_freq = cpu_clk_g->dvfs->freqs[0] / 1000;
6810 if (g_vmin_freq <= lp_backup_freq) {
6811 WARN(1, "%s: cannot make cpufreq table: LP CPU backup rate"
6812 " exceeds G CPU rate at Vmin\n", __func__);
6816 /* Start with backup frequencies */
6818 freq = lp_backup_freq;
6819 freq_table[i++].frequency = freq/4;
6820 freq_table[i++].frequency = freq/2;
6821 freq_table[i++].frequency = freq;
6823 /* Throttle low index at backup level*/
6824 freq_table_data.throttle_lowest_index = i - 1;
6827 * Next, set table steps along LP CPU dvfs ladder, but make sure G CPU
6828 * dvfs rate at minimum voltage is not missed (if it happens to be below
6831 max_freq = cpu_clk_lp->max_rate / 1000;
6832 for (j = 0; j < cpu_clk_lp->dvfs->num_freqs; j++) {
6833 freq = cpu_clk_lp->dvfs->freqs[j] / 1000;
6834 if (freq <= lp_backup_freq)
6837 if (!g_vmin_done && (freq >= g_vmin_freq)) {
6839 if (freq > g_vmin_freq)
6840 freq_table[i++].frequency = g_vmin_freq;
6842 freq_table[i++].frequency = freq;
6844 if (freq == max_freq)
6848 /* Set G CPU min rate at least one table step below LP maximum */
6849 cpu_clk_g->min_rate = min(freq_table[i-2].frequency, g_vmin_freq)*1000;
6851 /* Suspend index at max LP CPU */
6852 freq_table_data.suspend_index = i - 1;
6854 /* Fill in "hole" (if any) between LP CPU maximum rate and G CPU dvfs
6855 ladder rate at minimum voltage */
6856 if (freq < g_vmin_freq) {
6857 int n = (g_vmin_freq - freq) / CPU_FREQ_STEP;
6858 for (j = 0; j <= n; j++) {
6859 freq = g_vmin_freq - CPU_FREQ_STEP * (n - j);
6860 freq_table[i++].frequency = freq;
6864 /* Now, step along the rest of G CPU dvfs ladder */
6865 g_start_freq = freq;
6866 max_freq = cpu_clk_g->max_rate / 1000;
6867 for (j = 0; j < cpu_clk_g->dvfs->num_freqs; j++) {
6868 freq = cpu_clk_g->dvfs->freqs[j] / 1000;
6869 if (freq > g_start_freq)
6870 freq_table[i++].frequency = freq;
6871 if (freq == max_freq)
6875 /* Throttle high index one step below maximum */
6876 BUG_ON(i >= CPU_FREQ_TABLE_MAX_SIZE);
6877 freq_table_data.throttle_highest_index = i - 2;
6878 freq_table_data.freq_table = freq_table;
6879 return &freq_table_data;
6882 unsigned long tegra_emc_to_cpu_ratio(unsigned long cpu_rate)
6884 static unsigned long emc_max_rate;
6886 if (emc_max_rate == 0)
6887 emc_max_rate = clk_round_rate(
6888 tegra_get_clock_by_name("emc"), ULONG_MAX);
6890 /* Vote on memory bus frequency based on cpu frequency;
6891 cpu rate is in kHz, emc rate is in Hz */
6892 if (cpu_rate >= 1300000)
6893 return emc_max_rate; /* cpu >= 1.3GHz, emc max */
6894 else if (cpu_rate >= 975000)
6895 return 400000000; /* cpu >= 975 MHz, emc 400 MHz */
6896 else if (cpu_rate >= 725000)
6897 return 200000000; /* cpu >= 725 MHz, emc 200 MHz */
6898 else if (cpu_rate >= 500000)
6899 return 100000000; /* cpu >= 500 MHz, emc 100 MHz */
6900 else if (cpu_rate >= 275000)
6901 return 50000000; /* cpu >= 275 MHz, emc 50 MHz */
6903 return 0; /* emc min */
6906 int tegra_update_mselect_rate(unsigned long cpu_rate)
6908 static struct clk *mselect = NULL;
6910 unsigned long mselect_rate;
6913 mselect = tegra_get_clock_by_name("mselect");
6918 /* Vote on mselect frequency based on cpu frequency:
6919 keep mselect at half of cpu rate up to 102 MHz;
6920 cpu rate is in kHz, mselect rate is in Hz */
6921 mselect_rate = DIV_ROUND_UP(cpu_rate, 2) * 1000;
6922 mselect_rate = min(mselect_rate, 102000000UL);
6924 if (mselect_rate != clk_get_rate(mselect))
6925 return clk_set_rate(mselect, mselect_rate);
6931 #ifdef CONFIG_PM_SLEEP
6932 static u32 clk_rst_suspend[RST_DEVICES_NUM + CLK_OUT_ENB_NUM +
6933 PERIPH_CLK_SOURCE_NUM + 25];
6935 static int tegra11_clk_suspend(void)
6938 u32 *ctx = clk_rst_suspend;
6940 *ctx++ = clk_readl(OSC_CTRL) & OSC_CTRL_MASK;
6941 *ctx++ = clk_readl(CPU_SOFTRST_CTRL);
6942 *ctx++ = clk_readl(CPU_SOFTRST_CTRL1);
6943 *ctx++ = clk_readl(CPU_SOFTRST_CTRL2);
6945 *ctx++ = clk_readl(tegra_pll_p_out1.reg);
6946 *ctx++ = clk_readl(tegra_pll_p_out3.reg);
6948 *ctx++ = clk_readl(tegra_pll_a.reg + PLL_BASE);
6949 *ctx++ = clk_readl(tegra_pll_a.reg + PLL_MISC(&tegra_pll_a));
6950 *ctx++ = clk_readl(tegra_pll_d.reg + PLL_BASE);
6951 *ctx++ = clk_readl(tegra_pll_d.reg + PLL_MISC(&tegra_pll_d));
6952 *ctx++ = clk_readl(tegra_pll_d2.reg + PLL_BASE);
6953 *ctx++ = clk_readl(tegra_pll_d2.reg + PLL_MISC(&tegra_pll_d2));
6955 *ctx++ = clk_readl(tegra_pll_m_out1.reg);
6956 *ctx++ = clk_readl(tegra_pll_a_out0.reg);
6957 *ctx++ = clk_readl(tegra_pll_c_out1.reg);
6959 *ctx++ = clk_readl(tegra_clk_cclk_lp.reg);
6960 *ctx++ = clk_readl(tegra_clk_cclk_lp.reg + SUPER_CLK_DIVIDER);
6962 *ctx++ = clk_readl(tegra_clk_sclk.reg);
6963 *ctx++ = clk_readl(tegra_clk_sclk.reg + SUPER_CLK_DIVIDER);
6964 *ctx++ = clk_readl(tegra_clk_pclk.reg);
6966 for (off = PERIPH_CLK_SOURCE_I2S1; off <= PERIPH_CLK_SOURCE_OSC;
6968 if (off == PERIPH_CLK_SOURCE_EMC)
6970 *ctx++ = clk_readl(off);
6972 for (off = PERIPH_CLK_SOURCE_G3D2; off <= PERIPH_CLK_SOURCE_SE;
6974 *ctx++ = clk_readl(off);
6976 for (off = AUDIO_DLY_CLK; off <= AUDIO_SYNC_CLK_SPDIF; off+=4) {
6977 *ctx++ = clk_readl(off);
6979 for (off = PERIPH_CLK_SOURCE_XUSB_HOST;
6980 off <= PERIPH_CLK_SOURCE_SOC_THERM; off += 4)
6981 *ctx++ = clk_readl(off);
6983 *ctx++ = clk_readl(RST_DEVICES_L);
6984 *ctx++ = clk_readl(RST_DEVICES_H);
6985 *ctx++ = clk_readl(RST_DEVICES_U);
6986 *ctx++ = clk_readl(RST_DEVICES_V);
6987 *ctx++ = clk_readl(RST_DEVICES_W);
6988 *ctx++ = clk_readl(RST_DEVICES_X);
6990 *ctx++ = clk_readl(CLK_OUT_ENB_L);
6991 *ctx++ = clk_readl(CLK_OUT_ENB_H);
6992 *ctx++ = clk_readl(CLK_OUT_ENB_U);
6993 *ctx++ = clk_readl(CLK_OUT_ENB_V);
6994 *ctx++ = clk_readl(CLK_OUT_ENB_W);
6995 *ctx++ = clk_readl(CLK_OUT_ENB_X);
6997 *ctx++ = clk_readl(tegra_clk_cclk_g.reg);
6998 *ctx++ = clk_readl(tegra_clk_cclk_g.reg + SUPER_CLK_DIVIDER);
7000 *ctx++ = clk_readl(SPARE_REG);
7001 *ctx++ = clk_readl(MISC_CLK_ENB);
7002 *ctx++ = clk_readl(CLK_MASK_ARM);
7007 static void tegra11_clk_resume(void)
7010 const u32 *ctx = clk_rst_suspend;
7015 u32 pll_p_out12, pll_p_out34;
7016 u32 pll_a_out0, pll_m_out1, pll_c_out1;
7019 /* FIXME: OSC_CTRL already restored by warm boot code? */
7020 val = clk_readl(OSC_CTRL) & ~OSC_CTRL_MASK;
7022 clk_writel(val, OSC_CTRL);
7023 clk_writel(*ctx++, CPU_SOFTRST_CTRL);
7024 clk_writel(*ctx++, CPU_SOFTRST_CTRL1);
7025 clk_writel(*ctx++, CPU_SOFTRST_CTRL2);
7028 /* Since we are going to reset devices and switch clock sources in this
7029 * function, plls and secondary dividers is required to be enabled. The
7030 * actual value will be restored back later. Note that boot plls: pllm,
7031 * pllp, and pllu are already configured and enabled
7033 val = PLL_OUT_CLKEN | PLL_OUT_RESET_DISABLE;
7035 pll_p_out12 = *ctx++;
7036 clk_writel(pll_p_out12 | val, tegra_pll_p_out1.reg);
7037 pll_p_out34 = *ctx++;
7038 clk_writel(pll_p_out34 | val, tegra_pll_p_out3.reg);
7040 tegra11_pllcx_clk_resume_enable(&tegra_pll_c2);
7041 tegra11_pllcx_clk_resume_enable(&tegra_pll_c3);
7042 tegra11_pllxc_clk_resume_enable(&tegra_pll_c);
7043 tegra11_pllxc_clk_resume_enable(&tegra_pll_x);
7046 clk_writel(*ctx++, tegra_pll_a.reg + PLL_MISC(&tegra_pll_a));
7047 clk_writel(plla_base | PLL_BASE_ENABLE, tegra_pll_a.reg + PLL_BASE);
7050 clk_writel(*ctx++, tegra_pll_d.reg + PLL_MISC(&tegra_pll_d));
7051 clk_writel(plld_base | PLL_BASE_ENABLE, tegra_pll_d.reg + PLL_BASE);
7053 plld2_base = *ctx++;
7054 clk_writel(*ctx++, tegra_pll_d2.reg + PLL_MISC(&tegra_pll_d2));
7055 clk_writel(plld2_base | PLL_BASE_ENABLE, tegra_pll_d2.reg + PLL_BASE);
7059 val = PLL_OUT_CLKEN | PLL_OUT_RESET_DISABLE;
7060 pll_m_out1 = *ctx++;
7061 clk_writel(pll_m_out1 | val, tegra_pll_m_out1.reg);
7062 pll_a_out0 = *ctx++;
7063 clk_writel(pll_a_out0 | val, tegra_pll_a_out0.reg);
7064 pll_c_out1 = *ctx++;
7065 clk_writel(pll_c_out1 | val, tegra_pll_c_out1.reg);
7068 tegra11_super_clk_resume(&tegra_clk_cclk_lp,
7069 tegra_clk_virtual_cpu_lp.u.cpu.backup, val);
7070 clk_writel(*ctx++, tegra_clk_cclk_lp.reg + SUPER_CLK_DIVIDER);
7072 clk_writel(*ctx++, tegra_clk_sclk.reg);
7073 clk_writel(*ctx++, tegra_clk_sclk.reg + SUPER_CLK_DIVIDER);
7074 clk_writel(*ctx++, tegra_clk_pclk.reg);
7076 /* enable all clocks before configuring clock sources */
7077 clk_writel(0xfdfffff1ul, CLK_OUT_ENB_L);
7078 clk_writel(0xffddfff7ul, CLK_OUT_ENB_H);
7079 clk_writel(0xfbfffbfeul, CLK_OUT_ENB_U);
7080 clk_writel(0xfffffffful, CLK_OUT_ENB_V);
7081 clk_writel(0xff7ffffful, CLK_OUT_ENB_W);
7084 for (off = PERIPH_CLK_SOURCE_I2S1; off <= PERIPH_CLK_SOURCE_OSC;
7086 if (off == PERIPH_CLK_SOURCE_EMC)
7088 clk_writel(*ctx++, off);
7090 for (off = PERIPH_CLK_SOURCE_G3D2; off <= PERIPH_CLK_SOURCE_SE;
7092 clk_writel(*ctx++, off);
7094 for (off = AUDIO_DLY_CLK; off <= AUDIO_SYNC_CLK_SPDIF; off+=4) {
7095 clk_writel(*ctx++, off);
7097 for (off = PERIPH_CLK_SOURCE_XUSB_HOST;
7098 off <= PERIPH_CLK_SOURCE_SOC_THERM; off += 4)
7099 clk_writel(*ctx++, off);
7101 clk_writel(*ctx++, RST_DEVICES_L);
7102 clk_writel(*ctx++, RST_DEVICES_H);
7103 clk_writel(*ctx++, RST_DEVICES_U);
7104 clk_writel(*ctx++, RST_DEVICES_V);
7105 clk_writel(*ctx++, RST_DEVICES_W);
7106 clk_writel(*ctx++, RST_DEVICES_X);
7109 clk_writel(*ctx++, CLK_OUT_ENB_L);
7110 clk_writel(*ctx++, CLK_OUT_ENB_H);
7111 clk_writel(*ctx++, CLK_OUT_ENB_U);
7113 /* For LP0 resume, clk to lpcpu is required to be on */
7114 /* FIXME: should be saved as on? */
7116 val |= CLK_OUT_ENB_V_CLK_ENB_CPULP_EN;
7117 clk_writel(val, CLK_OUT_ENB_V);
7119 clk_writel(*ctx++, CLK_OUT_ENB_W);
7120 clk_writel(*ctx++, CLK_OUT_ENB_X);
7123 /* DFLL resume after cl_dvfs and i2c5 clocks are resumed */
7124 tegra11_dfll_clk_resume(&tegra_dfll_cpu);
7126 /* CPU G clock restored after DFLL and PLLs */
7127 clk_writel(*ctx++, tegra_clk_cclk_g.reg);
7128 clk_writel(*ctx++, tegra_clk_cclk_g.reg + SUPER_CLK_DIVIDER);
7130 clk_writel(*ctx++, SPARE_REG);
7131 clk_writel(*ctx++, MISC_CLK_ENB);
7132 clk_writel(*ctx++, CLK_MASK_ARM);
7134 /* Restore back the actual pll and secondary divider values */
7135 clk_writel(pll_p_out12, tegra_pll_p_out1.reg);
7136 clk_writel(pll_p_out34, tegra_pll_p_out3.reg);
7139 if (p->state == OFF)
7140 tegra11_pllcx_clk_disable(p);
7142 if (p->state == OFF)
7143 tegra11_pllcx_clk_disable(p);
7145 if (p->state == OFF)
7146 tegra11_pllxc_clk_disable(p);
7148 if (p->state == OFF)
7149 tegra11_pllxc_clk_disable(p);
7151 clk_writel(plla_base, tegra_pll_a.reg + PLL_BASE);
7152 clk_writel(plld_base, tegra_pll_d.reg + PLL_BASE);
7153 clk_writel(plld2_base, tegra_pll_d2.reg + PLL_BASE);
7155 clk_writel(pll_m_out1, tegra_pll_m_out1.reg);
7156 clk_writel(pll_a_out0, tegra_pll_a_out0.reg);
7157 clk_writel(pll_c_out1, tegra_pll_c_out1.reg);
7159 /* Since EMC clock is not restored, and may not preserve parent across
7160 suspend, update current state, and mark EMC DFS as out of sync */
7161 p = tegra_clk_emc.parent;
7162 tegra11_periph_clk_init(&tegra_clk_emc);
7164 if (p != tegra_clk_emc.parent) {
7165 /* FIXME: old parent is left enabled here even if EMC was its
7166 only child before suspend (may happen on Tegra11 !!) */
7167 pr_debug("EMC parent(refcount) across suspend: %s(%d) : %s(%d)",
7168 p->name, p->refcnt, tegra_clk_emc.parent->name,
7169 tegra_clk_emc.parent->refcnt);
7174 /* the new parent is enabled by low level code, but ref count
7175 need to be updated up to the root */
7176 p = tegra_clk_emc.parent;
7177 while (p && ((p->refcnt++) == 0))
7180 tegra_emc_timing_invalidate();
7182 tegra11_pll_clk_init(&tegra_pll_u); /* Re-init utmi parameters */
7183 tegra11_pllp_clk_resume(&tegra_pll_p); /* Fire a bug if not restored */
7186 static struct syscore_ops tegra_clk_syscore_ops = {
7187 .suspend = tegra11_clk_suspend,
7188 .resume = tegra11_clk_resume,
7192 static void tegra11_disable_cpu_clock(u32 cpu)
7196 void __init tegra11x_init_clocks(void)
7201 for (i = 0; i < ARRAY_SIZE(tegra_ptr_clks); i++)
7202 tegra11_init_one_clock(tegra_ptr_clks[i]);
7204 for (i = 0; i < ARRAY_SIZE(tegra_list_clks); i++)
7205 tegra11_init_one_clock(&tegra_list_clks[i]);
7207 for (i = 0; i < ARRAY_SIZE(tegra_clk_duplicates); i++) {
7208 c = tegra_get_clock_by_name(tegra_clk_duplicates[i].name);
7210 pr_err("%s: Unknown duplicate clock %s\n", __func__,
7211 tegra_clk_duplicates[i].name);
7215 tegra_clk_duplicates[i].lookup.clk = c;
7216 clkdev_add(&tegra_clk_duplicates[i].lookup);
7219 for (i = 0; i < ARRAY_SIZE(tegra_sync_source_list); i++)
7220 tegra11_init_one_clock(&tegra_sync_source_list[i]);
7221 for (i = 0; i < ARRAY_SIZE(tegra_clk_audio_list); i++)
7222 tegra11_init_one_clock(&tegra_clk_audio_list[i]);
7223 for (i = 0; i < ARRAY_SIZE(tegra_clk_audio_2x_list); i++)
7224 tegra11_init_one_clock(&tegra_clk_audio_2x_list[i]);
7227 for (i = 0; i < ARRAY_SIZE(tegra_clk_out_list); i++)
7228 tegra11_init_one_clock(&tegra_clk_out_list[i]);
7230 for (i = 0; i < ARRAY_SIZE(tegra_xusb_source_clks); i++)
7231 tegra11_init_one_clock(&tegra_xusb_source_clks[i]);
7233 for (i = 0; i < ARRAY_SIZE(tegra_xusb_coupled_clks); i++)
7234 tegra11_init_one_clock(&tegra_xusb_coupled_clks[i]);
7236 /* Initialize to default */
7237 tegra_init_cpu_edp_limits(0);
7239 /* To be ready for DFLL late init */
7240 tegra_dfll_cpu.ops->init = tegra11_dfll_cpu_late_init;
7242 #ifdef CONFIG_PM_SLEEP
7243 register_syscore_ops(&tegra_clk_syscore_ops);