2 * arch/arm/mach-tegra/tegra11_clocks.c
4 * Copyright (C) 2011-2012 NVIDIA Corporation
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * You should have received a copy of the GNU General Public License along
16 * with this program; if not, write to the Free Software Foundation, Inc.,
17 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
21 #include <linux/kernel.h>
22 #include <linux/module.h>
23 #include <linux/list.h>
24 #include <linux/spinlock.h>
25 #include <linux/delay.h>
26 #include <linux/err.h>
28 #include <linux/clk.h>
29 #include <linux/cpufreq.h>
30 #include <linux/syscore_ops.h>
31 #include <linux/platform_device.h>
32 #include <linux/clk/tegra.h>
34 #include <asm/clkdev.h>
37 #include <mach/hardware.h>
47 #include "tegra11_emc.h"
48 #include "tegra_cl_dvfs.h"
50 #define RST_DEVICES_L 0x004
51 #define RST_DEVICES_H 0x008
52 #define RST_DEVICES_U 0x00C
53 #define RST_DEVICES_V 0x358
54 #define RST_DEVICES_W 0x35C
55 #define RST_DEVICES_X 0x28C
56 #define RST_DEVICES_SET_L 0x300
57 #define RST_DEVICES_CLR_L 0x304
58 #define RST_DEVICES_SET_V 0x430
59 #define RST_DEVICES_CLR_V 0x434
60 #define RST_DEVICES_SET_X 0x290
61 #define RST_DEVICES_CLR_X 0x294
62 #define RST_DEVICES_NUM 6
64 #define CLK_OUT_ENB_L 0x010
65 #define CLK_OUT_ENB_H 0x014
66 #define CLK_OUT_ENB_U 0x018
67 #define CLK_OUT_ENB_V 0x360
68 #define CLK_OUT_ENB_W 0x364
69 #define CLK_OUT_ENB_X 0x280
70 #define CLK_OUT_ENB_SET_L 0x320
71 #define CLK_OUT_ENB_CLR_L 0x324
72 #define CLK_OUT_ENB_SET_V 0x440
73 #define CLK_OUT_ENB_CLR_V 0x444
74 #define CLK_OUT_ENB_SET_X 0x284
75 #define CLK_OUT_ENB_CLR_X 0x288
76 #define CLK_OUT_ENB_NUM 6
78 #define RST_DEVICES_V_SWR_CPULP_RST_DIS (0x1 << 1) /* Reserved on Tegra11 */
79 #define CLK_OUT_ENB_V_CLK_ENB_CPULP_EN (0x1 << 1)
81 #define PERIPH_CLK_TO_BIT(c) (1 << (c->u.periph.clk_num % 32))
82 #define PERIPH_CLK_TO_RST_REG(c) \
83 periph_clk_to_reg((c), RST_DEVICES_L, RST_DEVICES_V, RST_DEVICES_X, 4)
84 #define PERIPH_CLK_TO_RST_SET_REG(c) \
85 periph_clk_to_reg((c), RST_DEVICES_SET_L, RST_DEVICES_SET_V, \
87 #define PERIPH_CLK_TO_RST_CLR_REG(c) \
88 periph_clk_to_reg((c), RST_DEVICES_CLR_L, RST_DEVICES_CLR_V, \
91 #define PERIPH_CLK_TO_ENB_REG(c) \
92 periph_clk_to_reg((c), CLK_OUT_ENB_L, CLK_OUT_ENB_V, CLK_OUT_ENB_X, 4)
93 #define PERIPH_CLK_TO_ENB_SET_REG(c) \
94 periph_clk_to_reg((c), CLK_OUT_ENB_SET_L, CLK_OUT_ENB_SET_V, \
96 #define PERIPH_CLK_TO_ENB_CLR_REG(c) \
97 periph_clk_to_reg((c), CLK_OUT_ENB_CLR_L, CLK_OUT_ENB_CLR_V, \
100 #define CLK_MASK_ARM 0x44
101 #define MISC_CLK_ENB 0x48
103 #define OSC_CTRL 0x50
104 #define OSC_CTRL_OSC_FREQ_MASK (0xF<<28)
105 #define OSC_CTRL_OSC_FREQ_13MHZ (0x0<<28)
106 #define OSC_CTRL_OSC_FREQ_19_2MHZ (0x4<<28)
107 #define OSC_CTRL_OSC_FREQ_12MHZ (0x8<<28)
108 #define OSC_CTRL_OSC_FREQ_26MHZ (0xC<<28)
109 #define OSC_CTRL_OSC_FREQ_16_8MHZ (0x1<<28)
110 #define OSC_CTRL_OSC_FREQ_38_4MHZ (0x5<<28)
111 #define OSC_CTRL_OSC_FREQ_48MHZ (0x9<<28)
112 #define OSC_CTRL_MASK (0x3f2 | OSC_CTRL_OSC_FREQ_MASK)
114 #define OSC_CTRL_PLL_REF_DIV_MASK (3<<26)
115 #define OSC_CTRL_PLL_REF_DIV_1 (0<<26)
116 #define OSC_CTRL_PLL_REF_DIV_2 (1<<26)
117 #define OSC_CTRL_PLL_REF_DIV_4 (2<<26)
119 #define PERIPH_CLK_SOURCE_I2S1 0x100
120 #define PERIPH_CLK_SOURCE_EMC 0x19c
121 #define PERIPH_CLK_SOURCE_OSC 0x1fc
122 #define PERIPH_CLK_SOURCE_NUM1 \
123 ((PERIPH_CLK_SOURCE_OSC - PERIPH_CLK_SOURCE_I2S1) / 4)
125 #define PERIPH_CLK_SOURCE_G3D2 0x3b0
126 #define PERIPH_CLK_SOURCE_SE 0x42c
127 #define PERIPH_CLK_SOURCE_NUM2 \
128 ((PERIPH_CLK_SOURCE_SE - PERIPH_CLK_SOURCE_G3D2) / 4 + 1)
130 #define AUDIO_DLY_CLK 0x49c
131 #define AUDIO_SYNC_CLK_SPDIF 0x4b4
132 #define PERIPH_CLK_SOURCE_NUM3 \
133 ((AUDIO_SYNC_CLK_SPDIF - AUDIO_DLY_CLK) / 4 + 1)
135 #define SPARE_REG 0x55c
136 #define PERIPH_CLK_SOURCE_XUSB_HOST 0x600
137 #define PERIPH_CLK_SOURCE_SOC_THERM 0x644
138 #define PERIPH_CLK_SOURCE_NUM4 \
139 ((PERIPH_CLK_SOURCE_SOC_THERM - PERIPH_CLK_SOURCE_XUSB_HOST) / 4 + 1)
141 #define PERIPH_CLK_SOURCE_NUM (PERIPH_CLK_SOURCE_NUM1 + \
142 PERIPH_CLK_SOURCE_NUM2 + \
143 PERIPH_CLK_SOURCE_NUM3 + \
144 PERIPH_CLK_SOURCE_NUM4)
146 #define CPU_SOFTRST_CTRL 0x380
147 #define CPU_SOFTRST_CTRL1 0x384
148 #define CPU_SOFTRST_CTRL2 0x388
150 #define PERIPH_CLK_SOURCE_DIVU71_MASK 0xFF
151 #define PERIPH_CLK_SOURCE_DIVU16_MASK 0xFFFF
152 #define PERIPH_CLK_SOURCE_DIV_SHIFT 0
153 #define PERIPH_CLK_SOURCE_DIVIDLE_SHIFT 8
154 #define PERIPH_CLK_SOURCE_DIVIDLE_VAL 50
155 #define PERIPH_CLK_UART_DIV_ENB (1<<24)
156 #define PERIPH_CLK_VI_SEL_EX_SHIFT 24
157 #define PERIPH_CLK_VI_SEL_EX_MASK (0x3<<PERIPH_CLK_VI_SEL_EX_SHIFT)
158 #define PERIPH_CLK_NAND_DIV_EX_ENB (1<<8)
159 #define PERIPH_CLK_DTV_POLARITY_INV (1<<25)
161 #define AUDIO_SYNC_SOURCE_MASK 0x0F
162 #define AUDIO_SYNC_DISABLE_BIT 0x10
163 #define AUDIO_SYNC_TAP_NIBBLE_SHIFT(c) ((c->reg_shift - 24) * 4)
167 #define PLL_BASE_BYPASS (1<<31)
168 #define PLL_BASE_ENABLE (1<<30)
169 #define PLL_BASE_REF_ENABLE (1<<29)
170 #define PLL_BASE_OVERRIDE (1<<28)
171 #define PLL_BASE_LOCK (1<<27)
172 #define PLL_BASE_DIVP_MASK (0x7<<20)
173 #define PLL_BASE_DIVP_SHIFT 20
174 #define PLL_BASE_DIVN_MASK (0x3FF<<8)
175 #define PLL_BASE_DIVN_SHIFT 8
176 #define PLL_BASE_DIVM_MASK (0x1F)
177 #define PLL_BASE_DIVM_SHIFT 0
179 #define PLL_BASE_PARSE(pll, cfg, b) \
181 (cfg).m = ((b) & pll##_BASE_DIVM_MASK) >> PLL_BASE_DIVM_SHIFT; \
182 (cfg).n = ((b) & pll##_BASE_DIVN_MASK) >> PLL_BASE_DIVN_SHIFT; \
183 (cfg).p = ((b) & pll##_BASE_DIVP_MASK) >> PLL_BASE_DIVP_SHIFT; \
186 #define PLL_OUT_RATIO_MASK (0xFF<<8)
187 #define PLL_OUT_RATIO_SHIFT 8
188 #define PLL_OUT_OVERRIDE (1<<2)
189 #define PLL_OUT_CLKEN (1<<1)
190 #define PLL_OUT_RESET_DISABLE (1<<0)
192 #define PLL_MISC(c) \
193 (((c)->flags & PLL_ALT_MISC_REG) ? 0x4 : 0xc)
194 #define PLL_MISCN(c, n) \
195 ((c)->u.pll.misc1 + ((n) - 1) * PLL_MISC(c))
196 #define PLL_MISC_LOCK_ENABLE(c) \
197 (((c)->flags & (PLLU | PLLD)) ? (1<<22) : (1<<18))
199 #define PLL_MISC_DCCON_SHIFT 20
200 #define PLL_MISC_CPCON_SHIFT 8
201 #define PLL_MISC_CPCON_MASK (0xF<<PLL_MISC_CPCON_SHIFT)
202 #define PLL_MISC_LFCON_SHIFT 4
203 #define PLL_MISC_LFCON_MASK (0xF<<PLL_MISC_LFCON_SHIFT)
204 #define PLL_MISC_VCOCON_SHIFT 0
205 #define PLL_MISC_VCOCON_MASK (0xF<<PLL_MISC_VCOCON_SHIFT)
207 #define PLL_FIXED_MDIV(c, ref) ((ref) > (c)->u.pll.cf_max ? 2 : 1)
210 #define PLLU_BASE_OVERRIDE (1<<24)
211 #define PLLU_BASE_POST_DIV (1<<20)
214 #define PLLD_BASE_CSI_CLKENABLE (1<<26)
215 #define PLLD_BASE_DSI_MUX_SHIFT 25
216 #define PLLD_BASE_DSI_MUX_MASK (1<<PLLD_BASE_DSI_MUX_SHIFT)
217 #define PLLD_BASE_CSI_CLKSOURCE (1<<24)
219 #define PLLD_MISC_DSI_CLKENABLE (1<<30)
220 #define PLLD_MISC_DIV_RST (1<<23)
221 #define PLLD_MISC_DCCON_SHIFT 12
223 #define PLLDU_LFCON 2
225 /* PLLC2 and PLLC3 (PLLCX) */
226 #define PLLCX_USE_DYN_RAMP 0
227 #define PLLCX_BASE_PHASE_LOCK (1<<26)
228 #define PLLCX_BASE_DIVP_MASK (0x7<<PLL_BASE_DIVP_SHIFT)
229 #define PLLCX_BASE_DIVN_MASK (0xFF<<PLL_BASE_DIVN_SHIFT)
230 #define PLLCX_BASE_DIVM_MASK (0x3<<PLL_BASE_DIVM_SHIFT)
231 #define PLLCX_PDIV_MAX ((PLLCX_BASE_DIVP_MASK >> PLL_BASE_DIVP_SHIFT))
232 #define PLLCX_IS_DYN(new_p, old_p) (((new_p) <= 8) && ((old_p) <= 8))
234 #define PLLCX_MISC_STROBE (1<<31)
235 #define PLLCX_MISC_RESET (1<<30)
236 #define PLLCX_MISC_SDM_DIV_SHIFT 28
237 #define PLLCX_MISC_SDM_DIV_MASK (0x3 << PLLCX_MISC_SDM_DIV_SHIFT)
238 #define PLLCX_MISC_FILT_DIV_SHIFT 26
239 #define PLLCX_MISC_FILT_DIV_MASK (0x3 << PLLCX_MISC_FILT_DIV_SHIFT)
240 #define PLLCX_MISC_ALPHA_SHIFT 18
241 #define PLLCX_MISC_ALPHA_MASK (0xFF << PLLCX_MISC_ALPHA_SHIFT)
242 #define PLLCX_MISC_KB_SHIFT 9
243 #define PLLCX_MISC_KB_MASK (0x1FF << PLLCX_MISC_KB_SHIFT)
244 #define PLLCX_MISC_KA_SHIFT 2
245 #define PLLCX_MISC_KA_MASK (0x7F << PLLCX_MISC_KA_SHIFT)
246 #define PLLCX_MISC_VCO_GAIN_SHIFT 0
247 #define PLLCX_MISC_VCO_GAIN_MASK (0x3 << PLLCX_MISC_VCO_GAIN_SHIFT)
249 #define PLLCX_MISC_KOEF_LOW_RANGE \
250 ((0x14 << PLLCX_MISC_KA_SHIFT) | (0x38 << PLLCX_MISC_KB_SHIFT))
252 #define PLLCX_MISC_DIV_LOW_RANGE \
253 ((0x1 << PLLCX_MISC_SDM_DIV_SHIFT) | (0x1 << PLLCX_MISC_FILT_DIV_SHIFT))
254 #define PLLCX_MISC_DIV_HIGH_RANGE \
255 ((0x2 << PLLCX_MISC_SDM_DIV_SHIFT) | (0x2 << PLLCX_MISC_FILT_DIV_SHIFT))
257 #define PLLCX_MISC_DEFAULT_VALUE ((0x0 << PLLCX_MISC_VCO_GAIN_SHIFT) | \
258 PLLCX_MISC_KOEF_LOW_RANGE | \
259 (0x19 << PLLCX_MISC_ALPHA_SHIFT) | \
260 PLLCX_MISC_DIV_LOW_RANGE | \
262 #define PLLCX_MISC1_DEFAULT_VALUE 0x000d2308
263 #define PLLCX_MISC2_DEFAULT_VALUE 0x30211200
264 #define PLLCX_MISC3_DEFAULT_VALUE 0x200
266 /* PLLX and PLLC (PLLXC)*/
267 #define PLLXC_USE_DYN_RAMP 0
268 #define PLLXC_BASE_DIVP_MASK (0xF<<PLL_BASE_DIVP_SHIFT)
269 #define PLLXC_BASE_DIVN_MASK (0xFF<<PLL_BASE_DIVN_SHIFT)
270 #define PLLXC_BASE_DIVM_MASK (0xFF<<PLL_BASE_DIVM_SHIFT)
272 /* PLLXC has 4-bit PDIV, but entry 15 is not allowed in h/w,
273 and s/w usage is limited to 5 */
274 #define PLLXC_PDIV_MAX 14
275 #define PLLXC_SW_PDIV_MAX 5
278 #define PLLX_MISC2_DYNRAMP_STEPB_SHIFT 24
279 #define PLLX_MISC2_DYNRAMP_STEPB_MASK (0xFF << PLLX_MISC2_DYNRAMP_STEPB_SHIFT)
280 #define PLLX_MISC2_DYNRAMP_STEPA_SHIFT 16
281 #define PLLX_MISC2_DYNRAMP_STEPA_MASK (0xFF << PLLX_MISC2_DYNRAMP_STEPA_SHIFT)
282 #define PLLX_MISC2_NDIV_NEW_SHIFT 8
283 #define PLLX_MISC2_NDIV_NEW_MASK (0xFF << PLLX_MISC2_NDIV_NEW_SHIFT)
284 #define PLLX_MISC2_LOCK_OVERRIDE (0x1 << 4)
285 #define PLLX_MISC2_DYNRAMP_DONE (0x1 << 2)
286 #define PLLX_MISC2_CLAMP_NDIV (0x1 << 1)
287 #define PLLX_MISC2_EN_DYNRAMP (0x1 << 0)
289 #define PLLX_MISC3_IDDQ (0x1 << 3)
291 #define PLLX_HW_CTRL_CFG 0x548
292 #define PLLX_HW_CTRL_CFG_SWCTRL (0x1 << 0)
295 #define PLLC_BASE_LOCK_OVERRIDE (1<<28)
297 #define PLLC_MISC_IDDQ (0x1 << 26)
298 #define PLLC_MISC_LOCK_ENABLE (0x1 << 24)
300 #define PLLC_MISC1_CLAMP_NDIV (0x1 << 26)
301 #define PLLC_MISC1_EN_DYNRAMP (0x1 << 25)
302 #define PLLC_MISC1_DYNRAMP_STEPA_SHIFT 17
303 #define PLLC_MISC1_DYNRAMP_STEPA_MASK (0xFF << PLLC_MISC1_DYNRAMP_STEPA_SHIFT)
304 #define PLLC_MISC1_DYNRAMP_STEPB_SHIFT 9
305 #define PLLC_MISC1_DYNRAMP_STEPB_MASK (0xFF << PLLC_MISC1_DYNRAMP_STEPB_SHIFT)
306 #define PLLC_MISC1_NDIV_NEW_SHIFT 1
307 #define PLLC_MISC1_NDIV_NEW_MASK (0xFF << PLLC_MISC1_NDIV_NEW_SHIFT)
308 #define PLLC_MISC1_DYNRAMP_DONE (0x1 << 0)
311 #define PLLM_BASE_DIVP_MASK (0x1 << PLL_BASE_DIVP_SHIFT)
312 #define PLLM_BASE_DIVN_MASK (0xFF << PLL_BASE_DIVN_SHIFT)
313 #define PLLM_BASE_DIVM_MASK (0xFF << PLL_BASE_DIVM_SHIFT)
314 #define PLLM_PDIV_MAX 1
316 #define PLLM_MISC_FSM_SW_OVERRIDE (0x1 << 10)
317 #define PLLM_MISC_IDDQ (0x1 << 5)
318 #define PLLM_MISC_LOCK_DISABLE (0x1 << 4)
319 #define PLLM_MISC_LOCK_OVERRIDE (0x1 << 3)
321 #define PMC_PLLP_WB0_OVERRIDE 0xf8
322 #define PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE (1 << 12)
323 #define PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE (1 << 11)
325 /* M, N layout for PLLM override and base registers are the same */
326 #define PMC_PLLM_WB0_OVERRIDE 0x1dc
328 #define PMC_PLLM_WB0_OVERRIDE_2 0x2b0
329 #define PMC_PLLM_WB0_OVERRIDE_2_DIVP_MASK (0x1 << 27)
332 #define PLLRE_BASE_DIVP_SHIFT 16
333 #define PLLRE_BASE_DIVP_MASK (0xF << PLLRE_BASE_DIVP_SHIFT)
334 #define PLLRE_BASE_DIVN_MASK (0xFF << PLL_BASE_DIVN_SHIFT)
335 #define PLLRE_BASE_DIVM_MASK (0xFF << PLL_BASE_DIVM_SHIFT)
337 /* PLLRE has 4-bit PDIV, but entry 15 is not allowed in h/w,
338 and s/w usage is limited to 5 */
339 #define PLLRE_PDIV_MAX 14
340 #define PLLRE_SW_PDIV_MAX 5
342 #define PLLRE_MISC_LOCK_ENABLE (0x1 << 30)
343 #define PLLRE_MISC_LOCK_OVERRIDE (0x1 << 29)
344 #define PLLRE_MISC_LOCK (0x1 << 24)
345 #define PLLRE_MISC_IDDQ (0x1 << 16)
347 #define OUT_OF_TABLE_CPCON 0x8
349 #define SUPER_CLK_MUX 0x00
350 #define SUPER_STATE_SHIFT 28
351 #define SUPER_STATE_MASK (0xF << SUPER_STATE_SHIFT)
352 #define SUPER_STATE_STANDBY (0x0 << SUPER_STATE_SHIFT)
353 #define SUPER_STATE_IDLE (0x1 << SUPER_STATE_SHIFT)
354 #define SUPER_STATE_RUN (0x2 << SUPER_STATE_SHIFT)
355 #define SUPER_STATE_IRQ (0x3 << SUPER_STATE_SHIFT)
356 #define SUPER_STATE_FIQ (0x4 << SUPER_STATE_SHIFT)
357 #define SUPER_LP_DIV2_BYPASS (0x1 << 16)
358 #define SUPER_SOURCE_MASK 0xF
359 #define SUPER_FIQ_SOURCE_SHIFT 12
360 #define SUPER_IRQ_SOURCE_SHIFT 8
361 #define SUPER_RUN_SOURCE_SHIFT 4
362 #define SUPER_IDLE_SOURCE_SHIFT 0
364 #define SUPER_CLK_DIVIDER 0x04
365 #define SUPER_CLOCK_DIV_U71_SHIFT 16
366 #define SUPER_CLOCK_DIV_U71_MASK (0xff << SUPER_CLOCK_DIV_U71_SHIFT)
368 #define BUS_CLK_DISABLE (1<<3)
369 #define BUS_CLK_DIV_MASK 0x3
372 #define PMC_CTRL_BLINK_ENB (1 << 7)
374 #define PMC_DPD_PADS_ORIDE 0x1c
375 #define PMC_DPD_PADS_ORIDE_BLINK_ENB (1 << 20)
377 #define PMC_BLINK_TIMER_DATA_ON_SHIFT 0
378 #define PMC_BLINK_TIMER_DATA_ON_MASK 0x7fff
379 #define PMC_BLINK_TIMER_ENB (1 << 15)
380 #define PMC_BLINK_TIMER_DATA_OFF_SHIFT 16
381 #define PMC_BLINK_TIMER_DATA_OFF_MASK 0xffff
383 #define UTMIP_PLL_CFG2 0x488
384 #define UTMIP_PLL_CFG2_STABLE_COUNT(x) (((x) & 0xfff) << 6)
385 #define UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(x) (((x) & 0x3f) << 18)
386 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN (1 << 0)
387 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERUP (1 << 1)
388 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN (1 << 2)
389 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERUP (1 << 3)
390 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN (1 << 4)
391 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERUP (1 << 5)
392 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_D_POWERDOWN (1 << 24)
393 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_D_POWERUP (1 << 25)
395 #define UTMIP_PLL_CFG1 0x484
396 #define UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(x) (((x) & 0x1f) << 27)
397 #define UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(x) (((x) & 0xfff) << 0)
398 #define UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERUP (1 << 15)
399 #define UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN (1 << 14)
400 #define UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN (1 << 12)
401 #define UTMIP_PLL_CFG1_FORCE_PLLU_POWERUP (1 << 17)
402 #define UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN (1 << 16)
405 #define PLLE_BASE_LOCK_OVERRIDE (0x1 << 29)
406 #define PLLE_BASE_DIVCML_SHIFT 24
407 #define PLLE_BASE_DIVCML_MASK (0xf<<PLLE_BASE_DIVCML_SHIFT)
408 #define PLLE_BASE_DIVN_MASK (0xFF<<PLL_BASE_DIVN_SHIFT)
409 #define PLLE_BASE_DIVM_MASK (0xFF<<PLL_BASE_DIVM_SHIFT)
411 /* PLLE has 4-bit CMLDIV, but entry 15 is not allowed in h/w */
412 #define PLLE_CMLDIV_MAX 14
414 #define PLLE_MISC_READY (1<<15)
415 #define PLLE_MISC_IDDQ_SW_CTRL (1<<14)
416 #define PLLE_MISC_IDDQ_SW_VALUE (1<<13)
417 #define PLLE_MISC_LOCK (1<<11)
418 #define PLLE_MISC_LOCK_ENABLE (1<<9)
419 #define PLLE_MISC_PLLE_PTS (1<<8)
420 #define PLLE_MISC_VREG_BG_CTRL_SHIFT 4
421 #define PLLE_MISC_VREG_BG_CTRL_MASK (0x3<<PLLE_MISC_VREG_BG_CTRL_SHIFT)
422 #define PLLE_MISC_VREG_CTRL_SHIFT 2
423 #define PLLE_MISC_VREG_CTRL_MASK (0x3<<PLLE_MISC_VREG_CTRL_SHIFT)
425 #define PLLE_SS_CTRL 0x68
426 #define PLLE_SS_INCINTRV_SHIFT 24
427 #define PLLE_SS_INCINTRV_MASK (0x3f<<PLLE_SS_INCINTRV_SHIFT)
428 #define PLLE_SS_INC_SHIFT 16
429 #define PLLE_SS_INC_MASK (0xff<<PLLE_SS_INC_SHIFT)
430 #define PLLE_SS_CNTL_SSC_BYP (0x1 << 12)
431 #define PLLE_SS_CNTL_INTERP_RESET (0x1 << 11)
432 #define PLLE_SS_CNTL_BYPASS_SS (0x1 << 10)
433 #define PLLE_SS_MAX_SHIFT 0
434 #define PLLE_SS_MAX_MASK (0x1ff<<PLLE_SS_MAX_SHIFT)
435 #define PLLE_SS_COEFFICIENTS_MASK \
436 (PLLE_SS_INCINTRV_MASK | PLLE_SS_INC_MASK | PLLE_SS_MAX_MASK)
437 #define PLLE_SS_COEFFICIENTS_VAL \
438 ((0x20<<PLLE_SS_INCINTRV_SHIFT) | (0x1<<PLLE_SS_INC_SHIFT) | \
439 (0x25<<PLLE_SS_MAX_SHIFT))
440 #define PLLE_SS_DISABLE (PLLE_SS_CNTL_SSC_BYP |\
441 PLLE_SS_CNTL_INTERP_RESET | PLLE_SS_CNTL_BYPASS_SS)
443 #define PLLE_AUX 0x48c
444 #define PLLE_AUX_PLLRE_SEL (1<<28)
445 #define PLLE_AUX_SEQ_STATE_SHIFT 26
446 #define PLLE_AUX_SEQ_STATE_MASK (0x3<<PLLE_AUX_SEQ_STATE_SHIFT)
447 #define PLLE_AUX_SEQ_START_STATE (1<<25)
448 #define PLLE_AUX_SEQ_ENABLE (1<<24)
449 #define PLLE_AUX_SS_SWCTL (1<<6)
450 #define PLLE_AUX_ENABLE_SWCTL (1<<4)
451 #define PLLE_AUX_USE_LOCKDET (1<<3)
452 #define PLLE_AUX_PLLP_SEL (1<<2)
454 /* USB PLLs PD HW controls */
455 #define XUSBIO_PLL_CFG0 0x51c
456 #define XUSBIO_PLL_CFG0_SEQ_START_STATE (1<<25)
457 #define XUSBIO_PLL_CFG0_SEQ_ENABLE (1<<24)
458 #define XUSBIO_PLL_CFG0_PADPLL_USE_LOCKDET (1<<6)
459 #define XUSBIO_PLL_CFG0_CLK_ENABLE_SWCTL (1<<2)
460 #define XUSBIO_PLL_CFG0_PADPLL_RESET_SWCTL (1<<0)
462 /* XUSB PLL PAD controls */
463 #define XUSB_PADCTL_IOPHY_PLL0_CTL1 0x30
464 #define XUSB_PADCTL_IOPHY_PLL0_CTL1_PLL_PWR_OVRD (1<<3)
465 #define XUSB_PADCTL_IOPHY_PLL0_CTL1_PLL_IDDQ (1<<0)
467 #define UTMIPLL_HW_PWRDN_CFG0 0x52c
468 #define UTMIPLL_HW_PWRDN_CFG0_SEQ_START_STATE (1<<25)
469 #define UTMIPLL_HW_PWRDN_CFG0_SEQ_ENABLE (1<<24)
470 #define UTMIPLL_HW_PWRDN_CFG0_USE_LOCKDET (1<<6)
471 #define UTMIPLL_HW_PWRDN_CFG0_SEQ_RESET_INPUT_VALUE (1<<5)
472 #define UTMIPLL_HW_PWRDN_CFG0_SEQ_IN_SWCTL (1<<4)
473 #define UTMIPLL_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL (1<<2)
474 #define UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE (1<<1)
475 #define UTMIPLL_HW_PWRDN_CFG0_IDDQ_SWCTL (1<<0)
477 #define PLLU_HW_PWRDN_CFG0 0x530
478 #define PLLU_HW_PWRDN_CFG0_SEQ_START_STATE (1<<25)
479 #define PLLU_HW_PWRDN_CFG0_SEQ_ENABLE (1<<24)
480 #define PLLU_HW_PWRDN_CFG0_USE_LOCKDET (1<<6)
481 #define PLLU_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL (1<<2)
482 #define PLLU_HW_PWRDN_CFG0_CLK_SWITCH_SWCTL (1<<0)
484 #define USB_PLLS_SEQ_START_STATE (1<<25)
485 #define USB_PLLS_SEQ_ENABLE (1<<24)
486 #define USB_PLLS_USE_LOCKDET (1<<6)
487 #define USB_PLLS_ENABLE_SWCTL ((1<<2) | (1<<0))
490 #define DFLL_BASE 0x2f4
491 #define DFLL_BASE_RESET (1<<0)
493 #define LVL2_CLK_GATE_OVRE 0x554
495 #define ROUND_DIVIDER_UP 0
496 #define ROUND_DIVIDER_DOWN 1
497 #define DIVIDER_1_5_ALLOWED 0
499 /* Tegra CPU clock and reset control regs */
500 #define TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX 0x4c
501 #define TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET 0x340
502 #define TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR 0x344
503 #define TEGRA30_CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR 0x34c
504 #define TEGRA30_CLK_RST_CONTROLLER_CPU_CMPLX_STATUS 0x470
506 #define CPU_CLOCK(cpu) (0x1 << (8 + cpu))
507 #define CPU_RESET(cpu) (0x111001ul << (cpu))
509 /* PLLP default fixed rate in h/w controlled mode */
510 #define PLLP_DEFAULT_FIXED_RATE 216000000
512 /* Use PLL_RE as PLLE input (default - OSC via pll reference divider) */
513 #define USE_PLLE_INPUT_PLLRE 0
515 static bool tegra11_is_dyn_ramp(struct clk *c,
516 unsigned long rate, bool from_vco_min);
517 static void tegra11_pllp_init_dependencies(unsigned long pllp_rate);
518 static unsigned long tegra11_clk_shared_bus_update(
519 struct clk *bus, struct clk **bus_top, struct clk **bus_slow);
521 static bool detach_shared_bus;
522 module_param(detach_shared_bus, bool, 0644);
527 * Structure defining the fields for USB UTMI clocks Parameters.
529 struct utmi_clk_param
531 /* Oscillator Frequency in KHz */
533 /* UTMIP PLL Enable Delay Count */
534 u8 enable_delay_count;
535 /* UTMIP PLL Stable count */
537 /* UTMIP PLL Active delay count */
538 u8 active_delay_count;
539 /* UTMIP PLL Xtal frequency count */
543 static const struct utmi_clk_param utmi_parameters[] =
545 /* OSC_FREQUENCY, ENABLE_DLY, STABLE_CNT, ACTIVE_DLY, XTAL_FREQ_CNT */
546 {13000000, 0x02, 0x33, 0x05, 0x7F},
547 {19200000, 0x03, 0x4B, 0x06, 0xBB},
548 {12000000, 0x02, 0x2F, 0x04, 0x76},
549 {26000000, 0x04, 0x66, 0x09, 0xFE},
550 {16800000, 0x03, 0x41, 0x0A, 0xA4},
553 static void __iomem *reg_clk_base = IO_ADDRESS(TEGRA_CLK_RESET_BASE);
554 static void __iomem *reg_pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
555 static void __iomem *misc_gp_base = IO_ADDRESS(TEGRA_APB_MISC_BASE);
556 static void __iomem *reg_xusb_padctl_base = IO_ADDRESS(TEGRA_XUSB_PADCTL_BASE);
558 #define MISC_GP_HIDREV 0x804
559 #define MISC_GP_TRANSACTOR_SCRATCH_0 0x864
560 #define MISC_GP_TRANSACTOR_SCRATCH_LA_ENABLE (0x1 << 1)
561 #define MISC_GP_TRANSACTOR_SCRATCH_DDS_ENABLE (0x1 << 2)
562 #define MISC_GP_TRANSACTOR_SCRATCH_DP2_ENABLE (0x1 << 3)
565 * Some peripheral clocks share an enable bit, so refcount the enable bits
566 * in registers CLK_ENABLE_L, ... CLK_ENABLE_W, and protect refcount updates
569 static DEFINE_SPINLOCK(periph_refcount_lock);
570 static int tegra_periph_clk_enable_refcount[CLK_OUT_ENB_NUM * 32];
572 #define clk_writel(value, reg) \
573 __raw_writel(value, reg_clk_base + (reg))
574 #define clk_readl(reg) \
575 __raw_readl(reg_clk_base + (reg))
576 #define pmc_writel(value, reg) \
577 __raw_writel(value, reg_pmc_base + (reg))
578 #define pmc_readl(reg) \
579 __raw_readl(reg_pmc_base + (reg))
580 #define chipid_readl() \
581 __raw_readl(misc_gp_base + MISC_GP_HIDREV)
582 #define xusb_padctl_writel(value, reg) \
583 __raw_writel(value, reg_xusb_padctl_base + (reg))
584 #define xusb_padctl_readl(reg) \
585 __raw_readl(reg_xusb_padctl_base + (reg))
587 #define clk_writel_delay(value, reg) \
589 __raw_writel((value), reg_clk_base + (reg)); \
593 #define pll_writel_delay(value, reg) \
595 __raw_writel((value), reg_clk_base + (reg)); \
600 static inline int clk_set_div(struct clk *c, u32 n)
602 return clk_set_rate(c, (clk_get_rate(c->parent) + n-1) / n);
605 static inline u32 periph_clk_to_reg(
606 struct clk *c, u32 reg_L, u32 reg_V, u32 reg_X, int offs)
608 u32 reg = c->u.periph.clk_num / 32;
609 BUG_ON(reg >= RST_DEVICES_NUM);
611 reg = reg_L + (reg * offs);
613 reg = reg_V + ((reg - 3) * offs);
619 static int clk_div_x1_get_divider(unsigned long parent_rate, unsigned long rate,
621 u32 flags, u32 round_mode)
623 s64 divider_ux1 = parent_rate;
627 if (!(flags & DIV_U71_INT))
629 if (round_mode == ROUND_DIVIDER_UP)
630 divider_ux1 += rate - 1;
631 do_div(divider_ux1, rate);
632 if (flags & DIV_U71_INT)
635 if (divider_ux1 - 2 < 0)
638 if (divider_ux1 - 2 > max_x)
641 #if !DIVIDER_1_5_ALLOWED
642 if (divider_ux1 == 3)
643 divider_ux1 = (round_mode == ROUND_DIVIDER_UP) ? 4 : 2;
645 return divider_ux1 - 2;
648 static int clk_div71_get_divider(unsigned long parent_rate, unsigned long rate,
649 u32 flags, u32 round_mode)
651 return clk_div_x1_get_divider(parent_rate, rate, 0xFF,
655 static int clk_div151_get_divider(unsigned long parent_rate, unsigned long rate,
656 u32 flags, u32 round_mode)
658 return clk_div_x1_get_divider(parent_rate, rate, 0xFFFF,
662 static int clk_div16_get_divider(unsigned long parent_rate, unsigned long rate)
666 divider_u16 = parent_rate;
669 divider_u16 += rate - 1;
670 do_div(divider_u16, rate);
672 if (divider_u16 - 1 < 0)
675 if (divider_u16 - 1 > 0xFFFF)
678 return divider_u16 - 1;
681 static inline bool bus_user_is_slower(struct clk *a, struct clk *b)
683 return a->u.shared_bus_user.client->max_rate * a->div <
684 b->u.shared_bus_user.client->max_rate * b->div;
687 static inline bool bus_user_request_is_lower(struct clk *a, struct clk *b)
689 return a->u.shared_bus_user.rate * a->div <
690 b->u.shared_bus_user.rate * b->div;
693 /* clk_m functions */
694 static unsigned long tegra11_clk_m_autodetect_rate(struct clk *c)
696 u32 osc_ctrl = clk_readl(OSC_CTRL);
697 u32 auto_clock_control = osc_ctrl & ~OSC_CTRL_OSC_FREQ_MASK;
698 u32 pll_ref_div = osc_ctrl & OSC_CTRL_PLL_REF_DIV_MASK;
700 c->rate = tegra_clk_measure_input_freq();
703 auto_clock_control |= OSC_CTRL_OSC_FREQ_12MHZ;
704 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1);
707 auto_clock_control |= OSC_CTRL_OSC_FREQ_13MHZ;
708 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1);
711 auto_clock_control |= OSC_CTRL_OSC_FREQ_19_2MHZ;
712 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1);
715 auto_clock_control |= OSC_CTRL_OSC_FREQ_26MHZ;
716 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1);
719 auto_clock_control |= OSC_CTRL_OSC_FREQ_16_8MHZ;
720 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1);
723 auto_clock_control |= OSC_CTRL_OSC_FREQ_38_4MHZ;
724 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_2);
727 auto_clock_control |= OSC_CTRL_OSC_FREQ_48MHZ;
728 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_4);
730 case 115200: /* fake 13M for QT */
731 case 230400: /* fake 13M for QT */
732 auto_clock_control |= OSC_CTRL_OSC_FREQ_13MHZ;
734 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1);
737 pr_err("%s: Unexpected clock rate %ld", __func__, c->rate);
740 clk_writel(auto_clock_control, OSC_CTRL);
744 static void tegra11_clk_m_init(struct clk *c)
746 pr_debug("%s on clock %s\n", __func__, c->name);
747 tegra11_clk_m_autodetect_rate(c);
750 static int tegra11_clk_m_enable(struct clk *c)
752 pr_debug("%s on clock %s\n", __func__, c->name);
756 static void tegra11_clk_m_disable(struct clk *c)
758 pr_debug("%s on clock %s\n", __func__, c->name);
759 WARN(1, "Attempting to disable main SoC clock\n");
762 static struct clk_ops tegra_clk_m_ops = {
763 .init = tegra11_clk_m_init,
764 .enable = tegra11_clk_m_enable,
765 .disable = tegra11_clk_m_disable,
768 static struct clk_ops tegra_clk_m_div_ops = {
769 .enable = tegra11_clk_m_enable,
772 /* PLL reference divider functions */
773 static void tegra11_pll_ref_init(struct clk *c)
775 u32 pll_ref_div = clk_readl(OSC_CTRL) & OSC_CTRL_PLL_REF_DIV_MASK;
776 pr_debug("%s on clock %s\n", __func__, c->name);
778 switch (pll_ref_div) {
779 case OSC_CTRL_PLL_REF_DIV_1:
782 case OSC_CTRL_PLL_REF_DIV_2:
785 case OSC_CTRL_PLL_REF_DIV_4:
789 pr_err("%s: Invalid pll ref divider %d", __func__, pll_ref_div);
796 static struct clk_ops tegra_pll_ref_ops = {
797 .init = tegra11_pll_ref_init,
798 .enable = tegra11_clk_m_enable,
799 .disable = tegra11_clk_m_disable,
802 /* super clock functions */
803 /* "super clocks" on tegra11x have two-stage muxes, fractional 7.1 divider and
804 * clock skipping super divider. We will ignore the clock skipping divider,
805 * since we can't lower the voltage when using the clock skip, but we can if
806 * we lower the PLL frequency. Note that skipping divider can and will be used
807 * by thermal control h/w for automatic throttling. There is also a 7.1 divider
808 * that most CPU super-clock inputs can be routed through. We will not use it
809 * as well (keep default 1:1 state), to avoid high jitter on PLLX and DFLL path
810 * and possible concurrency access issues with thermal h/w (7.1 divider setting
811 * share register with clock skipping divider)
813 static void tegra11_super_clk_init(struct clk *c)
818 const struct clk_mux_sel *sel;
819 val = clk_readl(c->reg + SUPER_CLK_MUX);
821 BUG_ON(((val & SUPER_STATE_MASK) != SUPER_STATE_RUN) &&
822 ((val & SUPER_STATE_MASK) != SUPER_STATE_IDLE));
823 shift = ((val & SUPER_STATE_MASK) == SUPER_STATE_IDLE) ?
824 SUPER_IDLE_SOURCE_SHIFT : SUPER_RUN_SOURCE_SHIFT;
825 source = (val >> shift) & SUPER_SOURCE_MASK;
828 * Enforce PLLX DIV2 bypass setting as early as possible. It is always
829 * safe to do for both cclk_lp and cclk_g when booting on G CPU. (In
830 * case of booting on LP CPU, cclk_lp will be updated during the cpu
831 * rate change after boot, and cclk_g after the cluster switch.)
833 if ((c->flags & DIV_U71) && (!is_lp_cluster())) {
834 val |= SUPER_LP_DIV2_BYPASS;
835 clk_writel_delay(val, c->reg);
838 for (sel = c->inputs; sel->input != NULL; sel++) {
839 if (sel->value == source)
842 BUG_ON(sel->input == NULL);
843 c->parent = sel->input;
845 /* Update parent in case when LP CPU PLLX DIV2 bypassed */
846 if ((c->flags & DIV_2) && (c->parent->flags & PLLX) &&
847 (val & SUPER_LP_DIV2_BYPASS))
848 c->parent = c->parent->parent;
850 if (c->flags & DIV_U71) {
854 /* Make sure 7.1 divider is 1:1, clear s/w skipper control */
855 /* FIXME: set? preserve? thermal h/w skipper control */
856 val = clk_readl(c->reg + SUPER_CLK_DIVIDER);
857 BUG_ON(val & SUPER_CLOCK_DIV_U71_MASK);
859 clk_writel(val, c->reg + SUPER_CLK_DIVIDER);
862 clk_writel(0, c->reg + SUPER_CLK_DIVIDER);
865 static int tegra11_super_clk_enable(struct clk *c)
870 static void tegra11_super_clk_disable(struct clk *c)
872 /* since tegra 3 has 2 CPU super clocks - low power lp-mode clock and
873 geared up g-mode super clock - mode switch may request to disable
874 either of them; accept request with no affect on h/w */
877 static int tegra11_super_clk_set_parent(struct clk *c, struct clk *p)
880 const struct clk_mux_sel *sel;
883 val = clk_readl(c->reg + SUPER_CLK_MUX);
884 BUG_ON(((val & SUPER_STATE_MASK) != SUPER_STATE_RUN) &&
885 ((val & SUPER_STATE_MASK) != SUPER_STATE_IDLE));
886 shift = ((val & SUPER_STATE_MASK) == SUPER_STATE_IDLE) ?
887 SUPER_IDLE_SOURCE_SHIFT : SUPER_RUN_SOURCE_SHIFT;
888 for (sel = c->inputs; sel->input != NULL; sel++) {
889 if (sel->input == p) {
890 /* For LP mode super-clock switch between PLLX direct
891 and divided-by-2 outputs is allowed only when other
892 than PLLX clock source is current parent */
893 if ((c->flags & DIV_2) && (p->flags & PLLX) &&
894 ((sel->value ^ val) & SUPER_LP_DIV2_BYPASS)) {
895 if (c->parent->flags & PLLX)
897 val ^= SUPER_LP_DIV2_BYPASS;
898 clk_writel_delay(val, c->reg);
900 val &= ~(SUPER_SOURCE_MASK << shift);
901 val |= (sel->value & SUPER_SOURCE_MASK) << shift;
903 if (c->flags & DIV_U71) {
904 /* Make sure 7.1 divider is 1:1 */
905 u32 div = clk_readl(c->reg + SUPER_CLK_DIVIDER);
906 BUG_ON(div & SUPER_CLOCK_DIV_U71_MASK);
912 clk_writel_delay(val, c->reg);
914 if (c->refcnt && c->parent)
915 clk_disable(c->parent);
925 * Do not use super clocks "skippers", since dividing using a clock skipper
926 * does not allow the voltage to be scaled down. Instead adjust the rate of
927 * the parent clock. This requires that the parent of a super clock have no
928 * other children, otherwise the rate will change underneath the other
931 static int tegra11_super_clk_set_rate(struct clk *c, unsigned long rate)
933 /* In tegra11_cpu_clk_set_plls() and tegra11_sbus_cmplx_set_rate()
934 * this call is skipped by directly setting rate of source plls. If we
935 * ever use 7.1 divider at other than 1:1 setting, or exercise s/w
936 * skipper control, not only this function, but cpu and sbus set_rate
937 * APIs should be changed accordingly.
939 return clk_set_rate(c->parent, rate);
942 #ifdef CONFIG_PM_SLEEP
943 static void tegra11_super_clk_resume(struct clk *c, struct clk *backup,
947 const struct clk_mux_sel *sel;
950 /* For sclk and cclk_g super clock just restore saved value */
951 if (!(c->flags & DIV_2)) {
952 clk_writel_delay(setting, c->reg);
957 * For cclk_lp supper clock: switch to backup (= not PLLX) source,
958 * safely restore PLLX DIV2 bypass, and only then restore full
961 val = clk_readl(c->reg);
962 BUG_ON(((val & SUPER_STATE_MASK) != SUPER_STATE_RUN) &&
963 ((val & SUPER_STATE_MASK) != SUPER_STATE_IDLE));
964 shift = ((val & SUPER_STATE_MASK) == SUPER_STATE_IDLE) ?
965 SUPER_IDLE_SOURCE_SHIFT : SUPER_RUN_SOURCE_SHIFT;
966 for (sel = c->inputs; sel->input != NULL; sel++) {
967 if (sel->input == backup) {
968 val &= ~(SUPER_SOURCE_MASK << shift);
969 val |= (sel->value & SUPER_SOURCE_MASK) << shift;
971 BUG_ON(backup->flags & PLLX);
972 clk_writel_delay(val, c->reg);
974 val &= ~SUPER_LP_DIV2_BYPASS;
975 val |= (setting & SUPER_LP_DIV2_BYPASS);
976 clk_writel_delay(val, c->reg);
977 clk_writel_delay(setting, c->reg);
985 static struct clk_ops tegra_super_ops = {
986 .init = tegra11_super_clk_init,
987 .enable = tegra11_super_clk_enable,
988 .disable = tegra11_super_clk_disable,
989 .set_parent = tegra11_super_clk_set_parent,
990 .set_rate = tegra11_super_clk_set_rate,
993 /* virtual cpu clock functions */
994 /* some clocks can not be stopped (cpu, memory bus) while the SoC is running.
995 To change the frequency of these clocks, the parent pll may need to be
996 reprogrammed, so the clock must be moved off the pll, the pll reprogrammed,
997 and then the clock moved back to the pll. To hide this sequence, a virtual
1000 static void tegra11_cpu_clk_init(struct clk *c)
1002 c->state = (!is_lp_cluster() == (c->u.cpu.mode == MODE_G))? ON : OFF;
1005 static int tegra11_cpu_clk_enable(struct clk *c)
1010 static void tegra11_cpu_clk_disable(struct clk *c)
1012 /* since tegra 3 has 2 virtual CPU clocks - low power lp-mode clock
1013 and geared up g-mode clock - mode switch may request to disable
1014 either of them; accept request with no affect on h/w */
1017 static int tegra11_cpu_clk_set_plls(struct clk *c, unsigned long rate,
1018 unsigned long old_rate)
1021 bool on_main = false;
1022 unsigned long backup_rate, main_rate;
1023 unsigned long vco_min = c->u.cpu.main->u.pll.vco_min;
1026 * Take an extra reference to the main pll so it doesn't turn off when
1027 * we move the cpu off of it. If possible, use main pll dynamic ramp
1028 * to reach target rate in one shot. Otherwise, use dynamic ramp to
1029 * lower current rate to pll VCO minimum level before switching to
1032 if (c->parent->parent == c->u.cpu.main) {
1033 bool dramp = (rate > c->u.cpu.backup_rate) &&
1034 tegra11_is_dyn_ramp(c->u.cpu.main, rate, false);
1035 clk_enable(c->u.cpu.main);
1039 ((old_rate > vco_min) &&
1040 tegra11_is_dyn_ramp(c->u.cpu.main, vco_min, false))) {
1041 main_rate = dramp ? rate : vco_min;
1042 ret = clk_set_rate(c->u.cpu.main, main_rate);
1044 pr_err("Failed to set cpu rate %lu on source"
1045 " %s\n", main_rate, c->u.cpu.main->name);
1050 } else if (old_rate > vco_min) {
1051 #if PLLXC_USE_DYN_RAMP
1052 pr_warn("No dynamic ramp down: %s: %lu to %lu\n",
1053 c->u.cpu.main->name, old_rate, vco_min);
1058 /* Switch to back-up source, and stay on it if target rate is below
1060 if (c->parent->parent != c->u.cpu.backup) {
1061 ret = clk_set_parent(c->parent, c->u.cpu.backup);
1063 pr_err("Failed to switch cpu to %s\n",
1064 c->u.cpu.backup->name);
1069 backup_rate = min(rate, c->u.cpu.backup_rate);
1070 if (backup_rate != clk_get_rate_locked(c)) {
1071 ret = clk_set_rate(c->u.cpu.backup, backup_rate);
1073 pr_err("Failed to set cpu rate %lu on backup source\n",
1078 if (rate == backup_rate)
1081 /* Switch from backup source to main at rate not exceeding pll VCO
1082 minimum. Use dynamic ramp to reach target rate if it is above VCO
1085 if (rate > vco_min) {
1086 if (tegra11_is_dyn_ramp(c->u.cpu.main, rate, true))
1087 main_rate = vco_min;
1088 #if PLLXC_USE_DYN_RAMP
1090 pr_warn("No dynamic ramp up: %s: %lu to %lu\n",
1091 c->u.cpu.main->name, vco_min, rate);
1095 ret = clk_set_rate(c->u.cpu.main, main_rate);
1097 pr_err("Failed to set cpu rate %lu on source"
1098 " %s\n", main_rate, c->u.cpu.main->name);
1101 ret = clk_set_parent(c->parent, c->u.cpu.main);
1103 pr_err("Failed to switch cpu to %s\n", c->u.cpu.main->name);
1106 if (rate != main_rate) {
1107 ret = clk_set_rate(c->u.cpu.main, rate);
1109 pr_err("Failed to set cpu rate %lu on source"
1110 " %s\n", rate, c->u.cpu.main->name);
1117 clk_disable(c->u.cpu.main);
1122 static int tegra11_cpu_clk_dfll_on(struct clk *c, unsigned long rate,
1123 unsigned long old_rate)
1126 struct clk *dfll = c->u.cpu.dynamic;
1127 unsigned long dfll_rate_min = c->dvfs->dfll_data.use_dfll_rate_min;
1129 /* dfll rate request */
1130 ret = clk_set_rate(dfll, rate);
1132 pr_err("Failed to set cpu rate %lu on source"
1133 " %s\n", rate, dfll->name);
1137 /* 1st time - switch to dfll */
1138 if (c->parent->parent != dfll) {
1139 if (max(old_rate, rate) < dfll_rate_min) {
1140 /* set interim cpu dvfs rate at dfll_rate_min to
1141 prevent voltage drop below dfll Vmin */
1142 ret = tegra_dvfs_set_rate(c, dfll_rate_min);
1144 pr_err("Failed to set cpu dvfs rate %lu\n",
1150 ret = clk_set_parent(c->parent, dfll);
1152 pr_err("Failed to switch cpu to %s\n", dfll->name);
1155 ret = tegra_clk_cfg_ex(dfll, TEGRA_CLK_DFLL_LOCK, 1);
1156 WARN(ret, "Failed to lock %s at rate %lu\n", dfll->name, rate);
1158 /* prevent legacy dvfs voltage scaling */
1159 tegra_dvfs_dfll_mode_set(c->dvfs, rate);
1164 static int tegra11_cpu_clk_dfll_off(struct clk *c, unsigned long rate,
1165 unsigned long old_rate)
1169 struct clk *dfll = c->u.cpu.dynamic;
1170 unsigned long dfll_rate_min = c->dvfs->dfll_data.use_dfll_rate_min;
1172 rate = min(rate, c->max_rate - c->dvfs->dfll_data.max_rate_boost);
1173 pll = (rate <= c->u.cpu.backup_rate) ? c->u.cpu.backup : c->u.cpu.main;
1175 ret = tegra_clk_cfg_ex(dfll, TEGRA_CLK_DFLL_LOCK, 0);
1177 pr_err("Failed to unlock %s\n", dfll->name);
1181 /* restore legacy dvfs operations and set appropriate voltage */
1182 ret = tegra_dvfs_dfll_mode_clear(c->dvfs, max(rate, dfll_rate_min));
1184 pr_err("Failed to set cpu rail for rate %lu\n", rate);
1188 /* set pll to target rate and return to pll source */
1189 ret = clk_set_rate(pll, rate);
1191 pr_err("Failed to set cpu rate %lu on source"
1192 " %s\n", rate, pll->name);
1195 ret = clk_set_parent(c->parent, pll);
1197 pr_err("Failed to switch cpu to %s\n", pll->name);
1201 /* If going up, adjust voltage here (down path is taken care of by the
1202 framework after set rate exit) */
1203 if (old_rate <= rate)
1204 tegra_dvfs_set_rate(c, rate);
1209 tegra_clk_cfg_ex(dfll, TEGRA_CLK_DFLL_LOCK, 1);
1210 tegra_dvfs_dfll_mode_set(c->dvfs, old_rate);
1214 static int tegra11_cpu_clk_set_rate(struct clk *c, unsigned long rate)
1216 unsigned long old_rate = clk_get_rate_locked(c);
1217 bool has_dfll = c->u.cpu.dynamic &&
1218 (c->u.cpu.dynamic->state != UNINITIALIZED);
1219 bool is_dfll = c->parent->parent == c->u.cpu.dynamic;
1221 /* On SILICON allow CPU rate change only if cpu regulator is connected.
1222 Ignore regulator connection on FPGA and SIMULATION platforms. */
1223 #ifdef CONFIG_TEGRA_SILICON_PLATFORM
1225 if (!c->dvfs->dvfs_rail)
1227 else if ((!c->dvfs->dvfs_rail->reg) && (old_rate < rate)) {
1228 WARN(1, "Increasing CPU rate while regulator is not"
1229 " ready is not allowed\n");
1234 if (has_dfll && c->dvfs && c->dvfs->dvfs_rail) {
1235 if (tegra_dvfs_is_dfll_range(c->dvfs, rate))
1236 return tegra11_cpu_clk_dfll_on(c, rate, old_rate);
1238 return tegra11_cpu_clk_dfll_off(c, rate, old_rate);
1240 return tegra11_cpu_clk_set_plls(c, rate, old_rate);
1243 static long tegra11_cpu_clk_round_rate(struct clk *c, unsigned long rate)
1245 unsigned long max_rate = c->max_rate;
1247 /* Remove dfll boost to maximum rate when running on PLL */
1248 if (c->dvfs && !tegra_dvfs_is_dfll_scale(c->dvfs, rate))
1249 max_rate -= c->dvfs->dfll_data.max_rate_boost;
1251 if (rate > max_rate)
1253 else if (rate < c->min_rate)
1258 static struct clk_ops tegra_cpu_ops = {
1259 .init = tegra11_cpu_clk_init,
1260 .enable = tegra11_cpu_clk_enable,
1261 .disable = tegra11_cpu_clk_disable,
1262 .set_rate = tegra11_cpu_clk_set_rate,
1263 .round_rate = tegra11_cpu_clk_round_rate,
1267 static void tegra11_cpu_cmplx_clk_init(struct clk *c)
1269 int i = !!is_lp_cluster();
1271 BUG_ON(c->inputs[0].input->u.cpu.mode != MODE_G);
1272 BUG_ON(c->inputs[1].input->u.cpu.mode != MODE_LP);
1273 c->parent = c->inputs[i].input;
1276 /* cpu complex clock provides second level vitualization (on top of
1277 cpu virtual cpu rate control) in order to hide the CPU mode switch
1279 #if PARAMETERIZE_CLUSTER_SWITCH
1280 static unsigned int switch_delay;
1281 static unsigned int switch_flags;
1282 static DEFINE_SPINLOCK(parameters_lock);
1284 void tegra_cluster_switch_set_parameters(unsigned int us, unsigned int flags)
1286 spin_lock(¶meters_lock);
1288 switch_flags = flags;
1289 spin_unlock(¶meters_lock);
1293 static int tegra11_cpu_cmplx_clk_enable(struct clk *c)
1298 static void tegra11_cpu_cmplx_clk_disable(struct clk *c)
1300 pr_debug("%s on clock %s\n", __func__, c->name);
1302 /* oops - don't disable the CPU complex clock! */
1306 static int tegra11_cpu_cmplx_clk_set_rate(struct clk *c, unsigned long rate)
1308 unsigned long flags;
1310 struct clk *parent = c->parent;
1312 if (!parent->ops || !parent->ops->set_rate)
1315 clk_lock_save(parent, &flags);
1317 ret = clk_set_rate_locked(parent, rate);
1319 clk_unlock_restore(parent, &flags);
1324 static int tegra11_cpu_cmplx_clk_set_parent(struct clk *c, struct clk *p)
1327 unsigned int flags, delay;
1328 const struct clk_mux_sel *sel;
1329 unsigned long rate = clk_get_rate(c->parent);
1330 struct clk *dfll = c->parent->u.cpu.dynamic ? : p->u.cpu.dynamic;
1331 struct clk *p_source;
1333 pr_debug("%s: %s %s\n", __func__, c->name, p->name);
1334 BUG_ON(c->parent->u.cpu.mode != (is_lp_cluster() ? MODE_LP : MODE_G));
1336 for (sel = c->inputs; sel->input != NULL; sel++) {
1337 if (sel->input == p)
1343 #if PARAMETERIZE_CLUSTER_SWITCH
1344 spin_lock(¶meters_lock);
1345 flags = switch_flags;
1346 delay = switch_delay;
1348 spin_unlock(¶meters_lock);
1351 /* over/under-clocking after switch - allow, but update rate */
1352 if ((rate > p->max_rate) || (rate < p->min_rate)) {
1353 rate = rate > p->max_rate ? p->max_rate : p->min_rate;
1354 ret = clk_set_rate(c->parent, rate);
1356 pr_err("%s: Failed to set rate %lu for %s\n",
1357 __func__, rate, p->name);
1364 if (rate > p->max_rate) { /* over-clocking - no switch */
1365 pr_warn("%s: No %s mode switch to %s at rate %lu\n",
1366 __func__, c->name, p->name, rate);
1369 flags = TEGRA_POWER_CLUSTER_IMMEDIATE;
1370 flags |= TEGRA_POWER_CLUSTER_PART_DEFAULT;
1373 flags |= (p->u.cpu.mode == MODE_LP) ? TEGRA_POWER_CLUSTER_LP :
1374 TEGRA_POWER_CLUSTER_G;
1376 if (p == c->parent) {
1377 if (flags & TEGRA_POWER_CLUSTER_FORCE) {
1378 /* Allow parameterized switch to the same mode */
1379 ret = tegra_cluster_control(delay, flags);
1381 pr_err("%s: Failed to force %s mode to %s\n",
1382 __func__, c->name, p->name);
1385 return 0; /* already switched - exit */
1388 if (c->parent->parent->parent == dfll) {
1389 /* G (DFLL selected as clock source) => LP switch:
1390 * turn DFLL into open loop mode ("release" VDD_CPU rail)
1391 * select target p_source for LP, and get its rate ready
1393 ret = tegra_clk_cfg_ex(dfll, TEGRA_CLK_DFLL_LOCK, 0);
1397 p_source = rate <= p->u.cpu.backup_rate ?
1398 p->u.cpu.backup : p->u.cpu.main;
1399 ret = clk_set_rate(p_source, rate);
1402 } else if (p->parent->parent == dfll) {
1403 /* LP => G (DFLL selected as clock source) switch:
1404 * set DFLL rate ready (DFLL is still disabled)
1405 * (set target p_source as dfll, G source is already selected)
1408 ret = clk_set_rate(p_source, rate);
1412 /* DFLL is not selcted on either side of the switch:
1413 * set target p_source equal to current clock source
1415 p_source = c->parent->parent->parent;
1417 /* Switch new parent to target clock source if necessary */
1418 if (p->parent->parent != p_source) {
1419 ret = clk_set_parent(p->parent, p_source);
1421 pr_err("%s: Failed to set parent %s for %s\n",
1422 __func__, p_source->name, p->name);
1427 /* Enabling new parent scales new mode voltage rail in advanvce
1428 before the switch happens (if p_source is DFLL: open loop mode) */
1432 /* switch CPU mode */
1433 ret = tegra_cluster_control(delay, flags);
1437 pr_err("%s: Failed to switch %s mode to %s\n",
1438 __func__, c->name, p->name);
1442 /* Disabling old parent scales old mode voltage rail */
1444 clk_disable(c->parent);
1448 /* Lock DFLL now (resume closed loop VDD_CPU control) */
1449 if (p_source == dfll)
1450 tegra_clk_cfg_ex(dfll, TEGRA_CLK_DFLL_LOCK, 1);
1455 /* Re-lock DFLL if necessary after aborted switch */
1456 if (c->parent->parent->parent == dfll)
1457 tegra_clk_cfg_ex(dfll, TEGRA_CLK_DFLL_LOCK, 1);
1461 static long tegra11_cpu_cmplx_round_rate(struct clk *c,
1464 return clk_round_rate(c->parent, rate);
1467 static struct clk_ops tegra_cpu_cmplx_ops = {
1468 .init = tegra11_cpu_cmplx_clk_init,
1469 .enable = tegra11_cpu_cmplx_clk_enable,
1470 .disable = tegra11_cpu_cmplx_clk_disable,
1471 .set_rate = tegra11_cpu_cmplx_clk_set_rate,
1472 .set_parent = tegra11_cpu_cmplx_clk_set_parent,
1473 .round_rate = tegra11_cpu_cmplx_round_rate,
1476 /* virtual cop clock functions. Used to acquire the fake 'cop' clock to
1477 * reset the COP block (i.e. AVP) */
1478 static void tegra11_cop_clk_reset(struct clk *c, bool assert)
1480 unsigned long reg = assert ? RST_DEVICES_SET_L : RST_DEVICES_CLR_L;
1482 pr_debug("%s %s\n", __func__, assert ? "assert" : "deassert");
1483 clk_writel(1 << 1, reg);
1486 static struct clk_ops tegra_cop_ops = {
1487 .reset = tegra11_cop_clk_reset,
1490 /* bus clock functions */
1491 static void tegra11_bus_clk_init(struct clk *c)
1493 u32 val = clk_readl(c->reg);
1494 c->state = ((val >> c->reg_shift) & BUS_CLK_DISABLE) ? OFF : ON;
1495 c->div = ((val >> c->reg_shift) & BUS_CLK_DIV_MASK) + 1;
1499 static int tegra11_bus_clk_enable(struct clk *c)
1501 u32 val = clk_readl(c->reg);
1502 val &= ~(BUS_CLK_DISABLE << c->reg_shift);
1503 clk_writel(val, c->reg);
1507 static void tegra11_bus_clk_disable(struct clk *c)
1509 u32 val = clk_readl(c->reg);
1510 val |= BUS_CLK_DISABLE << c->reg_shift;
1511 clk_writel(val, c->reg);
1514 static int tegra11_bus_clk_set_rate(struct clk *c, unsigned long rate)
1516 u32 val = clk_readl(c->reg);
1517 unsigned long parent_rate = clk_get_rate(c->parent);
1519 for (i = 1; i <= 4; i++) {
1520 if (rate >= parent_rate / i) {
1521 val &= ~(BUS_CLK_DIV_MASK << c->reg_shift);
1522 val |= (i - 1) << c->reg_shift;
1523 clk_writel(val, c->reg);
1532 static struct clk_ops tegra_bus_ops = {
1533 .init = tegra11_bus_clk_init,
1534 .enable = tegra11_bus_clk_enable,
1535 .disable = tegra11_bus_clk_disable,
1536 .set_rate = tegra11_bus_clk_set_rate,
1539 /* Virtual system bus complex clock is used to hide the sequence of
1540 changing sclk/hclk/pclk parents and dividers to configure requested
1541 sclk target rate. */
1542 static void tegra11_sbus_cmplx_init(struct clk *c)
1546 c->max_rate = c->parent->max_rate;
1547 c->min_rate = c->parent->min_rate;
1549 /* Threshold must be an exact proper factor of low range parent,
1550 and both low/high range parents have 7.1 fractional dividers */
1551 rate = clk_get_rate(c->u.system.sclk_low->parent);
1552 if (c->u.system.threshold) {
1553 BUG_ON(c->u.system.threshold > rate) ;
1554 BUG_ON((rate % c->u.system.threshold) != 0);
1556 BUG_ON(!(c->u.system.sclk_low->flags & DIV_U71));
1557 BUG_ON(!(c->u.system.sclk_high->flags & DIV_U71));
1560 /* This special sbus round function is implemented because:
1562 * (a) sbus complex clock source is selected automatically based on rate
1564 * (b) since sbus is a shared bus, and its frequency is set to the highest
1565 * enabled shared_bus_user clock, the target rate should be rounded up divider
1566 * ladder (if max limit allows it) - for pll_div and peripheral_div common is
1567 * rounding down - special case again.
1569 * Note that final rate is trimmed (not rounded up) to avoid spiraling up in
1570 * recursive calls. Lost 1Hz is added in tegra11_sbus_cmplx_set_rate before
1571 * actually setting divider rate.
1573 static long tegra11_sbus_cmplx_round_rate(struct clk *c, unsigned long rate)
1576 unsigned long source_rate, round_rate;
1577 struct clk *new_parent;
1579 rate = max(rate, c->min_rate);
1581 new_parent = (rate <= c->u.system.threshold) ?
1582 c->u.system.sclk_low : c->u.system.sclk_high;
1583 source_rate = clk_get_rate(new_parent->parent);
1585 divider = clk_div71_get_divider(source_rate, rate,
1586 new_parent->flags, ROUND_DIVIDER_DOWN);
1593 round_rate = source_rate * 2 / (divider + 2);
1594 if (round_rate > c->max_rate) {
1595 divider += new_parent->flags & DIV_U71_INT ? 2 : 1;
1596 #if !DIVIDER_1_5_ALLOWED
1597 divider = max(2, divider);
1599 round_rate = source_rate * 2 / (divider + 2);
1602 if (new_parent == c->u.system.sclk_high) {
1603 /* Prevent oscillation across threshold */
1604 if (round_rate <= c->u.system.threshold)
1605 round_rate = c->u.system.threshold;
1610 static int tegra11_sbus_cmplx_set_rate(struct clk *c, unsigned long rate)
1613 struct clk *new_parent;
1615 /* - select the appropriate sclk parent
1616 - keep hclk at the same rate as sclk
1617 - set pclk at 1:2 rate of hclk unless pclk minimum is violated,
1618 in the latter case switch to 1:1 ratio */
1620 if (rate >= c->u.system.pclk->min_rate * 2) {
1621 ret = clk_set_div(c->u.system.pclk, 2);
1623 pr_err("Failed to set 1 : 2 pclk divider\n");
1628 new_parent = (rate <= c->u.system.threshold) ?
1629 c->u.system.sclk_low : c->u.system.sclk_high;
1631 ret = clk_set_rate(new_parent, rate + 1);
1633 pr_err("Failed to set sclk source %s to %lu\n",
1634 new_parent->name, rate);
1638 if (new_parent != clk_get_parent(c->parent)) {
1639 ret = clk_set_parent(c->parent, new_parent);
1641 pr_err("Failed to switch sclk source to %s\n",
1647 if (rate < c->u.system.pclk->min_rate * 2) {
1648 ret = clk_set_div(c->u.system.pclk, 1);
1650 pr_err("Failed to set 1 : 1 pclk divider\n");
1658 static int tegra11_clk_sbus_update(struct clk *bus)
1660 unsigned long rate, old_rate;
1662 if (detach_shared_bus)
1665 rate = tegra11_clk_shared_bus_update(bus, NULL, NULL);
1666 rate = clk_round_rate_locked(bus, rate);
1668 old_rate = clk_get_rate_locked(bus);
1669 if (rate == old_rate)
1672 return clk_set_rate_locked(bus, rate);
1675 static struct clk_ops tegra_sbus_cmplx_ops = {
1676 .init = tegra11_sbus_cmplx_init,
1677 .set_rate = tegra11_sbus_cmplx_set_rate,
1678 .round_rate = tegra11_sbus_cmplx_round_rate,
1679 .shared_bus_update = tegra11_clk_sbus_update,
1682 /* Blink output functions */
1684 static void tegra11_blink_clk_init(struct clk *c)
1688 val = pmc_readl(PMC_CTRL);
1689 c->state = (val & PMC_CTRL_BLINK_ENB) ? ON : OFF;
1691 val = pmc_readl(c->reg);
1693 if (val & PMC_BLINK_TIMER_ENB) {
1694 unsigned int on_off;
1696 on_off = (val >> PMC_BLINK_TIMER_DATA_ON_SHIFT) &
1697 PMC_BLINK_TIMER_DATA_ON_MASK;
1698 val >>= PMC_BLINK_TIMER_DATA_OFF_SHIFT;
1699 val &= PMC_BLINK_TIMER_DATA_OFF_MASK;
1701 /* each tick in the blink timer is 4 32KHz clocks */
1702 c->div = on_off * 4;
1708 static int tegra11_blink_clk_enable(struct clk *c)
1712 val = pmc_readl(PMC_DPD_PADS_ORIDE);
1713 pmc_writel(val | PMC_DPD_PADS_ORIDE_BLINK_ENB, PMC_DPD_PADS_ORIDE);
1715 val = pmc_readl(PMC_CTRL);
1716 pmc_writel(val | PMC_CTRL_BLINK_ENB, PMC_CTRL);
1721 static void tegra11_blink_clk_disable(struct clk *c)
1725 val = pmc_readl(PMC_CTRL);
1726 pmc_writel(val & ~PMC_CTRL_BLINK_ENB, PMC_CTRL);
1728 val = pmc_readl(PMC_DPD_PADS_ORIDE);
1729 pmc_writel(val & ~PMC_DPD_PADS_ORIDE_BLINK_ENB, PMC_DPD_PADS_ORIDE);
1732 static int tegra11_blink_clk_set_rate(struct clk *c, unsigned long rate)
1734 unsigned long parent_rate = clk_get_rate(c->parent);
1735 if (rate >= parent_rate) {
1737 pmc_writel(0, c->reg);
1739 unsigned int on_off;
1742 on_off = DIV_ROUND_UP(parent_rate / 8, rate);
1743 c->div = on_off * 8;
1745 val = (on_off & PMC_BLINK_TIMER_DATA_ON_MASK) <<
1746 PMC_BLINK_TIMER_DATA_ON_SHIFT;
1747 on_off &= PMC_BLINK_TIMER_DATA_OFF_MASK;
1748 on_off <<= PMC_BLINK_TIMER_DATA_OFF_SHIFT;
1750 val |= PMC_BLINK_TIMER_ENB;
1751 pmc_writel(val, c->reg);
1757 static struct clk_ops tegra_blink_clk_ops = {
1758 .init = &tegra11_blink_clk_init,
1759 .enable = &tegra11_blink_clk_enable,
1760 .disable = &tegra11_blink_clk_disable,
1761 .set_rate = &tegra11_blink_clk_set_rate,
1765 static int tegra11_pll_clk_wait_for_lock(
1766 struct clk *c, u32 lock_reg, u32 lock_bits)
1768 #ifndef CONFIG_TEGRA_SIMULATION_PLATFORM
1769 #if USE_PLL_LOCK_BITS
1771 for (i = 0; i < (c->u.pll.lock_delay / PLL_PRE_LOCK_DELAY + 1); i++) {
1772 udelay(PLL_PRE_LOCK_DELAY);
1773 if ((clk_readl(lock_reg) & lock_bits) == lock_bits) {
1774 udelay(PLL_POST_LOCK_DELAY);
1778 pr_err("Timed out waiting for lock bit on pll %s\n", c->name);
1781 udelay(c->u.pll.lock_delay);
1786 static void usb_plls_hw_control_enable(u32 reg)
1788 u32 val = clk_readl(reg);
1789 val |= USB_PLLS_USE_LOCKDET | USB_PLLS_SEQ_START_STATE;
1790 val &= ~USB_PLLS_ENABLE_SWCTL;
1791 val |= USB_PLLS_SEQ_START_STATE;
1792 pll_writel_delay(val, reg);
1794 val |= USB_PLLS_SEQ_ENABLE;
1795 pll_writel_delay(val, reg);
1798 static void tegra11_utmi_param_configure(struct clk *c)
1802 unsigned long main_rate =
1803 clk_get_rate(c->parent->parent);
1805 for (i = 0; i < ARRAY_SIZE(utmi_parameters); i++) {
1806 if (main_rate == utmi_parameters[i].osc_frequency) {
1811 if (i >= ARRAY_SIZE(utmi_parameters)) {
1812 pr_err("%s: Unexpected main rate %lu\n", __func__, main_rate);
1816 reg = clk_readl(UTMIP_PLL_CFG2);
1818 /* Program UTMIP PLL stable and active counts */
1819 /* [FIXME] arclk_rst.h says WRONG! This should be 1ms -> 0x50 Check! */
1820 reg &= ~UTMIP_PLL_CFG2_STABLE_COUNT(~0);
1821 reg |= UTMIP_PLL_CFG2_STABLE_COUNT(
1822 utmi_parameters[i].stable_count);
1824 reg &= ~UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(~0);
1826 reg |= UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(
1827 utmi_parameters[i].active_delay_count);
1829 /* Remove power downs from UTMIP PLL control bits */
1830 reg |= UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERUP;
1831 reg |= UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERUP;
1832 reg |= UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERUP;
1833 reg |= UTMIP_PLL_CFG2_FORCE_PD_SAMP_D_POWERUP;
1834 reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN;
1835 reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN;
1836 reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN;
1837 reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_D_POWERDOWN;
1839 clk_writel(reg, UTMIP_PLL_CFG2);
1841 /* Program UTMIP PLL delay and oscillator frequency counts */
1842 reg = clk_readl(UTMIP_PLL_CFG1);
1843 reg &= ~UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(~0);
1845 reg |= UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(
1846 utmi_parameters[i].enable_delay_count);
1848 reg &= ~UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(~0);
1849 reg |= UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(
1850 utmi_parameters[i].xtal_freq_count);
1852 /* Remove power downs from UTMIP PLL control bits */
1853 reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN;
1854 reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN;
1855 reg &= ~UTMIP_PLL_CFG1_FORCE_PLLU_POWERUP;
1856 reg &= ~UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN;
1857 clk_writel(reg, UTMIP_PLL_CFG1);
1859 /* Setup HW control of UTMIPLL */
1860 reg = clk_readl(UTMIPLL_HW_PWRDN_CFG0);
1861 reg |= UTMIPLL_HW_PWRDN_CFG0_USE_LOCKDET;
1862 reg &= ~UTMIPLL_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL;
1863 reg |= UTMIPLL_HW_PWRDN_CFG0_SEQ_START_STATE;
1864 clk_writel(reg, UTMIPLL_HW_PWRDN_CFG0);
1866 reg = clk_readl(UTMIP_PLL_CFG1);
1867 reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERUP;
1868 reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN;
1869 clk_writel(reg, UTMIP_PLL_CFG1);
1873 /* Setup SW override of UTMIPLL assuming USB2.0
1874 ports are assigned to USB2 */
1875 reg = clk_readl(UTMIPLL_HW_PWRDN_CFG0);
1876 reg |= UTMIPLL_HW_PWRDN_CFG0_IDDQ_SWCTL;
1877 reg |= UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE;
1878 clk_writel(reg, UTMIPLL_HW_PWRDN_CFG0);
1882 /* Enable HW control UTMIPLL */
1883 reg = clk_readl(UTMIPLL_HW_PWRDN_CFG0);
1884 reg |= UTMIPLL_HW_PWRDN_CFG0_SEQ_ENABLE;
1885 clk_writel(reg, UTMIPLL_HW_PWRDN_CFG0);
1888 static void tegra11_pll_clk_init(struct clk *c)
1890 u32 val = clk_readl(c->reg + PLL_BASE);
1892 c->state = (val & PLL_BASE_ENABLE) ? ON : OFF;
1894 if (c->flags & PLL_FIXED && !(val & PLL_BASE_OVERRIDE)) {
1895 const struct clk_pll_freq_table *sel;
1896 unsigned long input_rate = clk_get_rate(c->parent);
1897 c->u.pll.fixed_rate = PLLP_DEFAULT_FIXED_RATE;
1899 for (sel = c->u.pll.freq_table; sel->input_rate != 0; sel++) {
1900 if (sel->input_rate == input_rate &&
1901 sel->output_rate == c->u.pll.fixed_rate) {
1903 c->div = sel->m * sel->p;
1907 pr_err("Clock %s has unknown fixed frequency\n", c->name);
1909 } else if (val & PLL_BASE_BYPASS) {
1913 c->mul = (val & PLL_BASE_DIVN_MASK) >> PLL_BASE_DIVN_SHIFT;
1914 c->div = (val & PLL_BASE_DIVM_MASK) >> PLL_BASE_DIVM_SHIFT;
1915 if (c->flags & PLLU)
1916 c->div *= (val & PLLU_BASE_POST_DIV) ? 1 : 2;
1918 c->div *= (0x1 << ((val & PLL_BASE_DIVP_MASK) >>
1919 PLL_BASE_DIVP_SHIFT));
1922 if (c->flags & PLL_FIXED) {
1923 c->u.pll.fixed_rate = clk_get_rate_locked(c);
1926 if (c->flags & PLLU) {
1927 /* Configure UTMI PLL power management */
1928 tegra11_utmi_param_configure(c);
1930 /* Put PLLU under h/w control */
1931 usb_plls_hw_control_enable(PLLU_HW_PWRDN_CFG0);
1933 val = clk_readl(c->reg + PLL_BASE);
1934 val &= ~PLLU_BASE_OVERRIDE;
1935 clk_writel(val, c->reg + PLL_BASE);
1937 /* Set XUSB PLL pad pwr override and iddq */
1938 val = xusb_padctl_readl(XUSB_PADCTL_IOPHY_PLL0_CTL1);
1939 val |= XUSB_PADCTL_IOPHY_PLL0_CTL1_PLL_PWR_OVRD;
1940 val |= XUSB_PADCTL_IOPHY_PLL0_CTL1_PLL_IDDQ;
1941 xusb_padctl_writel(val, XUSB_PADCTL_IOPHY_PLL0_CTL1);
1945 static int tegra11_pll_clk_enable(struct clk *c)
1948 pr_debug("%s on clock %s\n", __func__, c->name);
1950 #if USE_PLL_LOCK_BITS
1951 /* toggle lock enable bit to reset lock detection circuit (couple
1952 register reads provide enough duration for reset pulse) */
1953 val = clk_readl(c->reg + PLL_MISC(c));
1954 val &= ~PLL_MISC_LOCK_ENABLE(c);
1955 clk_writel(val, c->reg + PLL_MISC(c));
1956 val = clk_readl(c->reg + PLL_MISC(c));
1957 val = clk_readl(c->reg + PLL_MISC(c));
1958 val |= PLL_MISC_LOCK_ENABLE(c);
1959 clk_writel(val, c->reg + PLL_MISC(c));
1961 val = clk_readl(c->reg + PLL_BASE);
1962 val &= ~PLL_BASE_BYPASS;
1963 val |= PLL_BASE_ENABLE;
1964 clk_writel(val, c->reg + PLL_BASE);
1966 tegra11_pll_clk_wait_for_lock(c, c->reg + PLL_BASE, PLL_BASE_LOCK);
1971 static void tegra11_pll_clk_disable(struct clk *c)
1974 pr_debug("%s on clock %s\n", __func__, c->name);
1976 val = clk_readl(c->reg);
1977 val &= ~(PLL_BASE_BYPASS | PLL_BASE_ENABLE);
1978 clk_writel(val, c->reg);
1981 static u8 get_pll_cpcon(struct clk *c, u16 n)
1983 if (c->flags & PLLD) {
1993 return c->u.pll.cpcon_default ? : OUT_OF_TABLE_CPCON;
1996 static int tegra11_pll_clk_set_rate(struct clk *c, unsigned long rate)
1998 u32 val, p_div, old_base;
1999 unsigned long input_rate;
2000 const struct clk_pll_freq_table *sel;
2001 struct clk_pll_freq_table cfg;
2003 pr_debug("%s: %s %lu\n", __func__, c->name, rate);
2005 if (c->flags & PLL_FIXED) {
2007 if (rate != c->u.pll.fixed_rate) {
2008 pr_err("%s: Can not change %s fixed rate %lu to %lu\n",
2009 __func__, c->name, c->u.pll.fixed_rate, rate);
2016 input_rate = clk_get_rate(c->parent);
2018 /* Check if the target rate is tabulated */
2019 for (sel = c->u.pll.freq_table; sel->input_rate != 0; sel++) {
2020 if (sel->input_rate == input_rate && sel->output_rate == rate) {
2021 if (c->flags & PLLU) {
2022 BUG_ON(sel->p < 1 || sel->p > 2);
2024 p_div = PLLU_BASE_POST_DIV;
2027 for (val = sel->p; val > 1; val >>= 1, p_div++);
2028 p_div <<= PLL_BASE_DIVP_SHIFT;
2034 /* Configure out-of-table rate */
2035 if (sel->input_rate == 0) {
2036 unsigned long cfreq, vco;
2037 BUG_ON(c->flags & PLLU);
2040 switch (input_rate) {
2043 cfreq = (rate <= 1000000 * 1000) ? 1000000 : 2000000;
2046 cfreq = (rate <= 1000000 * 1000) ? 1000000 : 2600000;
2050 cfreq = (rate <= 1200000 * 1000) ? 1200000 : 2400000;
2053 if (c->parent->flags & DIV_U71_FIXED) {
2054 /* PLLP_OUT1 rate is not in PLLA table */
2055 pr_warn("%s: failed %s ref/out rates %lu/%lu\n",
2056 __func__, c->name, input_rate, rate);
2057 cfreq = input_rate/(input_rate/1000000);
2060 pr_err("%s: Unexpected reference rate %lu\n",
2061 __func__, input_rate);
2065 /* Raise VCO to guarantee 0.5% accuracy, and vco min boundary */
2066 vco = max(200 * cfreq, c->u.pll.vco_min);
2067 for (cfg.output_rate = rate; cfg.output_rate < vco; p_div++)
2068 cfg.output_rate <<= 1;
2070 cfg.p = 0x1 << p_div;
2071 cfg.m = input_rate / cfreq;
2072 cfg.n = cfg.output_rate / cfreq;
2073 cfg.cpcon = get_pll_cpcon(c, cfg.n);
2075 if ((cfg.m > (PLL_BASE_DIVM_MASK >> PLL_BASE_DIVM_SHIFT)) ||
2076 (cfg.n > (PLL_BASE_DIVN_MASK >> PLL_BASE_DIVN_SHIFT)) ||
2077 (p_div > (PLL_BASE_DIVP_MASK >> PLL_BASE_DIVP_SHIFT)) ||
2078 (cfg.output_rate > c->u.pll.vco_max)) {
2079 pr_err("%s: Failed to set %s out-of-table rate %lu\n",
2080 __func__, c->name, rate);
2083 p_div <<= PLL_BASE_DIVP_SHIFT;
2087 c->div = sel->m * sel->p;
2089 old_base = val = clk_readl(c->reg + PLL_BASE);
2090 val &= ~(PLL_BASE_DIVM_MASK | PLL_BASE_DIVN_MASK |
2091 ((c->flags & PLLU) ? PLLU_BASE_POST_DIV : PLL_BASE_DIVP_MASK));
2092 val |= (sel->m << PLL_BASE_DIVM_SHIFT) |
2093 (sel->n << PLL_BASE_DIVN_SHIFT) | p_div;
2094 if (val == old_base)
2097 if (c->state == ON) {
2098 tegra11_pll_clk_disable(c);
2099 val &= ~(PLL_BASE_BYPASS | PLL_BASE_ENABLE);
2101 clk_writel(val, c->reg + PLL_BASE);
2103 if (c->flags & PLL_HAS_CPCON) {
2104 val = clk_readl(c->reg + PLL_MISC(c));
2105 val &= ~PLL_MISC_CPCON_MASK;
2106 val |= sel->cpcon << PLL_MISC_CPCON_SHIFT;
2107 if (c->flags & (PLLU | PLLD)) {
2108 val &= ~PLL_MISC_LFCON_MASK;
2109 val |= PLLDU_LFCON << PLL_MISC_LFCON_SHIFT;
2111 clk_writel(val, c->reg + PLL_MISC(c));
2115 tegra11_pll_clk_enable(c);
2120 static struct clk_ops tegra_pll_ops = {
2121 .init = tegra11_pll_clk_init,
2122 .enable = tegra11_pll_clk_enable,
2123 .disable = tegra11_pll_clk_disable,
2124 .set_rate = tegra11_pll_clk_set_rate,
2127 static void tegra11_pllp_clk_init(struct clk *c)
2129 tegra11_pll_clk_init(c);
2130 tegra11_pllp_init_dependencies(c->u.pll.fixed_rate);
2133 #ifdef CONFIG_PM_SLEEP
2134 static void tegra11_pllp_clk_resume(struct clk *c)
2136 unsigned long rate = c->u.pll.fixed_rate;
2137 tegra11_pll_clk_init(c);
2138 BUG_ON(rate != c->u.pll.fixed_rate);
2142 static struct clk_ops tegra_pllp_ops = {
2143 .init = tegra11_pllp_clk_init,
2144 .enable = tegra11_pll_clk_enable,
2145 .disable = tegra11_pll_clk_disable,
2146 .set_rate = tegra11_pll_clk_set_rate,
2150 tegra11_plld_clk_cfg_ex(struct clk *c, enum tegra_clk_ex_param p, u32 setting)
2155 case TEGRA_CLK_PLLD_CSI_OUT_ENB:
2156 mask = PLLD_BASE_CSI_CLKENABLE | PLLD_BASE_CSI_CLKSOURCE;
2157 reg = c->reg + PLL_BASE;
2159 case TEGRA_CLK_PLLD_DSI_OUT_ENB:
2160 mask = PLLD_MISC_DSI_CLKENABLE;
2161 reg = c->reg + PLL_MISC(c);
2163 case TEGRA_CLK_PLLD_MIPI_MUX_SEL:
2164 mask = PLLD_BASE_DSI_MUX_MASK;
2165 reg = c->reg + PLL_BASE;
2171 val = clk_readl(reg);
2176 clk_writel(val, reg);
2180 static struct clk_ops tegra_plld_ops = {
2181 .init = tegra11_pll_clk_init,
2182 .enable = tegra11_pll_clk_enable,
2183 .disable = tegra11_pll_clk_disable,
2184 .set_rate = tegra11_pll_clk_set_rate,
2185 .clk_cfg_ex = tegra11_plld_clk_cfg_ex,
2189 * Dynamic ramp PLLs:
2190 * PLLC2 and PLLC3 (PLLCX)
2191 * PLLX and PLLC (PLLXC)
2193 * When scaling PLLC and PLLX, dynamic ramp is allowed for any transition that
2194 * changes NDIV only. As a matter of policy we will make sure that switching
2195 * between output rates above VCO minimum is always dynamic. The pre-requisite
2196 * for the above guarantee is the following configuration convention:
2197 * - pll configured with fixed MDIV
2198 * - when output rate is above VCO minimum PDIV = 0 (p-value = 1)
2199 * Switching between output rates below VCO minimum may or may not be dynamic,
2200 * and switching across VCO minimum is never dynamic.
2202 * PLLC2 and PLLC3 in addition to dynamic ramp mechanism have also glitchless
2203 * output dividers. However dynamic ramp without overshoot is guaranteed only
2204 * when output divisor is less or equal 8.
2206 * Of course, dynamic ramp is applied provided PLL is already enabled.
2210 * Common configuration policy for dynamic ramp PLLs:
2211 * - always set fixed M-value based on the reference rate
2212 * - always set P-value value 1:1 for output rates above VCO minimum, and
2213 * choose minimum necessary P-value for output rates below VCO minimum
2214 * - calculate N-value based on selected M and P
2216 static int pll_dyn_ramp_cfg(struct clk *c, struct clk_pll_freq_table *cfg,
2217 unsigned long rate, unsigned long input_rate, u32 *pdiv)
2224 p = DIV_ROUND_UP(c->u.pll.vco_min, rate);
2225 p = c->u.pll.round_p_to_pdiv(p, pdiv);
2226 if (IS_ERR_VALUE(p))
2229 cfg->m = PLL_FIXED_MDIV(c, input_rate);
2231 cfg->output_rate = rate * cfg->p;
2232 cfg->n = cfg->output_rate * cfg->m / input_rate;
2234 /* can use PLLCX N-divider field layout for all dynamic ramp PLLs */
2235 if ((cfg->n > (PLLCX_BASE_DIVN_MASK >> PLL_BASE_DIVN_SHIFT)) ||
2236 (cfg->output_rate > c->u.pll.vco_max))
2242 static int pll_dyn_ramp_find_cfg(struct clk *c, struct clk_pll_freq_table *cfg,
2243 unsigned long rate, unsigned long input_rate, u32 *pdiv)
2245 const struct clk_pll_freq_table *sel;
2247 /* Check if the target rate is tabulated */
2248 for (sel = c->u.pll.freq_table; sel->input_rate != 0; sel++) {
2249 if (sel->input_rate == input_rate && sel->output_rate == rate) {
2250 u32 p = c->u.pll.round_p_to_pdiv(sel->p, pdiv);
2251 BUG_ON(IS_ERR_VALUE(p));
2252 BUG_ON(sel->m != PLL_FIXED_MDIV(c, input_rate));
2258 /* Configure out-of-table rate */
2259 if (pll_dyn_ramp_cfg(c, cfg, rate, input_rate, pdiv)) {
2260 pr_err("%s: Failed to set %s out-of-table rate %lu\n",
2261 __func__, c->name, rate);
2267 static inline void pll_do_iddq(struct clk *c, u32 offs, u32 iddq_bit, bool set)
2269 u32 val = clk_readl(c->reg + offs);
2274 clk_writel_delay(val, c->reg + offs);
2278 static u8 pllcx_p[PLLCX_PDIV_MAX + 1] = {
2279 /* PDIV: 0, 1, 2, 3, 4, 5, 6, 7 */
2280 /* p: */ 1, 2, 3, 4, 6, 8, 12, 16 };
2282 static u32 pllcx_round_p_to_pdiv(u32 p, u32 *pdiv)
2287 for (i = 0; i <= PLLCX_PDIV_MAX; i++) {
2288 /* Do not use DIV3 p values - mapped to even PDIV */
2289 if (i && ((i & 0x1) == 0))
2292 if (p <= pllcx_p[i]) {
2302 static void pllcx_update_dynamic_koef(struct clk *c, unsigned long input_rate,
2305 u32 val, n_threshold;
2307 switch (input_rate) {
2322 pr_err("%s: Unexpected reference rate %lu\n",
2323 __func__, input_rate);
2328 val = clk_readl(c->reg + PLL_MISC(c));
2329 val &= ~(PLLCX_MISC_SDM_DIV_MASK | PLLCX_MISC_FILT_DIV_MASK);
2330 val |= n <= n_threshold ?
2331 PLLCX_MISC_DIV_LOW_RANGE : PLLCX_MISC_DIV_HIGH_RANGE;
2332 clk_writel(val, c->reg + PLL_MISC(c));
2335 static void pllcx_strobe(struct clk *c)
2337 u32 reg = c->reg + PLL_MISC(c);
2338 u32 val = clk_readl(reg);
2340 val |= PLLCX_MISC_STROBE;
2341 pll_writel_delay(val, reg);
2343 val &= ~PLLCX_MISC_STROBE;
2344 clk_writel(val, reg);
2347 static void pllcx_set_defaults(struct clk *c, unsigned long input_rate, u32 n)
2349 clk_writel(PLLCX_MISC_DEFAULT_VALUE, c->reg + PLL_MISC(c));
2350 clk_writel(PLLCX_MISC1_DEFAULT_VALUE, c->reg + PLL_MISCN(c, 1));
2351 clk_writel(PLLCX_MISC2_DEFAULT_VALUE, c->reg + PLL_MISCN(c, 2));
2352 clk_writel(PLLCX_MISC3_DEFAULT_VALUE, c->reg + PLL_MISCN(c, 3));
2354 pllcx_update_dynamic_koef(c, input_rate, n);
2357 static void tegra11_pllcx_clk_init(struct clk *c)
2359 unsigned long input_rate = clk_get_rate(c->parent);
2362 /* clip vco_min to exact multiple of input rate to avoid crossover
2365 DIV_ROUND_UP(c->u.pll.vco_min, input_rate) * input_rate;
2366 c->min_rate = DIV_ROUND_UP(c->u.pll.vco_min, pllcx_p[PLLCX_PDIV_MAX]);
2368 val = clk_readl(c->reg + PLL_BASE);
2369 c->state = (val & PLL_BASE_ENABLE) ? ON : OFF;
2372 * PLLCX is not a boot PLL, it should be left disabled by boot-loader,
2373 * and no enabled module clocks should use it as a source during clock
2376 #ifndef CONFIG_TEGRA_SIMULATION_PLATFORM
2377 BUG_ON(c->state == ON);
2380 * Most of PLLCX register fields are shadowed, and can not be read
2381 * directly from PLL h/w. Hence, actual PLLCX boot state is unknown.
2382 * Initialize PLL to default state: disabled, reset; shadow registers
2383 * loaded with default parameters; dividers are preset for half of
2384 * minimum VCO rate (the latter assured that shadowed divider settings
2385 * are within supported range).
2387 m = PLL_FIXED_MDIV(c, input_rate);
2388 n = m * c->u.pll.vco_min / input_rate;
2390 val = (m << PLL_BASE_DIVM_SHIFT) | (n << PLL_BASE_DIVN_SHIFT) |
2391 (1 << PLL_BASE_DIVP_SHIFT);
2392 clk_writel(val, c->reg + PLL_BASE); /* PLL disabled */
2394 pllcx_set_defaults(c, input_rate, n);
2400 static int tegra11_pllcx_clk_enable(struct clk *c)
2403 pr_debug("%s on clock %s\n", __func__, c->name);
2405 val = clk_readl(c->reg + PLL_BASE);
2406 val &= ~PLL_BASE_BYPASS;
2407 val |= PLL_BASE_ENABLE;
2408 pll_writel_delay(val, c->reg + PLL_BASE);
2410 val = clk_readl(c->reg + PLL_MISC(c));
2411 val &= ~PLLCX_MISC_RESET;
2412 pll_writel_delay(val, c->reg + PLL_MISC(c));
2415 tegra11_pll_clk_wait_for_lock(c, c->reg + PLL_BASE,
2416 PLL_BASE_LOCK | PLLCX_BASE_PHASE_LOCK);
2420 static void tegra11_pllcx_clk_disable(struct clk *c)
2423 pr_debug("%s on clock %s\n", __func__, c->name);
2425 val = clk_readl(c->reg);
2426 val &= ~(PLL_BASE_BYPASS | PLL_BASE_ENABLE);
2427 clk_writel(val, c->reg);
2429 val = clk_readl(c->reg + PLL_MISC(c));
2430 val |= PLLCX_MISC_RESET;
2431 pll_writel_delay(val, c->reg + PLL_MISC(c));
2434 static int tegra11_pllcx_clk_set_rate(struct clk *c, unsigned long rate)
2437 unsigned long input_rate;
2438 struct clk_pll_freq_table cfg, old_cfg;
2439 const struct clk_pll_freq_table *sel = &cfg;
2441 pr_debug("%s: %s %lu\n", __func__, c->name, rate);
2443 input_rate = clk_get_rate(c->parent);
2445 if (pll_dyn_ramp_find_cfg(c, &cfg, rate, input_rate, &pdiv))
2449 c->div = sel->m * sel->p;
2451 val = clk_readl(c->reg + PLL_BASE);
2452 PLL_BASE_PARSE(PLLCX, old_cfg, val);
2453 old_cfg.p = pllcx_p[old_cfg.p];
2455 BUG_ON(old_cfg.m != sel->m);
2456 if ((sel->n == old_cfg.n) && (sel->p == old_cfg.p))
2459 #if PLLCX_USE_DYN_RAMP
2460 if (c->state == ON && ((sel->n == old_cfg.n) ||
2461 PLLCX_IS_DYN(sel->p, old_cfg.p))) {
2463 * Dynamic ramp if PLL is enabled, and M divider is unchanged:
2464 * - Change P divider 1st if intermediate rate is below either
2466 * - Change N divider with DFS strobe - target rate is either
2467 * final new rate or below old rate
2468 * - If divider has been changed, exit without waiting for lock.
2469 * Otherwise, wait for lock and change divider.
2471 if (sel->p > old_cfg.p) {
2472 val &= ~PLLCX_BASE_DIVP_MASK;
2473 val |= pdiv << PLL_BASE_DIVP_SHIFT;
2474 clk_writel(val, c->reg + PLL_BASE);
2477 if (sel->n != old_cfg.n) {
2478 pllcx_update_dynamic_koef(c, input_rate, sel->n);
2479 val &= ~PLLCX_BASE_DIVN_MASK;
2480 val |= sel->n << PLL_BASE_DIVN_SHIFT;
2481 pll_writel_delay(val, c->reg + PLL_BASE);
2484 tegra11_pll_clk_wait_for_lock(c, c->reg + PLL_BASE,
2485 PLL_BASE_LOCK | PLLCX_BASE_PHASE_LOCK);
2488 if (sel->p < old_cfg.p) {
2489 val &= ~PLLCX_BASE_DIVP_MASK;
2490 val |= pdiv << PLL_BASE_DIVP_SHIFT;
2491 clk_writel(val, c->reg + PLL_BASE);
2497 val &= ~(PLLCX_BASE_DIVN_MASK | PLLCX_BASE_DIVP_MASK);
2498 val |= (sel->n << PLL_BASE_DIVN_SHIFT) |
2499 (pdiv << PLL_BASE_DIVP_SHIFT);
2501 if (c->state == ON) {
2502 tegra11_pllcx_clk_disable(c);
2503 val &= ~(PLL_BASE_BYPASS | PLL_BASE_ENABLE);
2505 pllcx_update_dynamic_koef(c, input_rate, sel->n);
2506 clk_writel(val, c->reg + PLL_BASE);
2508 tegra11_pllcx_clk_enable(c);
2513 #ifdef CONFIG_PM_SLEEP
2514 static void tegra11_pllcx_clk_resume_enable(struct clk *c)
2516 unsigned long rate = clk_get_rate_all_locked(c->parent);
2517 u32 val = clk_readl(c->reg + PLL_BASE);
2518 enum clk_state state = c->state;
2520 if (val & PLL_BASE_ENABLE)
2521 return; /* already resumed */
2523 /* Restore input divider */
2524 val &= ~PLLCX_BASE_DIVM_MASK;
2525 val |= PLL_FIXED_MDIV(c, rate) << PLL_BASE_DIVM_SHIFT;
2526 clk_writel(val, c->reg + PLL_BASE);
2528 /* temporarily sync h/w and s/w states, final sync happens
2529 in tegra_clk_resume later */
2531 pllcx_set_defaults(c, rate, c->mul);
2533 rate = clk_get_rate_all_locked(c) + 1;
2534 tegra11_pllcx_clk_set_rate(c, rate);
2535 tegra11_pllcx_clk_enable(c);
2540 static struct clk_ops tegra_pllcx_ops = {
2541 .init = tegra11_pllcx_clk_init,
2542 .enable = tegra11_pllcx_clk_enable,
2543 .disable = tegra11_pllcx_clk_disable,
2544 .set_rate = tegra11_pllcx_clk_set_rate,
2548 /* non-monotonic mapping below is not a typo */
2549 static u8 pllxc_p[PLLXC_PDIV_MAX + 1] = {
2550 /* PDIV: 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 */
2551 /* p: */ 1, 2, 3, 4, 5, 6, 8, 10, 12, 16, 12, 16, 20, 24, 32 };
2553 static u32 pllxc_round_p_to_pdiv(u32 p, u32 *pdiv)
2555 if (!p || (p > PLLXC_SW_PDIV_MAX + 1))
2563 static void pllxc_get_dyn_steps(struct clk *c, unsigned long input_rate,
2564 u32 *step_a, u32 *step_b)
2566 switch (input_rate) {
2582 pr_err("%s: Unexpected reference rate %lu\n",
2583 __func__, input_rate);
2588 static void pllx_set_defaults(struct clk *c, unsigned long input_rate)
2593 /* Only s/w dyn ramp control is supported */
2594 val = clk_readl(PLLX_HW_CTRL_CFG);
2595 #ifndef CONFIG_TEGRA_SIMULATION_PLATFORM
2596 BUG_ON(!(val & PLLX_HW_CTRL_CFG_SWCTRL));
2599 pllxc_get_dyn_steps(c, input_rate, &step_a, &step_b);
2600 val = step_a << PLLX_MISC2_DYNRAMP_STEPA_SHIFT;
2601 val |= step_b << PLLX_MISC2_DYNRAMP_STEPB_SHIFT;
2603 /* Get ready dyn ramp state machine, disable lock override */
2604 clk_writel(val, c->reg + PLL_MISCN(c, 2));
2606 /* Enable outputs to CPUs and configure lock */
2608 #if USE_PLL_LOCK_BITS
2609 val |= PLL_MISC_LOCK_ENABLE(c);
2611 clk_writel(val, c->reg + PLL_MISC(c));
2613 /* Check/set IDDQ */
2614 val = clk_readl(c->reg + PLL_MISCN(c, 3));
2615 if (c->state == ON) {
2616 #ifndef CONFIG_TEGRA_SIMULATION_PLATFORM
2617 BUG_ON(val & PLLX_MISC3_IDDQ);
2620 val |= PLLX_MISC3_IDDQ;
2621 clk_writel(val, c->reg + PLL_MISCN(c, 3));
2625 static void pllc_set_defaults(struct clk *c, unsigned long input_rate)
2630 /* Get ready dyn ramp state machine */
2631 pllxc_get_dyn_steps(c, input_rate, &step_a, &step_b);
2632 val = step_a << PLLC_MISC1_DYNRAMP_STEPA_SHIFT;
2633 val |= step_b << PLLC_MISC1_DYNRAMP_STEPB_SHIFT;
2634 clk_writel(val, c->reg + PLL_MISCN(c, 1));
2636 /* Configure lock and check/set IDDQ */
2637 val = clk_readl(c->reg + PLL_BASE);
2638 val &= ~PLLC_BASE_LOCK_OVERRIDE;
2639 clk_writel(val, c->reg + PLL_BASE);
2641 val = clk_readl(c->reg + PLL_MISC(c));
2642 #if USE_PLL_LOCK_BITS
2643 val |= PLLC_MISC_LOCK_ENABLE;
2645 val &= ~PLLC_MISC_LOCK_ENABLE;
2647 clk_writel(val, c->reg + PLL_MISC(c));
2649 if (c->state == ON) {
2650 #ifndef CONFIG_TEGRA_SIMULATION_PLATFORM
2651 BUG_ON(val & PLLC_MISC_IDDQ);
2654 val |= PLLC_MISC_IDDQ;
2655 clk_writel(val, c->reg + PLL_MISC(c));
2659 static void tegra11_pllxc_clk_init(struct clk *c)
2661 unsigned long input_rate = clk_get_rate(c->parent);
2664 /* clip vco_min to exact multiple of input rate to avoid crossover
2667 DIV_ROUND_UP(c->u.pll.vco_min, input_rate) * input_rate;
2669 DIV_ROUND_UP(c->u.pll.vco_min, pllxc_p[PLLXC_SW_PDIV_MAX]);
2671 val = clk_readl(c->reg + PLL_BASE);
2672 c->state = (val & PLL_BASE_ENABLE) ? ON : OFF;
2674 m = (val & PLLXC_BASE_DIVM_MASK) >> PLL_BASE_DIVM_SHIFT;
2675 p = (val & PLLXC_BASE_DIVP_MASK) >> PLL_BASE_DIVP_SHIFT;
2676 BUG_ON(p > PLLXC_PDIV_MAX);
2680 c->mul = (val & PLLXC_BASE_DIVN_MASK) >> PLL_BASE_DIVN_SHIFT;
2682 if (c->flags & PLLX)
2683 pllx_set_defaults(c, input_rate);
2685 pllc_set_defaults(c, input_rate);
2688 static int tegra11_pllxc_clk_enable(struct clk *c)
2691 pr_debug("%s on clock %s\n", __func__, c->name);
2693 if (c->flags & PLLX)
2694 pll_do_iddq(c, PLL_MISCN(c, 3), PLLX_MISC3_IDDQ, false);
2696 pll_do_iddq(c, PLL_MISC(c), PLLC_MISC_IDDQ, false);
2698 val = clk_readl(c->reg + PLL_BASE);
2699 val |= PLL_BASE_ENABLE;
2700 clk_writel(val, c->reg + PLL_BASE);
2702 tegra11_pll_clk_wait_for_lock(c, c->reg + PLL_BASE, PLL_BASE_LOCK);
2707 static void tegra11_pllxc_clk_disable(struct clk *c)
2710 pr_debug("%s on clock %s\n", __func__, c->name);
2712 val = clk_readl(c->reg + PLL_BASE);
2713 val &= ~PLL_BASE_ENABLE;
2714 clk_writel(val, c->reg + PLL_BASE);
2716 if (c->flags & PLLX)
2717 pll_do_iddq(c, PLL_MISCN(c, 3), PLLX_MISC3_IDDQ, true);
2719 pll_do_iddq(c, PLL_MISC(c), PLLC_MISC_IDDQ, true);
2723 #define PLLXC_DYN_RAMP(pll_misc, reg) \
2725 u32 misc = clk_readl((reg)); \
2727 misc &= ~pll_misc##_NDIV_NEW_MASK; \
2728 misc |= sel->n << pll_misc##_NDIV_NEW_SHIFT; \
2729 pll_writel_delay(misc, (reg)); \
2731 misc |= pll_misc##_EN_DYNRAMP; \
2732 clk_writel(misc, (reg)); \
2733 tegra11_pll_clk_wait_for_lock(c, (reg), \
2734 pll_misc##_DYNRAMP_DONE); \
2736 val &= ~PLLXC_BASE_DIVN_MASK; \
2737 val |= sel->n << PLL_BASE_DIVN_SHIFT; \
2738 pll_writel_delay(val, c->reg + PLL_BASE); \
2740 misc &= ~pll_misc##_EN_DYNRAMP; \
2741 pll_writel_delay(misc, (reg)); \
2744 static int tegra11_pllxc_clk_set_rate(struct clk *c, unsigned long rate)
2747 unsigned long input_rate;
2748 struct clk_pll_freq_table cfg, old_cfg;
2749 const struct clk_pll_freq_table *sel = &cfg;
2751 pr_debug("%s: %s %lu\n", __func__, c->name, rate);
2753 input_rate = clk_get_rate(c->parent);
2755 if (pll_dyn_ramp_find_cfg(c, &cfg, rate, input_rate, &pdiv))
2759 c->div = sel->m * sel->p;
2761 val = clk_readl(c->reg + PLL_BASE);
2762 PLL_BASE_PARSE(PLLXC, old_cfg, val);
2763 old_cfg.p = pllxc_p[old_cfg.p];
2765 if ((sel->m == old_cfg.m) && (sel->n == old_cfg.n) &&
2766 (sel->p == old_cfg.p))
2769 #if PLLXC_USE_DYN_RAMP
2771 * Dynamic ramp can be used if M, P dividers are unchanged
2772 * (coveres superset of conventional dynamic ramps)
2774 if ((c->state == ON) && (sel->m == old_cfg.m) &&
2775 (sel->p == old_cfg.p)) {
2777 if (c->flags & PLLX) {
2778 u32 reg = c->reg + PLL_MISCN(c, 2);
2779 PLLXC_DYN_RAMP(PLLX_MISC2, reg);
2781 u32 reg = c->reg + PLL_MISCN(c, 1);
2782 PLLXC_DYN_RAMP(PLLC_MISC1, reg);
2788 if (c->state == ON) {
2789 /* Use "ENABLE" pulse without placing PLL into IDDQ */
2790 val &= ~PLL_BASE_ENABLE;
2791 pll_writel_delay(val, c->reg + PLL_BASE);
2794 val &= ~(PLLXC_BASE_DIVM_MASK |
2795 PLLXC_BASE_DIVN_MASK | PLLXC_BASE_DIVP_MASK);
2796 val |= (sel->m << PLL_BASE_DIVM_SHIFT) |
2797 (sel->n << PLL_BASE_DIVN_SHIFT) | (pdiv << PLL_BASE_DIVP_SHIFT);
2798 clk_writel(val, c->reg + PLL_BASE);
2800 if (c->state == ON) {
2801 val |= PLL_BASE_ENABLE;
2802 clk_writel(val, c->reg + PLL_BASE);
2803 tegra11_pll_clk_wait_for_lock(c, c->reg + PLL_BASE,
2809 #ifdef CONFIG_PM_SLEEP
2810 static void tegra11_pllxc_clk_resume_enable(struct clk *c)
2812 unsigned long rate = clk_get_rate_all_locked(c->parent);
2813 enum clk_state state = c->state;
2815 if (clk_readl(c->reg + PLL_BASE) & PLL_BASE_ENABLE)
2816 return; /* already resumed */
2818 /* temporarily sync h/w and s/w states, final sync happens
2819 in tegra_clk_resume later */
2821 if (c->flags & PLLX)
2822 pllx_set_defaults(c, rate);
2824 pllc_set_defaults(c, rate);
2826 rate = clk_get_rate_all_locked(c) + 1;
2827 tegra11_pllxc_clk_set_rate(c, rate);
2828 tegra11_pllxc_clk_enable(c);
2833 static struct clk_ops tegra_pllxc_ops = {
2834 .init = tegra11_pllxc_clk_init,
2835 .enable = tegra11_pllxc_clk_enable,
2836 .disable = tegra11_pllxc_clk_disable,
2837 .set_rate = tegra11_pllxc_clk_set_rate,
2841 /* FIXME: pllm suspend/resume */
2843 static u32 pllm_round_p_to_pdiv(u32 p, u32 *pdiv)
2853 static void pllm_set_defaults(struct clk *c, unsigned long input_rate)
2855 u32 val = clk_readl(c->reg + PLL_MISC(c));
2857 val &= ~PLLM_MISC_LOCK_OVERRIDE;
2858 #if USE_PLL_LOCK_BITS
2859 val &= ~PLLM_MISC_LOCK_DISABLE;
2861 val |= PLLM_MISC_LOCK_DISABLE;
2865 val |= PLLM_MISC_IDDQ;
2866 #ifndef CONFIG_TEGRA_SIMULATION_PLATFORM
2868 BUG_ON(val & PLLM_MISC_IDDQ);
2871 clk_writel(val, c->reg + PLL_MISC(c));
2874 static void tegra11_pllm_clk_init(struct clk *c)
2876 unsigned long input_rate = clk_get_rate(c->parent);
2879 /* clip vco_min to exact multiple of input rate to avoid crossover
2882 DIV_ROUND_UP(c->u.pll.vco_min, input_rate) * input_rate;
2884 DIV_ROUND_UP(c->u.pll.vco_min, 2);
2886 val = pmc_readl(PMC_PLLP_WB0_OVERRIDE);
2887 if (val & PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE) {
2888 c->state = (val & PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE) ? ON : OFF;
2889 val = pmc_readl(PMC_PLLM_WB0_OVERRIDE_2);
2890 p = (val & PMC_PLLM_WB0_OVERRIDE_2_DIVP_MASK) ? 2 : 1;
2892 val = pmc_readl(PMC_PLLM_WB0_OVERRIDE);
2894 val = clk_readl(c->reg + PLL_BASE);
2895 c->state = (val & PLL_BASE_ENABLE) ? ON : OFF;
2896 p = (val & PLLM_BASE_DIVP_MASK) ? 2 : 1;
2899 m = (val & PLLM_BASE_DIVM_MASK) >> PLL_BASE_DIVM_SHIFT;
2900 BUG_ON(m != PLL_FIXED_MDIV(c, input_rate));
2902 c->mul = (val & PLLM_BASE_DIVN_MASK) >> PLL_BASE_DIVN_SHIFT;
2904 pllm_set_defaults(c, input_rate);
2907 static int tegra11_pllm_clk_enable(struct clk *c)
2910 pr_debug("%s on clock %s\n", __func__, c->name);
2912 pll_do_iddq(c, PLL_MISC(c), PLLM_MISC_IDDQ, false);
2914 /* Just enable both base and override - one would work */
2915 val = clk_readl(c->reg + PLL_BASE);
2916 val |= PLL_BASE_ENABLE;
2917 clk_writel(val, c->reg + PLL_BASE);
2919 val = pmc_readl(PMC_PLLP_WB0_OVERRIDE);
2920 val |= PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE;
2921 pmc_writel(val, PMC_PLLP_WB0_OVERRIDE);
2922 val = pmc_readl(PMC_PLLP_WB0_OVERRIDE);
2924 tegra11_pll_clk_wait_for_lock(c, c->reg + PLL_BASE, PLL_BASE_LOCK);
2928 static void tegra11_pllm_clk_disable(struct clk *c)
2931 pr_debug("%s on clock %s\n", __func__, c->name);
2933 /* Just disable both base and override - one would work */
2934 val = pmc_readl(PMC_PLLP_WB0_OVERRIDE);
2935 val &= ~PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE;
2936 pmc_writel(val, PMC_PLLP_WB0_OVERRIDE);
2937 val = pmc_readl(PMC_PLLP_WB0_OVERRIDE);
2939 val = clk_readl(c->reg + PLL_BASE);
2940 val &= ~PLL_BASE_ENABLE;
2941 clk_writel(val, c->reg + PLL_BASE);
2943 pll_do_iddq(c, PLL_MISC(c), PLLM_MISC_IDDQ, true);
2946 static int tegra11_pllm_clk_set_rate(struct clk *c, unsigned long rate)
2949 unsigned long input_rate;
2950 struct clk_pll_freq_table cfg;
2951 const struct clk_pll_freq_table *sel = &cfg;
2953 pr_debug("%s: %s %lu\n", __func__, c->name, rate);
2955 if (c->state == ON) {
2956 if (rate != clk_get_rate_locked(c)) {
2957 pr_err("%s: Can not change memory %s rate in flight\n",
2964 input_rate = clk_get_rate(c->parent);
2966 if (pll_dyn_ramp_find_cfg(c, &cfg, rate, input_rate, &pdiv))
2970 c->div = sel->m * sel->p;
2972 val = pmc_readl(PMC_PLLP_WB0_OVERRIDE);
2973 if (val & PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE) {
2974 val = pmc_readl(PMC_PLLM_WB0_OVERRIDE_2);
2975 val = pdiv ? (val | PMC_PLLM_WB0_OVERRIDE_2_DIVP_MASK) :
2976 (val & ~PMC_PLLM_WB0_OVERRIDE_2_DIVP_MASK);
2977 pmc_writel(val, PMC_PLLM_WB0_OVERRIDE_2);
2979 val = pmc_readl(PMC_PLLM_WB0_OVERRIDE);
2980 val &= ~(PLLM_BASE_DIVM_MASK | PLLM_BASE_DIVN_MASK);
2981 val |= (sel->m << PLL_BASE_DIVM_SHIFT) |
2982 (sel->n << PLL_BASE_DIVN_SHIFT);
2983 pmc_writel(val, PMC_PLLM_WB0_OVERRIDE);
2985 val = clk_readl(c->reg + PLL_BASE);
2986 val &= ~(PLLM_BASE_DIVM_MASK | PLLM_BASE_DIVN_MASK |
2987 PLLM_BASE_DIVP_MASK);
2988 val |= (sel->m << PLL_BASE_DIVM_SHIFT) |
2989 (sel->n << PLL_BASE_DIVN_SHIFT) |
2990 (pdiv ? PLLM_BASE_DIVP_MASK : 0);
2991 clk_writel(val, c->reg + PLL_BASE);
2997 static struct clk_ops tegra_pllm_ops = {
2998 .init = tegra11_pllm_clk_init,
2999 .enable = tegra11_pllm_clk_enable,
3000 .disable = tegra11_pllm_clk_disable,
3001 .set_rate = tegra11_pllm_clk_set_rate,
3005 /* non-monotonic mapping below is not a typo */
3006 static u8 pllre_p[PLLRE_PDIV_MAX + 1] = {
3007 /* PDIV: 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 */
3008 /* p: */ 1, 2, 3, 4, 5, 6, 8, 10, 12, 16, 12, 16, 20, 24, 32 };
3010 static u32 pllre_round_p_to_pdiv(u32 p, u32 *pdiv)
3012 if (!p || (p > PLLRE_SW_PDIV_MAX + 1))
3020 static void pllre_set_defaults(struct clk *c, unsigned long input_rate)
3022 u32 val = clk_readl(c->reg + PLL_MISC(c));
3024 val &= ~PLLRE_MISC_LOCK_OVERRIDE;
3025 #if USE_PLL_LOCK_BITS
3026 val |= PLLRE_MISC_LOCK_ENABLE;
3028 val &= ~PLLRE_MISC_LOCK_ENABLE;
3032 val |= PLLRE_MISC_IDDQ;
3033 #ifndef CONFIG_TEGRA_SIMULATION_PLATFORM
3035 BUG_ON(val & PLLRE_MISC_IDDQ);
3038 clk_writel(val, c->reg + PLL_MISC(c));
3041 static void tegra11_pllre_clk_init(struct clk *c)
3043 unsigned long input_rate = clk_get_rate(c->parent);
3046 /* clip vco_min to exact multiple of input rate to avoid crossover
3049 DIV_ROUND_UP(c->u.pll.vco_min, input_rate) * input_rate;
3050 c->min_rate = c->u.pll.vco_min;
3052 val = clk_readl(c->reg + PLL_BASE);
3053 c->state = (val & PLL_BASE_ENABLE) ? ON : OFF;
3056 /* overwrite h/w por state with min setting */
3057 m = PLL_FIXED_MDIV(c, input_rate);
3058 val = (m << PLL_BASE_DIVM_SHIFT) |
3059 (c->min_rate / input_rate << PLL_BASE_DIVN_SHIFT);
3060 clk_writel(val, c->reg + PLL_BASE);
3063 m = (val & PLLRE_BASE_DIVM_MASK) >> PLL_BASE_DIVM_SHIFT;
3064 BUG_ON(m != PLL_FIXED_MDIV(c, input_rate));
3067 c->mul = (val & PLLRE_BASE_DIVN_MASK) >> PLL_BASE_DIVN_SHIFT;
3069 pllre_set_defaults(c, input_rate);
3072 static int tegra11_pllre_clk_enable(struct clk *c)
3075 pr_debug("%s on clock %s\n", __func__, c->name);
3077 pll_do_iddq(c, PLL_MISC(c), PLLRE_MISC_IDDQ, false);
3079 val = clk_readl(c->reg + PLL_BASE);
3080 val |= PLL_BASE_ENABLE;
3081 clk_writel(val, c->reg + PLL_BASE);
3083 tegra11_pll_clk_wait_for_lock(c, c->reg + PLL_MISC(c), PLLRE_MISC_LOCK);
3087 static void tegra11_pllre_clk_disable(struct clk *c)
3090 pr_debug("%s on clock %s\n", __func__, c->name);
3092 val = clk_readl(c->reg + PLL_BASE);
3093 val &= ~PLL_BASE_ENABLE;
3094 clk_writel(val, c->reg + PLL_BASE);
3096 pll_do_iddq(c, PLL_MISC(c), PLLRE_MISC_IDDQ, true);
3099 static int tegra11_pllre_clk_set_rate(struct clk *c, unsigned long rate)
3102 unsigned long input_rate;
3103 struct clk_pll_freq_table cfg;
3105 pr_debug("%s: %s %lu\n", __func__, c->name, rate);
3107 if (rate < c->min_rate) {
3108 pr_err("%s: Failed to set %s rate %lu\n",
3109 __func__, c->name, rate);
3113 input_rate = clk_get_rate(c->parent);
3114 cfg.m = PLL_FIXED_MDIV(c, input_rate);
3115 cfg.n = rate * cfg.m / input_rate;
3120 val = old_base = clk_readl(c->reg + PLL_BASE);
3121 val &= ~(PLLRE_BASE_DIVM_MASK | PLLRE_BASE_DIVN_MASK);
3122 val |= (cfg.m << PLL_BASE_DIVM_SHIFT) | (cfg.n << PLL_BASE_DIVN_SHIFT);
3123 if (val == old_base)
3126 if (c->state == ON) {
3127 /* Use "ENABLE" pulse without placing PLL into IDDQ */
3128 val &= ~PLL_BASE_ENABLE;
3129 old_base &= ~PLL_BASE_ENABLE;
3130 pll_writel_delay(old_base, c->reg + PLL_BASE);
3133 clk_writel(val, c->reg + PLL_BASE);
3135 if (c->state == ON) {
3136 val |= PLL_BASE_ENABLE;
3137 clk_writel(val, c->reg + PLL_BASE);
3138 tegra11_pll_clk_wait_for_lock(
3139 c, c->reg + PLL_MISC(c), PLLRE_MISC_LOCK);
3144 static struct clk_ops tegra_pllre_ops = {
3145 .init = tegra11_pllre_clk_init,
3146 .enable = tegra11_pllre_clk_enable,
3147 .disable = tegra11_pllre_clk_disable,
3148 .set_rate = tegra11_pllre_clk_set_rate,
3151 static void tegra11_pllre_out_clk_init(struct clk *c)
3155 val = clk_readl(c->reg);
3156 p = (val & PLLRE_BASE_DIVP_MASK) >> PLLRE_BASE_DIVP_SHIFT;
3157 BUG_ON(p > PLLRE_PDIV_MAX);
3162 c->state = c->parent->state;
3165 static int tegra11_pllre_out_clk_enable(struct clk *c)
3170 static void tegra11_pllre_out_clk_disable(struct clk *c)
3174 static int tegra11_pllre_out_clk_set_rate(struct clk *c, unsigned long rate)
3177 unsigned long input_rate, flags;
3179 pr_debug("%s: %s %lu\n", __func__, c->name, rate);
3181 clk_lock_save(c->parent, &flags);
3182 input_rate = clk_get_rate_locked(c->parent);
3184 p = DIV_ROUND_UP(input_rate, rate);
3185 p = c->parent->u.pll.round_p_to_pdiv(p, &pdiv);
3186 if (IS_ERR_VALUE(p)) {
3187 pr_err("%s: Failed to set %s rate %lu\n",
3188 __func__, c->name, rate);
3189 clk_unlock_restore(c->parent, &flags);
3194 val = clk_readl(c->reg);
3195 val &= ~PLLRE_BASE_DIVP_MASK;
3196 val |= pdiv << PLLRE_BASE_DIVP_SHIFT;
3197 clk_writel(val, c->reg);
3199 clk_unlock_restore(c->parent, &flags);
3203 static struct clk_ops tegra_pllre_out_ops = {
3204 .init = tegra11_pllre_out_clk_init,
3205 .enable = tegra11_pllre_out_clk_enable,
3206 .disable = tegra11_pllre_out_clk_disable,
3207 .set_rate = tegra11_pllre_out_clk_set_rate,
3210 #ifdef CONFIG_PM_SLEEP
3211 /* Resume both pllre_vco and pllre_out */
3212 static void tegra11_pllre_clk_resume_enable(struct clk *c)
3215 u32 val = clk_readl(c->reg + PLL_BASE);
3216 unsigned long rate = clk_get_rate_all_locked(c->parent->parent);
3217 enum clk_state state = c->parent->state;
3219 if (val & PLL_BASE_ENABLE)
3220 return; /* already resumed */
3222 /* temporarily sync h/w and s/w states, final sync happens
3223 in tegra_clk_resume later */
3224 c->parent->state = OFF;
3225 pllre_set_defaults(c->parent, rate);
3227 /* restore PLLRE VCO feedback loop (m, n) */
3228 rate = clk_get_rate_all_locked(c->parent) + 1;
3229 tegra11_pllre_clk_set_rate(c->parent, rate);
3231 /* restore PLLRE post-divider */
3232 c->parent->u.pll.round_p_to_pdiv(c->div, &pdiv);
3233 val = clk_readl(c->reg);
3234 val &= ~PLLRE_BASE_DIVP_MASK;
3235 val |= pdiv << PLLRE_BASE_DIVP_SHIFT;
3236 clk_writel(val, c->reg);
3238 tegra11_pllre_clk_enable(c->parent);
3239 c->parent->state = state;
3243 /* non-monotonic mapping below is not a typo */
3244 static u8 plle_p[PLLE_CMLDIV_MAX + 1] = {
3245 /* CMLDIV: 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 */
3246 /* p: */ 1, 2, 3, 4, 5, 6, 8, 10, 12, 16, 12, 16, 20, 24, 32 };
3248 static inline void select_pll_e_input(u32 aux_reg)
3250 #if USE_PLLE_INPUT_PLLRE
3251 aux_reg |= PLLE_AUX_PLLRE_SEL;
3253 aux_reg &= ~(PLLE_AUX_PLLRE_SEL | PLLE_AUX_PLLP_SEL);
3255 clk_writel(aux_reg, PLLE_AUX);
3258 static void tegra11_plle_clk_init(struct clk *c)
3261 struct clk *pll_ref = tegra_get_clock_by_name("pll_ref");
3262 struct clk *re_vco = tegra_get_clock_by_name("pll_re_vco");
3263 struct clk *pllp = tegra_get_clock_by_name("pllp");
3264 #if USE_PLLE_INPUT_PLLRE
3265 struct clk *ref = re_vco;
3267 struct clk *ref = pll_ref;
3271 val = clk_readl(c->reg + PLL_BASE);
3272 c->state = (val & PLL_BASE_ENABLE) ? ON : OFF;
3273 c->mul = (val & PLLE_BASE_DIVN_MASK) >> PLL_BASE_DIVN_SHIFT;
3274 c->div = (val & PLLE_BASE_DIVM_MASK) >> PLL_BASE_DIVM_SHIFT;
3275 p = (val & PLLE_BASE_DIVCML_MASK) >> PLLE_BASE_DIVCML_SHIFT;
3276 c->div *= plle_p[p];
3278 val = clk_readl(PLLE_AUX);
3279 c->parent = (val & PLLE_AUX_PLLRE_SEL) ? re_vco :
3280 (val & PLLE_AUX_PLLP_SEL) ? pllp : pll_ref;
3281 if (c->parent != ref) {
3282 if (c->state == ON) {
3283 WARN(1, "%s: pll_e is left enabled with %s input\n",
3284 __func__, c->parent->name);
3287 select_pll_e_input(val);
3292 static void tegra11_plle_clk_disable(struct clk *c)
3295 pr_debug("%s on clock %s\n", __func__, c->name);
3297 /* FIXME: do we need to restore other s/w controls ? */
3298 val = clk_readl(c->reg + PLL_BASE);
3299 val &= ~PLL_BASE_ENABLE;
3300 clk_writel(val, c->reg + PLL_BASE);
3302 val = clk_readl(c->reg + PLL_MISC(c));
3303 val |= PLLE_MISC_IDDQ_SW_CTRL | PLLE_MISC_IDDQ_SW_VALUE;
3304 pll_writel_delay(val, c->reg + PLL_MISC(c));
3307 static int tegra11_plle_clk_enable(struct clk *c)
3310 const struct clk_pll_freq_table *sel;
3311 unsigned long rate = c->u.pll.fixed_rate;
3312 unsigned long input_rate = clk_get_rate(c->parent);
3314 if (c->state == ON) {
3315 /* BL left plle enabled - don't change configuartion */
3316 pr_warn("%s: pll_e is already enabled\n", __func__);
3320 for (sel = c->u.pll.freq_table; sel->input_rate != 0; sel++) {
3321 if (sel->input_rate == input_rate && sel->output_rate == rate)
3325 if (sel->input_rate == 0) {
3326 pr_err("%s: %s input rate %lu is out-of-table\n",
3327 __func__, c->name, input_rate);
3331 /* setup locking configuration, s/w control of IDDQ and enable modes,
3332 take pll out of IDDQ via s/w control, setup VREG */
3333 val = clk_readl(c->reg + PLL_BASE);
3334 val &= ~PLLE_BASE_LOCK_OVERRIDE;
3335 clk_writel(val, c->reg + PLL_BASE);
3337 val = clk_readl(c->reg + PLL_MISC(c));
3338 val |= PLLE_MISC_LOCK_ENABLE;
3339 val |= PLLE_MISC_IDDQ_SW_CTRL;
3340 val &= ~PLLE_MISC_IDDQ_SW_VALUE;
3341 val |= PLLE_MISC_PLLE_PTS;
3342 val |= PLLE_MISC_VREG_BG_CTRL_MASK | PLLE_MISC_VREG_CTRL_MASK;
3343 clk_writel(val, c->reg + PLL_MISC(c));
3346 /* configure dividers, disable SS */
3347 val = clk_readl(PLLE_SS_CTRL);
3348 val |= PLLE_SS_DISABLE;
3349 clk_writel(val, PLLE_SS_CTRL);
3351 val = clk_readl(c->reg + PLL_BASE);
3352 val &= ~(PLLE_BASE_DIVM_MASK | PLLE_BASE_DIVN_MASK |
3353 PLLE_BASE_DIVCML_MASK);
3354 val |= (sel->m << PLL_BASE_DIVM_SHIFT) |
3355 (sel->n << PLL_BASE_DIVN_SHIFT) |
3356 (sel->cpcon << PLLE_BASE_DIVCML_SHIFT);
3357 pll_writel_delay(val, c->reg + PLL_BASE);
3359 c->div = sel->m * sel->p;
3361 /* enable and lock pll */
3362 val |= PLL_BASE_ENABLE;
3363 clk_writel(val, c->reg + PLL_BASE);
3364 tegra11_pll_clk_wait_for_lock(
3365 c, c->reg + PLL_MISC(c), PLLE_MISC_LOCK);
3367 val = clk_readl(PLLE_SS_CTRL);
3368 val &= ~PLLE_SS_COEFFICIENTS_MASK;
3369 val |= PLLE_SS_COEFFICIENTS_VAL;
3370 clk_writel(val, PLLE_SS_CTRL);
3371 val &= ~(PLLE_SS_CNTL_SSC_BYP | PLLE_SS_CNTL_BYPASS_SS);
3372 pll_writel_delay(val, PLLE_SS_CTRL);
3373 val &= ~PLLE_SS_CNTL_INTERP_RESET;
3374 pll_writel_delay(val, PLLE_SS_CTRL);
3377 /* switch pll under h/w control */
3378 val = clk_readl(c->reg + PLL_MISC(c));
3379 val &= ~PLLE_MISC_IDDQ_SW_CTRL;
3380 clk_writel(val, c->reg + PLL_MISC(c));
3382 val = clk_readl(PLLE_AUX);
3383 val |= PLLE_AUX_USE_LOCKDET | PLLE_AUX_SEQ_START_STATE;
3384 val &= ~(PLLE_AUX_ENABLE_SWCTL | PLLE_AUX_SS_SWCTL);
3385 pll_writel_delay(val, PLLE_AUX);
3386 val |= PLLE_AUX_SEQ_ENABLE;
3387 pll_writel_delay(val, PLLE_AUX);
3389 /* clear XUSB PLL pad pwr override and iddq */
3390 val = xusb_padctl_readl(XUSB_PADCTL_IOPHY_PLL0_CTL1);
3391 val &= ~XUSB_PADCTL_IOPHY_PLL0_CTL1_PLL_PWR_OVRD;
3392 val &= ~XUSB_PADCTL_IOPHY_PLL0_CTL1_PLL_IDDQ;
3393 xusb_padctl_writel(val, XUSB_PADCTL_IOPHY_PLL0_CTL1);
3395 /* enable hw control of xusb brick pll */
3396 usb_plls_hw_control_enable(XUSBIO_PLL_CFG0);
3401 #ifdef CONFIG_PM_SLEEP
3402 static void tegra11_plle_clk_resume(struct clk *c)
3404 u32 val = clk_readl(c->reg + PLL_BASE);
3405 if (val & PLL_BASE_ENABLE)
3406 return; /* already resumed */
3408 /* Restore parent */
3409 val = clk_readl(PLLE_AUX);
3410 select_pll_e_input(val);
3414 static struct clk_ops tegra_plle_ops = {
3415 .init = tegra11_plle_clk_init,
3416 .enable = tegra11_plle_clk_enable,
3417 .disable = tegra11_plle_clk_disable,
3421 * Tegra11 includes dynamic frequency lock loop (DFLL) with automatic voltage
3422 * control as possible CPU clock source. It is included in the Tegra11 clock
3423 * tree as "complex PLL" with standard Tegra clock framework APIs. However,
3424 * DFLL locking logic h/w access APIs are separated in the tegra_cl_dvfs.c
3425 * module. Hence, DFLL operations, with the exception of initialization, are
3426 * basically cl-dvfs wrappers.
3429 #ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS
3430 /* DFLL operations */
3431 static void __init tegra11_dfll_cpu_late_init(struct clk *c)
3433 #ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS
3435 struct clk *cpu = tegra_get_clock_by_name("cpu");
3437 #ifdef CONFIG_TEGRA_FPGA_PLATFORM
3438 u32 netlist, patchid;
3439 tegra_get_netlist_revision(&netlist, &patchid);
3441 pr_err("%s: CL-DVFS is not available on net %d\n",
3446 /* release dfll clock source reset, init cl_dvfs control logic, and
3447 move dfll to initialized state, so it can be used as CPU source */
3448 tegra_periph_reset_deassert(c);
3449 ret = tegra_init_cl_dvfs();
3452 c->u.dfll.cl_dvfs = platform_get_drvdata(&tegra_cl_dvfs_device);
3454 use_dfll = CONFIG_TEGRA_USE_DFLL_RANGE;
3455 tegra_dvfs_set_dfll_range(cpu->parent->dvfs, use_dfll);
3456 pr_info("Tegra CPU DFLL is initialized\n");
3462 static int tegra11_dfll_clk_enable(struct clk *c)
3464 return tegra_cl_dvfs_enable(c->u.dfll.cl_dvfs);
3467 static void tegra11_dfll_clk_disable(struct clk *c)
3469 tegra_cl_dvfs_disable(c->u.dfll.cl_dvfs);
3472 static int tegra11_dfll_clk_set_rate(struct clk *c, unsigned long rate)
3474 int ret = tegra_cl_dvfs_request_rate(c->u.dfll.cl_dvfs, rate);
3477 c->rate = tegra_cl_dvfs_request_get(c->u.dfll.cl_dvfs);
3482 static void tegra11_dfll_clk_reset(struct clk *c, bool assert)
3484 u32 val = assert ? DFLL_BASE_RESET : 0;
3485 clk_writel_delay(val, c->reg);
3489 tegra11_dfll_clk_cfg_ex(struct clk *c, enum tegra_clk_ex_param p, u32 setting)
3491 if (p == TEGRA_CLK_DFLL_LOCK)
3492 return setting ? tegra_cl_dvfs_lock(c->u.dfll.cl_dvfs) :
3493 tegra_cl_dvfs_unlock(c->u.dfll.cl_dvfs);
3497 #ifdef CONFIG_PM_SLEEP
3498 static void tegra11_dfll_clk_resume(struct clk *c)
3500 if (!(clk_readl(c->reg) & DFLL_BASE_RESET))
3501 return; /* already resumed */
3503 if (c->state != UNINITIALIZED) {
3504 tegra_periph_reset_deassert(c);
3505 tegra_cl_dvfs_resume(c->u.dfll.cl_dvfs);
3510 static struct clk_ops tegra_dfll_ops = {
3511 .enable = tegra11_dfll_clk_enable,
3512 .disable = tegra11_dfll_clk_disable,
3513 .set_rate = tegra11_dfll_clk_set_rate,
3514 .reset = tegra11_dfll_clk_reset,
3515 .clk_cfg_ex = tegra11_dfll_clk_cfg_ex,
3518 /* DFLL sysfs interface */
3519 static int tegra11_use_dfll_cb(const char *arg, const struct kernel_param *kp)
3522 unsigned long c_flags, p_flags;
3523 unsigned int old_use_dfll;
3524 struct clk *c = tegra_get_clock_by_name("cpu");
3526 if (!c->parent || !c->parent->dvfs)
3529 clk_lock_save(c, &c_flags);
3530 if (c->parent->u.cpu.mode == MODE_LP) {
3531 pr_err("%s: DFLL is not used on LP CPU\n", __func__);
3532 clk_unlock_restore(c, &c_flags);
3536 clk_lock_save(c->parent, &p_flags);
3537 old_use_dfll = use_dfll;
3538 param_set_int(arg, kp);
3540 if (use_dfll != old_use_dfll) {
3541 ret = tegra_dvfs_set_dfll_range(c->parent->dvfs, use_dfll);
3543 use_dfll = old_use_dfll;
3545 ret = clk_set_rate_locked(c->parent,
3546 clk_get_rate_locked(c->parent));
3548 use_dfll = old_use_dfll;
3549 tegra_dvfs_set_dfll_range(
3550 c->parent->dvfs, use_dfll);
3554 clk_unlock_restore(c->parent, &p_flags);
3555 clk_unlock_restore(c, &c_flags);
3556 tegra_recalculate_cpu_edp_limits();
3560 static struct kernel_param_ops tegra11_use_dfll_ops = {
3561 .set = tegra11_use_dfll_cb,
3562 .get = param_get_int,
3564 module_param_cb(use_dfll, &tegra11_use_dfll_ops, &use_dfll, 0644);
3567 /* Clock divider ops (non-atomic shared register access) */
3568 static DEFINE_SPINLOCK(pll_div_lock);
3570 static int tegra11_pll_div_clk_set_rate(struct clk *c, unsigned long rate);
3571 static void tegra11_pll_div_clk_init(struct clk *c)
3573 if (c->flags & DIV_U71) {
3575 u32 val = clk_readl(c->reg);
3576 val >>= c->reg_shift;
3577 c->state = (val & PLL_OUT_CLKEN) ? ON : OFF;
3578 if (!(val & PLL_OUT_RESET_DISABLE))
3581 if (c->u.pll_div.default_rate) {
3582 int ret = tegra11_pll_div_clk_set_rate(
3583 c, c->u.pll_div.default_rate);
3587 divu71 = (val & PLL_OUT_RATIO_MASK) >> PLL_OUT_RATIO_SHIFT;
3588 c->div = (divu71 + 2);
3590 } else if (c->flags & DIV_2) {
3592 if (c->flags & (PLLD | PLLX)) {
3598 } else if (c->flags & PLLU) {
3599 u32 val = clk_readl(c->reg);
3600 c->state = val & (0x1 << c->reg_shift) ? ON : OFF;
3608 static int tegra11_pll_div_clk_enable(struct clk *c)
3612 unsigned long flags;
3614 pr_debug("%s: %s\n", __func__, c->name);
3615 if (c->flags & DIV_U71) {
3616 spin_lock_irqsave(&pll_div_lock, flags);
3617 val = clk_readl(c->reg);
3618 new_val = val >> c->reg_shift;
3621 new_val |= PLL_OUT_CLKEN | PLL_OUT_RESET_DISABLE;
3623 val &= ~(0xFFFF << c->reg_shift);
3624 val |= new_val << c->reg_shift;
3625 clk_writel_delay(val, c->reg);
3626 spin_unlock_irqrestore(&pll_div_lock, flags);
3628 } else if (c->flags & DIV_2) {
3630 } else if (c->flags & PLLU) {
3631 clk_lock_save(c->parent, &flags);
3632 val = clk_readl(c->reg) | (0x1 << c->reg_shift);
3633 clk_writel_delay(val, c->reg);
3634 clk_unlock_restore(c->parent, &flags);
3640 static void tegra11_pll_div_clk_disable(struct clk *c)
3644 unsigned long flags;
3646 pr_debug("%s: %s\n", __func__, c->name);
3647 if (c->flags & DIV_U71) {
3648 spin_lock_irqsave(&pll_div_lock, flags);
3649 val = clk_readl(c->reg);
3650 new_val = val >> c->reg_shift;
3653 new_val &= ~(PLL_OUT_CLKEN | PLL_OUT_RESET_DISABLE);
3655 val &= ~(0xFFFF << c->reg_shift);
3656 val |= new_val << c->reg_shift;
3657 clk_writel_delay(val, c->reg);
3658 spin_unlock_irqrestore(&pll_div_lock, flags);
3659 } else if (c->flags & PLLU) {
3660 clk_lock_save(c->parent, &flags);
3661 val = clk_readl(c->reg) & (~(0x1 << c->reg_shift));
3662 clk_writel_delay(val, c->reg);
3663 clk_unlock_restore(c->parent, &flags);
3667 static int tegra11_pll_div_clk_set_rate(struct clk *c, unsigned long rate)
3672 unsigned long parent_rate = clk_get_rate(c->parent);
3673 unsigned long flags;
3675 pr_debug("%s: %s %lu\n", __func__, c->name, rate);
3676 if (c->flags & DIV_U71) {
3677 divider_u71 = clk_div71_get_divider(
3678 parent_rate, rate, c->flags, ROUND_DIVIDER_UP);
3679 if (divider_u71 >= 0) {
3680 spin_lock_irqsave(&pll_div_lock, flags);
3681 val = clk_readl(c->reg);
3682 new_val = val >> c->reg_shift;
3684 if (c->flags & DIV_U71_FIXED)
3685 new_val |= PLL_OUT_OVERRIDE;
3686 new_val &= ~PLL_OUT_RATIO_MASK;
3687 new_val |= divider_u71 << PLL_OUT_RATIO_SHIFT;
3689 val &= ~(0xFFFF << c->reg_shift);
3690 val |= new_val << c->reg_shift;
3691 clk_writel_delay(val, c->reg);
3692 c->div = divider_u71 + 2;
3694 spin_unlock_irqrestore(&pll_div_lock, flags);
3697 } else if (c->flags & DIV_2)
3698 return clk_set_rate(c->parent, rate * 2);
3703 static long tegra11_pll_div_clk_round_rate(struct clk *c, unsigned long rate)
3706 unsigned long parent_rate = clk_get_rate(c->parent);
3707 pr_debug("%s: %s %lu\n", __func__, c->name, rate);
3709 if (c->flags & DIV_U71) {
3710 divider = clk_div71_get_divider(
3711 parent_rate, rate, c->flags, ROUND_DIVIDER_UP);
3714 return DIV_ROUND_UP(parent_rate * 2, divider + 2);
3715 } else if (c->flags & DIV_2)
3716 /* no rounding - fixed DIV_2 dividers pass rate to parent PLL */
3722 static struct clk_ops tegra_pll_div_ops = {
3723 .init = tegra11_pll_div_clk_init,
3724 .enable = tegra11_pll_div_clk_enable,
3725 .disable = tegra11_pll_div_clk_disable,
3726 .set_rate = tegra11_pll_div_clk_set_rate,
3727 .round_rate = tegra11_pll_div_clk_round_rate,
3730 /* Periph clk ops */
3731 static inline u32 periph_clk_source_mask(struct clk *c)
3733 if (c->u.periph.src_mask)
3734 return c->u.periph.src_mask;
3735 else if (c->flags & MUX8)
3737 else if (c->flags & MUX_PWM)
3739 else if (c->flags & MUX_CLK_OUT)
3740 return 3 << (c->u.periph.clk_num + 4);
3741 else if (c->flags & PLLD)
3742 return PLLD_BASE_DSI_MUX_MASK;
3747 static inline u32 periph_clk_source_shift(struct clk *c)
3749 if (c->u.periph.src_shift)
3750 return c->u.periph.src_shift;
3751 else if (c->flags & MUX8)
3753 else if (c->flags & MUX_PWM)
3755 else if (c->flags & MUX_CLK_OUT)
3756 return c->u.periph.clk_num + 4;
3757 else if (c->flags & PLLD)
3758 return PLLD_BASE_DSI_MUX_SHIFT;
3763 static void tegra11_periph_clk_init(struct clk *c)
3765 u32 val = clk_readl(c->reg);
3766 const struct clk_mux_sel *mux = 0;
3767 const struct clk_mux_sel *sel;
3768 if (c->flags & MUX) {
3769 for (sel = c->inputs; sel->input != NULL; sel++) {
3770 if (((val & periph_clk_source_mask(c)) >>
3771 periph_clk_source_shift(c)) == sel->value)
3776 c->parent = mux->input;
3778 if (c->flags & PLLU) {
3779 /* for xusb_hs clock enforce PLLU source during init */
3780 val &= ~periph_clk_source_mask(c);
3781 val |= c->inputs[0].value << periph_clk_source_shift(c);
3782 clk_writel_delay(val, c->reg);
3784 c->parent = c->inputs[0].input;
3787 if (c->flags & DIV_U71) {
3788 u32 divu71 = val & PERIPH_CLK_SOURCE_DIVU71_MASK;
3789 if (c->flags & DIV_U71_IDLE) {
3790 val &= ~(PERIPH_CLK_SOURCE_DIVU71_MASK <<
3791 PERIPH_CLK_SOURCE_DIVIDLE_SHIFT);
3792 val |= (PERIPH_CLK_SOURCE_DIVIDLE_VAL <<
3793 PERIPH_CLK_SOURCE_DIVIDLE_SHIFT);
3794 clk_writel(val, c->reg);
3796 c->div = divu71 + 2;
3798 } else if (c->flags & DIV_U151) {
3799 u32 divu151 = val & PERIPH_CLK_SOURCE_DIVU16_MASK;
3800 if ((c->flags & DIV_U151_UART) &&
3801 (!(val & PERIPH_CLK_UART_DIV_ENB))) {
3804 c->div = divu151 + 2;
3806 } else if (c->flags & DIV_U16) {
3807 u32 divu16 = val & PERIPH_CLK_SOURCE_DIVU16_MASK;
3808 c->div = divu16 + 1;
3815 if (c->flags & PERIPH_NO_ENB) {
3816 c->state = c->parent->state;
3822 if (!(clk_readl(PERIPH_CLK_TO_ENB_REG(c)) & PERIPH_CLK_TO_BIT(c)))
3824 if (!(c->flags & PERIPH_NO_RESET))
3825 if (clk_readl(PERIPH_CLK_TO_RST_REG(c)) & PERIPH_CLK_TO_BIT(c))
3829 static int tegra11_periph_clk_enable(struct clk *c)
3831 unsigned long flags;
3832 pr_debug("%s on clock %s\n", __func__, c->name);
3834 if (c->flags & PERIPH_NO_ENB)
3837 spin_lock_irqsave(&periph_refcount_lock, flags);
3839 tegra_periph_clk_enable_refcount[c->u.periph.clk_num]++;
3840 if (tegra_periph_clk_enable_refcount[c->u.periph.clk_num] > 1) {
3841 spin_unlock_irqrestore(&periph_refcount_lock, flags);
3845 clk_writel_delay(PERIPH_CLK_TO_BIT(c), PERIPH_CLK_TO_ENB_SET_REG(c));
3846 if (!(c->flags & PERIPH_NO_RESET) && !(c->flags & PERIPH_MANUAL_RESET)) {
3847 if (clk_readl(PERIPH_CLK_TO_RST_REG(c)) & PERIPH_CLK_TO_BIT(c)) {
3848 udelay(5); /* reset propagation delay */
3849 clk_writel(PERIPH_CLK_TO_BIT(c), PERIPH_CLK_TO_RST_CLR_REG(c));
3852 spin_unlock_irqrestore(&periph_refcount_lock, flags);
3856 static void tegra11_periph_clk_disable(struct clk *c)
3858 unsigned long val, flags;
3859 pr_debug("%s on clock %s\n", __func__, c->name);
3861 if (c->flags & PERIPH_NO_ENB)
3864 spin_lock_irqsave(&periph_refcount_lock, flags);
3867 tegra_periph_clk_enable_refcount[c->u.periph.clk_num]--;
3869 if (tegra_periph_clk_enable_refcount[c->u.periph.clk_num] == 0) {
3870 /* If peripheral is in the APB bus then read the APB bus to
3871 * flush the write operation in apb bus. This will avoid the
3872 * peripheral access after disabling clock*/
3873 if (c->flags & PERIPH_ON_APB)
3874 val = chipid_readl();
3877 PERIPH_CLK_TO_BIT(c), PERIPH_CLK_TO_ENB_CLR_REG(c));
3879 spin_unlock_irqrestore(&periph_refcount_lock, flags);
3882 static void tegra11_periph_clk_reset(struct clk *c, bool assert)
3885 pr_debug("%s %s on clock %s\n", __func__,
3886 assert ? "assert" : "deassert", c->name);
3888 if (c->flags & PERIPH_NO_ENB)
3891 if (!(c->flags & PERIPH_NO_RESET)) {
3893 /* If peripheral is in the APB bus then read the APB
3894 * bus to flush the write operation in apb bus. This
3895 * will avoid the peripheral access after disabling
3897 if (c->flags & PERIPH_ON_APB)
3898 val = chipid_readl();
3900 clk_writel(PERIPH_CLK_TO_BIT(c),
3901 PERIPH_CLK_TO_RST_SET_REG(c));
3903 clk_writel(PERIPH_CLK_TO_BIT(c),
3904 PERIPH_CLK_TO_RST_CLR_REG(c));
3908 static int tegra11_periph_clk_set_parent(struct clk *c, struct clk *p)
3911 const struct clk_mux_sel *sel;
3912 pr_debug("%s: %s %s\n", __func__, c->name, p->name);
3914 if (!(c->flags & MUX))
3915 return (p == c->parent) ? 0 : (-EINVAL);
3917 for (sel = c->inputs; sel->input != NULL; sel++) {
3918 if (sel->input == p) {
3919 val = clk_readl(c->reg);
3920 val &= ~periph_clk_source_mask(c);
3921 val |= (sel->value << periph_clk_source_shift(c));
3926 clk_writel_delay(val, c->reg);
3928 if (c->refcnt && c->parent)
3929 clk_disable(c->parent);
3939 static int tegra11_periph_clk_set_rate(struct clk *c, unsigned long rate)
3943 unsigned long parent_rate = clk_get_rate(c->parent);
3945 if (c->flags & DIV_U71) {
3946 divider = clk_div71_get_divider(
3947 parent_rate, rate, c->flags, ROUND_DIVIDER_UP);
3949 val = clk_readl(c->reg);
3950 val &= ~PERIPH_CLK_SOURCE_DIVU71_MASK;
3952 clk_writel_delay(val, c->reg);
3953 c->div = divider + 2;
3957 } else if (c->flags & DIV_U151) {
3958 divider = clk_div151_get_divider(
3959 parent_rate, rate, c->flags, ROUND_DIVIDER_UP);
3961 val = clk_readl(c->reg);
3962 val &= ~PERIPH_CLK_SOURCE_DIVU16_MASK;
3964 if (c->flags & DIV_U151_UART) {
3966 val |= PERIPH_CLK_UART_DIV_ENB;
3968 val &= ~PERIPH_CLK_UART_DIV_ENB;
3970 clk_writel_delay(val, c->reg);
3971 c->div = divider + 2;
3975 } else if (c->flags & DIV_U16) {
3976 divider = clk_div16_get_divider(parent_rate, rate);
3978 val = clk_readl(c->reg);
3979 val &= ~PERIPH_CLK_SOURCE_DIVU16_MASK;
3981 clk_writel_delay(val, c->reg);
3982 c->div = divider + 1;
3986 } else if (parent_rate <= rate) {
3994 static long tegra11_periph_clk_round_rate(struct clk *c,
3998 unsigned long parent_rate = clk_get_rate(c->parent);
3999 pr_debug("%s: %s %lu\n", __func__, c->name, rate);
4001 if (c->flags & DIV_U71) {
4002 divider = clk_div71_get_divider(
4003 parent_rate, rate, c->flags, ROUND_DIVIDER_UP);
4007 return DIV_ROUND_UP(parent_rate * 2, divider + 2);
4008 } else if (c->flags & DIV_U151) {
4009 divider = clk_div151_get_divider(
4010 parent_rate, rate, c->flags, ROUND_DIVIDER_UP);
4014 return DIV_ROUND_UP(parent_rate * 2, divider + 2);
4015 } else if (c->flags & DIV_U16) {
4016 divider = clk_div16_get_divider(parent_rate, rate);
4019 return DIV_ROUND_UP(parent_rate, divider + 1);
4024 static struct clk_ops tegra_periph_clk_ops = {
4025 .init = &tegra11_periph_clk_init,
4026 .enable = &tegra11_periph_clk_enable,
4027 .disable = &tegra11_periph_clk_disable,
4028 .set_parent = &tegra11_periph_clk_set_parent,
4029 .set_rate = &tegra11_periph_clk_set_rate,
4030 .round_rate = &tegra11_periph_clk_round_rate,
4031 .reset = &tegra11_periph_clk_reset,
4035 #if !defined(CONFIG_TEGRA_SIMULATION_PLATFORM)
4036 /* msenc clock propagation WAR for bug 1005168 */
4037 static int tegra11_msenc_clk_enable(struct clk *c)
4039 int ret = tegra11_periph_clk_enable(c);
4043 clk_writel(0, LVL2_CLK_GATE_OVRE);
4044 clk_writel(0x00400000, LVL2_CLK_GATE_OVRE);
4046 clk_writel(0, LVL2_CLK_GATE_OVRE);
4050 static struct clk_ops tegra_msenc_clk_ops = {
4051 .init = &tegra11_periph_clk_init,
4052 .enable = &tegra11_msenc_clk_enable,
4053 .disable = &tegra11_periph_clk_disable,
4054 .set_parent = &tegra11_periph_clk_set_parent,
4055 .set_rate = &tegra11_periph_clk_set_rate,
4056 .round_rate = &tegra11_periph_clk_round_rate,
4057 .reset = &tegra11_periph_clk_reset,
4060 /* Periph extended clock configuration ops */
4062 tegra11_vi_clk_cfg_ex(struct clk *c, enum tegra_clk_ex_param p, u32 setting)
4064 if (p == TEGRA_CLK_VI_INP_SEL) {
4065 u32 val = clk_readl(c->reg);
4066 val &= ~PERIPH_CLK_VI_SEL_EX_MASK;
4067 val |= (setting << PERIPH_CLK_VI_SEL_EX_SHIFT) &
4068 PERIPH_CLK_VI_SEL_EX_MASK;
4069 clk_writel(val, c->reg);
4075 static struct clk_ops tegra_vi_clk_ops = {
4076 .init = &tegra11_periph_clk_init,
4077 .enable = &tegra11_periph_clk_enable,
4078 .disable = &tegra11_periph_clk_disable,
4079 .set_parent = &tegra11_periph_clk_set_parent,
4080 .set_rate = &tegra11_periph_clk_set_rate,
4081 .round_rate = &tegra11_periph_clk_round_rate,
4082 .clk_cfg_ex = &tegra11_vi_clk_cfg_ex,
4083 .reset = &tegra11_periph_clk_reset,
4087 tegra11_nand_clk_cfg_ex(struct clk *c, enum tegra_clk_ex_param p, u32 setting)
4089 if (p == TEGRA_CLK_NAND_PAD_DIV2_ENB) {
4090 u32 val = clk_readl(c->reg);
4092 val |= PERIPH_CLK_NAND_DIV_EX_ENB;
4094 val &= ~PERIPH_CLK_NAND_DIV_EX_ENB;
4095 clk_writel(val, c->reg);
4101 static struct clk_ops tegra_nand_clk_ops = {
4102 .init = &tegra11_periph_clk_init,
4103 .enable = &tegra11_periph_clk_enable,
4104 .disable = &tegra11_periph_clk_disable,
4105 .set_parent = &tegra11_periph_clk_set_parent,
4106 .set_rate = &tegra11_periph_clk_set_rate,
4107 .round_rate = &tegra11_periph_clk_round_rate,
4108 .clk_cfg_ex = &tegra11_nand_clk_cfg_ex,
4109 .reset = &tegra11_periph_clk_reset,
4114 tegra11_dtv_clk_cfg_ex(struct clk *c, enum tegra_clk_ex_param p, u32 setting)
4116 if (p == TEGRA_CLK_DTV_INVERT) {
4117 u32 val = clk_readl(c->reg);
4119 val |= PERIPH_CLK_DTV_POLARITY_INV;
4121 val &= ~PERIPH_CLK_DTV_POLARITY_INV;
4122 clk_writel(val, c->reg);
4128 static struct clk_ops tegra_dtv_clk_ops = {
4129 .init = &tegra11_periph_clk_init,
4130 .enable = &tegra11_periph_clk_enable,
4131 .disable = &tegra11_periph_clk_disable,
4132 .set_parent = &tegra11_periph_clk_set_parent,
4133 .set_rate = &tegra11_periph_clk_set_rate,
4134 .round_rate = &tegra11_periph_clk_round_rate,
4135 .clk_cfg_ex = &tegra11_dtv_clk_cfg_ex,
4136 .reset = &tegra11_periph_clk_reset,
4139 static int tegra11_dsi_clk_set_parent(struct clk *c, struct clk *p)
4141 const struct clk_mux_sel *sel;
4142 struct clk *d = tegra_get_clock_by_name("pll_d");
4143 if (c->reg != d->reg)
4144 d = tegra_get_clock_by_name("pll_d2");
4146 pr_debug("%s: %s %s\n", __func__, c->name, p->name);
4148 for (sel = c->inputs; sel->input != NULL; sel++) {
4149 if (sel->input == p) {
4153 /* The DSI parent selection bit is in PLLD base
4154 register - can not do direct r-m-w, must be
4155 protected by PLLD lock */
4157 d, TEGRA_CLK_PLLD_MIPI_MUX_SEL, sel->value);
4159 if (c->refcnt && c->parent)
4160 clk_disable(c->parent);
4170 static struct clk_ops tegra_dsi_clk_ops = {
4171 .init = &tegra11_periph_clk_init,
4172 .enable = &tegra11_periph_clk_enable,
4173 .disable = &tegra11_periph_clk_disable,
4174 .set_parent = &tegra11_dsi_clk_set_parent,
4175 .set_rate = &tegra11_periph_clk_set_rate,
4176 .round_rate = &tegra11_periph_clk_round_rate,
4177 .reset = &tegra11_periph_clk_reset,
4180 /* pciex clock support only reset function */
4181 static struct clk_ops tegra_pciex_clk_ops = {
4182 .reset = tegra11_periph_clk_reset,
4185 /* Output clock ops */
4187 static DEFINE_SPINLOCK(clk_out_lock);
4189 static void tegra11_clk_out_init(struct clk *c)
4191 const struct clk_mux_sel *mux = 0;
4192 const struct clk_mux_sel *sel;
4193 u32 val = pmc_readl(c->reg);
4195 c->state = (val & (0x1 << c->u.periph.clk_num)) ? ON : OFF;
4199 for (sel = c->inputs; sel->input != NULL; sel++) {
4200 if (((val & periph_clk_source_mask(c)) >>
4201 periph_clk_source_shift(c)) == sel->value)
4205 c->parent = mux->input;
4208 static int tegra11_clk_out_enable(struct clk *c)
4211 unsigned long flags;
4213 pr_debug("%s on clock %s\n", __func__, c->name);
4215 spin_lock_irqsave(&clk_out_lock, flags);
4216 val = pmc_readl(c->reg);
4217 val |= (0x1 << c->u.periph.clk_num);
4218 pmc_writel(val, c->reg);
4219 spin_unlock_irqrestore(&clk_out_lock, flags);
4224 static void tegra11_clk_out_disable(struct clk *c)
4227 unsigned long flags;
4229 pr_debug("%s on clock %s\n", __func__, c->name);
4231 spin_lock_irqsave(&clk_out_lock, flags);
4232 val = pmc_readl(c->reg);
4233 val &= ~(0x1 << c->u.periph.clk_num);
4234 pmc_writel(val, c->reg);
4235 spin_unlock_irqrestore(&clk_out_lock, flags);
4238 static int tegra11_clk_out_set_parent(struct clk *c, struct clk *p)
4241 unsigned long flags;
4242 const struct clk_mux_sel *sel;
4244 pr_debug("%s: %s %s\n", __func__, c->name, p->name);
4246 for (sel = c->inputs; sel->input != NULL; sel++) {
4247 if (sel->input == p) {
4251 spin_lock_irqsave(&clk_out_lock, flags);
4252 val = pmc_readl(c->reg);
4253 val &= ~periph_clk_source_mask(c);
4254 val |= (sel->value << periph_clk_source_shift(c));
4255 pmc_writel(val, c->reg);
4256 spin_unlock_irqrestore(&clk_out_lock, flags);
4258 if (c->refcnt && c->parent)
4259 clk_disable(c->parent);
4268 static struct clk_ops tegra_clk_out_ops = {
4269 .init = &tegra11_clk_out_init,
4270 .enable = &tegra11_clk_out_enable,
4271 .disable = &tegra11_clk_out_disable,
4272 .set_parent = &tegra11_clk_out_set_parent,
4276 /* External memory controller clock ops */
4277 static void tegra11_emc_clk_init(struct clk *c)
4279 tegra11_periph_clk_init(c);
4280 tegra_emc_dram_type_init(c);
4283 static long tegra11_emc_clk_round_rate(struct clk *c, unsigned long rate)
4285 long new_rate = max(rate, c->min_rate);
4287 new_rate = tegra_emc_round_rate(new_rate);
4289 new_rate = c->max_rate;
4294 static int tegra11_emc_clk_set_rate(struct clk *c, unsigned long rate)
4300 /* The tegra11x memory controller has an interlock with the clock
4301 * block that allows memory shadowed registers to be updated,
4302 * and then transfer them to the main registers at the same
4303 * time as the clock update without glitches. During clock change
4304 * operation both clock parent and divider may change simultaneously
4305 * to achieve requested rate. */
4306 p = tegra_emc_predict_parent(rate, &div_value);
4307 div_value += 2; /* emc has fractional DIV_U71 divider */
4308 if (IS_ERR_OR_NULL(p)) {
4309 pr_err("%s: Failed to predict emc parent for rate %lu\n",
4314 if (p == c->parent) {
4315 if (div_value == c->div)
4317 } else if (c->refcnt)
4320 ret = tegra_emc_set_rate(rate);
4324 if (p != c->parent) {
4325 if(c->refcnt && c->parent)
4326 clk_disable(c->parent);
4334 static int tegra11_clk_emc_bus_update(struct clk *bus)
4336 struct clk *p = NULL;
4337 unsigned long rate, old_rate, parent_rate, backup_rate;
4339 if (detach_shared_bus)
4342 rate = tegra11_clk_shared_bus_update(bus, NULL, NULL);
4343 rate = clk_round_rate_locked(bus, rate);
4345 old_rate = clk_get_rate_locked(bus);
4346 if (rate == old_rate)
4349 if (!tegra_emc_is_parent_ready(rate, &p, &parent_rate, &backup_rate)) {
4350 if (bus->parent == p) {
4351 /* need backup to re-lock current parent */
4353 if (IS_ERR_VALUE(backup_rate)) {
4354 pr_err("%s: No backup for %s rate %lu\n",
4355 __func__, bus->name, rate);
4359 if (backup_rate < old_rate) /* skip lowering voltage */
4360 bus->auto_dvfs = false;
4361 ret = clk_set_rate_locked(bus, backup_rate);
4362 bus->auto_dvfs = true;
4364 pr_err("%s: Failed to backup %s for rate %lu\n",
4365 __func__, bus->name, rate);
4370 pr_err("%s: %s has other than emc child\n",
4375 if (clk_set_rate(p, parent_rate)) {
4376 pr_err("%s: Failed to set %s rate %lu\n",
4377 __func__, p->name, parent_rate);
4382 return clk_set_rate_locked(bus, rate);
4385 static struct clk_ops tegra_emc_clk_ops = {
4386 .init = &tegra11_emc_clk_init,
4387 .enable = &tegra11_periph_clk_enable,
4388 .disable = &tegra11_periph_clk_disable,
4389 .set_rate = &tegra11_emc_clk_set_rate,
4390 .round_rate = &tegra11_emc_clk_round_rate,
4391 .reset = &tegra11_periph_clk_reset,
4392 .shared_bus_update = &tegra11_clk_emc_bus_update,
4395 /* Clock doubler ops (non-atomic shared register access) */
4396 static DEFINE_SPINLOCK(doubler_lock);
4398 static void tegra11_clk_double_init(struct clk *c)
4400 u32 val = clk_readl(c->reg);
4401 c->mul = val & (0x1 << c->reg_shift) ? 1 : 2;
4404 if (!(clk_readl(PERIPH_CLK_TO_ENB_REG(c)) & PERIPH_CLK_TO_BIT(c)))
4408 static int tegra11_clk_double_set_rate(struct clk *c, unsigned long rate)
4411 unsigned long parent_rate = clk_get_rate(c->parent);
4412 unsigned long flags;
4414 if (rate == parent_rate) {
4415 spin_lock_irqsave(&doubler_lock, flags);
4416 val = clk_readl(c->reg) | (0x1 << c->reg_shift);
4417 clk_writel(val, c->reg);
4420 spin_unlock_irqrestore(&doubler_lock, flags);
4422 } else if (rate == 2 * parent_rate) {
4423 spin_lock_irqsave(&doubler_lock, flags);
4424 val = clk_readl(c->reg) & (~(0x1 << c->reg_shift));
4425 clk_writel(val, c->reg);
4428 spin_unlock_irqrestore(&doubler_lock, flags);
4434 static struct clk_ops tegra_clk_double_ops = {
4435 .init = &tegra11_clk_double_init,
4436 .enable = &tegra11_periph_clk_enable,
4437 .disable = &tegra11_periph_clk_disable,
4438 .set_rate = &tegra11_clk_double_set_rate,
4441 /* Audio sync clock ops */
4442 static int tegra11_sync_source_set_rate(struct clk *c, unsigned long rate)
4448 static struct clk_ops tegra_sync_source_ops = {
4449 .set_rate = &tegra11_sync_source_set_rate,
4452 static void tegra11_audio_sync_clk_init(struct clk *c)
4455 const struct clk_mux_sel *sel;
4456 u32 val = clk_readl(c->reg);
4457 c->state = (val & AUDIO_SYNC_DISABLE_BIT) ? OFF : ON;
4458 source = val & AUDIO_SYNC_SOURCE_MASK;
4459 for (sel = c->inputs; sel->input != NULL; sel++)
4460 if (sel->value == source)
4462 BUG_ON(sel->input == NULL);
4463 c->parent = sel->input;
4466 static int tegra11_audio_sync_clk_enable(struct clk *c)
4468 u32 val = clk_readl(c->reg);
4469 clk_writel((val & (~AUDIO_SYNC_DISABLE_BIT)), c->reg);
4473 static void tegra11_audio_sync_clk_disable(struct clk *c)
4475 u32 val = clk_readl(c->reg);
4476 clk_writel((val | AUDIO_SYNC_DISABLE_BIT), c->reg);
4479 static int tegra11_audio_sync_clk_set_parent(struct clk *c, struct clk *p)
4482 const struct clk_mux_sel *sel;
4483 for (sel = c->inputs; sel->input != NULL; sel++) {
4484 if (sel->input == p) {
4485 val = clk_readl(c->reg);
4486 val &= ~AUDIO_SYNC_SOURCE_MASK;
4492 clk_writel(val, c->reg);
4494 if (c->refcnt && c->parent)
4495 clk_disable(c->parent);
4505 static struct clk_ops tegra_audio_sync_clk_ops = {
4506 .init = tegra11_audio_sync_clk_init,
4507 .enable = tegra11_audio_sync_clk_enable,
4508 .disable = tegra11_audio_sync_clk_disable,
4509 .set_parent = tegra11_audio_sync_clk_set_parent,
4515 * Some clocks require dynamic re-locking of source PLL in order to
4516 * achieve frequency scaling granularity that matches characterized
4517 * core voltage steps. The cbus clock creates a shared bus that
4518 * provides a virtual root for such clocks to hide and synchronize
4519 * parent PLL re-locking as well as backup operations.
4522 static void tegra11_clk_cbus_init(struct clk *c)
4528 static int tegra11_clk_cbus_enable(struct clk *c)
4533 static long tegra11_clk_cbus_round_rate(struct clk *c, unsigned long rate)
4539 c->min_rate = c->parent->min_rate;
4540 rate = max(rate, c->min_rate);
4544 /* update min now, since no dvfs table was available during init
4545 (skip placeholder entries set to 1 kHz) */
4547 for (i = 0; i < (c->dvfs->num_freqs - 1); i++) {
4548 if (c->dvfs->freqs[i] > 1 * c->dvfs->freqs_mult) {
4549 c->min_rate = c->dvfs->freqs[i];
4553 BUG_ON(!c->min_rate);
4555 rate = max(rate, c->min_rate);
4557 for (i = 0; i < (c->dvfs->num_freqs - 1); i++) {
4558 unsigned long f = c->dvfs->freqs[i];
4559 int mv = c->dvfs->millivolts[i];
4560 if ((f >= rate) || (mv >= c->dvfs->max_millivolts))
4563 return c->dvfs->freqs[i];
4566 static int cbus_switch_one(struct clk *c, struct clk *p, u32 div, bool abort)
4570 /* set new divider if it is bigger than the current one */
4571 if (c->div < c->mul * div) {
4572 ret = clk_set_div(c, div);
4574 pr_err("%s: failed to set %s clock divider %u: %d\n",
4575 __func__, c->name, div, ret);
4581 if (c->parent != p) {
4582 ret = clk_set_parent(c, p);
4584 pr_err("%s: failed to set %s clock parent %s: %d\n",
4585 __func__, c->name, p->name, ret);
4591 /* set new divider if it is smaller than the current one */
4592 if (c->div > c->mul * div) {
4593 ret = clk_set_div(c, div);
4595 pr_err("%s: failed to set %s clock divider %u: %d\n",
4596 __func__, c->name, div, ret);
4602 static int cbus_backup(struct clk *c)
4607 list_for_each_entry(user, &c->shared_bus_list,
4608 u.shared_bus_user.node) {
4609 struct clk *client = user->u.shared_bus_user.client;
4610 if (client && (client->state == ON) &&
4611 (client->parent == c->parent)) {
4612 ret = cbus_switch_one(client,
4613 c->shared_bus_backup.input,
4614 c->shared_bus_backup.value *
4623 static int cbus_dvfs_set_rate(struct clk *c, unsigned long rate)
4628 list_for_each_entry(user, &c->shared_bus_list,
4629 u.shared_bus_user.node) {
4630 struct clk *client = user->u.shared_bus_user.client;
4631 if (client && client->refcnt && (client->parent == c->parent)) {
4632 ret = tegra_dvfs_set_rate(c, rate);
4640 static void cbus_restore(struct clk *c)
4644 list_for_each_entry(user, &c->shared_bus_list,
4645 u.shared_bus_user.node) {
4646 if (user->u.shared_bus_user.client)
4647 cbus_switch_one(user->u.shared_bus_user.client,
4648 c->parent, c->div * user->div, false);
4652 static int get_next_backup_div(struct clk *c, unsigned long rate)
4655 unsigned long backup_rate = clk_get_rate(c->shared_bus_backup.input);
4657 rate = max(rate, clk_get_rate_locked(c));
4658 rate = rate - (rate >> 2); /* 25% margin for backup rate */
4659 if ((u64)rate * div < backup_rate)
4660 div = DIV_ROUND_UP(backup_rate, rate);
4666 static int tegra11_clk_cbus_set_rate(struct clk *c, unsigned long rate)
4674 ret = clk_enable(c->parent);
4676 pr_err("%s: failed to enable %s clock: %d\n",
4677 __func__, c->name, ret);
4681 dramp = tegra11_is_dyn_ramp(c->parent, rate * c->div, false);
4683 c->shared_bus_backup.value = get_next_backup_div(c, rate);
4684 ret = cbus_backup(c);
4689 ret = clk_set_rate(c->parent, rate * c->div);
4691 pr_err("%s: failed to set %s clock rate %lu: %d\n",
4692 __func__, c->name, rate, ret);
4696 /* Safe voltage setting is taken care of by cbus clock dvfs; the call
4697 * below only records requirements for each enabled client.
4700 ret = cbus_dvfs_set_rate(c, rate);
4705 clk_disable(c->parent);
4709 static inline void cbus_move_enabled_user(
4710 struct clk *user, struct clk *dst, struct clk *src)
4713 list_move_tail(&user->u.shared_bus_user.node, &dst->shared_bus_list);
4715 clk_reparent(user, dst);
4718 #ifdef CONFIG_TEGRA_DYNAMIC_CBUS
4719 static int tegra11_clk_cbus_update(struct clk *bus)
4722 struct clk *slow = NULL;
4723 struct clk *top = NULL;
4725 unsigned long old_rate;
4727 if (detach_shared_bus)
4730 rate = tegra11_clk_shared_bus_update(bus, &top, &slow);
4732 /* use dvfs table of the slowest enabled client as cbus dvfs table */
4733 if (bus->dvfs && slow && (slow != bus->u.cbus.slow_user)) {
4735 unsigned long *dest = &bus->dvfs->freqs[0];
4736 unsigned long *src =
4737 &slow->u.shared_bus_user.client->dvfs->freqs[0];
4739 for (i = 0; i < bus->dvfs->num_freqs; i++)
4740 dest[i] = src[i] * slow->div;
4742 memcpy(dest, src, sizeof(*dest) * bus->dvfs->num_freqs);
4745 /* update bus state variables and rate */
4746 bus->u.cbus.slow_user = slow;
4747 bus->u.cbus.top_user = top;
4749 rate = bus->ops->round_rate(bus, rate);
4750 mv = tegra_dvfs_predict_millivolts(bus, rate);
4751 if (IS_ERR_VALUE(mv))
4755 mv -= bus->dvfs->cur_millivolts;
4756 if (bus->refcnt && (mv > 0)) {
4757 ret = tegra_dvfs_set_rate(bus, rate);
4763 old_rate = clk_get_rate_locked(bus);
4764 if (IS_ENABLED(CONFIG_TEGRA_MIGRATE_CBUS_USERS) || (old_rate != rate)) {
4765 ret = bus->ops->set_rate(bus, rate);
4771 if (bus->refcnt && (mv <= 0)) {
4772 ret = tegra_dvfs_set_rate(bus, rate);
4778 clk_rate_change_notify(bus, rate);
4782 static int tegra11_clk_cbus_update(struct clk *bus)
4784 unsigned long rate, old_rate;
4786 if (detach_shared_bus)
4789 rate = tegra11_clk_shared_bus_update(bus, NULL, NULL);
4790 rate = clk_round_rate_locked(bus, rate);
4792 old_rate = clk_get_rate_locked(bus);
4793 if (rate == old_rate)
4796 return clk_set_rate_locked(bus, rate);
4800 static int tegra11_clk_cbus_migrate_users(struct clk *user)
4802 #ifdef CONFIG_TEGRA_MIGRATE_CBUS_USERS
4803 struct clk *src_bus, *dst_bus, *top_user, *c;
4804 struct list_head *pos, *n;
4806 if (!user->u.shared_bus_user.client || !user->inputs)
4809 /* Dual cbus on Tegra11 */
4810 src_bus = user->inputs[0].input;
4811 dst_bus = user->inputs[1].input;
4813 if (!src_bus->u.cbus.top_user && !dst_bus->u.cbus.top_user)
4816 /* Make sure top user on the source bus is requesting highest rate */
4817 if (!src_bus->u.cbus.top_user || (dst_bus->u.cbus.top_user &&
4818 bus_user_request_is_lower(src_bus->u.cbus.top_user,
4819 dst_bus->u.cbus.top_user)))
4820 swap(src_bus, dst_bus);
4822 /* If top user is the slow one on its own (source) bus, do nothing */
4823 top_user = src_bus->u.cbus.top_user;
4824 BUG_ON(!top_user->u.shared_bus_user.client);
4825 if (!bus_user_is_slower(src_bus->u.cbus.slow_user, top_user))
4828 /* If source bus top user is slower than all users on destination bus,
4829 move top user; otherwise move all users slower than the top one */
4830 if (!dst_bus->u.cbus.slow_user ||
4831 !bus_user_is_slower(dst_bus->u.cbus.slow_user, top_user)) {
4832 cbus_move_enabled_user(top_user, dst_bus, src_bus);
4834 list_for_each_safe(pos, n, &src_bus->shared_bus_list) {
4835 c = list_entry(pos, struct clk, u.shared_bus_user.node);
4836 if (c->u.shared_bus_user.enabled &&
4837 c->u.shared_bus_user.client &&
4838 bus_user_is_slower(c, top_user))
4839 cbus_move_enabled_user(c, dst_bus, src_bus);
4843 /* Update destination bus 1st (move clients), then source */
4844 tegra_clk_shared_bus_update(dst_bus);
4845 tegra_clk_shared_bus_update(src_bus);
4850 static struct clk_ops tegra_clk_cbus_ops = {
4851 .init = tegra11_clk_cbus_init,
4852 .enable = tegra11_clk_cbus_enable,
4853 .set_rate = tegra11_clk_cbus_set_rate,
4854 .round_rate = tegra11_clk_cbus_round_rate,
4855 .shared_bus_update = tegra11_clk_cbus_update,
4858 /* shared bus ops */
4860 * Some clocks may have multiple downstream users that need to request a
4861 * higher clock rate. Shared bus clocks provide a unique shared_bus_user
4862 * clock to each user. The frequency of the bus is set to the highest
4863 * enabled shared_bus_user clock, with a minimum value set by the
4866 * Optionally shared bus may support users migration. Since shared bus and
4867 * its * children (users) have reversed rate relations: user rates determine
4868 * bus rate, * switching user from one parent/bus to another may change rates
4869 * of both parents. Therefore we need a cross-bus lock on top of individual
4870 * user and bus locks. For now, limit bus switch support to cbus only if
4871 * CONFIG_TEGRA_MIGRATE_CBUS_USERS is set.
4874 static unsigned long tegra11_clk_shared_bus_update(
4875 struct clk *bus, struct clk **bus_top, struct clk **bus_slow)
4878 struct clk *slow = NULL;
4879 struct clk *top = NULL;
4881 unsigned long override_rate = 0;
4882 unsigned long top_rate = 0;
4883 unsigned long rate = bus->min_rate;
4884 unsigned long bw = 0;
4885 unsigned long ceiling = bus->max_rate;
4886 u8 emc_bw_efficiency = tegra_emc_bw_efficiency;
4888 list_for_each_entry(c, &bus->shared_bus_list,
4889 u.shared_bus_user.node) {
4891 * Ignore requests from disabled floor and bw users, and from
4892 * auto-users riding the bus. Always honor ceiling users, even
4893 * if they are disabled - we do not want to keep enabled parent
4894 * bus just because ceiling is set.
4896 if (c->u.shared_bus_user.enabled ||
4897 (c->u.shared_bus_user.mode == SHARED_CEILING)) {
4898 unsigned long request_rate = c->u.shared_bus_user.rate *
4901 switch (c->u.shared_bus_user.mode) {
4904 if (bw > bus->max_rate)
4907 case SHARED_CEILING:
4908 ceiling = min(request_rate, ceiling);
4910 case SHARED_OVERRIDE:
4911 if (override_rate == 0)
4912 override_rate = request_rate;
4918 rate = max(request_rate, rate);
4919 if (c->u.shared_bus_user.client
4921 if (top_rate < request_rate) {
4922 top_rate = request_rate;
4924 } else if ((top_rate == request_rate) &&
4925 bus_user_is_slower(c, top)) {
4930 if (c->u.shared_bus_user.client &&
4931 (!slow || bus_user_is_slower(c, slow)))
4936 if ((bus->flags & PERIPH_EMC_ENB) && bw && (emc_bw_efficiency < 100)) {
4937 bw = emc_bw_efficiency ?
4938 (bw / emc_bw_efficiency) : bus->max_rate;
4939 bw = (bw < bus->max_rate / 100) ? (bw * 100) : bus->max_rate;
4942 rate = override_rate ? : min(max(rate, bw), ceiling);
4951 static int tegra_clk_shared_bus_migrate_users(struct clk *user)
4953 if (detach_shared_bus)
4956 /* Only cbus migration is supported */
4957 if (user->flags & PERIPH_ON_CBUS)
4958 return tegra11_clk_cbus_migrate_users(user);
4962 static void tegra_clk_shared_bus_user_init(struct clk *c)
4964 c->max_rate = c->parent->max_rate;
4965 c->u.shared_bus_user.rate = c->parent->max_rate;
4969 if (c->u.shared_bus_user.mode == SHARED_CEILING) {
4974 if (c->u.shared_bus_user.client_id) {
4975 c->u.shared_bus_user.client =
4976 tegra_get_clock_by_name(c->u.shared_bus_user.client_id);
4977 if (!c->u.shared_bus_user.client) {
4978 pr_err("%s: could not find clk %s\n", __func__,
4979 c->u.shared_bus_user.client_id);
4982 c->u.shared_bus_user.client->flags |=
4983 c->parent->flags & PERIPH_ON_CBUS;
4984 c->flags |= c->parent->flags & PERIPH_ON_CBUS;
4985 c->div = c->u.shared_bus_user.client_div ? : 1;
4989 list_add_tail(&c->u.shared_bus_user.node,
4990 &c->parent->shared_bus_list);
4993 static int tegra_clk_shared_bus_user_set_parent(struct clk *c, struct clk *p)
4996 const struct clk_mux_sel *sel;
4998 if (detach_shared_bus)
5004 if (!(c->inputs && c->cross_clk_mutex && clk_cansleep(c)))
5007 for (sel = c->inputs; sel->input != NULL; sel++) {
5008 if (sel->input == p)
5017 list_move_tail(&c->u.shared_bus_user.node, &p->shared_bus_list);
5018 ret = tegra_clk_shared_bus_update(p);
5020 list_move_tail(&c->u.shared_bus_user.node,
5021 &c->parent->shared_bus_list);
5022 tegra_clk_shared_bus_update(c->parent);
5027 tegra_clk_shared_bus_update(c->parent);
5030 clk_disable(c->parent);
5037 static int tegra_clk_shared_bus_user_set_rate(struct clk *c, unsigned long rate)
5041 c->u.shared_bus_user.rate = rate;
5042 ret = tegra_clk_shared_bus_update(c->parent);
5044 if (!ret && c->cross_clk_mutex && clk_cansleep(c))
5045 tegra_clk_shared_bus_migrate_users(c);
5050 static long tegra_clk_shared_bus_user_round_rate(
5051 struct clk *c, unsigned long rate)
5053 /* Defer rounding requests until aggregated. BW users must not be
5054 rounded at all, others just clipped to bus range (some clients
5055 may use round api to find limits) */
5056 if (c->u.shared_bus_user.mode != SHARED_BW) {
5060 if (rate > c->parent->max_rate)
5061 rate = c->parent->max_rate;
5062 else if (rate < c->parent->min_rate)
5063 rate = c->parent->min_rate;
5071 static int tegra_clk_shared_bus_user_enable(struct clk *c)
5075 c->u.shared_bus_user.enabled = true;
5076 ret = tegra_clk_shared_bus_update(c->parent);
5077 if (!ret && c->u.shared_bus_user.client)
5078 ret = clk_enable(c->u.shared_bus_user.client);
5080 if (!ret && c->cross_clk_mutex && clk_cansleep(c))
5081 tegra_clk_shared_bus_migrate_users(c);
5086 static void tegra_clk_shared_bus_user_disable(struct clk *c)
5088 if (c->u.shared_bus_user.client)
5089 clk_disable(c->u.shared_bus_user.client);
5090 c->u.shared_bus_user.enabled = false;
5091 tegra_clk_shared_bus_update(c->parent);
5093 if (c->cross_clk_mutex && clk_cansleep(c))
5094 tegra_clk_shared_bus_migrate_users(c);
5097 static void tegra_clk_shared_bus_user_reset(struct clk *c, bool assert)
5099 if (c->u.shared_bus_user.client) {
5100 if (c->u.shared_bus_user.client->ops &&
5101 c->u.shared_bus_user.client->ops->reset)
5102 c->u.shared_bus_user.client->ops->reset(
5103 c->u.shared_bus_user.client, assert);
5107 static struct clk_ops tegra_clk_shared_bus_user_ops = {
5108 .init = tegra_clk_shared_bus_user_init,
5109 .enable = tegra_clk_shared_bus_user_enable,
5110 .disable = tegra_clk_shared_bus_user_disable,
5111 .set_parent = tegra_clk_shared_bus_user_set_parent,
5112 .set_rate = tegra_clk_shared_bus_user_set_rate,
5113 .round_rate = tegra_clk_shared_bus_user_round_rate,
5114 .reset = tegra_clk_shared_bus_user_reset,
5117 /* coupled gate ops */
5119 * Some clocks may have common enable/disable control, but run at different
5120 * rates, and have different dvfs tables. Coupled gate clock synchronize
5121 * enable/disable operations for such clocks.
5124 static int tegra11_clk_coupled_gate_enable(struct clk *c)
5127 const struct clk_mux_sel *sel;
5130 pr_debug("%s on clock %s\n", __func__, c->name);
5132 for (sel = c->inputs; sel->input != NULL; sel++) {
5133 if (sel->input == c->parent)
5136 ret = clk_enable(sel->input);
5138 while(sel != c->inputs) {
5140 if (sel->input == c->parent)
5142 clk_disable(sel->input);
5148 return tegra11_periph_clk_enable(c);
5151 static void tegra11_clk_coupled_gate_disable(struct clk *c)
5153 const struct clk_mux_sel *sel;
5156 pr_debug("%s on clock %s\n", __func__, c->name);
5158 tegra11_periph_clk_disable(c);
5160 if (!c->refcnt) /* happens only on boot clean-up: don't propagate */
5163 for (sel = c->inputs; sel->input != NULL; sel++) {
5164 if (sel->input == c->parent)
5167 if (sel->input->set) /* enforce coupling after boot only */
5168 clk_disable(sel->input);
5172 static struct clk_ops tegra_clk_coupled_gate_ops = {
5173 .init = tegra11_periph_clk_init,
5174 .enable = tegra11_clk_coupled_gate_enable,
5175 .disable = tegra11_clk_coupled_gate_disable,
5176 .reset = &tegra11_periph_clk_reset,
5180 /* Clock definitions */
5181 static struct clk tegra_clk_32k = {
5188 static struct clk tegra_clk_m = {
5190 .flags = ENABLE_ON_INIT,
5191 .ops = &tegra_clk_m_ops,
5194 .max_rate = 48000000,
5197 static struct clk tegra_clk_m_div2 = {
5198 .name = "clk_m_div2",
5199 .ops = &tegra_clk_m_div_ops,
5200 .parent = &tegra_clk_m,
5204 .max_rate = 24000000,
5207 static struct clk tegra_clk_m_div4 = {
5208 .name = "clk_m_div4",
5209 .ops = &tegra_clk_m_div_ops,
5210 .parent = &tegra_clk_m,
5214 .max_rate = 12000000,
5217 static struct clk tegra_pll_ref = {
5219 .flags = ENABLE_ON_INIT,
5220 .ops = &tegra_pll_ref_ops,
5221 .parent = &tegra_clk_m,
5222 .max_rate = 26000000,
5225 static struct clk_pll_freq_table tegra_pll_c_freq_table[] = {
5226 { 12000000, 624000000, 104, 1, 2},
5227 { 12000000, 600000000, 100, 1, 2},
5228 { 13000000, 600000000, 92, 1, 2}, /* actual: 598.0 MHz */
5229 { 16800000, 600000000, 71, 1, 2}, /* actual: 596.4 MHz */
5230 { 19200000, 600000000, 62, 1, 2}, /* actual: 595.2 MHz */
5231 { 26000000, 600000000, 92, 2, 2}, /* actual: 598.0 MHz */
5232 { 0, 0, 0, 0, 0, 0 },
5235 static struct clk tegra_pll_c = {
5237 .ops = &tegra_pllxc_ops,
5239 .parent = &tegra_pll_ref,
5240 .max_rate = 1400000000,
5242 .input_min = 12000000,
5243 .input_max = 800000000,
5245 .cf_max = 19200000, /* s/w policy, h/w capability 50 MHz */
5246 .vco_min = 600000000,
5247 .vco_max = 1400000000,
5248 .freq_table = tegra_pll_c_freq_table,
5250 .misc1 = 0x88 - 0x80,
5251 .round_p_to_pdiv = pllxc_round_p_to_pdiv,
5255 static struct clk tegra_pll_c_out1 = {
5256 .name = "pll_c_out1",
5257 .ops = &tegra_pll_div_ops,
5258 #ifdef CONFIG_TEGRA_DUAL_CBUS
5259 .flags = DIV_U71 | DIV_U71_INT,
5261 .flags = DIV_U71 | DIV_U71_INT | PERIPH_ON_CBUS,
5263 .parent = &tegra_pll_c,
5266 .max_rate = 700000000,
5269 static struct clk_pll_freq_table tegra_pll_cx_freq_table[] = {
5270 { 12000000, 600000000, 100, 1, 2},
5271 { 13000000, 600000000, 92, 1, 2}, /* actual: 598.0 MHz */
5272 { 16800000, 600000000, 71, 1, 2}, /* actual: 596.4 MHz */
5273 { 19200000, 600000000, 62, 1, 2}, /* actual: 595.2 MHz */
5274 { 26000000, 600000000, 92, 2, 2}, /* actual: 598.0 MHz */
5275 { 0, 0, 0, 0, 0, 0 },
5278 static struct clk tegra_pll_c2 = {
5280 .ops = &tegra_pllcx_ops,
5281 .flags = PLL_ALT_MISC_REG,
5283 .parent = &tegra_pll_ref,
5284 .max_rate = 1200000000,
5286 .input_min = 12000000,
5287 .input_max = 48000000,
5290 .vco_min = 624000000,
5291 .vco_max = 1248000000,
5292 .freq_table = tegra_pll_cx_freq_table,
5294 .misc1 = 0x4f0 - 0x4e8,
5295 .round_p_to_pdiv = pllcx_round_p_to_pdiv,
5299 static struct clk tegra_pll_c3 = {
5301 .ops = &tegra_pllcx_ops,
5302 .flags = PLL_ALT_MISC_REG,
5304 .parent = &tegra_pll_ref,
5305 .max_rate = 1200000000,
5307 .input_min = 12000000,
5308 .input_max = 48000000,
5311 .vco_min = 624000000,
5312 .vco_max = 1248000000,
5313 .freq_table = tegra_pll_cx_freq_table,
5315 .misc1 = 0x504 - 0x4fc,
5316 .round_p_to_pdiv = pllcx_round_p_to_pdiv,
5320 static struct clk_pll_freq_table tegra_pll_m_freq_table[] = {
5321 { 12000000, 800000000, 66, 1, 1}, /* actual: 792.0 MHz */
5322 { 13000000, 800000000, 61, 1, 1}, /* actual: 793.0 MHz */
5323 { 16800000, 800000000, 47, 1, 1}, /* actual: 789.6 MHz */
5324 { 19200000, 800000000, 41, 1, 1}, /* actual: 787.2 MHz */
5325 { 26000000, 800000000, 61, 2, 1}, /* actual: 793.0 MHz */
5326 { 0, 0, 0, 0, 0, 0 },
5329 static struct clk tegra_pll_m = {
5332 .ops = &tegra_pllm_ops,
5334 .parent = &tegra_pll_ref,
5335 .max_rate = 1066000000,
5337 .input_min = 12000000,
5338 .input_max = 500000000,
5340 .cf_max = 19200000, /* s/w policy, h/w capability 50 MHz */
5341 .vco_min = 400000000,
5342 .vco_max = 1066000000,
5343 .freq_table = tegra_pll_m_freq_table,
5345 .misc1 = 0x98 - 0x90,
5346 .round_p_to_pdiv = pllm_round_p_to_pdiv,
5350 static struct clk tegra_pll_m_out1 = {
5351 .name = "pll_m_out1",
5352 .ops = &tegra_pll_div_ops,
5353 .flags = DIV_U71 | DIV_U71_INT,
5354 .parent = &tegra_pll_m,
5357 .max_rate = 600000000,
5360 static struct clk_pll_freq_table tegra_pll_p_freq_table[] = {
5361 { 12000000, 216000000, 432, 12, 2, 8},
5362 { 13000000, 216000000, 432, 13, 2, 8},
5363 { 16800000, 216000000, 360, 14, 2, 8},
5364 { 19200000, 216000000, 360, 16, 2, 8},
5365 { 26000000, 216000000, 432, 26, 2, 8},
5366 { 0, 0, 0, 0, 0, 0 },
5369 static struct clk tegra_pll_p = {
5371 .flags = ENABLE_ON_INIT | PLL_FIXED | PLL_HAS_CPCON,
5372 .ops = &tegra_pllp_ops,
5374 .parent = &tegra_pll_ref,
5375 .max_rate = 432000000,
5377 .input_min = 2000000,
5378 .input_max = 31000000,
5381 .vco_min = 200000000,
5382 .vco_max = 700000000,
5383 .freq_table = tegra_pll_p_freq_table,
5388 static struct clk tegra_pll_p_out1 = {
5389 .name = "pll_p_out1",
5390 .ops = &tegra_pll_div_ops,
5391 .flags = DIV_U71 | DIV_U71_FIXED,
5392 .parent = &tegra_pll_p,
5395 .max_rate = 432000000,
5398 static struct clk tegra_pll_p_out2 = {
5399 .name = "pll_p_out2",
5400 .ops = &tegra_pll_div_ops,
5401 .flags = DIV_U71 | DIV_U71_FIXED | DIV_U71_INT,
5402 .parent = &tegra_pll_p,
5405 .max_rate = 432000000,
5408 static struct clk tegra_pll_p_out3 = {
5409 .name = "pll_p_out3",
5410 .ops = &tegra_pll_div_ops,
5411 .flags = DIV_U71 | DIV_U71_FIXED,
5412 .parent = &tegra_pll_p,
5415 .max_rate = 432000000,
5418 static struct clk tegra_pll_p_out4 = {
5419 .name = "pll_p_out4",
5420 .ops = &tegra_pll_div_ops,
5421 .flags = DIV_U71 | DIV_U71_FIXED,
5422 .parent = &tegra_pll_p,
5425 .max_rate = 432000000,
5428 static struct clk_pll_freq_table tegra_pll_a_freq_table[] = {
5429 { 9600000, 282240000, 147, 5, 1, 4},
5430 { 9600000, 368640000, 192, 5, 1, 4},
5431 { 9600000, 240000000, 200, 8, 1, 8},
5433 { 28800000, 282240000, 245, 25, 1, 8},
5434 { 28800000, 368640000, 320, 25, 1, 8},
5435 { 28800000, 240000000, 200, 24, 1, 8},
5436 { 0, 0, 0, 0, 0, 0 },
5439 static struct clk tegra_pll_a = {
5441 .flags = PLL_HAS_CPCON,
5442 .ops = &tegra_pll_ops,
5444 .parent = &tegra_pll_p_out1,
5445 .max_rate = 700000000,
5447 .input_min = 2000000,
5448 .input_max = 31000000,
5451 .vco_min = 200000000,
5452 .vco_max = 700000000,
5453 .freq_table = tegra_pll_a_freq_table,
5458 static struct clk tegra_pll_a_out0 = {
5459 .name = "pll_a_out0",
5460 .ops = &tegra_pll_div_ops,
5462 .parent = &tegra_pll_a,
5465 .max_rate = 100000000,
5468 static struct clk_pll_freq_table tegra_pll_d_freq_table[] = {
5469 { 12000000, 216000000, 864, 12, 4, 12},
5470 { 13000000, 216000000, 864, 13, 4, 12},
5471 { 16800000, 216000000, 720, 14, 4, 12},
5472 { 19200000, 216000000, 720, 16, 4, 12},
5473 { 26000000, 216000000, 864, 26, 4, 12},
5475 { 12000000, 594000000, 99, 2, 1, 8},
5476 { 13000000, 594000000, 594, 13, 1, 12},
5477 { 16800000, 594000000, 495, 14, 1, 12},
5478 { 19200000, 594000000, 495, 16, 1, 12},
5479 { 26000000, 594000000, 594, 26, 1, 12},
5481 { 12000000, 1000000000, 1000, 12, 1, 12},
5482 { 13000000, 1000000000, 1000, 13, 1, 12},
5483 { 19200000, 1000000000, 625, 12, 1, 12},
5484 { 26000000, 1000000000, 1000, 26, 1, 12},
5486 { 0, 0, 0, 0, 0, 0 },
5489 static struct clk tegra_pll_d = {
5491 .flags = PLL_HAS_CPCON | PLLD,
5492 .ops = &tegra_plld_ops,
5494 .parent = &tegra_pll_ref,
5495 .max_rate = 1000000000,
5497 .input_min = 2000000,
5498 .input_max = 40000000,
5501 .vco_min = 500000000,
5502 .vco_max = 1000000000,
5503 .freq_table = tegra_pll_d_freq_table,
5508 static struct clk tegra_pll_d_out0 = {
5509 .name = "pll_d_out0",
5510 .ops = &tegra_pll_div_ops,
5511 .flags = DIV_2 | PLLD,
5512 .parent = &tegra_pll_d,
5513 .max_rate = 500000000,
5516 static struct clk tegra_pll_d2 = {
5518 .flags = PLL_HAS_CPCON | PLL_ALT_MISC_REG | PLLD,
5519 .ops = &tegra_plld_ops,
5521 .parent = &tegra_pll_ref,
5522 .max_rate = 1000000000,
5524 .input_min = 2000000,
5525 .input_max = 40000000,
5528 .vco_min = 500000000,
5529 .vco_max = 1000000000,
5530 .freq_table = tegra_pll_d_freq_table,
5535 static struct clk tegra_pll_d2_out0 = {
5536 .name = "pll_d2_out0",
5537 .ops = &tegra_pll_div_ops,
5538 .flags = DIV_2 | PLLD,
5539 .parent = &tegra_pll_d2,
5540 .max_rate = 500000000,
5543 static struct clk_pll_freq_table tegra_pll_u_freq_table[] = {
5544 { 12000000, 480000000, 960, 12, 2, 12},
5545 { 13000000, 480000000, 960, 13, 2, 12},
5546 { 16800000, 480000000, 400, 7, 2, 5},
5547 { 19200000, 480000000, 200, 4, 2, 3},
5548 { 26000000, 480000000, 960, 26, 2, 12},
5549 { 0, 0, 0, 0, 0, 0 },
5552 static struct clk tegra_pll_u = {
5554 .flags = PLL_HAS_CPCON | PLLU,
5555 .ops = &tegra_pll_ops,
5557 .parent = &tegra_pll_ref,
5558 .max_rate = 480000000,
5560 .input_min = 2000000,
5561 .input_max = 40000000,
5564 .vco_min = 480000000,
5565 .vco_max = 960000000,
5566 .freq_table = tegra_pll_u_freq_table,
5568 .cpcon_default = 12,
5572 static struct clk tegra_pll_u_480M = {
5573 .name = "pll_u_480M",
5575 .ops = &tegra_pll_div_ops,
5578 .parent = &tegra_pll_u,
5581 .max_rate = 480000000,
5584 static struct clk tegra_pll_u_60M = {
5585 .name = "pll_u_60M",
5587 .ops = &tegra_pll_div_ops,
5590 .parent = &tegra_pll_u,
5593 .max_rate = 60000000,
5596 static struct clk tegra_pll_u_48M = {
5597 .name = "pll_u_48M",
5599 .ops = &tegra_pll_div_ops,
5602 .parent = &tegra_pll_u,
5605 .max_rate = 48000000,
5608 static struct clk tegra_pll_u_12M = {
5609 .name = "pll_u_12M",
5611 .ops = &tegra_pll_div_ops,
5614 .parent = &tegra_pll_u,
5617 .max_rate = 12000000,
5620 static struct clk_pll_freq_table tegra_pll_x_freq_table[] = {
5622 { 12000000, 1000000000, 83, 1, 1}, /* actual: 996.0 MHz */
5623 { 13000000, 1000000000, 76, 1, 1}, /* actual: 988.0 MHz */
5624 { 16800000, 1000000000, 59, 1, 1}, /* actual: 991.2 MHz */
5625 { 19200000, 1000000000, 52, 1, 1}, /* actual: 998.4 MHz */
5626 { 26000000, 1000000000, 76, 2, 1}, /* actual: 988.0 MHz */
5628 { 0, 0, 0, 0, 0, 0 },
5631 static struct clk tegra_pll_x = {
5633 .flags = PLL_ALT_MISC_REG | PLLX,
5634 .ops = &tegra_pllxc_ops,
5636 .parent = &tegra_pll_ref,
5637 .max_rate = 1800000000,
5639 .input_min = 12000000,
5640 .input_max = 800000000,
5642 .cf_max = 19200000, /* s/w policy, h/w capability 50 MHz */
5643 .vco_min = 700000000,
5644 .vco_max = 2400000000U,
5645 .freq_table = tegra_pll_x_freq_table,
5647 .misc1 = 0x510 - 0xe0,
5648 .round_p_to_pdiv = pllxc_round_p_to_pdiv,
5652 static struct clk tegra_pll_x_out0 = {
5653 .name = "pll_x_out0",
5654 .ops = &tegra_pll_div_ops,
5655 .flags = DIV_2 | PLLX,
5656 .parent = &tegra_pll_x,
5657 .max_rate = 700000000,
5660 /* FIXME: remove; for now, should be always checked-in as "0" */
5661 #define USE_LP_CPU_TO_TEST_DFLL 0
5663 static struct clk tegra_dfll_cpu = {
5666 .ops = &tegra_dfll_ops,
5668 .max_rate = 2000000000,
5671 static struct clk tegra_pll_re_vco = {
5672 .name = "pll_re_vco",
5673 .flags = PLL_ALT_MISC_REG,
5674 .ops = &tegra_pllre_ops,
5676 .parent = &tegra_pll_ref,
5677 .max_rate = 672000000,
5679 .input_min = 12000000,
5680 .input_max = 1000000000,
5682 .cf_max = 19200000, /* s/w policy, h/w capability 38 MHz */
5683 .vco_min = 300000000,
5684 .vco_max = 672000000,
5686 .round_p_to_pdiv = pllre_round_p_to_pdiv,
5690 static struct clk tegra_pll_re_out = {
5691 .name = "pll_re_out",
5692 .ops = &tegra_pllre_out_ops,
5693 .parent = &tegra_pll_re_vco,
5695 .max_rate = 672000000,
5698 static struct clk_pll_freq_table tegra_pll_e_freq_table[] = {
5699 /* PLLE special case: use cpcon field to store cml divider value */
5700 { 336000000, 100000000, 100, 21, 16, 11},
5701 { 312000000, 100000000, 200, 26, 24, 13},
5702 { 12000000, 100000000, 200, 1, 24, 13},
5703 { 0, 0, 0, 0, 0, 0 },
5706 static struct clk tegra_pll_e = {
5708 .flags = PLL_ALT_MISC_REG,
5709 .ops = &tegra_plle_ops,
5711 .max_rate = 100000000,
5713 .input_min = 12000000,
5714 .input_max = 1000000000,
5717 .vco_min = 1600000000,
5718 .vco_max = 2400000000U,
5719 .freq_table = tegra_pll_e_freq_table,
5721 .fixed_rate = 100000000,
5725 static struct clk tegra_pciex_clk = {
5727 .parent = &tegra_pll_e,
5728 .ops = &tegra_pciex_clk_ops,
5729 .max_rate = 100000000,
5735 /* Audio sync clocks */
5736 #define SYNC_SOURCE(_id, _dev) \
5738 .name = #_id "_sync", \
5741 .con_id = "ext_audio_sync", \
5744 .max_rate = 24000000, \
5745 .ops = &tegra_sync_source_ops \
5747 static struct clk tegra_sync_source_list[] = {
5748 SYNC_SOURCE(spdif_in, tegra30-spdif),
5749 SYNC_SOURCE(i2s0, tegra30-i2s.0),
5750 SYNC_SOURCE(i2s1, tegra30-i2s.1),
5751 SYNC_SOURCE(i2s2, tegra30-i2s.2),
5752 SYNC_SOURCE(i2s3, tegra30-i2s.3),
5753 SYNC_SOURCE(i2s4, tegra30-i2s.4),
5754 SYNC_SOURCE(vimclk, vimclk),
5757 static struct clk_mux_sel mux_d_audio_clk[] = {
5758 { .input = &tegra_pll_a_out0, .value = 0},
5759 { .input = &tegra_pll_p, .value = 0x8000},
5760 { .input = &tegra_clk_m, .value = 0xc000},
5761 { .input = &tegra_sync_source_list[0], .value = 0xE000},
5762 { .input = &tegra_sync_source_list[1], .value = 0xE001},
5763 { .input = &tegra_sync_source_list[2], .value = 0xE002},
5764 { .input = &tegra_sync_source_list[3], .value = 0xE003},
5765 { .input = &tegra_sync_source_list[4], .value = 0xE004},
5766 { .input = &tegra_sync_source_list[5], .value = 0xE005},
5767 { .input = &tegra_pll_a_out0, .value = 0xE006},
5768 { .input = &tegra_sync_source_list[6], .value = 0xE007},
5772 static struct clk_mux_sel mux_audio_sync_clk[] =
5774 { .input = &tegra_sync_source_list[0], .value = 0},
5775 { .input = &tegra_sync_source_list[1], .value = 1},
5776 { .input = &tegra_sync_source_list[2], .value = 2},
5777 { .input = &tegra_sync_source_list[3], .value = 3},
5778 { .input = &tegra_sync_source_list[4], .value = 4},
5779 { .input = &tegra_sync_source_list[5], .value = 5},
5780 { .input = &tegra_pll_a_out0, .value = 6},
5781 { .input = &tegra_sync_source_list[6], .value = 7},
5785 #define AUDIO_SYNC_CLK(_id, _dev, _index) \
5790 .con_id = "audio_sync", \
5792 .inputs = mux_audio_sync_clk, \
5793 .reg = 0x4A0 + (_index) * 4, \
5794 .max_rate = 24000000, \
5795 .ops = &tegra_audio_sync_clk_ops \
5797 static struct clk tegra_clk_audio_list[] = {
5798 AUDIO_SYNC_CLK(audio0, tegra30-i2s.0, 0),
5799 AUDIO_SYNC_CLK(audio1, tegra30-i2s.1, 1),
5800 AUDIO_SYNC_CLK(audio2, tegra30-i2s.2, 2),
5801 AUDIO_SYNC_CLK(audio3, tegra30-i2s.3, 3),
5802 AUDIO_SYNC_CLK(audio4, tegra30-i2s.4, 4),
5803 AUDIO_SYNC_CLK(audio, tegra30-spdif, 5), /* SPDIF */
5806 #define AUDIO_SYNC_2X_CLK(_id, _dev, _index) \
5808 .name = #_id "_2x", \
5811 .con_id = "audio_sync_2x" \
5813 .flags = PERIPH_NO_RESET, \
5814 .max_rate = 48000000, \
5815 .ops = &tegra_clk_double_ops, \
5817 .reg_shift = 24 + (_index), \
5818 .parent = &tegra_clk_audio_list[(_index)], \
5820 .clk_num = 113 + (_index), \
5823 static struct clk tegra_clk_audio_2x_list[] = {
5824 AUDIO_SYNC_2X_CLK(audio0, tegra30-i2s.0, 0),
5825 AUDIO_SYNC_2X_CLK(audio1, tegra30-i2s.1, 1),
5826 AUDIO_SYNC_2X_CLK(audio2, tegra30-i2s.2, 2),
5827 AUDIO_SYNC_2X_CLK(audio3, tegra30-i2s.3, 3),
5828 AUDIO_SYNC_2X_CLK(audio4, tegra30-i2s.4, 4),
5829 AUDIO_SYNC_2X_CLK(audio, tegra30-spdif, 5), /* SPDIF */
5832 #define MUX_I2S_SPDIF(_id, _index) \
5833 static struct clk_mux_sel mux_pllaout0_##_id##_2x_pllp_clkm[] = { \
5834 {.input = &tegra_pll_a_out0, .value = 0}, \
5835 {.input = &tegra_clk_audio_2x_list[(_index)], .value = 1}, \
5836 {.input = &tegra_pll_p, .value = 2}, \
5837 {.input = &tegra_clk_m, .value = 3}, \
5840 MUX_I2S_SPDIF(audio0, 0);
5841 MUX_I2S_SPDIF(audio1, 1);
5842 MUX_I2S_SPDIF(audio2, 2);
5843 MUX_I2S_SPDIF(audio3, 3);
5844 MUX_I2S_SPDIF(audio4, 4);
5845 MUX_I2S_SPDIF(audio, 5); /* SPDIF */
5847 /* External clock outputs (through PMC) */
5848 #define MUX_EXTERN_OUT(_id) \
5849 static struct clk_mux_sel mux_clkm_clkm2_clkm4_extern##_id[] = { \
5850 {.input = &tegra_clk_m, .value = 0}, \
5851 {.input = &tegra_clk_m_div2, .value = 1}, \
5852 {.input = &tegra_clk_m_div4, .value = 2}, \
5853 {.input = NULL, .value = 3}, /* placeholder */ \
5860 static struct clk_mux_sel *mux_extern_out_list[] = {
5861 mux_clkm_clkm2_clkm4_extern1,
5862 mux_clkm_clkm2_clkm4_extern2,
5863 mux_clkm_clkm2_clkm4_extern3,
5866 #define CLK_OUT_CLK(_id, _max_rate) \
5868 .name = "clk_out_" #_id, \
5870 .dev_id = "clk_out_" #_id, \
5871 .con_id = "extern" #_id, \
5873 .ops = &tegra_clk_out_ops, \
5875 .inputs = mux_clkm_clkm2_clkm4_extern##_id, \
5876 .flags = MUX_CLK_OUT, \
5877 .max_rate = _max_rate, \
5879 .clk_num = (_id - 1) * 8 + 2, \
5882 static struct clk tegra_clk_out_list[] = {
5883 CLK_OUT_CLK(1, 12288000),
5884 CLK_OUT_CLK(2, 40800000),
5885 CLK_OUT_CLK(3, 12288000),
5888 /* called after peripheral external clocks are initialized */
5889 static void init_clk_out_mux(void)
5894 /* output clock con_id is the name of peripheral
5895 external clock connected to input 3 of the output mux */
5896 for (i = 0; i < ARRAY_SIZE(tegra_clk_out_list); i++) {
5897 c = tegra_get_clock_by_name(
5898 tegra_clk_out_list[i].lookup.con_id);
5900 pr_err("%s: could not find clk %s\n", __func__,
5901 tegra_clk_out_list[i].lookup.con_id);
5902 mux_extern_out_list[i][3].input = c;
5906 /* Peripheral muxes */
5907 static struct clk_mux_sel mux_cclk_g[] = {
5908 { .input = &tegra_clk_m, .value = 0},
5909 { .input = &tegra_pll_c, .value = 1},
5910 { .input = &tegra_clk_32k, .value = 2},
5911 { .input = &tegra_pll_m, .value = 3},
5912 { .input = &tegra_pll_p, .value = 4},
5913 { .input = &tegra_pll_p_out4, .value = 5},
5914 /* { .input = &tegra_pll_c2, .value = 6}, - no use on tegra11x */
5915 /* { .input = &tegra_clk_c3, .value = 7}, - no use on tegra11x */
5916 { .input = &tegra_pll_x, .value = 8},
5917 { .input = &tegra_dfll_cpu, .value = 15},
5921 static struct clk_mux_sel mux_cclk_lp[] = {
5922 { .input = &tegra_clk_m, .value = 0},
5923 { .input = &tegra_pll_c, .value = 1},
5924 { .input = &tegra_clk_32k, .value = 2},
5925 { .input = &tegra_pll_m, .value = 3},
5926 { .input = &tegra_pll_p, .value = 4},
5927 { .input = &tegra_pll_p_out4, .value = 5},
5928 /* { .input = &tegra_pll_c2, .value = 6}, - no use on tegra11x */
5929 /* { .input = &tegra_clk_c3, .value = 7}, - no use on tegra11x */
5930 { .input = &tegra_pll_x_out0, .value = 8},
5931 #if USE_LP_CPU_TO_TEST_DFLL
5932 { .input = &tegra_dfll_cpu, .value = 15},
5934 { .input = &tegra_pll_x, .value = 8 | SUPER_LP_DIV2_BYPASS},
5938 static struct clk_mux_sel mux_sclk[] = {
5939 { .input = &tegra_clk_m, .value = 0},
5940 { .input = &tegra_pll_c_out1, .value = 1},
5941 { .input = &tegra_pll_p_out4, .value = 2},
5942 { .input = &tegra_pll_p, .value = 3},
5943 { .input = &tegra_pll_p_out2, .value = 4},
5944 /* { .input = &tegra_clk_d, .value = 5}, - no use on tegra11x */
5945 { .input = &tegra_clk_32k, .value = 6},
5946 { .input = &tegra_pll_m_out1, .value = 7},
5950 static struct clk tegra_clk_cclk_g = {
5952 .flags = DIV_U71 | DIV_U71_INT | MUX,
5953 .inputs = mux_cclk_g,
5955 .ops = &tegra_super_ops,
5956 .max_rate = 2000000000,
5959 static struct clk tegra_clk_cclk_lp = {
5961 .flags = DIV_2 | DIV_U71 | DIV_U71_INT | MUX,
5962 .inputs = mux_cclk_lp,
5964 .ops = &tegra_super_ops,
5965 .max_rate = 816000000,
5968 static struct clk tegra_clk_sclk = {
5972 .ops = &tegra_super_ops,
5973 .max_rate = 384000000,
5974 .min_rate = 12000000,
5977 static struct clk tegra_clk_virtual_cpu_g = {
5979 .parent = &tegra_clk_cclk_g,
5980 .ops = &tegra_cpu_ops,
5981 .max_rate = 2000000000,
5983 .main = &tegra_pll_x,
5984 .backup = &tegra_pll_p_out4,
5985 .dynamic = &tegra_dfll_cpu,
5990 static struct clk tegra_clk_virtual_cpu_lp = {
5992 .parent = &tegra_clk_cclk_lp,
5993 .ops = &tegra_cpu_ops,
5994 .max_rate = 816000000,
5996 .main = &tegra_pll_x,
5997 .backup = &tegra_pll_p_out4,
5998 #if USE_LP_CPU_TO_TEST_DFLL
5999 .dynamic = &tegra_dfll_cpu,
6005 static struct clk_mux_sel mux_cpu_cmplx[] = {
6006 { .input = &tegra_clk_virtual_cpu_g, .value = 0},
6007 { .input = &tegra_clk_virtual_cpu_lp, .value = 1},
6011 static struct clk tegra_clk_cpu_cmplx = {
6013 .inputs = mux_cpu_cmplx,
6014 .ops = &tegra_cpu_cmplx_ops,
6015 .max_rate = 2000000000,
6018 static struct clk tegra_clk_cop = {
6020 .parent = &tegra_clk_sclk,
6021 .ops = &tegra_cop_ops,
6022 .max_rate = 384000000,
6025 static struct clk tegra_clk_hclk = {
6028 .parent = &tegra_clk_sclk,
6031 .ops = &tegra_bus_ops,
6032 .max_rate = 384000000,
6033 .min_rate = 12000000,
6036 static struct clk tegra_clk_pclk = {
6039 .parent = &tegra_clk_hclk,
6042 .ops = &tegra_bus_ops,
6043 .max_rate = 192000000,
6044 .min_rate = 12000000,
6047 static struct raw_notifier_head sbus_rate_change_nh;
6049 static struct clk tegra_clk_sbus_cmplx = {
6051 .parent = &tegra_clk_sclk,
6052 .ops = &tegra_sbus_cmplx_ops,
6054 .pclk = &tegra_clk_pclk,
6055 .hclk = &tegra_clk_hclk,
6056 .sclk_low = &tegra_pll_p_out2,
6057 #ifdef CONFIG_TEGRA_PLLM_SCALED
6058 .sclk_high = &tegra_pll_c_out1,
6060 .sclk_high = &tegra_pll_m_out1,
6063 .rate_change_nh = &sbus_rate_change_nh,
6066 static struct clk tegra_clk_blink = {
6068 .parent = &tegra_clk_32k,
6070 .ops = &tegra_blink_clk_ops,
6075 /* Multimedia modules muxes */
6076 static struct clk_mux_sel mux_pllm_pllc2_c_c3_pllp_plla[] = {
6077 { .input = &tegra_pll_m, .value = 0},
6078 { .input = &tegra_pll_c2, .value = 1},
6079 { .input = &tegra_pll_c, .value = 2},
6080 { .input = &tegra_pll_c3, .value = 3},
6081 { .input = &tegra_pll_p, .value = 4},
6082 { .input = &tegra_pll_a_out0, .value = 6},
6086 static struct clk_mux_sel mux_pllm_pllc_pllp_plla[] = {
6087 { .input = &tegra_pll_m, .value = 0},
6088 { .input = &tegra_pll_c, .value = 1},
6089 { .input = &tegra_pll_p, .value = 2},
6090 { .input = &tegra_pll_a_out0, .value = 3},
6094 static struct clk_mux_sel mux_plla_pllc_pllp_clkm[] = {
6095 { .input = &tegra_pll_a_out0, .value = 0},
6096 { .input = &tegra_pll_c, .value = 1},
6097 { .input = &tegra_pll_p, .value = 2},
6098 { .input = &tegra_clk_m, .value = 3},
6103 /* FIXME: add EMC latency mux */
6104 static struct clk_mux_sel mux_pllm_pllc_pllp_clkm[] = {
6105 { .input = &tegra_pll_m, .value = 0},
6106 { .input = &tegra_pll_c, .value = 1},
6107 { .input = &tegra_pll_p, .value = 2},
6108 { .input = &tegra_clk_m, .value = 3},
6109 { .input = &tegra_pll_m, .value = 4}, /* low jitter PLLM input */
6114 /* Display subsystem muxes */
6115 static struct clk_mux_sel mux_pllp_pllm_plld_plla_pllc_plld2_clkm[] = {
6116 {.input = &tegra_pll_p, .value = 0},
6117 {.input = &tegra_pll_m, .value = 1},
6118 {.input = &tegra_pll_d_out0, .value = 2},
6119 {.input = &tegra_pll_a_out0, .value = 3},
6120 {.input = &tegra_pll_c, .value = 4},
6121 {.input = &tegra_pll_d2_out0, .value = 5},
6122 {.input = &tegra_clk_m, .value = 6},
6126 static struct clk_mux_sel mux_plld_out0_plld2_out0[] = {
6127 { .input = &tegra_pll_d_out0, .value = 0},
6128 { .input = &tegra_pll_d2_out0, .value = 1},
6132 static struct clk_mux_sel mux_pllp_pllc_clkm[] = {
6133 {.input = &tegra_pll_p, .value = 0},
6134 {.input = &tegra_pll_c, .value = 1},
6135 {.input = &tegra_clk_m, .value = 3},
6139 /* Peripheral muxes */
6140 static struct clk_mux_sel mux_pllp_pllc2_c_c3_pllm_clkm[] = {
6141 { .input = &tegra_pll_p, .value = 0},
6142 { .input = &tegra_pll_c2, .value = 1},
6143 { .input = &tegra_pll_c, .value = 2},
6144 { .input = &tegra_pll_c3, .value = 3},
6145 { .input = &tegra_pll_m, .value = 4},
6146 { .input = &tegra_clk_m, .value = 6},
6150 static struct clk_mux_sel mux_pllp_pllc_pllm_clkm[] = {
6151 { .input = &tegra_pll_p, .value = 0},
6152 { .input = &tegra_pll_c, .value = 1},
6153 { .input = &tegra_pll_m, .value = 2},
6154 { .input = &tegra_clk_m, .value = 3},
6158 static struct clk_mux_sel mux_pllp_pllc_pllm[] = {
6159 {.input = &tegra_pll_p, .value = 0},
6160 {.input = &tegra_pll_c, .value = 1},
6161 {.input = &tegra_pll_m, .value = 2},
6165 static struct clk_mux_sel mux_pllp_clkm[] = {
6166 { .input = &tegra_pll_p, .value = 0},
6167 { .input = &tegra_clk_m, .value = 3},
6171 static struct clk_mux_sel mux_pllp_pllc_clk32_clkm[] = {
6172 {.input = &tegra_pll_p, .value = 0},
6173 {.input = &tegra_pll_c, .value = 1},
6174 {.input = &tegra_clk_32k, .value = 2},
6175 {.input = &tegra_clk_m, .value = 3},
6179 static struct clk_mux_sel mux_pllp_pllc_clkm_clk32[] = {
6180 {.input = &tegra_pll_p, .value = 0},
6181 {.input = &tegra_pll_c, .value = 1},
6182 {.input = &tegra_clk_m, .value = 2},
6183 {.input = &tegra_clk_32k, .value = 3},
6187 static struct clk_mux_sel mux_plla_clk32_pllp_clkm_plle[] = {
6188 { .input = &tegra_pll_a_out0, .value = 0},
6189 { .input = &tegra_clk_32k, .value = 1},
6190 { .input = &tegra_pll_p, .value = 2},
6191 { .input = &tegra_clk_m, .value = 3},
6192 { .input = &tegra_pll_e, .value = 4},
6196 static struct clk_mux_sel mux_clkm_pllp_pllc_pllre[] = {
6197 { .input = &tegra_clk_m, .value = 0},
6198 { .input = &tegra_pll_p, .value = 1},
6199 { .input = &tegra_pll_c, .value = 3},
6200 { .input = &tegra_pll_re_vco, .value = 5},
6204 static struct clk_mux_sel mux_clkm_48M_pllp_480M[] = {
6205 { .input = &tegra_clk_m, .value = 0},
6206 { .input = &tegra_pll_u_48M, .value = 1},
6207 { .input = &tegra_pll_p, .value = 2},
6208 { .input = &tegra_pll_u_480M, .value = 3},
6212 static struct clk_mux_sel mux_clkm_pllre_clk32_480M_pllc_ref[] = {
6213 { .input = &tegra_clk_m, .value = 0},
6214 { .input = &tegra_pll_re_vco, .value = 1},
6215 { .input = &tegra_clk_32k, .value = 2},
6216 { .input = &tegra_pll_u_480M, .value = 3},
6217 { .input = &tegra_pll_c, .value = 4},
6218 { .input = &tegra_pll_ref, .value = 7},
6222 /* Single clock source ("fake") muxes */
6223 static struct clk_mux_sel mux_clk_m[] = {
6224 { .input = &tegra_clk_m, .value = 0},
6228 static struct clk_mux_sel mux_pllp_out3[] = {
6229 { .input = &tegra_pll_p_out3, .value = 0},
6233 static struct clk_mux_sel mux_clk_32k[] = {
6234 { .input = &tegra_clk_32k, .value = 0},
6238 /* xusb_hs has an alternative source, that is not used - therefore, xusb_hs
6239 is modeled as a single source mux */
6240 static struct clk_mux_sel mux_pllu_60M[] = {
6241 { .input = &tegra_pll_u_60M, .value = 1},
6245 static struct raw_notifier_head emc_rate_change_nh;
6247 static struct clk tegra_clk_emc = {
6249 .ops = &tegra_emc_clk_ops,
6251 .max_rate = 1066000000,
6252 .min_rate = 12750000,
6253 .inputs = mux_pllm_pllc_pllp_clkm,
6254 .flags = MUX | MUX8 | DIV_U71 | PERIPH_EMC_ENB,
6258 .rate_change_nh = &emc_rate_change_nh,
6261 #ifdef CONFIG_TEGRA_DUAL_CBUS
6263 static struct raw_notifier_head c2bus_rate_change_nh;
6264 static struct raw_notifier_head c3bus_rate_change_nh;
6266 static struct clk tegra_clk_c2bus = {
6268 .parent = &tegra_pll_c2,
6269 .ops = &tegra_clk_cbus_ops,
6270 .max_rate = 700000000,
6273 .flags = PERIPH_ON_CBUS,
6274 .shared_bus_backup = {
6275 .input = &tegra_pll_p,
6277 .rate_change_nh = &c2bus_rate_change_nh,
6279 static struct clk tegra_clk_c3bus = {
6281 .parent = &tegra_pll_c3,
6282 .ops = &tegra_clk_cbus_ops,
6283 .max_rate = 700000000,
6286 .flags = PERIPH_ON_CBUS,
6287 .shared_bus_backup = {
6288 .input = &tegra_pll_p,
6290 .rate_change_nh = &c3bus_rate_change_nh,
6293 #ifdef CONFIG_TEGRA_MIGRATE_CBUS_USERS
6294 static DEFINE_MUTEX(cbus_mutex);
6295 #define CROSS_CBUS_MUTEX (&cbus_mutex)
6297 #define CROSS_CBUS_MUTEX NULL
6301 static struct clk_mux_sel mux_clk_cbus[] = {
6302 { .input = &tegra_clk_c2bus, .value = 0},
6303 { .input = &tegra_clk_c3bus, .value = 1},
6307 #define DUAL_CBUS_CLK(_name, _dev, _con, _parent, _id, _div, _mode)\
6314 .ops = &tegra_clk_shared_bus_user_ops, \
6315 .parent = _parent, \
6316 .inputs = mux_clk_cbus, \
6318 .u.shared_bus_user = { \
6320 .client_div = _div, \
6323 .cross_clk_mutex = CROSS_CBUS_MUTEX, \
6328 static struct raw_notifier_head cbus_rate_change_nh;
6330 static struct clk tegra_clk_cbus = {
6332 .parent = &tegra_pll_c,
6333 .ops = &tegra_clk_cbus_ops,
6334 .max_rate = 700000000,
6337 .flags = PERIPH_ON_CBUS,
6338 .shared_bus_backup = {
6339 .input = &tegra_pll_p,
6341 .rate_change_nh = &cbus_rate_change_nh,
6345 #define PERIPH_CLK(_name, _dev, _con, _clk_num, _reg, _max, _inputs, _flags) \
6352 .ops = &tegra_periph_clk_ops, \
6354 .inputs = _inputs, \
6358 .clk_num = _clk_num, \
6362 #define PERIPH_CLK_EX(_name, _dev, _con, _clk_num, _reg, _max, _inputs, \
6372 .inputs = _inputs, \
6376 .clk_num = _clk_num, \
6380 #define D_AUDIO_CLK(_name, _dev, _con, _clk_num, _reg, _max, _inputs, _flags) \
6387 .ops = &tegra_periph_clk_ops, \
6389 .inputs = _inputs, \
6393 .clk_num = _clk_num, \
6394 .src_mask = 0xE01F << 16, \
6399 #define SHARED_CLK(_name, _dev, _con, _parent, _id, _div, _mode)\
6406 .ops = &tegra_clk_shared_bus_user_ops, \
6407 .parent = _parent, \
6408 .u.shared_bus_user = { \
6410 .client_div = _div, \
6414 struct clk tegra_list_clks[] = {
6415 PERIPH_CLK("apbdma", "tegra-apbdma", NULL, 34, 0, 26000000, mux_clk_m, 0),
6416 PERIPH_CLK("rtc", "rtc-tegra", NULL, 4, 0, 32768, mux_clk_32k, PERIPH_NO_RESET | PERIPH_ON_APB),
6417 PERIPH_CLK("kbc", "tegra-kbc", NULL, 36, 0, 32768, mux_clk_32k, PERIPH_NO_RESET | PERIPH_ON_APB),
6418 PERIPH_CLK("timer", "timer", NULL, 5, 0, 26000000, mux_clk_m, 0),
6419 PERIPH_CLK("kfuse", "kfuse-tegra", NULL, 40, 0, 26000000, mux_clk_m, PERIPH_ON_APB),
6420 PERIPH_CLK("fuse", "fuse-tegra", "fuse", 39, 0, 26000000, mux_clk_m, PERIPH_ON_APB),
6421 PERIPH_CLK("fuse_burn", "fuse-tegra", "fuse_burn", 39, 0, 26000000, mux_clk_m, PERIPH_ON_APB),
6422 PERIPH_CLK("apbif", "tegra30-ahub", "apbif", 107, 0, 26000000, mux_clk_m, PERIPH_ON_APB),
6423 PERIPH_CLK("i2s0", "tegra30-i2s.0", NULL, 30, 0x1d8, 24576000, mux_pllaout0_audio0_2x_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
6424 PERIPH_CLK("i2s1", "tegra30-i2s.1", NULL, 11, 0x100, 24576000, mux_pllaout0_audio1_2x_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
6425 PERIPH_CLK("i2s2", "tegra30-i2s.2", NULL, 18, 0x104, 24576000, mux_pllaout0_audio2_2x_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
6426 PERIPH_CLK("i2s3", "tegra30-i2s.3", NULL, 101, 0x3bc, 24576000, mux_pllaout0_audio3_2x_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
6427 PERIPH_CLK("i2s4", "tegra30-i2s.4", NULL, 102, 0x3c0, 24576000, mux_pllaout0_audio4_2x_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
6428 PERIPH_CLK("spdif_out", "tegra30-spdif", "spdif_out", 10, 0x108, 24576000, mux_pllaout0_audio_2x_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
6429 PERIPH_CLK("spdif_in", "tegra30-spdif", "spdif_in", 10, 0x10c, 100000000, mux_pllp_pllc_pllm, MUX | DIV_U71 | PERIPH_ON_APB),
6430 PERIPH_CLK("pwm", "tegra-pwm", NULL, 17, 0x110, 48000000, mux_pllp_pllc_clk32_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
6431 D_AUDIO_CLK("d_audio", "tegra30-ahub", "d_audio", 106, 0x3d0, 48000000, mux_d_audio_clk, MUX | DIV_U71 | PERIPH_ON_APB),
6432 D_AUDIO_CLK("dam0", "tegra30-dam.0", NULL, 108, 0x3d8, 19910000, mux_d_audio_clk, MUX | DIV_U71 | PERIPH_ON_APB),
6433 D_AUDIO_CLK("dam1", "tegra30-dam.1", NULL, 109, 0x3dc, 19910000, mux_d_audio_clk, MUX | DIV_U71 | PERIPH_ON_APB),
6434 D_AUDIO_CLK("dam2", "tegra30-dam.2", NULL, 110, 0x3e0, 19910000, mux_d_audio_clk, MUX | DIV_U71 | PERIPH_ON_APB),
6435 PERIPH_CLK("adx", "adx", NULL, 154, 0x638, 19910000, mux_plla_pllc_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
6436 PERIPH_CLK("amx", "amx", NULL, 153, 0x63c, 19910000, mux_plla_pllc_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
6437 PERIPH_CLK("hda", "tegra30-hda", "hda", 125, 0x428, 48000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
6438 PERIPH_CLK("hda2codec_2x", "tegra30-hda", "hda2codec", 111, 0x3e4, 48000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
6439 PERIPH_CLK("hda2hdmi", "tegra30-hda", "hda2hdmi", 128, 0, 48000000, mux_clk_m, PERIPH_ON_APB),
6440 PERIPH_CLK("sbc1", "spi-tegra114.0", NULL, 41, 0x134, 52000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
6441 PERIPH_CLK("sbc2", "spi-tegra114.1", NULL, 44, 0x118, 52000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
6442 PERIPH_CLK("sbc3", "spi-tegra114.2", NULL, 46, 0x11c, 52000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
6443 PERIPH_CLK("sbc4", "spi-tegra114.3", NULL, 68, 0x1b4, 52000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
6444 PERIPH_CLK("sbc5", "spi-tegra114.4", NULL, 104, 0x3c8, 52000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
6445 PERIPH_CLK("sbc6", "spi-tegra114.5", NULL, 105, 0x3cc, 52000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
6446 PERIPH_CLK("sata_oob", "tegra_sata_oob", NULL, 123, 0x420, 216000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
6447 PERIPH_CLK("sata", "tegra_sata", NULL, 124, 0x424, 216000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
6448 PERIPH_CLK("sata_cold", "tegra_sata_cold", NULL, 129, 0, 48000000, mux_clk_m, PERIPH_ON_APB),
6449 PERIPH_CLK_EX("ndflash", "tegra_nand", NULL, 13, 0x160, 240000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB, &tegra_nand_clk_ops),
6450 PERIPH_CLK("ndspeed", "tegra_nand_speed", NULL, 80, 0x3f8, 240000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
6451 PERIPH_CLK("vfir", "vfir", NULL, 7, 0x168, 72000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
6452 PERIPH_CLK("sdmmc1", "sdhci-tegra.0", NULL, 14, 0x150, 208000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
6453 PERIPH_CLK("sdmmc2", "sdhci-tegra.1", NULL, 9, 0x154, 102000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
6454 PERIPH_CLK("sdmmc3", "sdhci-tegra.2", NULL, 69, 0x1bc, 208000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
6455 PERIPH_CLK("sdmmc4", "sdhci-tegra.3", NULL, 15, 0x164, 200000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
6456 PERIPH_CLK("vcp", "tegra-avp", "vcp", 29, 0, 250000000, mux_clk_m, 0),
6457 PERIPH_CLK("bsea", "tegra-avp", "bsea", 62, 0, 250000000, mux_clk_m, 0),
6458 PERIPH_CLK("bsev", "tegra-aes", "bsev", 63, 0, 250000000, mux_clk_m, 0),
6459 PERIPH_CLK("vde", "vde", NULL, 61, 0x1c8, 600000000, mux_pllp_pllc2_c_c3_pllm_clkm, MUX | MUX8 | DIV_U71 | DIV_U71_INT),
6460 PERIPH_CLK("csite", "csite", NULL, 73, 0x1d4, 144000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
6461 PERIPH_CLK("la", "la", NULL, 76, 0x1f8, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
6462 PERIPH_CLK("trace", "trace", NULL, 77, 0x634, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
6463 PERIPH_CLK("owr", "tegra_w1", NULL, 71, 0x1cc, 12000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
6464 PERIPH_CLK("nor", "tegra-nor", NULL, 42, 0x1d0, 127000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
6465 PERIPH_CLK("mipi", "mipi", NULL, 50, 0x174, 60000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
6466 PERIPH_CLK("i2c1", "tegra11-i2c.0", "div-clk", 12, 0x124, 136000000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB),
6467 PERIPH_CLK("i2c2", "tegra11-i2c.1", "div-clk", 54, 0x198, 136000000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB),
6468 PERIPH_CLK("i2c3", "tegra11-i2c.2", "div-clk", 67, 0x1b8, 136000000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB),
6469 PERIPH_CLK("i2c4", "tegra11-i2c.3", "div-clk", 103, 0x3c4, 136000000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB),
6470 PERIPH_CLK("i2c5", "tegra11-i2c.4", "div-clk", 47, 0x128, 58300000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB),
6471 PERIPH_CLK("mipi-cal", "mipi-cal", NULL, 56, 0, 60000000, mux_clk_m, 0),
6472 PERIPH_CLK("uarta", "tegra_uart.0", NULL, 6, 0x178, 800000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U151 | DIV_U151_UART | PERIPH_ON_APB),
6473 PERIPH_CLK("uartb", "tegra_uart.1", NULL, 7, 0x17c, 800000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U151 | DIV_U151_UART | PERIPH_ON_APB),
6474 PERIPH_CLK("uartc", "tegra_uart.2", NULL, 55, 0x1a0, 800000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U151 | DIV_U151_UART | PERIPH_ON_APB),
6475 PERIPH_CLK("uartd", "tegra_uart.3", NULL, 65, 0x1c0, 800000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U151 | DIV_U151_UART | PERIPH_ON_APB),
6476 PERIPH_CLK("uarte", "tegra_uart.4", NULL, 66, 0x1c4, 800000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U151 | DIV_U151_UART | PERIPH_ON_APB),
6477 PERIPH_CLK("3d", "3d", NULL, 24, 0x158, 700000000, mux_pllm_pllc2_c_c3_pllp_plla, MUX | MUX8 | DIV_U71 | DIV_U71_INT | DIV_U71_IDLE | PERIPH_MANUAL_RESET),
6478 PERIPH_CLK("2d", "2d", NULL, 21, 0x15c, 700000000, mux_pllm_pllc2_c_c3_pllp_plla, MUX | MUX8 | DIV_U71 | DIV_U71_INT | DIV_U71_IDLE),
6479 PERIPH_CLK_EX("vi", "tegra_camera", "vi", 20, 0x148, 425000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | DIV_U71_INT, &tegra_vi_clk_ops),
6480 PERIPH_CLK("vi_sensor", "tegra_camera", "vi_sensor", 20, 0x1a8, 150000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | PERIPH_NO_RESET),
6481 PERIPH_CLK("epp", "epp", NULL, 19, 0x16c, 700000000, mux_pllm_pllc2_c_c3_pllp_plla, MUX | MUX8 | DIV_U71 | DIV_U71_INT),
6482 #ifdef CONFIG_TEGRA_SIMULATION_PLATFORM
6483 PERIPH_CLK("msenc", "msenc", NULL, 60, 0x170, 600000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | DIV_U71_INT),
6485 PERIPH_CLK_EX("msenc", "msenc", NULL, 91, 0x1f0, 600000000, mux_pllm_pllc2_c_c3_pllp_plla, MUX | MUX8 | DIV_U71 | DIV_U71_INT, &tegra_msenc_clk_ops),
6487 PERIPH_CLK("tsec", "tsec", NULL, 83, 0x1f4, 600000000, mux_pllp_pllc2_c_c3_pllm_clkm, MUX | MUX8 | DIV_U71 | DIV_U71_INT),
6488 PERIPH_CLK("host1x", "host1x", NULL, 28, 0x180, 384000000, mux_pllm_pllc2_c_c3_pllp_plla, MUX | MUX8 | DIV_U71 | DIV_U71_INT),
6489 PERIPH_CLK_EX("dtv", "dtv", NULL, 79, 0x1dc, 250000000, mux_clk_m, PERIPH_ON_APB, &tegra_dtv_clk_ops),
6490 PERIPH_CLK("hdmi", "hdmi", NULL, 51, 0x18c, 297000000, mux_pllp_pllm_plld_plla_pllc_plld2_clkm, MUX | MUX8 | DIV_U71),
6491 PERIPH_CLK("disp1", "tegradc.0", NULL, 27, 0x138, 600000000, mux_pllp_pllm_plld_plla_pllc_plld2_clkm, MUX | MUX8),
6492 PERIPH_CLK("disp2", "tegradc.1", NULL, 26, 0x13c, 600000000, mux_pllp_pllm_plld_plla_pllc_plld2_clkm, MUX | MUX8),
6493 PERIPH_CLK("usbd", "tegra-udc.0", NULL, 22, 0, 480000000, mux_clk_m, 0),
6494 PERIPH_CLK("usb2", "tegra-ehci.1", NULL, 58, 0, 480000000, mux_clk_m, 0),
6495 PERIPH_CLK("usb3", "tegra-ehci.2", NULL, 59, 0, 480000000, mux_clk_m, 0),
6496 PERIPH_CLK_EX("dsia", "tegradc.0", "dsia", 48, 0xd0, 500000000, mux_plld_out0_plld2_out0, MUX | PLLD, &tegra_dsi_clk_ops),
6497 PERIPH_CLK_EX("dsib", "tegradc.1", "dsib", 82, 0x4b8, 500000000, mux_plld_out0_plld2_out0, MUX | PLLD, &tegra_dsi_clk_ops),
6498 PERIPH_CLK("dsi1-fixed", "tegradc.0", "dsi-fixed", 0, 0, 108000000, mux_pllp_out3, PERIPH_NO_ENB),
6499 PERIPH_CLK("dsi2-fixed", "tegradc.1", "dsi-fixed", 0, 0, 108000000, mux_pllp_out3, PERIPH_NO_ENB),
6500 PERIPH_CLK("csi", "tegra_camera", "csi", 52, 0, 102000000, mux_pllp_out3, 0),
6501 PERIPH_CLK("isp", "tegra_camera", "isp", 23, 0, 150000000, mux_clk_m, 0), /* same frequency as VI */
6502 PERIPH_CLK("csus", "tegra_camera", "csus", 92, 0, 150000000, mux_clk_m, PERIPH_NO_RESET),
6503 PERIPH_CLK("cilab", "tegra_camera", "cilab", 144, 0x614, 102000000, mux_pllp_pllc_clkm, MUX | DIV_U71),
6504 PERIPH_CLK("cilcd", "tegra_camera", "cilcd", 145, 0x618, 102000000, mux_pllp_pllc_clkm, MUX | DIV_U71),
6505 PERIPH_CLK("cile", "tegra_camera", "cile", 146, 0x61c, 102000000, mux_pllp_pllc_clkm, MUX | DIV_U71),
6506 PERIPH_CLK("dsialp", "tegradc.0", "dsialp", 147, 0x620, 102000000, mux_pllp_pllc_clkm, MUX | DIV_U71),
6507 PERIPH_CLK("dsiblp", "tegradc.1", "dsiblp", 148, 0x624, 102000000, mux_pllp_pllc_clkm, MUX | DIV_U71),
6509 PERIPH_CLK("tsensor", "tegra-tsensor", NULL, 100, 0x3b8, 12000000, mux_pllp_pllc_clkm_clk32, MUX | DIV_U71 | PERIPH_ON_APB),
6510 PERIPH_CLK("actmon", "actmon", NULL, 119, 0x3e8, 216000000, mux_pllp_pllc_clk32_clkm, MUX | DIV_U71),
6511 PERIPH_CLK("extern1", "extern1", NULL, 120, 0x3ec, 216000000, mux_plla_clk32_pllp_clkm_plle, MUX | MUX8 | DIV_U71),
6512 PERIPH_CLK("extern2", "extern2", NULL, 121, 0x3f0, 216000000, mux_plla_clk32_pllp_clkm_plle, MUX | MUX8 | DIV_U71),
6513 PERIPH_CLK("extern3", "extern3", NULL, 122, 0x3f4, 216000000, mux_plla_clk32_pllp_clkm_plle, MUX | MUX8 | DIV_U71),
6514 PERIPH_CLK("i2cslow", "i2cslow", NULL, 81, 0x3fc, 26000000, mux_pllp_pllc_clk32_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
6515 PERIPH_CLK("pcie", "tegra-pcie", "pcie", 70, 0, 250000000, mux_clk_m, 0),
6516 PERIPH_CLK("afi", "tegra-pcie", "afi", 72, 0, 250000000, mux_clk_m, 0),
6517 PERIPH_CLK("se", "se", NULL, 127, 0x42c, 600000000, mux_pllp_pllc2_c_c3_pllm_clkm, MUX | MUX8 | DIV_U71 | DIV_U71_INT | PERIPH_ON_APB),
6518 PERIPH_CLK("mselect", "mselect", NULL, 99, 0x3b4, 102000000, mux_pllp_clkm, MUX | DIV_U71 | DIV_U71_INT),
6519 PERIPH_CLK("cl_dvfs_ref", "tegra_cl_dvfs", "ref", 155, 0x62c, 54000000, mux_pllp_clkm, MUX | DIV_U71 | DIV_U71_INT | PERIPH_ON_APB),
6520 PERIPH_CLK("cl_dvfs_soc", "tegra_cl_dvfs", "soc", 155, 0x630, 54000000, mux_pllp_clkm, MUX | DIV_U71 | DIV_U71_INT | PERIPH_ON_APB),
6521 PERIPH_CLK("soc_therm", "soc_therm", NULL, 78, 0x644, 136000000, mux_pllm_pllc_pllp_plla, MUX | MUX8 | DIV_U71 | PERIPH_ON_APB),
6523 PERIPH_CLK("dds", "dds", NULL, 150, 0, 26000000, mux_clk_m, PERIPH_ON_APB),
6524 PERIPH_CLK("dp2", "dp2", NULL, 152, 0, 26000000, mux_clk_m, PERIPH_ON_APB),
6526 SHARED_CLK("avp.sclk", "tegra-avp", "sclk", &tegra_clk_sbus_cmplx, NULL, 0, 0),
6527 SHARED_CLK("bsea.sclk", "tegra-aes", "sclk", &tegra_clk_sbus_cmplx, NULL, 0, 0),
6528 SHARED_CLK("usbd.sclk", "tegra-udc.0", "sclk", &tegra_clk_sbus_cmplx, NULL, 0, 0),
6529 SHARED_CLK("usb1.sclk", "tegra-ehci.0", "sclk", &tegra_clk_sbus_cmplx, NULL, 0, 0),
6530 SHARED_CLK("usb2.sclk", "tegra-ehci.1", "sclk", &tegra_clk_sbus_cmplx, NULL, 0, 0),
6531 SHARED_CLK("usb3.sclk", "tegra-ehci.2", "sclk", &tegra_clk_sbus_cmplx, NULL, 0, 0),
6532 SHARED_CLK("wake.sclk", "wake_sclk", "sclk", &tegra_clk_sbus_cmplx, NULL, 0, 0),
6533 SHARED_CLK("mon.avp", "tegra_actmon", "avp", &tegra_clk_sbus_cmplx, NULL, 0, 0),
6534 SHARED_CLK("cap.sclk", "cap_sclk", NULL, &tegra_clk_sbus_cmplx, NULL, 0, SHARED_CEILING),
6535 SHARED_CLK("cap.throttle.sclk", "cap_throttle", NULL, &tegra_clk_sbus_cmplx, NULL, 0, SHARED_CEILING),
6536 SHARED_CLK("floor.sclk", "floor_sclk", NULL, &tegra_clk_sbus_cmplx, NULL, 0, 0),
6537 SHARED_CLK("override.sclk", "override_sclk", NULL, &tegra_clk_sbus_cmplx, NULL, 0, SHARED_OVERRIDE),
6538 SHARED_CLK("sbc1.sclk", "tegra11-spi.0", "sclk", &tegra_clk_sbus_cmplx, NULL, 0, 0),
6539 SHARED_CLK("sbc2.sclk", "tegra11-spi.1", "sclk", &tegra_clk_sbus_cmplx, NULL, 0, 0),
6540 SHARED_CLK("sbc3.sclk", "tegra11-spi.2", "sclk", &tegra_clk_sbus_cmplx, NULL, 0, 0),
6541 SHARED_CLK("sbc4.sclk", "tegra11-spi.3", "sclk", &tegra_clk_sbus_cmplx, NULL, 0, 0),
6542 SHARED_CLK("sbc5.sclk", "tegra11-spi.4", "sclk", &tegra_clk_sbus_cmplx, NULL, 0, 0),
6543 SHARED_CLK("sbc6.sclk", "tegra11-spi.5", "sclk", &tegra_clk_sbus_cmplx, NULL, 0, 0),
6545 SHARED_CLK("avp.emc", "tegra-avp", "emc", &tegra_clk_emc, NULL, 0, 0),
6546 SHARED_CLK("cpu.emc", "cpu", "emc", &tegra_clk_emc, NULL, 0, 0),
6547 SHARED_CLK("disp1.emc", "tegradc.0", "emc", &tegra_clk_emc, NULL, 0, SHARED_BW),
6548 SHARED_CLK("disp2.emc", "tegradc.1", "emc", &tegra_clk_emc, NULL, 0, SHARED_BW),
6549 SHARED_CLK("hdmi.emc", "hdmi", "emc", &tegra_clk_emc, NULL, 0, 0),
6550 SHARED_CLK("usbd.emc", "tegra-udc.0", "emc", &tegra_clk_emc, NULL, 0, 0),
6551 SHARED_CLK("usb1.emc", "tegra-ehci.0", "emc", &tegra_clk_emc, NULL, 0, 0),
6552 SHARED_CLK("usb2.emc", "tegra-ehci.1", "emc", &tegra_clk_emc, NULL, 0, 0),
6553 SHARED_CLK("usb3.emc", "tegra-ehci.2", "emc", &tegra_clk_emc, NULL, 0, 0),
6554 SHARED_CLK("mon.emc", "tegra_actmon", "emc", &tegra_clk_emc, NULL, 0, 0),
6555 SHARED_CLK("cap.emc", "cap.emc", NULL, &tegra_clk_emc, NULL, 0, SHARED_CEILING),
6556 SHARED_CLK("cap.throttle.emc", "cap_throttle", NULL, &tegra_clk_emc, NULL, 0, SHARED_CEILING),
6557 SHARED_CLK("3d.emc", "tegra_gr3d", "emc", &tegra_clk_emc, NULL, 0, 0),
6558 SHARED_CLK("2d.emc", "tegra_gr2d", "emc", &tegra_clk_emc, NULL, 0, 0),
6559 SHARED_CLK("msenc.emc", "tegra_msenc", "emc", &tegra_clk_emc, NULL, 0, SHARED_BW),
6560 SHARED_CLK("tsec.emc", "tegra_tsec", "emc", &tegra_clk_emc, NULL, 0, 0),
6561 SHARED_CLK("sdmmc4.emc", "sdhci-tegra.3", "emc", &tegra_clk_emc, NULL, 0, 0),
6562 SHARED_CLK("camera.emc", "tegra_camera", "emc", &tegra_clk_emc, NULL, 0, SHARED_BW),
6563 SHARED_CLK("iso.emc", "iso", "emc", &tegra_clk_emc, NULL, 0, SHARED_BW),
6564 SHARED_CLK("floor.emc", "floor.emc", NULL, &tegra_clk_emc, NULL, 0, 0),
6565 SHARED_CLK("override.emc", "override.emc", NULL, &tegra_clk_emc, NULL, 0, SHARED_OVERRIDE),
6566 SHARED_CLK("edp.emc", "edp.emc", NULL, &tegra_clk_emc, NULL, 0, SHARED_CEILING),
6568 #ifdef CONFIG_TEGRA_DUAL_CBUS
6569 DUAL_CBUS_CLK("3d.cbus", "tegra_gr3d", "gr3d", &tegra_clk_c2bus, "3d", 0, 0),
6570 DUAL_CBUS_CLK("2d.cbus", "tegra_gr2d", "gr2d", &tegra_clk_c2bus, "2d", 0, 0),
6571 DUAL_CBUS_CLK("epp.cbus", "tegra_gr2d", "epp", &tegra_clk_c2bus, "epp", 0, 0),
6572 SHARED_CLK("cap.c2bus", "cap.c2bus", NULL, &tegra_clk_c2bus, NULL, 0, SHARED_CEILING),
6573 SHARED_CLK("cap.throttle.c2bus", "cap_throttle", NULL, &tegra_clk_c2bus, NULL, 0, SHARED_CEILING),
6574 SHARED_CLK("floor.c2bus", "floor.c2bus", NULL, &tegra_clk_c2bus, NULL, 0, 0),
6575 SHARED_CLK("override.c2bus", "override.c2bus", NULL, &tegra_clk_c2bus, NULL, 0, SHARED_OVERRIDE),
6576 SHARED_CLK("edp.c2bus", "edp.c2bus", NULL, &tegra_clk_c2bus, NULL, 0, SHARED_CEILING),
6578 DUAL_CBUS_CLK("msenc.cbus", "tegra_msenc", "msenc", &tegra_clk_c3bus, "msenc", 0, 0),
6579 DUAL_CBUS_CLK("tsec.cbus", "tegra_tsec", "tsec", &tegra_clk_c3bus, "tsec", 0, 0),
6580 DUAL_CBUS_CLK("vde.cbus", "tegra-avp", "vde", &tegra_clk_c3bus, "vde", 0, 0),
6581 DUAL_CBUS_CLK("se.cbus", "tegra11-se", NULL, &tegra_clk_c3bus, "se", 0, 0),
6582 SHARED_CLK("cap.c3bus", "cap.c3bus", NULL, &tegra_clk_c3bus, NULL, 0, SHARED_CEILING),
6583 SHARED_CLK("cap.throttle.c3bus", "cap_throttle", NULL, &tegra_clk_c3bus, NULL, 0, SHARED_CEILING),
6584 SHARED_CLK("floor.c3bus", "floor.c3bus", NULL, &tegra_clk_c3bus, NULL, 0, 0),
6585 SHARED_CLK("override.c3bus", "override.c3bus", NULL, &tegra_clk_c3bus, NULL, 0, SHARED_OVERRIDE),
6587 SHARED_CLK("3d.cbus", "tegra_gr3d", "gr3d", &tegra_clk_cbus, "3d", 0, 0),
6588 SHARED_CLK("2d.cbus", "tegra_gr2d", "gr2d", &tegra_clk_cbus, "2d", 0, 0),
6589 SHARED_CLK("epp.cbus", "tegra_gr2d", "epp", &tegra_clk_cbus, "epp", 0, 0),
6590 SHARED_CLK("msenc.cbus","tegra_msenc", "msenc",&tegra_clk_cbus, "msenc", 0, 0),
6591 SHARED_CLK("tsec.cbus", "tegra_tsec", "tsec", &tegra_clk_cbus, "tsec", 0, 0),
6592 SHARED_CLK("vde.cbus", "tegra-avp", "vde", &tegra_clk_cbus, "vde", 0, 0),
6593 SHARED_CLK("se.cbus", "tegra11-se", NULL, &tegra_clk_cbus, "se", 0, 0),
6594 SHARED_CLK("cap.cbus", "cap.cbus", NULL, &tegra_clk_cbus, NULL, 0, SHARED_CEILING),
6595 SHARED_CLK("cap.throttle.cbus", "cap_throttle", NULL, &tegra_clk_cbus, NULL, 0, SHARED_CEILING),
6596 SHARED_CLK("floor.cbus", "floor.cbus", NULL, &tegra_clk_cbus, NULL, 0, 0),
6597 SHARED_CLK("override.cbus", "override.cbus", NULL, &tegra_clk_cbus, NULL, 0, SHARED_OVERRIDE),
6598 SHARED_CLK("edp.cbus", "edp.cbus", NULL, &tegra_clk_cbus, NULL, 0, SHARED_CEILING),
6604 #define XUSB_ID "tegra-xhci"
6606 static struct clk tegra_xusb_source_clks[] = {
6607 PERIPH_CLK("xusb_host_src", XUSB_ID, "host_src", 143, 0x600, 120000000, mux_clkm_pllp_pllc_pllre, MUX | MUX8 | DIV_U71 | DIV_U71_INT | PERIPH_NO_RESET | PERIPH_ON_APB),
6608 PERIPH_CLK("xusb_falcon_src", XUSB_ID, "falcon_src", 143, 0x604, 350000000, mux_clkm_pllp_pllc_pllre, MUX | MUX8 | DIV_U71 | DIV_U71_INT | PERIPH_NO_RESET),
6609 PERIPH_CLK("xusb_fs_src", XUSB_ID, "fs_src", 143, 0x608, 48000000, mux_clkm_48M_pllp_480M, MUX | DIV_U71 | DIV_U71_INT | PERIPH_NO_RESET),
6610 PERIPH_CLK("xusb_ss_src", XUSB_ID, "ss_src", 143, 0x610, 120000000, mux_clkm_pllre_clk32_480M_pllc_ref, MUX | MUX8 | DIV_U71 | DIV_U71_INT | PERIPH_NO_RESET),
6611 PERIPH_CLK("xusb_dev_src", XUSB_ID, "dev_src", 95, 0x60c, 120000000, mux_clkm_pllp_pllc_pllre, MUX | MUX8 | DIV_U71 | DIV_U71_INT | PERIPH_NO_RESET | PERIPH_ON_APB),
6613 .name = "xusb_hs_src",
6618 .ops = &tegra_periph_clk_ops,
6620 .inputs = mux_pllu_60M,
6621 .flags = PLLU | PERIPH_NO_ENB,
6622 .max_rate = 60000000,
6624 .src_mask = 0x1 << 25,
6628 SHARED_CLK("xusb.emc", "XUSB_ID", "emc", &tegra_clk_emc, NULL, 0, SHARED_BW),
6631 static struct clk_mux_sel mux_xusb_host[] = {
6632 { .input = &tegra_xusb_source_clks[0], .value = 0},
6633 { .input = &tegra_xusb_source_clks[1], .value = 1},
6634 { .input = &tegra_xusb_source_clks[2], .value = 2},
6635 { .input = &tegra_xusb_source_clks[5], .value = 5},
6639 static struct clk_mux_sel mux_xusb_ss[] = {
6640 { .input = &tegra_xusb_source_clks[3], .value = 3},
6641 { .input = &tegra_xusb_source_clks[0], .value = 0},
6642 { .input = &tegra_xusb_source_clks[1], .value = 1},
6646 static struct clk_mux_sel mux_xusb_dev[] = {
6647 { .input = &tegra_xusb_source_clks[4], .value = 4},
6648 { .input = &tegra_xusb_source_clks[2], .value = 2},
6649 { .input = &tegra_xusb_source_clks[3], .value = 3},
6653 static struct clk tegra_xusb_coupled_clks[] = {
6654 PERIPH_CLK_EX("xusb_host", XUSB_ID, "host", 89, 0, 350000000, mux_xusb_host, 0, &tegra_clk_coupled_gate_ops),
6655 PERIPH_CLK_EX("xusb_ss", XUSB_ID, "ss", 156, 0, 350000000, mux_xusb_ss, 0, &tegra_clk_coupled_gate_ops),
6656 PERIPH_CLK_EX("xusb_dev", XUSB_ID, "dev", 95, 0, 120000000, mux_xusb_dev, 0, &tegra_clk_coupled_gate_ops),
6660 #define CLK_DUPLICATE(_name, _dev, _con) \
6669 /* Some clocks may be used by different drivers depending on the board
6670 * configuration. List those here to register them twice in the clock lookup
6671 * table under two names.
6673 struct clk_duplicate tegra_clk_duplicates[] = {
6674 CLK_DUPLICATE("uarta", "serial8250.0", NULL),
6675 CLK_DUPLICATE("uartb", "serial8250.1", NULL),
6676 CLK_DUPLICATE("uartc", "serial8250.2", NULL),
6677 CLK_DUPLICATE("uartd", "serial8250.3", NULL),
6678 CLK_DUPLICATE("uarte", "serial8250.4", NULL),
6679 CLK_DUPLICATE("usbd", XUSB_ID, "utmip-pad"),
6680 CLK_DUPLICATE("usbd", "utmip-pad", NULL),
6681 CLK_DUPLICATE("usbd", "tegra-ehci.0", NULL),
6682 CLK_DUPLICATE("usbd", "tegra-otg", NULL),
6683 CLK_DUPLICATE("disp1", "tegra_dc_dsi_vs1.0", NULL),
6684 CLK_DUPLICATE("disp1.emc", "tegra_dc_dsi_vs1.0", "emc"),
6685 CLK_DUPLICATE("disp1", "tegra_dc_dsi_vs1.1", NULL),
6686 CLK_DUPLICATE("disp1.emc", "tegra_dc_dsi_vs1.1", "emc"),
6687 CLK_DUPLICATE("hdmi", "tegradc.0", "hdmi"),
6688 CLK_DUPLICATE("hdmi", "tegradc.1", "hdmi"),
6689 CLK_DUPLICATE("dsib", "tegradc.0", "dsib"),
6690 CLK_DUPLICATE("dsia", "tegradc.1", "dsia"),
6691 CLK_DUPLICATE("dsiblp", "tegradc.0", "dsiblp"),
6692 CLK_DUPLICATE("dsialp", "tegradc.1", "dsialp"),
6693 CLK_DUPLICATE("dsia", "tegra_dc_dsi_vs1.0", "dsia"),
6694 CLK_DUPLICATE("dsia", "tegra_dc_dsi_vs1.1", "dsia"),
6695 CLK_DUPLICATE("dsialp", "tegra_dc_dsi_vs1.0", "dsialp"),
6696 CLK_DUPLICATE("dsialp", "tegra_dc_dsi_vs1.1", "dsialp"),
6697 CLK_DUPLICATE("dsi1-fixed", "tegra_dc_dsi_vs1.0", "dsi-fixed"),
6698 CLK_DUPLICATE("dsi1-fixed", "tegra_dc_dsi_vs1.1", "dsi-fixed"),
6699 CLK_DUPLICATE("cop", "tegra-avp", "cop"),
6700 CLK_DUPLICATE("bsev", "tegra-avp", "bsev"),
6701 CLK_DUPLICATE("cop", "nvavp", "cop"),
6702 CLK_DUPLICATE("bsev", "nvavp", "bsev"),
6703 CLK_DUPLICATE("vde", "tegra-aes", "vde"),
6704 CLK_DUPLICATE("bsea", "tegra-aes", "bsea"),
6705 CLK_DUPLICATE("bsea", "nvavp", "bsea"),
6706 CLK_DUPLICATE("pciex", "tegra_pcie", "pciex"),
6707 CLK_DUPLICATE("clk_m", NULL, "apb_pclk"),
6708 CLK_DUPLICATE("i2c1", "tegra-i2c-slave.0", NULL),
6709 CLK_DUPLICATE("i2c2", "tegra-i2c-slave.1", NULL),
6710 CLK_DUPLICATE("i2c3", "tegra-i2c-slave.2", NULL),
6711 CLK_DUPLICATE("i2c4", "tegra-i2c-slave.3", NULL),
6712 CLK_DUPLICATE("i2c5", "tegra-i2c-slave.4", NULL),
6713 CLK_DUPLICATE("sbc1", "tegra11-spi-slave.0", NULL),
6714 CLK_DUPLICATE("sbc2", "tegra11-spi-slave.1", NULL),
6715 CLK_DUPLICATE("sbc3", "tegra11-spi-slave.2", NULL),
6716 CLK_DUPLICATE("sbc4", "tegra11-spi-slave.3", NULL),
6717 CLK_DUPLICATE("sbc5", "tegra11-spi-slave.4", NULL),
6718 CLK_DUPLICATE("sbc6", "tegra11-spi-slave.5", NULL),
6719 CLK_DUPLICATE("vcp", "nvavp", "vcp"),
6720 CLK_DUPLICATE("avp.sclk", "nvavp", "sclk"),
6721 CLK_DUPLICATE("avp.emc", "nvavp", "emc"),
6722 CLK_DUPLICATE("vde.cbus", "nvavp", "vde"),
6723 CLK_DUPLICATE("i2c5", "tegra_cl_dvfs", "i2c"),
6724 CLK_DUPLICATE("cpu_g", "tegra_cl_dvfs", "safe_dvfs"),
6725 CLK_DUPLICATE("host1x", "tegra_host1x", "host1x"),
6726 CLK_DUPLICATE("epp.cbus", "tegra_isp", "epp"),
6729 struct clk *tegra_ptr_clks[] = {
6769 &tegra_clk_virtual_cpu_g,
6770 &tegra_clk_virtual_cpu_lp,
6771 &tegra_clk_cpu_cmplx,
6774 &tegra_clk_sbus_cmplx,
6776 #ifdef CONFIG_TEGRA_DUAL_CBUS
6784 /* Return true from this function if the target rate can be locked without
6785 switching pll clients to back-up source */
6786 static bool tegra11_is_dyn_ramp(
6787 struct clk *c, unsigned long rate, bool from_vco_min)
6789 #if PLLCX_USE_DYN_RAMP
6790 /* PLLC2, PLLC3 support dynamic ramp only when output divider <= 8 */
6791 if ((c == &tegra_pll_c2) || (c == &tegra_pll_c3)) {
6792 struct clk_pll_freq_table cfg, old_cfg;
6793 unsigned long input_rate = clk_get_rate(c->parent);
6795 u32 val = clk_readl(c->reg + PLL_BASE);
6796 PLL_BASE_PARSE(PLLCX, old_cfg, val);
6797 old_cfg.p = pllcx_p[old_cfg.p];
6799 if (!pll_dyn_ramp_find_cfg(c, &cfg, rate, input_rate, NULL)) {
6800 if ((cfg.n == old_cfg.n) ||
6801 PLLCX_IS_DYN(cfg.p, old_cfg.p))
6807 #if PLLXC_USE_DYN_RAMP
6808 /* PPLX, PLLC support dynamic ramp when changing NDIV only */
6809 if ((c == &tegra_pll_x) || (c == &tegra_pll_c)) {
6810 struct clk_pll_freq_table cfg, old_cfg;
6811 unsigned long input_rate = clk_get_rate(c->parent);
6814 old_cfg.m = PLL_FIXED_MDIV(c, input_rate);
6817 u32 val = clk_readl(c->reg + PLL_BASE);
6818 PLL_BASE_PARSE(PLLXC, old_cfg, val);
6819 old_cfg.p = pllxc_p[old_cfg.p];
6822 if (!pll_dyn_ramp_find_cfg(c, &cfg, rate, input_rate, NULL)) {
6823 if ((cfg.m == old_cfg.m) && (cfg.p == old_cfg.p))
6832 * Backup pll is used as transitional CPU clock source while main pll is
6833 * relocking; in addition all CPU rates below backup level are sourced from
6834 * backup pll only. Target backup levels for each CPU mode are selected high
6835 * enough to avoid voltage droop when CPU clock is switched between backup and
6836 * main plls. Actual backup rates will be rounded to match backup source fixed
6837 * frequency. Backup rates are also used as stay-on-backup thresholds, and must
6838 * be kept the same in G and LP mode (will need to add a separate stay-on-backup
6839 * parameter to allow different backup rates if necessary).
6841 * Sbus threshold must be exact factor of pll_p rate.
6843 #define CPU_G_BACKUP_RATE_TARGET 200000000
6844 #define CPU_LP_BACKUP_RATE_TARGET 200000000
6846 static void tegra11_pllp_init_dependencies(unsigned long pllp_rate)
6849 unsigned long backup_rate;
6851 switch (pllp_rate) {
6853 tegra_pll_p_out1.u.pll_div.default_rate = 28800000;
6854 tegra_pll_p_out3.u.pll_div.default_rate = 72000000;
6855 tegra_clk_sbus_cmplx.u.system.threshold = 108000000;
6858 tegra_pll_p_out1.u.pll_div.default_rate = 9600000;
6859 tegra_pll_p_out3.u.pll_div.default_rate = 102000000;
6860 tegra_clk_sbus_cmplx.u.system.threshold = 204000000;
6863 tegra_pll_p_out1.u.pll_div.default_rate = 4800000;
6864 tegra_pll_p_out3.u.pll_div.default_rate = 102000000;
6865 tegra_clk_sbus_cmplx.u.system.threshold = 204000000;
6868 pr_err("tegra: PLLP rate: %lu is not supported\n", pllp_rate);
6871 pr_info("tegra: PLLP fixed rate: %lu\n", pllp_rate);
6873 div = pllp_rate / CPU_G_BACKUP_RATE_TARGET;
6874 backup_rate = pllp_rate / div;
6875 tegra_clk_virtual_cpu_g.u.cpu.backup_rate = backup_rate;
6877 div = pllp_rate / CPU_LP_BACKUP_RATE_TARGET;
6878 backup_rate = pllp_rate / div;
6879 tegra_clk_virtual_cpu_lp.u.cpu.backup_rate = backup_rate;
6882 static void tegra11_init_one_clock(struct clk *c)
6885 INIT_LIST_HEAD(&c->shared_bus_list);
6886 if (!c->lookup.dev_id && !c->lookup.con_id)
6887 c->lookup.con_id = c->name;
6889 clkdev_add(&c->lookup);
6892 int tegra11_cpu_backup_rate_exchange(unsigned long *rate)
6894 struct clk *backup = tegra_clk_cpu_cmplx.parent->u.cpu.backup;
6895 unsigned long old_rate = clk_get_rate(backup);
6896 unsigned long new_rate = min(
6897 *rate, tegra_clk_cpu_cmplx.parent->u.cpu.backup_rate);
6899 if (new_rate != old_rate)
6900 return clk_set_rate(backup, new_rate);
6904 void tegra_edp_throttle_cpu_now(u8 factor)
6906 /* empty definition for tegra11 */
6910 bool tegra_clk_is_parent_allowed(struct clk *c, struct clk *p)
6913 * Most of the Tegra11 multimedia and peripheral muxes include pll_c2
6914 * and pll_c3 as possible inputs. However, per clock policy these plls
6915 * are allowed to be used only by handful devices aggregated on cbus.
6916 * For all others, instead of enforcing policy at run-time in this
6917 * function, we simply stripped out pll_c2 and pll_c3 options from the
6918 * respective muxes statically.
6922 * In configuration with dual cbus pll_c can be used as a scaled clock
6923 * source for EMC only when pll_m is fixed, or as a general fixed rate
6924 * clock source for EMC and other peripherals if pll_m is scaled. In
6925 * configuration with single cbus pll_c can be used as a scaled cbus
6926 * clock source only.
6928 if ((p == &tegra_pll_c) && (c != &tegra_pll_c_out1)) {
6929 #ifdef CONFIG_TEGRA_DUAL_CBUS
6930 #ifndef CONFIG_TEGRA_PLLM_SCALED
6931 return c->flags & PERIPH_EMC_ENB;
6934 return c->flags & PERIPH_ON_CBUS;
6939 * In any configuration pll_m must not be used as a clock source for
6940 * cbus modules. If pll_m is scaled it can be used as EMC source only.
6941 * Otherwise fixed rate pll_m can be used as clock source for EMC and
6942 * other peripherals.
6944 if ((p == &tegra_pll_m) && (c != &tegra_pll_m_out1)) {
6945 if (c->flags & PERIPH_ON_CBUS)
6947 #ifdef CONFIG_TEGRA_PLLM_SCALED
6948 return c->flags & PERIPH_EMC_ENB;
6954 /* Internal LA may request some clocks to be enabled on init via TRANSACTION
6955 SCRATCH register settings */
6956 void __init tegra11x_clk_init_la(void)
6959 u32 reg = readl(misc_gp_base + MISC_GP_TRANSACTOR_SCRATCH_0);
6961 if (!(reg & MISC_GP_TRANSACTOR_SCRATCH_LA_ENABLE))
6964 c = tegra_get_clock_by_name("la");
6965 if (WARN(!c, "%s: could not find la clk\n", __func__))
6969 if (reg & MISC_GP_TRANSACTOR_SCRATCH_DDS_ENABLE) {
6970 c = tegra_get_clock_by_name("dds");
6971 if (WARN(!c, "%s: could not find la clk\n", __func__))
6975 if (reg & MISC_GP_TRANSACTOR_SCRATCH_DP2_ENABLE) {
6976 c = tegra_get_clock_by_name("dp2");
6977 if (WARN(!c, "%s: could not find la clk\n", __func__))
6981 c = tegra_get_clock_by_name("hdmi");
6982 if (WARN(!c, "%s: could not find la clk\n", __func__))
6988 #ifdef CONFIG_CPU_FREQ
6991 * Frequency table index must be sequential starting at 0 and frequencies
6992 * must be ascending.
6994 #define CPU_FREQ_STEP 102000 /* 102MHz cpu_g table step */
6995 #define CPU_FREQ_TABLE_MAX_SIZE (2 * MAX_DVFS_FREQS + 1)
6997 static struct cpufreq_frequency_table freq_table[CPU_FREQ_TABLE_MAX_SIZE];
6998 static struct tegra_cpufreq_table_data freq_table_data;
7000 struct tegra_cpufreq_table_data *tegra_cpufreq_table_get(void)
7003 bool g_vmin_done = false;
7004 unsigned int freq, lp_backup_freq, g_vmin_freq, g_start_freq, max_freq;
7005 struct clk *cpu_clk_g = tegra_get_clock_by_name("cpu_g");
7006 struct clk *cpu_clk_lp = tegra_get_clock_by_name("cpu_lp");
7008 /* Initialize once */
7009 if (freq_table_data.freq_table)
7010 return &freq_table_data;
7013 for (i = 0; i < CPU_FREQ_TABLE_MAX_SIZE; i++) {
7014 freq_table[i].index = i;
7015 freq_table[i].frequency = CPUFREQ_TABLE_END;
7018 lp_backup_freq = cpu_clk_lp->u.cpu.backup_rate / 1000;
7019 if (!lp_backup_freq) {
7020 WARN(1, "%s: cannot make cpufreq table: no LP CPU backup rate\n",
7024 if (!cpu_clk_lp->dvfs) {
7025 WARN(1, "%s: cannot make cpufreq table: no LP CPU dvfs\n",
7029 if (!cpu_clk_g->dvfs) {
7030 WARN(1, "%s: cannot make cpufreq table: no G CPU dvfs\n",
7034 g_vmin_freq = cpu_clk_g->dvfs->freqs[0] / 1000;
7035 if (g_vmin_freq <= lp_backup_freq) {
7036 WARN(1, "%s: cannot make cpufreq table: LP CPU backup rate"
7037 " exceeds G CPU rate at Vmin\n", __func__);
7041 /* Start with backup frequencies */
7043 freq = lp_backup_freq;
7044 freq_table[i++].frequency = freq/4;
7045 freq_table[i++].frequency = freq/2;
7046 freq_table[i++].frequency = freq;
7048 /* Throttle low index at backup level*/
7049 freq_table_data.throttle_lowest_index = i - 1;
7052 * Next, set table steps along LP CPU dvfs ladder, but make sure G CPU
7053 * dvfs rate at minimum voltage is not missed (if it happens to be below
7056 max_freq = cpu_clk_lp->max_rate / 1000;
7057 for (j = 0; j < cpu_clk_lp->dvfs->num_freqs; j++) {
7058 freq = cpu_clk_lp->dvfs->freqs[j] / 1000;
7059 if (freq <= lp_backup_freq)
7062 if (!g_vmin_done && (freq >= g_vmin_freq)) {
7064 if (freq > g_vmin_freq)
7065 freq_table[i++].frequency = g_vmin_freq;
7067 freq_table[i++].frequency = freq;
7069 if (freq == max_freq)
7073 /* Set G CPU min rate at least one table step below LP maximum */
7074 cpu_clk_g->min_rate = min(freq_table[i-2].frequency, g_vmin_freq)*1000;
7076 /* Suspend index at max LP CPU */
7077 freq_table_data.suspend_index = i - 1;
7079 /* Fill in "hole" (if any) between LP CPU maximum rate and G CPU dvfs
7080 ladder rate at minimum voltage */
7081 if (freq < g_vmin_freq) {
7082 int n = (g_vmin_freq - freq) / CPU_FREQ_STEP;
7083 for (j = 0; j <= n; j++) {
7084 freq = g_vmin_freq - CPU_FREQ_STEP * (n - j);
7085 freq_table[i++].frequency = freq;
7089 /* Now, step along the rest of G CPU dvfs ladder */
7090 g_start_freq = freq;
7091 max_freq = cpu_clk_g->max_rate / 1000;
7092 for (j = 0; j < cpu_clk_g->dvfs->num_freqs; j++) {
7093 freq = cpu_clk_g->dvfs->freqs[j] / 1000;
7094 if (freq > g_start_freq)
7095 freq_table[i++].frequency = freq;
7096 if (freq == max_freq)
7100 /* Throttle high index one step below maximum */
7101 BUG_ON(i >= CPU_FREQ_TABLE_MAX_SIZE);
7102 freq_table_data.throttle_highest_index = i - 2;
7103 freq_table_data.freq_table = freq_table;
7104 return &freq_table_data;
7107 unsigned long tegra_emc_to_cpu_ratio(unsigned long cpu_rate)
7109 static unsigned long emc_max_rate;
7111 if (emc_max_rate == 0)
7112 emc_max_rate = clk_round_rate(
7113 tegra_get_clock_by_name("emc"), ULONG_MAX);
7115 /* Vote on memory bus frequency based on cpu frequency;
7116 cpu rate is in kHz, emc rate is in Hz */
7117 if (cpu_rate >= 1300000)
7118 return emc_max_rate; /* cpu >= 1.3GHz, emc max */
7119 else if (cpu_rate >= 975000)
7120 return 400000000; /* cpu >= 975 MHz, emc 400 MHz */
7121 else if (cpu_rate >= 725000)
7122 return 200000000; /* cpu >= 725 MHz, emc 200 MHz */
7123 else if (cpu_rate >= 500000)
7124 return 100000000; /* cpu >= 500 MHz, emc 100 MHz */
7125 else if (cpu_rate >= 275000)
7126 return 50000000; /* cpu >= 275 MHz, emc 50 MHz */
7128 return 0; /* emc min */
7131 int tegra_update_mselect_rate(unsigned long cpu_rate)
7133 static struct clk *mselect = NULL;
7135 unsigned long mselect_rate;
7138 mselect = tegra_get_clock_by_name("mselect");
7143 /* Vote on mselect frequency based on cpu frequency:
7144 keep mselect at half of cpu rate up to 102 MHz;
7145 cpu rate is in kHz, mselect rate is in Hz */
7146 mselect_rate = DIV_ROUND_UP(cpu_rate, 2) * 1000;
7147 mselect_rate = min(mselect_rate, 102000000UL);
7149 if (mselect_rate != clk_get_rate(mselect))
7150 return clk_set_rate(mselect, mselect_rate);
7156 #ifdef CONFIG_PM_SLEEP
7157 static u32 clk_rst_suspend[RST_DEVICES_NUM + CLK_OUT_ENB_NUM +
7158 PERIPH_CLK_SOURCE_NUM + 25];
7160 static int tegra11_clk_suspend(void)
7163 u32 *ctx = clk_rst_suspend;
7165 *ctx++ = clk_readl(OSC_CTRL) & OSC_CTRL_MASK;
7166 *ctx++ = clk_readl(CPU_SOFTRST_CTRL);
7167 *ctx++ = clk_readl(CPU_SOFTRST_CTRL1);
7168 *ctx++ = clk_readl(CPU_SOFTRST_CTRL2);
7170 *ctx++ = clk_readl(tegra_pll_p_out1.reg);
7171 *ctx++ = clk_readl(tegra_pll_p_out3.reg);
7173 *ctx++ = clk_readl(tegra_pll_a.reg + PLL_BASE);
7174 *ctx++ = clk_readl(tegra_pll_a.reg + PLL_MISC(&tegra_pll_a));
7175 *ctx++ = clk_readl(tegra_pll_d.reg + PLL_BASE);
7176 *ctx++ = clk_readl(tegra_pll_d.reg + PLL_MISC(&tegra_pll_d));
7177 *ctx++ = clk_readl(tegra_pll_d2.reg + PLL_BASE);
7178 *ctx++ = clk_readl(tegra_pll_d2.reg + PLL_MISC(&tegra_pll_d2));
7180 *ctx++ = clk_readl(tegra_pll_m_out1.reg);
7181 *ctx++ = clk_readl(tegra_pll_a_out0.reg);
7182 *ctx++ = clk_readl(tegra_pll_c_out1.reg);
7184 *ctx++ = clk_readl(tegra_clk_cclk_lp.reg);
7185 *ctx++ = clk_readl(tegra_clk_cclk_lp.reg + SUPER_CLK_DIVIDER);
7187 *ctx++ = clk_readl(tegra_clk_sclk.reg);
7188 *ctx++ = clk_readl(tegra_clk_sclk.reg + SUPER_CLK_DIVIDER);
7189 *ctx++ = clk_readl(tegra_clk_pclk.reg);
7191 for (off = PERIPH_CLK_SOURCE_I2S1; off <= PERIPH_CLK_SOURCE_OSC;
7193 if (off == PERIPH_CLK_SOURCE_EMC)
7195 *ctx++ = clk_readl(off);
7197 for (off = PERIPH_CLK_SOURCE_G3D2; off <= PERIPH_CLK_SOURCE_SE;
7199 *ctx++ = clk_readl(off);
7201 for (off = AUDIO_DLY_CLK; off <= AUDIO_SYNC_CLK_SPDIF; off+=4) {
7202 *ctx++ = clk_readl(off);
7204 for (off = PERIPH_CLK_SOURCE_XUSB_HOST;
7205 off <= PERIPH_CLK_SOURCE_SOC_THERM; off += 4)
7206 *ctx++ = clk_readl(off);
7208 *ctx++ = clk_readl(RST_DEVICES_L);
7209 *ctx++ = clk_readl(RST_DEVICES_H);
7210 *ctx++ = clk_readl(RST_DEVICES_U);
7211 *ctx++ = clk_readl(RST_DEVICES_V);
7212 *ctx++ = clk_readl(RST_DEVICES_W);
7213 *ctx++ = clk_readl(RST_DEVICES_X);
7215 *ctx++ = clk_readl(CLK_OUT_ENB_L);
7216 *ctx++ = clk_readl(CLK_OUT_ENB_H);
7217 *ctx++ = clk_readl(CLK_OUT_ENB_U);
7218 *ctx++ = clk_readl(CLK_OUT_ENB_V);
7219 *ctx++ = clk_readl(CLK_OUT_ENB_W);
7220 *ctx++ = clk_readl(CLK_OUT_ENB_X);
7222 *ctx++ = clk_readl(tegra_clk_cclk_g.reg);
7223 *ctx++ = clk_readl(tegra_clk_cclk_g.reg + SUPER_CLK_DIVIDER);
7225 *ctx++ = clk_readl(SPARE_REG);
7226 *ctx++ = clk_readl(MISC_CLK_ENB);
7227 *ctx++ = clk_readl(CLK_MASK_ARM);
7232 static void tegra11_clk_resume(void)
7235 const u32 *ctx = clk_rst_suspend;
7240 u32 pll_p_out12, pll_p_out34;
7241 u32 pll_a_out0, pll_m_out1, pll_c_out1;
7244 /* FIXME: OSC_CTRL already restored by warm boot code? */
7245 val = clk_readl(OSC_CTRL) & ~OSC_CTRL_MASK;
7247 clk_writel(val, OSC_CTRL);
7248 clk_writel(*ctx++, CPU_SOFTRST_CTRL);
7249 clk_writel(*ctx++, CPU_SOFTRST_CTRL1);
7250 clk_writel(*ctx++, CPU_SOFTRST_CTRL2);
7253 /* Since we are going to reset devices and switch clock sources in this
7254 * function, plls and secondary dividers is required to be enabled. The
7255 * actual value will be restored back later. Note that boot plls: pllm,
7256 * pllp, and pllu are already configured and enabled
7258 val = PLL_OUT_CLKEN | PLL_OUT_RESET_DISABLE;
7260 pll_p_out12 = *ctx++;
7261 clk_writel(pll_p_out12 | val, tegra_pll_p_out1.reg);
7262 pll_p_out34 = *ctx++;
7263 clk_writel(pll_p_out34 | val, tegra_pll_p_out3.reg);
7265 tegra11_pllcx_clk_resume_enable(&tegra_pll_c2);
7266 tegra11_pllcx_clk_resume_enable(&tegra_pll_c3);
7267 tegra11_pllxc_clk_resume_enable(&tegra_pll_c);
7268 tegra11_pllxc_clk_resume_enable(&tegra_pll_x);
7269 tegra11_pllre_clk_resume_enable(&tegra_pll_re_out);
7272 clk_writel(*ctx++, tegra_pll_a.reg + PLL_MISC(&tegra_pll_a));
7273 clk_writel(plla_base | PLL_BASE_ENABLE, tegra_pll_a.reg + PLL_BASE);
7276 clk_writel(*ctx++, tegra_pll_d.reg + PLL_MISC(&tegra_pll_d));
7277 clk_writel(plld_base | PLL_BASE_ENABLE, tegra_pll_d.reg + PLL_BASE);
7279 plld2_base = *ctx++;
7280 clk_writel(*ctx++, tegra_pll_d2.reg + PLL_MISC(&tegra_pll_d2));
7281 clk_writel(plld2_base | PLL_BASE_ENABLE, tegra_pll_d2.reg + PLL_BASE);
7285 val = PLL_OUT_CLKEN | PLL_OUT_RESET_DISABLE;
7286 pll_m_out1 = *ctx++;
7287 clk_writel(pll_m_out1 | val, tegra_pll_m_out1.reg);
7288 pll_a_out0 = *ctx++;
7289 clk_writel(pll_a_out0 | val, tegra_pll_a_out0.reg);
7290 pll_c_out1 = *ctx++;
7291 clk_writel(pll_c_out1 | val, tegra_pll_c_out1.reg);
7294 tegra11_super_clk_resume(&tegra_clk_cclk_lp,
7295 tegra_clk_virtual_cpu_lp.u.cpu.backup, val);
7296 clk_writel(*ctx++, tegra_clk_cclk_lp.reg + SUPER_CLK_DIVIDER);
7298 clk_writel(*ctx++, tegra_clk_sclk.reg);
7299 clk_writel(*ctx++, tegra_clk_sclk.reg + SUPER_CLK_DIVIDER);
7300 clk_writel(*ctx++, tegra_clk_pclk.reg);
7302 /* enable all clocks before configuring clock sources */
7303 clk_writel(0xfdfffff1ul, CLK_OUT_ENB_L);
7304 clk_writel(0xffddfff7ul, CLK_OUT_ENB_H);
7305 clk_writel(0xfbfffbfeul, CLK_OUT_ENB_U);
7306 clk_writel(0xfffffffful, CLK_OUT_ENB_V);
7307 clk_writel(0xff7ffffful, CLK_OUT_ENB_W);
7310 for (off = PERIPH_CLK_SOURCE_I2S1; off <= PERIPH_CLK_SOURCE_OSC;
7312 if (off == PERIPH_CLK_SOURCE_EMC)
7314 clk_writel(*ctx++, off);
7316 for (off = PERIPH_CLK_SOURCE_G3D2; off <= PERIPH_CLK_SOURCE_SE;
7318 clk_writel(*ctx++, off);
7320 for (off = AUDIO_DLY_CLK; off <= AUDIO_SYNC_CLK_SPDIF; off+=4) {
7321 clk_writel(*ctx++, off);
7323 for (off = PERIPH_CLK_SOURCE_XUSB_HOST;
7324 off <= PERIPH_CLK_SOURCE_SOC_THERM; off += 4)
7325 clk_writel(*ctx++, off);
7327 clk_writel(*ctx++, RST_DEVICES_L);
7328 clk_writel(*ctx++, RST_DEVICES_H);
7329 clk_writel(*ctx++, RST_DEVICES_U);
7330 clk_writel(*ctx++, RST_DEVICES_V);
7331 clk_writel(*ctx++, RST_DEVICES_W);
7332 clk_writel(*ctx++, RST_DEVICES_X);
7335 clk_writel(*ctx++, CLK_OUT_ENB_L);
7336 clk_writel(*ctx++, CLK_OUT_ENB_H);
7337 clk_writel(*ctx++, CLK_OUT_ENB_U);
7339 /* For LP0 resume, clk to lpcpu is required to be on */
7340 /* FIXME: should be saved as on? */
7342 val |= CLK_OUT_ENB_V_CLK_ENB_CPULP_EN;
7343 clk_writel(val, CLK_OUT_ENB_V);
7345 clk_writel(*ctx++, CLK_OUT_ENB_W);
7346 clk_writel(*ctx++, CLK_OUT_ENB_X);
7349 /* DFLL resume after cl_dvfs and i2c5 clocks are resumed */
7350 tegra11_dfll_clk_resume(&tegra_dfll_cpu);
7352 /* CPU G clock restored after DFLL and PLLs */
7353 clk_writel(*ctx++, tegra_clk_cclk_g.reg);
7354 clk_writel(*ctx++, tegra_clk_cclk_g.reg + SUPER_CLK_DIVIDER);
7356 clk_writel(*ctx++, SPARE_REG);
7357 clk_writel(*ctx++, MISC_CLK_ENB);
7358 clk_writel(*ctx++, CLK_MASK_ARM);
7360 /* Restore back the actual pll and secondary divider values */
7361 clk_writel(pll_p_out12, tegra_pll_p_out1.reg);
7362 clk_writel(pll_p_out34, tegra_pll_p_out3.reg);
7365 if (p->state == OFF)
7366 tegra11_pllcx_clk_disable(p);
7368 if (p->state == OFF)
7369 tegra11_pllcx_clk_disable(p);
7371 if (p->state == OFF)
7372 tegra11_pllxc_clk_disable(p);
7374 if (p->state == OFF)
7375 tegra11_pllxc_clk_disable(p);
7376 p = &tegra_pll_re_vco;
7377 if (p->state == OFF)
7378 tegra11_pllre_clk_disable(p);
7380 clk_writel(plla_base, tegra_pll_a.reg + PLL_BASE);
7381 clk_writel(plld_base, tegra_pll_d.reg + PLL_BASE);
7382 clk_writel(plld2_base, tegra_pll_d2.reg + PLL_BASE);
7384 clk_writel(pll_m_out1, tegra_pll_m_out1.reg);
7385 clk_writel(pll_a_out0, tegra_pll_a_out0.reg);
7386 clk_writel(pll_c_out1, tegra_pll_c_out1.reg);
7388 /* Since EMC clock is not restored, and may not preserve parent across
7389 suspend, update current state, and mark EMC DFS as out of sync */
7390 p = tegra_clk_emc.parent;
7391 tegra11_periph_clk_init(&tegra_clk_emc);
7393 if (p != tegra_clk_emc.parent) {
7394 /* FIXME: old parent is left enabled here even if EMC was its
7395 only child before suspend (may happen on Tegra11 !!) */
7396 pr_debug("EMC parent(refcount) across suspend: %s(%d) : %s(%d)",
7397 p->name, p->refcnt, tegra_clk_emc.parent->name,
7398 tegra_clk_emc.parent->refcnt);
7403 /* the new parent is enabled by low level code, but ref count
7404 need to be updated up to the root */
7405 p = tegra_clk_emc.parent;
7406 while (p && ((p->refcnt++) == 0))
7409 tegra_emc_timing_invalidate();
7411 tegra11_pll_clk_init(&tegra_pll_u); /* Re-init utmi parameters */
7412 tegra11_plle_clk_resume(&tegra_pll_e); /* Restore plle parent as pll_re_vco */
7413 tegra11_pllp_clk_resume(&tegra_pll_p); /* Fire a bug if not restored */
7416 static struct syscore_ops tegra_clk_syscore_ops = {
7417 .suspend = tegra11_clk_suspend,
7418 .resume = tegra11_clk_resume,
7422 /* Tegra11 CPU clock and reset control functions */
7423 static void tegra11_wait_cpu_in_reset(u32 cpu)
7428 reg = readl(reg_clk_base +
7429 TEGRA30_CLK_RST_CONTROLLER_CPU_CMPLX_STATUS);
7431 } while (!(reg & (1 << cpu))); /* check CPU been reset or not */
7436 static void tegra11_put_cpu_in_reset(u32 cpu)
7438 writel(CPU_RESET(cpu),
7439 reg_clk_base + TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET);
7443 static void tegra11_cpu_out_of_reset(u32 cpu)
7445 writel(CPU_RESET(cpu),
7446 reg_clk_base + TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR);
7450 static void tegra11_enable_cpu_clock(u32 cpu)
7454 writel(CPU_CLOCK(cpu),
7455 reg_clk_base + TEGRA30_CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR);
7456 reg = readl(reg_clk_base +
7457 TEGRA30_CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR);
7459 static void tegra11_disable_cpu_clock(u32 cpu)
7463 static struct tegra_cpu_car_ops tegra11_cpu_car_ops = {
7464 .wait_for_reset = tegra11_wait_cpu_in_reset,
7465 .put_in_reset = tegra11_put_cpu_in_reset,
7466 .out_of_reset = tegra11_cpu_out_of_reset,
7467 .enable_clock = tegra11_enable_cpu_clock,
7468 .disable_clock = tegra11_disable_cpu_clock,
7471 static void __init tegra11_cpu_car_ops_init(void)
7473 tegra_cpu_car_ops = &tegra11_cpu_car_ops;
7476 void __init tegra11x_init_clocks(void)
7481 for (i = 0; i < ARRAY_SIZE(tegra_ptr_clks); i++)
7482 tegra11_init_one_clock(tegra_ptr_clks[i]);
7484 for (i = 0; i < ARRAY_SIZE(tegra_list_clks); i++)
7485 tegra11_init_one_clock(&tegra_list_clks[i]);
7487 for (i = 0; i < ARRAY_SIZE(tegra_clk_duplicates); i++) {
7488 c = tegra_get_clock_by_name(tegra_clk_duplicates[i].name);
7490 pr_err("%s: Unknown duplicate clock %s\n", __func__,
7491 tegra_clk_duplicates[i].name);
7495 tegra_clk_duplicates[i].lookup.clk = c;
7496 clkdev_add(&tegra_clk_duplicates[i].lookup);
7499 for (i = 0; i < ARRAY_SIZE(tegra_sync_source_list); i++)
7500 tegra11_init_one_clock(&tegra_sync_source_list[i]);
7501 for (i = 0; i < ARRAY_SIZE(tegra_clk_audio_list); i++)
7502 tegra11_init_one_clock(&tegra_clk_audio_list[i]);
7503 for (i = 0; i < ARRAY_SIZE(tegra_clk_audio_2x_list); i++)
7504 tegra11_init_one_clock(&tegra_clk_audio_2x_list[i]);
7507 for (i = 0; i < ARRAY_SIZE(tegra_clk_out_list); i++)
7508 tegra11_init_one_clock(&tegra_clk_out_list[i]);
7510 for (i = 0; i < ARRAY_SIZE(tegra_xusb_source_clks); i++)
7511 tegra11_init_one_clock(&tegra_xusb_source_clks[i]);
7513 for (i = 0; i < ARRAY_SIZE(tegra_xusb_coupled_clks); i++)
7514 tegra11_init_one_clock(&tegra_xusb_coupled_clks[i]);
7516 /* Initialize to default */
7517 tegra_init_cpu_edp_limits(0);
7519 #ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS
7520 /* To be ready for DFLL late init */
7521 tegra_dfll_cpu.ops->init = tegra11_dfll_cpu_late_init;
7524 tegra11_cpu_car_ops_init();
7526 #ifdef CONFIG_PM_SLEEP
7527 register_syscore_ops(&tegra_clk_syscore_ops);