2 * arch/arm/mach-tegra/tegra11_clocks.c
4 * Copyright (c) 2011-2013, NVIDIA CORPORATION. All rights reserved.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * You should have received a copy of the GNU General Public License along
16 * with this program; if not, write to the Free Software Foundation, Inc.,
17 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
21 #include <linux/kernel.h>
22 #include <linux/module.h>
23 #include <linux/list.h>
24 #include <linux/spinlock.h>
25 #include <linux/delay.h>
26 #include <linux/err.h>
28 #include <linux/clk.h>
29 #include <linux/cpufreq.h>
30 #include <linux/syscore_ops.h>
31 #include <linux/platform_device.h>
32 #include <linux/clk/tegra.h>
33 #include <linux/tegra-soc.h>
34 #include <linux/tegra-powergate.h>
36 #include <asm/clkdev.h>
47 #include "tegra11_emc.h"
48 #include "tegra_cl_dvfs.h"
50 #define RST_DEVICES_L 0x004
51 #define RST_DEVICES_H 0x008
52 #define RST_DEVICES_U 0x00C
53 #define RST_DEVICES_V 0x358
54 #define RST_DEVICES_W 0x35C
55 #define RST_DEVICES_X 0x28C
56 #define RST_DEVICES_SET_L 0x300
57 #define RST_DEVICES_CLR_L 0x304
58 #define RST_DEVICES_SET_V 0x430
59 #define RST_DEVICES_CLR_V 0x434
60 #define RST_DEVICES_SET_X 0x290
61 #define RST_DEVICES_CLR_X 0x294
62 #define RST_DEVICES_NUM 6
64 #define CLK_OUT_ENB_L 0x010
65 #define CLK_OUT_ENB_H 0x014
66 #define CLK_OUT_ENB_U 0x018
67 #define CLK_OUT_ENB_V 0x360
68 #define CLK_OUT_ENB_W 0x364
69 #define CLK_OUT_ENB_X 0x280
70 #define CLK_OUT_ENB_SET_L 0x320
71 #define CLK_OUT_ENB_CLR_L 0x324
72 #define CLK_OUT_ENB_SET_V 0x440
73 #define CLK_OUT_ENB_CLR_V 0x444
74 #define CLK_OUT_ENB_SET_X 0x284
75 #define CLK_OUT_ENB_CLR_X 0x288
76 #define CLK_OUT_ENB_NUM 6
78 #define RST_DEVICES_V_SWR_CPULP_RST_DIS (0x1 << 1) /* Reserved on Tegra11 */
79 #define CLK_OUT_ENB_V_CLK_ENB_CPULP_EN (0x1 << 1)
81 #define PERIPH_CLK_TO_BIT(c) (1 << (c->u.periph.clk_num % 32))
82 #define PERIPH_CLK_TO_RST_REG(c) \
83 periph_clk_to_reg((c), RST_DEVICES_L, RST_DEVICES_V, RST_DEVICES_X, 4)
84 #define PERIPH_CLK_TO_RST_SET_REG(c) \
85 periph_clk_to_reg((c), RST_DEVICES_SET_L, RST_DEVICES_SET_V, \
87 #define PERIPH_CLK_TO_RST_CLR_REG(c) \
88 periph_clk_to_reg((c), RST_DEVICES_CLR_L, RST_DEVICES_CLR_V, \
91 #define PERIPH_CLK_TO_ENB_REG(c) \
92 periph_clk_to_reg((c), CLK_OUT_ENB_L, CLK_OUT_ENB_V, CLK_OUT_ENB_X, 4)
93 #define PERIPH_CLK_TO_ENB_SET_REG(c) \
94 periph_clk_to_reg((c), CLK_OUT_ENB_SET_L, CLK_OUT_ENB_SET_V, \
96 #define PERIPH_CLK_TO_ENB_CLR_REG(c) \
97 periph_clk_to_reg((c), CLK_OUT_ENB_CLR_L, CLK_OUT_ENB_CLR_V, \
100 #define CLK_MASK_ARM 0x44
101 #define MISC_CLK_ENB 0x48
103 #define OSC_CTRL 0x50
104 #define OSC_CTRL_OSC_FREQ_MASK (0xF<<28)
105 #define OSC_CTRL_OSC_FREQ_13MHZ (0x0<<28)
106 #define OSC_CTRL_OSC_FREQ_19_2MHZ (0x4<<28)
107 #define OSC_CTRL_OSC_FREQ_12MHZ (0x8<<28)
108 #define OSC_CTRL_OSC_FREQ_26MHZ (0xC<<28)
109 #define OSC_CTRL_OSC_FREQ_16_8MHZ (0x1<<28)
110 #define OSC_CTRL_OSC_FREQ_38_4MHZ (0x5<<28)
111 #define OSC_CTRL_OSC_FREQ_48MHZ (0x9<<28)
112 #define OSC_CTRL_MASK (0x3f2 | OSC_CTRL_OSC_FREQ_MASK)
114 #define OSC_CTRL_PLL_REF_DIV_MASK (3<<26)
115 #define OSC_CTRL_PLL_REF_DIV_1 (0<<26)
116 #define OSC_CTRL_PLL_REF_DIV_2 (1<<26)
117 #define OSC_CTRL_PLL_REF_DIV_4 (2<<26)
119 #define PERIPH_CLK_SOURCE_I2S1 0x100
120 #define PERIPH_CLK_SOURCE_EMC 0x19c
121 #define PERIPH_CLK_SOURCE_OSC 0x1fc
122 #define PERIPH_CLK_SOURCE_NUM1 \
123 ((PERIPH_CLK_SOURCE_OSC - PERIPH_CLK_SOURCE_I2S1) / 4)
125 #define PERIPH_CLK_SOURCE_G3D2 0x3b0
126 #define PERIPH_CLK_SOURCE_SE 0x42c
127 #define PERIPH_CLK_SOURCE_NUM2 \
128 ((PERIPH_CLK_SOURCE_SE - PERIPH_CLK_SOURCE_G3D2) / 4 + 1)
130 #define AUDIO_DLY_CLK 0x49c
131 #define AUDIO_SYNC_CLK_SPDIF 0x4b4
132 #define PERIPH_CLK_SOURCE_NUM3 \
133 ((AUDIO_SYNC_CLK_SPDIF - AUDIO_DLY_CLK) / 4 + 1)
135 #define SPARE_REG 0x55c
136 #define PERIPH_CLK_SOURCE_XUSB_HOST 0x600
137 #define PERIPH_CLK_SOURCE_SOC_THERM 0x644
138 #define PERIPH_CLK_SOURCE_NUM4 \
139 ((PERIPH_CLK_SOURCE_SOC_THERM - PERIPH_CLK_SOURCE_XUSB_HOST) / 4 + 1)
141 #define PERIPH_CLK_SOURCE_NUM (PERIPH_CLK_SOURCE_NUM1 + \
142 PERIPH_CLK_SOURCE_NUM2 + \
143 PERIPH_CLK_SOURCE_NUM3 + \
144 PERIPH_CLK_SOURCE_NUM4)
146 #define CPU_SOFTRST_CTRL 0x380
147 #define CPU_SOFTRST_CTRL1 0x384
148 #define CPU_SOFTRST_CTRL2 0x388
150 #define PERIPH_CLK_SOURCE_DIVU71_MASK 0xFF
151 #define PERIPH_CLK_SOURCE_DIVU16_MASK 0xFFFF
152 #define PERIPH_CLK_SOURCE_DIV_SHIFT 0
153 #define PERIPH_CLK_SOURCE_DIVIDLE_SHIFT 8
154 #define PERIPH_CLK_SOURCE_DIVIDLE_VAL 50
155 #define PERIPH_CLK_UART_DIV_ENB (1<<24)
156 #define PERIPH_CLK_VI_SEL_EX_SHIFT 24
157 #define PERIPH_CLK_VI_SEL_EX_MASK (0x3<<PERIPH_CLK_VI_SEL_EX_SHIFT)
158 #define PERIPH_CLK_NAND_DIV_EX_ENB (1<<8)
159 #define PERIPH_CLK_DTV_POLARITY_INV (1<<25)
161 #define AUDIO_SYNC_SOURCE_MASK 0x0F
162 #define AUDIO_SYNC_DISABLE_BIT 0x10
163 #define AUDIO_SYNC_TAP_NIBBLE_SHIFT(c) ((c->reg_shift - 24) * 4)
167 #define PLL_BASE_BYPASS (1<<31)
168 #define PLL_BASE_ENABLE (1<<30)
169 #define PLL_BASE_REF_ENABLE (1<<29)
170 #define PLL_BASE_OVERRIDE (1<<28)
171 #define PLL_BASE_LOCK (1<<27)
172 #define PLL_BASE_DIVP_MASK (0x7<<20)
173 #define PLL_BASE_DIVP_SHIFT 20
174 #define PLL_BASE_DIVN_MASK (0x3FF<<8)
175 #define PLL_BASE_DIVN_SHIFT 8
176 #define PLL_BASE_DIVM_MASK (0x1F)
177 #define PLL_BASE_DIVM_SHIFT 0
179 #define PLL_BASE_PARSE(pll, cfg, b) \
181 (cfg).m = ((b) & pll##_BASE_DIVM_MASK) >> PLL_BASE_DIVM_SHIFT; \
182 (cfg).n = ((b) & pll##_BASE_DIVN_MASK) >> PLL_BASE_DIVN_SHIFT; \
183 (cfg).p = ((b) & pll##_BASE_DIVP_MASK) >> PLL_BASE_DIVP_SHIFT; \
186 #define PLL_OUT_RATIO_MASK (0xFF<<8)
187 #define PLL_OUT_RATIO_SHIFT 8
188 #define PLL_OUT_OVERRIDE (1<<2)
189 #define PLL_OUT_CLKEN (1<<1)
190 #define PLL_OUT_RESET_DISABLE (1<<0)
192 #define PLL_MISC(c) \
193 (((c)->flags & PLL_ALT_MISC_REG) ? 0x4 : 0xc)
194 #define PLL_MISCN(c, n) \
195 ((c)->u.pll.misc1 + ((n) - 1) * PLL_MISC(c))
196 #define PLL_MISC_LOCK_ENABLE(c) \
197 (((c)->flags & (PLLU | PLLD)) ? (1<<22) : (1<<18))
199 #define PLL_MISC_DCCON_SHIFT 20
200 #define PLL_MISC_CPCON_SHIFT 8
201 #define PLL_MISC_CPCON_MASK (0xF<<PLL_MISC_CPCON_SHIFT)
202 #define PLL_MISC_LFCON_SHIFT 4
203 #define PLL_MISC_LFCON_MASK (0xF<<PLL_MISC_LFCON_SHIFT)
204 #define PLL_MISC_VCOCON_SHIFT 0
205 #define PLL_MISC_VCOCON_MASK (0xF<<PLL_MISC_VCOCON_SHIFT)
207 #define PLL_FIXED_MDIV(c, ref) ((ref) > (c)->u.pll.cf_max ? 2 : 1)
210 #define PLLU_BASE_OVERRIDE (1<<24)
211 #define PLLU_BASE_POST_DIV (1<<20)
214 #define PLLD_BASE_CSI_CLKENABLE (1<<26)
215 #define PLLD_BASE_DSI_MUX_SHIFT 25
216 #define PLLD_BASE_DSI_MUX_MASK (1<<PLLD_BASE_DSI_MUX_SHIFT)
217 #define PLLD_BASE_CSI_CLKSOURCE (1<<24)
219 #define PLLD_MISC_DSI_CLKENABLE (1<<30)
220 #define PLLD_MISC_DIV_RST (1<<23)
221 #define PLLD_MISC_DCCON_SHIFT 12
223 #define PLLDU_LFCON 2
225 /* PLLC2 and PLLC3 (PLLCX) */
226 #define PLLCX_USE_DYN_RAMP 0
227 #define PLLCX_BASE_PHASE_LOCK (1<<26)
228 #define PLLCX_BASE_DIVP_MASK (0x7<<PLL_BASE_DIVP_SHIFT)
229 #define PLLCX_BASE_DIVN_MASK (0xFF<<PLL_BASE_DIVN_SHIFT)
230 #define PLLCX_BASE_DIVM_MASK (0x3<<PLL_BASE_DIVM_SHIFT)
231 #define PLLCX_PDIV_MAX ((PLLCX_BASE_DIVP_MASK >> PLL_BASE_DIVP_SHIFT))
232 #define PLLCX_IS_DYN(new_p, old_p) (((new_p) <= 8) && ((old_p) <= 8))
234 #define PLLCX_MISC_STROBE (1<<31)
235 #define PLLCX_MISC_RESET (1<<30)
236 #define PLLCX_MISC_SDM_DIV_SHIFT 28
237 #define PLLCX_MISC_SDM_DIV_MASK (0x3 << PLLCX_MISC_SDM_DIV_SHIFT)
238 #define PLLCX_MISC_FILT_DIV_SHIFT 26
239 #define PLLCX_MISC_FILT_DIV_MASK (0x3 << PLLCX_MISC_FILT_DIV_SHIFT)
240 #define PLLCX_MISC_ALPHA_SHIFT 18
241 #define PLLCX_MISC_ALPHA_MASK (0xFF << PLLCX_MISC_ALPHA_SHIFT)
242 #define PLLCX_MISC_KB_SHIFT 9
243 #define PLLCX_MISC_KB_MASK (0x1FF << PLLCX_MISC_KB_SHIFT)
244 #define PLLCX_MISC_KA_SHIFT 2
245 #define PLLCX_MISC_KA_MASK (0x7F << PLLCX_MISC_KA_SHIFT)
246 #define PLLCX_MISC_VCO_GAIN_SHIFT 0
247 #define PLLCX_MISC_VCO_GAIN_MASK (0x3 << PLLCX_MISC_VCO_GAIN_SHIFT)
249 #define PLLCX_MISC_KOEF_LOW_RANGE \
250 ((0x14 << PLLCX_MISC_KA_SHIFT) | (0x38 << PLLCX_MISC_KB_SHIFT))
252 #define PLLCX_MISC_DIV_LOW_RANGE \
253 ((0x1 << PLLCX_MISC_SDM_DIV_SHIFT) | (0x1 << PLLCX_MISC_FILT_DIV_SHIFT))
254 #define PLLCX_MISC_DIV_HIGH_RANGE \
255 ((0x2 << PLLCX_MISC_SDM_DIV_SHIFT) | (0x2 << PLLCX_MISC_FILT_DIV_SHIFT))
257 #define PLLCX_MISC_DEFAULT_VALUE ((0x0 << PLLCX_MISC_VCO_GAIN_SHIFT) | \
258 PLLCX_MISC_KOEF_LOW_RANGE | \
259 (0x19 << PLLCX_MISC_ALPHA_SHIFT) | \
260 PLLCX_MISC_DIV_LOW_RANGE | \
262 #define PLLCX_MISC1_DEFAULT_VALUE 0x000d2308
263 #define PLLCX_MISC2_DEFAULT_VALUE 0x30211200
264 #define PLLCX_MISC3_DEFAULT_VALUE 0x200
266 /* PLLX and PLLC (PLLXC)*/
267 #define PLLXC_USE_DYN_RAMP 0
268 #define PLLXC_BASE_DIVP_MASK (0xF<<PLL_BASE_DIVP_SHIFT)
269 #define PLLXC_BASE_DIVN_MASK (0xFF<<PLL_BASE_DIVN_SHIFT)
270 #define PLLXC_BASE_DIVM_MASK (0xFF<<PLL_BASE_DIVM_SHIFT)
272 /* PLLXC has 4-bit PDIV, but entry 15 is not allowed in h/w,
273 and s/w usage is limited to 5 */
274 #define PLLXC_PDIV_MAX 14
275 #define PLLXC_SW_PDIV_MAX 5
278 #define PLLX_MISC2_DYNRAMP_STEPB_SHIFT 24
279 #define PLLX_MISC2_DYNRAMP_STEPB_MASK (0xFF << PLLX_MISC2_DYNRAMP_STEPB_SHIFT)
280 #define PLLX_MISC2_DYNRAMP_STEPA_SHIFT 16
281 #define PLLX_MISC2_DYNRAMP_STEPA_MASK (0xFF << PLLX_MISC2_DYNRAMP_STEPA_SHIFT)
282 #define PLLX_MISC2_NDIV_NEW_SHIFT 8
283 #define PLLX_MISC2_NDIV_NEW_MASK (0xFF << PLLX_MISC2_NDIV_NEW_SHIFT)
284 #define PLLX_MISC2_LOCK_OVERRIDE (0x1 << 4)
285 #define PLLX_MISC2_DYNRAMP_DONE (0x1 << 2)
286 #define PLLX_MISC2_CLAMP_NDIV (0x1 << 1)
287 #define PLLX_MISC2_EN_DYNRAMP (0x1 << 0)
289 #define PLLX_MISC3_IDDQ (0x1 << 3)
291 #define PLLX_HW_CTRL_CFG 0x548
292 #define PLLX_HW_CTRL_CFG_SWCTRL (0x1 << 0)
295 #define PLLC_BASE_LOCK_OVERRIDE (1<<28)
297 #define PLLC_MISC_IDDQ (0x1 << 26)
298 #define PLLC_MISC_LOCK_ENABLE (0x1 << 24)
300 #define PLLC_MISC1_CLAMP_NDIV (0x1 << 26)
301 #define PLLC_MISC1_EN_DYNRAMP (0x1 << 25)
302 #define PLLC_MISC1_DYNRAMP_STEPA_SHIFT 17
303 #define PLLC_MISC1_DYNRAMP_STEPA_MASK (0xFF << PLLC_MISC1_DYNRAMP_STEPA_SHIFT)
304 #define PLLC_MISC1_DYNRAMP_STEPB_SHIFT 9
305 #define PLLC_MISC1_DYNRAMP_STEPB_MASK (0xFF << PLLC_MISC1_DYNRAMP_STEPB_SHIFT)
306 #define PLLC_MISC1_NDIV_NEW_SHIFT 1
307 #define PLLC_MISC1_NDIV_NEW_MASK (0xFF << PLLC_MISC1_NDIV_NEW_SHIFT)
308 #define PLLC_MISC1_DYNRAMP_DONE (0x1 << 0)
311 #define PLLM_BASE_DIVP_MASK (0x1 << PLL_BASE_DIVP_SHIFT)
312 #define PLLM_BASE_DIVN_MASK (0xFF << PLL_BASE_DIVN_SHIFT)
313 #define PLLM_BASE_DIVM_MASK (0xFF << PLL_BASE_DIVM_SHIFT)
314 #define PLLM_PDIV_MAX 1
316 #define PLLM_MISC_FSM_SW_OVERRIDE (0x1 << 10)
317 #define PLLM_MISC_IDDQ (0x1 << 5)
318 #define PLLM_MISC_LOCK_DISABLE (0x1 << 4)
319 #define PLLM_MISC_LOCK_OVERRIDE (0x1 << 3)
321 #define PMC_PLLP_WB0_OVERRIDE 0xf8
322 #define PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE (1 << 12)
323 #define PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE (1 << 11)
325 /* M, N layout for PLLM override and base registers are the same */
326 #define PMC_PLLM_WB0_OVERRIDE 0x1dc
328 #define PMC_PLLM_WB0_OVERRIDE_2 0x2b0
329 #define PMC_PLLM_WB0_OVERRIDE_2_DIVP_MASK (0x1 << 27)
332 #define PLLRE_BASE_DIVP_SHIFT 16
333 #define PLLRE_BASE_DIVP_MASK (0xF << PLLRE_BASE_DIVP_SHIFT)
334 #define PLLRE_BASE_DIVN_MASK (0xFF << PLL_BASE_DIVN_SHIFT)
335 #define PLLRE_BASE_DIVM_MASK (0xFF << PLL_BASE_DIVM_SHIFT)
337 /* PLLRE has 4-bit PDIV, but entry 15 is not allowed in h/w,
338 and s/w usage is limited to 5 */
339 #define PLLRE_PDIV_MAX 14
340 #define PLLRE_SW_PDIV_MAX 5
342 #define PLLRE_MISC_LOCK_ENABLE (0x1 << 30)
343 #define PLLRE_MISC_LOCK_OVERRIDE (0x1 << 29)
344 #define PLLRE_MISC_LOCK (0x1 << 24)
345 #define PLLRE_MISC_IDDQ (0x1 << 16)
347 #define OUT_OF_TABLE_CPCON 0x8
349 #define SUPER_CLK_MUX 0x00
350 #define SUPER_STATE_SHIFT 28
351 #define SUPER_STATE_MASK (0xF << SUPER_STATE_SHIFT)
352 #define SUPER_STATE_STANDBY (0x0 << SUPER_STATE_SHIFT)
353 #define SUPER_STATE_IDLE (0x1 << SUPER_STATE_SHIFT)
354 #define SUPER_STATE_RUN (0x2 << SUPER_STATE_SHIFT)
355 #define SUPER_STATE_IRQ (0x3 << SUPER_STATE_SHIFT)
356 #define SUPER_STATE_FIQ (0x4 << SUPER_STATE_SHIFT)
357 #define SUPER_LP_DIV2_BYPASS (0x1 << 16)
358 #define SUPER_SOURCE_MASK 0xF
359 #define SUPER_FIQ_SOURCE_SHIFT 12
360 #define SUPER_IRQ_SOURCE_SHIFT 8
361 #define SUPER_RUN_SOURCE_SHIFT 4
362 #define SUPER_IDLE_SOURCE_SHIFT 0
364 #define SUPER_CLK_DIVIDER 0x04
365 #define SUPER_CLOCK_DIV_U71_SHIFT 16
366 #define SUPER_CLOCK_DIV_U71_MASK (0xff << SUPER_CLOCK_DIV_U71_SHIFT)
368 #define BUS_CLK_DISABLE (1<<3)
369 #define BUS_CLK_DIV_MASK 0x3
372 #define PMC_CTRL_BLINK_ENB (1 << 7)
374 #define PMC_DPD_PADS_ORIDE 0x1c
375 #define PMC_DPD_PADS_ORIDE_BLINK_ENB (1 << 20)
377 #define PMC_BLINK_TIMER_DATA_ON_SHIFT 0
378 #define PMC_BLINK_TIMER_DATA_ON_MASK 0x7fff
379 #define PMC_BLINK_TIMER_ENB (1 << 15)
380 #define PMC_BLINK_TIMER_DATA_OFF_SHIFT 16
381 #define PMC_BLINK_TIMER_DATA_OFF_MASK 0xffff
383 #define UTMIP_PLL_CFG2 0x488
384 #define UTMIP_PLL_CFG2_STABLE_COUNT(x) (((x) & 0xfff) << 6)
385 #define UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(x) (((x) & 0x3f) << 18)
386 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN (1 << 0)
387 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERUP (1 << 1)
388 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN (1 << 2)
389 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERUP (1 << 3)
390 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN (1 << 4)
391 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERUP (1 << 5)
392 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_D_POWERDOWN (1 << 24)
393 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_D_POWERUP (1 << 25)
395 #define UTMIP_PLL_CFG1 0x484
396 #define UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(x) (((x) & 0x1f) << 27)
397 #define UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(x) (((x) & 0xfff) << 0)
398 #define UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERUP (1 << 15)
399 #define UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN (1 << 14)
400 #define UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN (1 << 12)
401 #define UTMIP_PLL_CFG1_FORCE_PLLU_POWERUP (1 << 17)
402 #define UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN (1 << 16)
405 #define PLLE_BASE_LOCK_OVERRIDE (0x1 << 29)
406 #define PLLE_BASE_DIVCML_SHIFT 24
407 #define PLLE_BASE_DIVCML_MASK (0xf<<PLLE_BASE_DIVCML_SHIFT)
408 #define PLLE_BASE_DIVN_MASK (0xFF<<PLL_BASE_DIVN_SHIFT)
409 #define PLLE_BASE_DIVM_MASK (0xFF<<PLL_BASE_DIVM_SHIFT)
411 /* PLLE has 4-bit CMLDIV, but entry 15 is not allowed in h/w */
412 #define PLLE_CMLDIV_MAX 14
414 #define PLLE_MISC_READY (1<<15)
415 #define PLLE_MISC_IDDQ_SW_CTRL (1<<14)
416 #define PLLE_MISC_IDDQ_SW_VALUE (1<<13)
417 #define PLLE_MISC_LOCK (1<<11)
418 #define PLLE_MISC_LOCK_ENABLE (1<<9)
419 #define PLLE_MISC_PLLE_PTS (1<<8)
420 #define PLLE_MISC_VREG_BG_CTRL_SHIFT 4
421 #define PLLE_MISC_VREG_BG_CTRL_MASK (0x3<<PLLE_MISC_VREG_BG_CTRL_SHIFT)
422 #define PLLE_MISC_VREG_CTRL_SHIFT 2
423 #define PLLE_MISC_VREG_CTRL_MASK (0x3<<PLLE_MISC_VREG_CTRL_SHIFT)
425 #define PLLE_SS_CTRL 0x68
426 #define PLLE_SS_INCINTRV_SHIFT 24
427 #define PLLE_SS_INCINTRV_MASK (0x3f<<PLLE_SS_INCINTRV_SHIFT)
428 #define PLLE_SS_INC_SHIFT 16
429 #define PLLE_SS_INC_MASK (0xff<<PLLE_SS_INC_SHIFT)
430 #define PLLE_SS_CNTL_INVERT (0x1 << 15)
431 #define PLLE_SS_CNTL_CENTER (0x1 << 14)
432 #define PLLE_SS_CNTL_SSC_BYP (0x1 << 12)
433 #define PLLE_SS_CNTL_INTERP_RESET (0x1 << 11)
434 #define PLLE_SS_CNTL_BYPASS_SS (0x1 << 10)
435 #define PLLE_SS_MAX_SHIFT 0
436 #define PLLE_SS_MAX_MASK (0x1ff<<PLLE_SS_MAX_SHIFT)
437 #define PLLE_SS_COEFFICIENTS_MASK \
438 (PLLE_SS_INCINTRV_MASK | PLLE_SS_INC_MASK | PLLE_SS_MAX_MASK)
439 #define PLLE_SS_COEFFICIENTS_VAL \
440 ((0x20<<PLLE_SS_INCINTRV_SHIFT) | (0x1<<PLLE_SS_INC_SHIFT) | \
441 (0x25<<PLLE_SS_MAX_SHIFT))
442 #define PLLE_SS_DISABLE (PLLE_SS_CNTL_SSC_BYP |\
443 PLLE_SS_CNTL_INTERP_RESET | PLLE_SS_CNTL_BYPASS_SS)
445 #define PLLE_AUX 0x48c
446 #define PLLE_AUX_PLLRE_SEL (1<<28)
447 #define PLLE_AUX_SEQ_STATE_SHIFT 26
448 #define PLLE_AUX_SEQ_STATE_MASK (0x3<<PLLE_AUX_SEQ_STATE_SHIFT)
449 #define PLLE_AUX_SEQ_START_STATE (1<<25)
450 #define PLLE_AUX_SEQ_ENABLE (1<<24)
451 #define PLLE_AUX_SS_SWCTL (1<<6)
452 #define PLLE_AUX_ENABLE_SWCTL (1<<4)
453 #define PLLE_AUX_USE_LOCKDET (1<<3)
454 #define PLLE_AUX_PLLP_SEL (1<<2)
456 /* USB PLLs PD HW controls */
457 #define XUSBIO_PLL_CFG0 0x51c
458 #define XUSBIO_PLL_CFG0_SEQ_START_STATE (1<<25)
459 #define XUSBIO_PLL_CFG0_SEQ_ENABLE (1<<24)
460 #define XUSBIO_PLL_CFG0_PADPLL_USE_LOCKDET (1<<6)
461 #define XUSBIO_PLL_CFG0_CLK_ENABLE_SWCTL (1<<2)
462 #define XUSBIO_PLL_CFG0_PADPLL_RESET_SWCTL (1<<0)
464 /* XUSB PLL PAD controls */
465 #define XUSB_PADCTL_IOPHY_PLL0_CTL1 0x30
466 #define XUSB_PADCTL_IOPHY_PLL0_CTL1_PLL_PWR_OVRD (1<<3)
467 #define XUSB_PADCTL_IOPHY_PLL0_CTL1_PLL_IDDQ (1<<0)
469 #define UTMIPLL_HW_PWRDN_CFG0 0x52c
470 #define UTMIPLL_HW_PWRDN_CFG0_SEQ_START_STATE (1<<25)
471 #define UTMIPLL_HW_PWRDN_CFG0_SEQ_ENABLE (1<<24)
472 #define UTMIPLL_HW_PWRDN_CFG0_USE_LOCKDET (1<<6)
473 #define UTMIPLL_HW_PWRDN_CFG0_SEQ_RESET_INPUT_VALUE (1<<5)
474 #define UTMIPLL_HW_PWRDN_CFG0_SEQ_IN_SWCTL (1<<4)
475 #define UTMIPLL_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL (1<<2)
476 #define UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE (1<<1)
477 #define UTMIPLL_HW_PWRDN_CFG0_IDDQ_SWCTL (1<<0)
479 #define PLLU_HW_PWRDN_CFG0 0x530
480 #define PLLU_HW_PWRDN_CFG0_SEQ_START_STATE (1<<25)
481 #define PLLU_HW_PWRDN_CFG0_SEQ_ENABLE (1<<24)
482 #define PLLU_HW_PWRDN_CFG0_USE_LOCKDET (1<<6)
483 #define PLLU_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL (1<<2)
484 #define PLLU_HW_PWRDN_CFG0_CLK_SWITCH_SWCTL (1<<0)
486 #define USB_PLLS_SEQ_START_STATE (1<<25)
487 #define USB_PLLS_SEQ_ENABLE (1<<24)
488 #define USB_PLLS_USE_LOCKDET (1<<6)
489 #define USB_PLLS_ENABLE_SWCTL ((1<<2) | (1<<0))
491 /* CPU clock trimmers */
492 #define CPU_FINETRIM_BYP 0x4d0
493 #define CPU_FINETRIM_SELECT 0x4d4
494 #define CPU_FINETRIM_DR 0x4d8
495 #define CPU_FINETRIM_DF 0x4dc
496 #define CPU_FINETRIM_F 0x4e0
497 #define CPU_FINETRIM_R 0x4e4
500 #define DFLL_BASE 0x2f4
501 #define DFLL_BASE_RESET (1<<0)
503 #define LVL2_CLK_GATE_OVRE 0x554
505 #define ROUND_DIVIDER_UP 0
506 #define ROUND_DIVIDER_DOWN 1
507 #define DIVIDER_1_5_ALLOWED 0
509 /* Tegra CPU clock and reset control regs */
510 #define TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX 0x4c
511 #define TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET 0x340
512 #define TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR 0x344
513 #define TEGRA30_CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR 0x34c
514 #define TEGRA30_CLK_RST_CONTROLLER_CPU_CMPLX_STATUS 0x470
516 #define CPU_CLOCK(cpu) (0x1 << (8 + cpu))
517 #define CPU_RESET(cpu) (0x111001ul << (cpu))
519 /* PLLP default fixed rate in h/w controlled mode */
520 #define PLLP_DEFAULT_FIXED_RATE 216000000
522 /* Use PLL_RE as PLLE input (default - OSC via pll reference divider) */
523 #define USE_PLLE_INPUT_PLLRE 0
525 static bool tegra11_is_dyn_ramp(struct clk *c,
526 unsigned long rate, bool from_vco_min);
527 static void tegra11_pllp_init_dependencies(unsigned long pllp_rate);
528 static unsigned long tegra11_clk_shared_bus_update(struct clk *bus,
529 struct clk **bus_top, struct clk **bus_slow, unsigned long *rate_cap);
530 static unsigned long tegra11_clk_cap_shared_bus(struct clk *bus,
531 unsigned long rate, unsigned long ceiling);
533 static bool detach_shared_bus;
534 module_param(detach_shared_bus, bool, 0644);
539 * Structure defining the fields for USB UTMI clocks Parameters.
541 struct utmi_clk_param
543 /* Oscillator Frequency in KHz */
545 /* UTMIP PLL Enable Delay Count */
546 u8 enable_delay_count;
547 /* UTMIP PLL Stable count */
549 /* UTMIP PLL Active delay count */
550 u8 active_delay_count;
551 /* UTMIP PLL Xtal frequency count */
555 static const struct utmi_clk_param utmi_parameters[] =
557 /* OSC_FREQUENCY, ENABLE_DLY, STABLE_CNT, ACTIVE_DLY, XTAL_FREQ_CNT */
558 {13000000, 0x02, 0x33, 0x05, 0x7F},
559 {19200000, 0x03, 0x4B, 0x06, 0xBB},
560 {12000000, 0x02, 0x2F, 0x04, 0x76},
561 {26000000, 0x04, 0x66, 0x09, 0xFE},
562 {16800000, 0x03, 0x41, 0x0A, 0xA4},
565 static void __iomem *reg_clk_base = IO_ADDRESS(TEGRA_CLK_RESET_BASE);
566 static void __iomem *reg_pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
567 static void __iomem *misc_gp_base = IO_ADDRESS(TEGRA_APB_MISC_BASE);
568 static void __iomem *reg_xusb_padctl_base = IO_ADDRESS(TEGRA_XUSB_PADCTL_BASE);
570 #define MISC_GP_TRANSACTOR_SCRATCH_0 0x864
571 #define MISC_GP_TRANSACTOR_SCRATCH_LA_ENABLE (0x1 << 1)
572 #define MISC_GP_TRANSACTOR_SCRATCH_DDS_ENABLE (0x1 << 2)
573 #define MISC_GP_TRANSACTOR_SCRATCH_DP2_ENABLE (0x1 << 3)
576 * Some peripheral clocks share an enable bit, so refcount the enable bits
577 * in registers CLK_ENABLE_L, ... CLK_ENABLE_W, and protect refcount updates
580 static DEFINE_SPINLOCK(periph_refcount_lock);
581 static int tegra_periph_clk_enable_refcount[CLK_OUT_ENB_NUM * 32];
583 #define clk_writel(value, reg) \
584 __raw_writel(value, reg_clk_base + (reg))
585 #define clk_readl(reg) \
586 __raw_readl(reg_clk_base + (reg))
587 #define pmc_writel(value, reg) \
588 __raw_writel(value, reg_pmc_base + (reg))
589 #define pmc_readl(reg) \
590 __raw_readl(reg_pmc_base + (reg))
591 #define xusb_padctl_writel(value, reg) \
592 __raw_writel(value, reg_xusb_padctl_base + (reg))
593 #define xusb_padctl_readl(reg) \
594 __raw_readl(reg_xusb_padctl_base + (reg))
596 #define clk_writel_delay(value, reg) \
598 __raw_writel((value), reg_clk_base + (reg)); \
599 __raw_readl(reg_clk_base + (reg)); \
603 #define pll_writel_delay(value, reg) \
605 __raw_writel((value), reg_clk_base + (reg)); \
606 __raw_readl(reg_clk_base + (reg)); \
611 static inline int clk_set_div(struct clk *c, u32 n)
613 return clk_set_rate(c, (clk_get_rate(c->parent) + n-1) / n);
616 static inline u32 periph_clk_to_reg(
617 struct clk *c, u32 reg_L, u32 reg_V, u32 reg_X, int offs)
619 u32 reg = c->u.periph.clk_num / 32;
620 BUG_ON(reg >= RST_DEVICES_NUM);
622 reg = reg_L + (reg * offs);
624 reg = reg_V + ((reg - 3) * offs);
630 static int clk_div_x1_get_divider(unsigned long parent_rate, unsigned long rate,
632 u32 flags, u32 round_mode)
634 s64 divider_ux1 = parent_rate;
638 if (!(flags & DIV_U71_INT))
640 if (round_mode == ROUND_DIVIDER_UP)
641 divider_ux1 += rate - 1;
642 do_div(divider_ux1, rate);
643 if (flags & DIV_U71_INT)
646 if (divider_ux1 - 2 < 0)
649 if (divider_ux1 - 2 > max_x)
652 #if !DIVIDER_1_5_ALLOWED
653 if (divider_ux1 == 3)
654 divider_ux1 = (round_mode == ROUND_DIVIDER_UP) ? 4 : 2;
656 return divider_ux1 - 2;
659 static int clk_div71_get_divider(unsigned long parent_rate, unsigned long rate,
660 u32 flags, u32 round_mode)
662 return clk_div_x1_get_divider(parent_rate, rate, 0xFF,
666 static int clk_div151_get_divider(unsigned long parent_rate, unsigned long rate,
667 u32 flags, u32 round_mode)
669 return clk_div_x1_get_divider(parent_rate, rate, 0xFFFF,
673 static int clk_div16_get_divider(unsigned long parent_rate, unsigned long rate)
677 divider_u16 = parent_rate;
680 divider_u16 += rate - 1;
681 do_div(divider_u16, rate);
683 if (divider_u16 - 1 < 0)
686 if (divider_u16 - 1 > 0xFFFF)
689 return divider_u16 - 1;
692 static inline bool bus_user_is_slower(struct clk *a, struct clk *b)
694 return a->u.shared_bus_user.client->max_rate * a->div <
695 b->u.shared_bus_user.client->max_rate * b->div;
698 static inline bool bus_user_request_is_lower(struct clk *a, struct clk *b)
700 return a->u.shared_bus_user.rate * a->div <
701 b->u.shared_bus_user.rate * b->div;
704 /* clk_m functions */
705 static unsigned long tegra11_clk_m_autodetect_rate(struct clk *c)
707 u32 osc_ctrl = clk_readl(OSC_CTRL);
708 u32 auto_clock_control = osc_ctrl & ~OSC_CTRL_OSC_FREQ_MASK;
709 u32 pll_ref_div = osc_ctrl & OSC_CTRL_PLL_REF_DIV_MASK;
711 c->rate = tegra_clk_measure_input_freq();
714 auto_clock_control |= OSC_CTRL_OSC_FREQ_12MHZ;
715 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1);
718 auto_clock_control |= OSC_CTRL_OSC_FREQ_13MHZ;
719 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1);
722 auto_clock_control |= OSC_CTRL_OSC_FREQ_19_2MHZ;
723 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1);
726 auto_clock_control |= OSC_CTRL_OSC_FREQ_26MHZ;
727 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1);
730 auto_clock_control |= OSC_CTRL_OSC_FREQ_16_8MHZ;
731 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1);
734 auto_clock_control |= OSC_CTRL_OSC_FREQ_38_4MHZ;
735 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_2);
738 auto_clock_control |= OSC_CTRL_OSC_FREQ_48MHZ;
739 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_4);
741 case 115200: /* fake 13M for QT */
742 case 230400: /* fake 13M for QT */
743 auto_clock_control |= OSC_CTRL_OSC_FREQ_13MHZ;
745 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1);
748 pr_err("%s: Unexpected clock rate %ld", __func__, c->rate);
751 clk_writel(auto_clock_control, OSC_CTRL);
755 static void tegra11_clk_m_init(struct clk *c)
757 pr_debug("%s on clock %s\n", __func__, c->name);
758 tegra11_clk_m_autodetect_rate(c);
761 static int tegra11_clk_m_enable(struct clk *c)
763 pr_debug("%s on clock %s\n", __func__, c->name);
767 static void tegra11_clk_m_disable(struct clk *c)
769 pr_debug("%s on clock %s\n", __func__, c->name);
770 WARN(1, "Attempting to disable main SoC clock\n");
773 static struct clk_ops tegra_clk_m_ops = {
774 .init = tegra11_clk_m_init,
775 .enable = tegra11_clk_m_enable,
776 .disable = tegra11_clk_m_disable,
779 static struct clk_ops tegra_clk_m_div_ops = {
780 .enable = tegra11_clk_m_enable,
783 /* PLL reference divider functions */
784 static void tegra11_pll_ref_init(struct clk *c)
786 u32 pll_ref_div = clk_readl(OSC_CTRL) & OSC_CTRL_PLL_REF_DIV_MASK;
787 pr_debug("%s on clock %s\n", __func__, c->name);
789 switch (pll_ref_div) {
790 case OSC_CTRL_PLL_REF_DIV_1:
793 case OSC_CTRL_PLL_REF_DIV_2:
796 case OSC_CTRL_PLL_REF_DIV_4:
800 pr_err("%s: Invalid pll ref divider %d", __func__, pll_ref_div);
807 static struct clk_ops tegra_pll_ref_ops = {
808 .init = tegra11_pll_ref_init,
809 .enable = tegra11_clk_m_enable,
810 .disable = tegra11_clk_m_disable,
813 /* super clock functions */
814 /* "super clocks" on tegra11x have two-stage muxes, fractional 7.1 divider and
815 * clock skipping super divider. We will ignore the clock skipping divider,
816 * since we can't lower the voltage when using the clock skip, but we can if
817 * we lower the PLL frequency. Note that skipping divider can and will be used
818 * by thermal control h/w for automatic throttling. There is also a 7.1 divider
819 * that most CPU super-clock inputs can be routed through. We will not use it
820 * as well (keep default 1:1 state), to avoid high jitter on PLLX and DFLL path
821 * and possible concurrency access issues with thermal h/w (7.1 divider setting
822 * share register with clock skipping divider)
824 static void tegra11_super_clk_init(struct clk *c)
829 const struct clk_mux_sel *sel;
830 val = clk_readl(c->reg + SUPER_CLK_MUX);
832 BUG_ON(((val & SUPER_STATE_MASK) != SUPER_STATE_RUN) &&
833 ((val & SUPER_STATE_MASK) != SUPER_STATE_IDLE));
834 shift = ((val & SUPER_STATE_MASK) == SUPER_STATE_IDLE) ?
835 SUPER_IDLE_SOURCE_SHIFT : SUPER_RUN_SOURCE_SHIFT;
836 source = (val >> shift) & SUPER_SOURCE_MASK;
839 * Enforce PLLX DIV2 bypass setting as early as possible. It is always
840 * safe to do for both cclk_lp and cclk_g when booting on G CPU. (In
841 * case of booting on LP CPU, cclk_lp will be updated during the cpu
842 * rate change after boot, and cclk_g after the cluster switch.)
844 if ((c->flags & DIV_U71) && (!is_lp_cluster())) {
845 val |= SUPER_LP_DIV2_BYPASS;
846 clk_writel_delay(val, c->reg);
849 for (sel = c->inputs; sel->input != NULL; sel++) {
850 if (sel->value == source)
853 BUG_ON(sel->input == NULL);
854 c->parent = sel->input;
856 /* Update parent in case when LP CPU PLLX DIV2 bypassed */
857 if ((c->flags & DIV_2) && (c->parent->flags & PLLX) &&
858 (val & SUPER_LP_DIV2_BYPASS))
859 c->parent = c->parent->parent;
861 if (c->flags & DIV_U71) {
866 * Make sure 7.1 divider is 1:1; clear h/w skipper control -
867 * it will be enabled by soctherm later
869 val = clk_readl(c->reg + SUPER_CLK_DIVIDER);
870 BUG_ON(val & SUPER_CLOCK_DIV_U71_MASK);
872 clk_writel(val, c->reg + SUPER_CLK_DIVIDER);
875 clk_writel(0, c->reg + SUPER_CLK_DIVIDER);
878 static int tegra11_super_clk_enable(struct clk *c)
883 static void tegra11_super_clk_disable(struct clk *c)
885 /* since tegra 3 has 2 CPU super clocks - low power lp-mode clock and
886 geared up g-mode super clock - mode switch may request to disable
887 either of them; accept request with no affect on h/w */
890 static int tegra11_super_clk_set_parent(struct clk *c, struct clk *p)
893 const struct clk_mux_sel *sel;
896 val = clk_readl(c->reg + SUPER_CLK_MUX);
897 BUG_ON(((val & SUPER_STATE_MASK) != SUPER_STATE_RUN) &&
898 ((val & SUPER_STATE_MASK) != SUPER_STATE_IDLE));
899 shift = ((val & SUPER_STATE_MASK) == SUPER_STATE_IDLE) ?
900 SUPER_IDLE_SOURCE_SHIFT : SUPER_RUN_SOURCE_SHIFT;
901 for (sel = c->inputs; sel->input != NULL; sel++) {
902 if (sel->input == p) {
903 /* For LP mode super-clock switch between PLLX direct
904 and divided-by-2 outputs is allowed only when other
905 than PLLX clock source is current parent */
906 if ((c->flags & DIV_2) && (p->flags & PLLX) &&
907 ((sel->value ^ val) & SUPER_LP_DIV2_BYPASS)) {
908 if (c->parent->flags & PLLX)
910 val ^= SUPER_LP_DIV2_BYPASS;
911 clk_writel_delay(val, c->reg);
913 val &= ~(SUPER_SOURCE_MASK << shift);
914 val |= (sel->value & SUPER_SOURCE_MASK) << shift;
916 if (c->flags & DIV_U71) {
917 /* Make sure 7.1 divider is 1:1 */
918 u32 div = clk_readl(c->reg + SUPER_CLK_DIVIDER);
919 BUG_ON(div & SUPER_CLOCK_DIV_U71_MASK);
925 clk_writel_delay(val, c->reg);
927 if (c->refcnt && c->parent)
928 clk_disable(c->parent);
938 * Do not use super clocks "skippers", since dividing using a clock skipper
939 * does not allow the voltage to be scaled down. Instead adjust the rate of
940 * the parent clock. This requires that the parent of a super clock have no
941 * other children, otherwise the rate will change underneath the other
944 static int tegra11_super_clk_set_rate(struct clk *c, unsigned long rate)
946 /* In tegra11_cpu_clk_set_plls() and tegra11_sbus_cmplx_set_rate()
947 * this call is skipped by directly setting rate of source plls. If we
948 * ever use 7.1 divider at other than 1:1 setting, or exercise s/w
949 * skipper control, not only this function, but cpu and sbus set_rate
950 * APIs should be changed accordingly.
952 return clk_set_rate(c->parent, rate);
955 #ifdef CONFIG_PM_SLEEP
956 static void tegra11_super_clk_resume(struct clk *c, struct clk *backup,
960 const struct clk_mux_sel *sel;
963 /* For sclk and cclk_g super clock just restore saved value */
964 if (!(c->flags & DIV_2)) {
965 clk_writel_delay(setting, c->reg);
970 * For cclk_lp supper clock: switch to backup (= not PLLX) source,
971 * safely restore PLLX DIV2 bypass, and only then restore full
974 val = clk_readl(c->reg);
975 BUG_ON(((val & SUPER_STATE_MASK) != SUPER_STATE_RUN) &&
976 ((val & SUPER_STATE_MASK) != SUPER_STATE_IDLE));
977 shift = ((val & SUPER_STATE_MASK) == SUPER_STATE_IDLE) ?
978 SUPER_IDLE_SOURCE_SHIFT : SUPER_RUN_SOURCE_SHIFT;
979 for (sel = c->inputs; sel->input != NULL; sel++) {
980 if (sel->input == backup) {
981 val &= ~(SUPER_SOURCE_MASK << shift);
982 val |= (sel->value & SUPER_SOURCE_MASK) << shift;
984 BUG_ON(backup->flags & PLLX);
985 clk_writel_delay(val, c->reg);
987 val &= ~SUPER_LP_DIV2_BYPASS;
988 val |= (setting & SUPER_LP_DIV2_BYPASS);
989 clk_writel_delay(val, c->reg);
990 clk_writel_delay(setting, c->reg);
998 static struct clk_ops tegra_super_ops = {
999 .init = tegra11_super_clk_init,
1000 .enable = tegra11_super_clk_enable,
1001 .disable = tegra11_super_clk_disable,
1002 .set_parent = tegra11_super_clk_set_parent,
1003 .set_rate = tegra11_super_clk_set_rate,
1006 /* virtual cpu clock functions */
1007 /* some clocks can not be stopped (cpu, memory bus) while the SoC is running.
1008 To change the frequency of these clocks, the parent pll may need to be
1009 reprogrammed, so the clock must be moved off the pll, the pll reprogrammed,
1010 and then the clock moved back to the pll. To hide this sequence, a virtual
1013 static void tegra11_cpu_clk_init(struct clk *c)
1015 c->state = (!is_lp_cluster() == (c->u.cpu.mode == MODE_G))? ON : OFF;
1018 static int tegra11_cpu_clk_enable(struct clk *c)
1023 static void tegra11_cpu_clk_disable(struct clk *c)
1025 /* since tegra 3 has 2 virtual CPU clocks - low power lp-mode clock
1026 and geared up g-mode clock - mode switch may request to disable
1027 either of them; accept request with no affect on h/w */
1030 static int tegra11_cpu_clk_set_plls(struct clk *c, unsigned long rate,
1031 unsigned long old_rate)
1034 bool on_main = false;
1035 unsigned long backup_rate, main_rate;
1036 unsigned long vco_min = c->u.cpu.main->u.pll.vco_min;
1039 * Take an extra reference to the main pll so it doesn't turn off when
1040 * we move the cpu off of it. If possible, use main pll dynamic ramp
1041 * to reach target rate in one shot. Otherwise, use dynamic ramp to
1042 * lower current rate to pll VCO minimum level before switching to
1045 if (c->parent->parent == c->u.cpu.main) {
1046 bool dramp = (rate > c->u.cpu.backup_rate) &&
1047 tegra11_is_dyn_ramp(c->u.cpu.main, rate, false);
1048 clk_enable(c->u.cpu.main);
1052 ((old_rate > vco_min) &&
1053 tegra11_is_dyn_ramp(c->u.cpu.main, vco_min, false))) {
1054 main_rate = dramp ? rate : vco_min;
1055 ret = clk_set_rate(c->u.cpu.main, main_rate);
1057 pr_err("Failed to set cpu rate %lu on source"
1058 " %s\n", main_rate, c->u.cpu.main->name);
1063 } else if (old_rate > vco_min) {
1064 #if PLLXC_USE_DYN_RAMP
1065 pr_warn("No dynamic ramp down: %s: %lu to %lu\n",
1066 c->u.cpu.main->name, old_rate, vco_min);
1071 /* Switch to back-up source, and stay on it if target rate is below
1073 if (c->parent->parent != c->u.cpu.backup) {
1074 ret = clk_set_parent(c->parent, c->u.cpu.backup);
1076 pr_err("Failed to switch cpu to %s\n",
1077 c->u.cpu.backup->name);
1082 backup_rate = min(rate, c->u.cpu.backup_rate);
1083 if (backup_rate != clk_get_rate_locked(c)) {
1084 ret = clk_set_rate(c->u.cpu.backup, backup_rate);
1086 pr_err("Failed to set cpu rate %lu on backup source\n",
1091 if (rate == backup_rate)
1094 /* Switch from backup source to main at rate not exceeding pll VCO
1095 minimum. Use dynamic ramp to reach target rate if it is above VCO
1098 if (rate > vco_min) {
1099 if (tegra11_is_dyn_ramp(c->u.cpu.main, rate, true))
1100 main_rate = vco_min;
1101 #if PLLXC_USE_DYN_RAMP
1103 pr_warn("No dynamic ramp up: %s: %lu to %lu\n",
1104 c->u.cpu.main->name, vco_min, rate);
1108 ret = clk_set_rate(c->u.cpu.main, main_rate);
1110 pr_err("Failed to set cpu rate %lu on source"
1111 " %s\n", main_rate, c->u.cpu.main->name);
1114 ret = clk_set_parent(c->parent, c->u.cpu.main);
1116 pr_err("Failed to switch cpu to %s\n", c->u.cpu.main->name);
1119 if (rate != main_rate) {
1120 ret = clk_set_rate(c->u.cpu.main, rate);
1122 pr_err("Failed to set cpu rate %lu on source"
1123 " %s\n", rate, c->u.cpu.main->name);
1130 clk_disable(c->u.cpu.main);
1135 static int tegra11_cpu_clk_dfll_on(struct clk *c, unsigned long rate,
1136 unsigned long old_rate)
1139 struct clk *dfll = c->u.cpu.dynamic;
1140 unsigned long dfll_rate_min = c->dvfs->dfll_data.use_dfll_rate_min;
1142 /* dfll rate request */
1143 ret = clk_set_rate(dfll, rate);
1145 pr_err("Failed to set cpu rate %lu on source"
1146 " %s\n", rate, dfll->name);
1150 /* 1st time - switch to dfll */
1151 if (c->parent->parent != dfll) {
1152 if (max(old_rate, rate) < dfll_rate_min) {
1153 /* set interim cpu dvfs rate at dfll_rate_min to
1154 prevent voltage drop below dfll Vmin */
1155 ret = tegra_dvfs_set_rate(c, dfll_rate_min);
1157 pr_err("Failed to set cpu dvfs rate %lu\n",
1163 tegra_dvfs_rail_mode_updating(tegra_cpu_rail, true);
1164 ret = clk_set_parent(c->parent, dfll);
1166 tegra_dvfs_rail_mode_updating(tegra_cpu_rail, false);
1167 pr_err("Failed to switch cpu to %s\n", dfll->name);
1170 ret = tegra_clk_cfg_ex(dfll, TEGRA_CLK_DFLL_LOCK, 1);
1171 WARN(ret, "Failed to lock %s at rate %lu\n", dfll->name, rate);
1173 /* prevent legacy dvfs voltage scaling */
1174 tegra_dvfs_dfll_mode_set(c->dvfs, rate);
1175 tegra_dvfs_rail_mode_updating(tegra_cpu_rail, false);
1180 static int tegra11_cpu_clk_dfll_off(struct clk *c, unsigned long rate,
1181 unsigned long old_rate)
1185 struct clk *dfll = c->u.cpu.dynamic;
1186 unsigned long dfll_rate_min = c->dvfs->dfll_data.use_dfll_rate_min;
1188 rate = min(rate, c->max_rate - c->dvfs->dfll_data.max_rate_boost);
1189 pll = (rate <= c->u.cpu.backup_rate) ? c->u.cpu.backup : c->u.cpu.main;
1190 dfll_rate_min = max(rate, dfll_rate_min);
1192 /* set target rate last time in dfll mode */
1193 if (old_rate != dfll_rate_min) {
1194 ret = tegra_dvfs_set_rate(c, dfll_rate_min);
1196 ret = clk_set_rate(dfll, dfll_rate_min);
1199 pr_err("Failed to set cpu rate %lu on source %s\n",
1200 dfll_rate_min, dfll->name);
1205 /* unlock dfll - release volatge rail control */
1206 tegra_dvfs_rail_mode_updating(tegra_cpu_rail, true);
1207 ret = tegra_clk_cfg_ex(dfll, TEGRA_CLK_DFLL_LOCK, 0);
1209 pr_err("Failed to unlock %s\n", dfll->name);
1213 /* restore legacy dvfs operations and set appropriate voltage */
1214 ret = tegra_dvfs_dfll_mode_clear(c->dvfs, dfll_rate_min);
1216 pr_err("Failed to set cpu rail for rate %lu\n", rate);
1220 /* set pll to target rate and return to pll source */
1221 ret = clk_set_rate(pll, rate);
1223 pr_err("Failed to set cpu rate %lu on source"
1224 " %s\n", rate, pll->name);
1227 ret = clk_set_parent(c->parent, pll);
1229 pr_err("Failed to switch cpu to %s\n", pll->name);
1233 /* If going up, adjust voltage here (down path is taken care of by the
1234 framework after set rate exit) */
1235 if (old_rate <= rate)
1236 tegra_dvfs_set_rate(c, rate);
1238 tegra_dvfs_rail_mode_updating(tegra_cpu_rail, false);
1242 tegra_clk_cfg_ex(dfll, TEGRA_CLK_DFLL_LOCK, 1);
1243 tegra_dvfs_dfll_mode_set(c->dvfs, old_rate);
1244 tegra_dvfs_rail_mode_updating(tegra_cpu_rail, false);
1248 static int tegra11_cpu_clk_set_rate(struct clk *c, unsigned long rate)
1250 unsigned long old_rate = clk_get_rate_locked(c);
1251 bool has_dfll = c->u.cpu.dynamic &&
1252 (c->u.cpu.dynamic->state != UNINITIALIZED);
1253 bool is_dfll = c->parent->parent == c->u.cpu.dynamic;
1255 /* On SILICON allow CPU rate change only if cpu regulator is connected.
1256 Ignore regulator connection on FPGA platforms. */
1257 #ifdef CONFIG_TEGRA_SILICON_PLATFORM
1259 if (!c->dvfs->dvfs_rail)
1261 else if ((!c->dvfs->dvfs_rail->reg) && (old_rate < rate) &&
1262 (c->boot_rate < rate)) {
1263 WARN(1, "Increasing CPU rate while regulator is not"
1264 " ready is not allowed\n");
1269 if (has_dfll && c->dvfs && c->dvfs->dvfs_rail) {
1270 if (tegra_dvfs_is_dfll_range(c->dvfs, rate))
1271 return tegra11_cpu_clk_dfll_on(c, rate, old_rate);
1273 return tegra11_cpu_clk_dfll_off(c, rate, old_rate);
1275 return tegra11_cpu_clk_set_plls(c, rate, old_rate);
1278 static long tegra11_cpu_clk_round_rate(struct clk *c, unsigned long rate)
1280 unsigned long max_rate = c->max_rate;
1282 /* Remove dfll boost to maximum rate when running on PLL */
1283 if (c->dvfs && !tegra_dvfs_is_dfll_scale(c->dvfs, rate))
1284 max_rate -= c->dvfs->dfll_data.max_rate_boost;
1286 if (rate > max_rate)
1288 else if (rate < c->min_rate)
1293 static struct clk_ops tegra_cpu_ops = {
1294 .init = tegra11_cpu_clk_init,
1295 .enable = tegra11_cpu_clk_enable,
1296 .disable = tegra11_cpu_clk_disable,
1297 .set_rate = tegra11_cpu_clk_set_rate,
1298 .round_rate = tegra11_cpu_clk_round_rate,
1302 static void tegra11_cpu_cmplx_clk_init(struct clk *c)
1304 int i = !!is_lp_cluster();
1306 BUG_ON(c->inputs[0].input->u.cpu.mode != MODE_G);
1307 BUG_ON(c->inputs[1].input->u.cpu.mode != MODE_LP);
1308 c->parent = c->inputs[i].input;
1311 /* cpu complex clock provides second level vitualization (on top of
1312 cpu virtual cpu rate control) in order to hide the CPU mode switch
1314 #if PARAMETERIZE_CLUSTER_SWITCH
1315 static unsigned int switch_delay;
1316 static unsigned int switch_flags;
1317 static DEFINE_SPINLOCK(parameters_lock);
1319 void tegra_cluster_switch_set_parameters(unsigned int us, unsigned int flags)
1321 spin_lock(¶meters_lock);
1323 switch_flags = flags;
1324 spin_unlock(¶meters_lock);
1328 static int tegra11_cpu_cmplx_clk_enable(struct clk *c)
1333 static void tegra11_cpu_cmplx_clk_disable(struct clk *c)
1335 pr_debug("%s on clock %s\n", __func__, c->name);
1337 /* oops - don't disable the CPU complex clock! */
1341 static int tegra11_cpu_cmplx_clk_set_rate(struct clk *c, unsigned long rate)
1343 unsigned long flags;
1345 struct clk *parent = c->parent;
1347 if (!parent->ops || !parent->ops->set_rate)
1350 clk_lock_save(parent, &flags);
1352 ret = clk_set_rate_locked(parent, rate);
1354 clk_unlock_restore(parent, &flags);
1359 static int tegra11_cpu_cmplx_clk_set_parent(struct clk *c, struct clk *p)
1362 unsigned int flags, delay;
1363 const struct clk_mux_sel *sel;
1364 unsigned long rate = clk_get_rate(c->parent);
1365 struct clk *dfll = c->parent->u.cpu.dynamic ? : p->u.cpu.dynamic;
1366 struct clk *p_source_old = NULL;
1367 struct clk *p_source;
1369 pr_debug("%s: %s %s\n", __func__, c->name, p->name);
1370 BUG_ON(c->parent->u.cpu.mode != (is_lp_cluster() ? MODE_LP : MODE_G));
1372 for (sel = c->inputs; sel->input != NULL; sel++) {
1373 if (sel->input == p)
1379 #if PARAMETERIZE_CLUSTER_SWITCH
1380 spin_lock(¶meters_lock);
1381 flags = switch_flags;
1382 delay = switch_delay;
1384 spin_unlock(¶meters_lock);
1387 /* over/under-clocking after switch - allow, but update rate */
1388 if ((rate > p->max_rate) || (rate < p->min_rate)) {
1389 rate = rate > p->max_rate ? p->max_rate : p->min_rate;
1390 ret = clk_set_rate(c->parent, rate);
1392 pr_err("%s: Failed to set rate %lu for %s\n",
1393 __func__, rate, p->name);
1400 if (rate > p->max_rate) { /* over-clocking - no switch */
1401 pr_warn("%s: No %s mode switch to %s at rate %lu\n",
1402 __func__, c->name, p->name, rate);
1405 flags = TEGRA_POWER_CLUSTER_IMMEDIATE;
1406 flags |= TEGRA_POWER_CLUSTER_PART_DEFAULT;
1409 flags |= (p->u.cpu.mode == MODE_LP) ? TEGRA_POWER_CLUSTER_LP :
1410 TEGRA_POWER_CLUSTER_G;
1412 if (p == c->parent) {
1413 if (flags & TEGRA_POWER_CLUSTER_FORCE) {
1414 /* Allow parameterized switch to the same mode */
1415 ret = tegra_cluster_control(delay, flags);
1417 pr_err("%s: Failed to force %s mode to %s\n",
1418 __func__, c->name, p->name);
1421 return 0; /* already switched - exit */
1424 tegra_dvfs_rail_mode_updating(tegra_cpu_rail, true);
1425 if (c->parent->parent->parent == dfll) {
1426 /* G (DFLL selected as clock source) => LP switch:
1427 * turn DFLL into open loop mode ("release" VDD_CPU rail)
1428 * select target p_source for LP, and get its rate ready
1430 ret = tegra_clk_cfg_ex(dfll, TEGRA_CLK_DFLL_LOCK, 0);
1434 p_source = rate <= p->u.cpu.backup_rate ?
1435 p->u.cpu.backup : p->u.cpu.main;
1436 ret = clk_set_rate(p_source, rate);
1439 } else if ((p->parent->parent == dfll) ||
1440 (p->dvfs && tegra_dvfs_is_dfll_range(p->dvfs, rate))) {
1441 /* LP => G (DFLL selected as clock source) switch:
1442 * set DFLL rate ready (DFLL is still disabled)
1443 * (set target p_source as dfll, G source is already selected)
1446 ret = clk_set_rate(dfll,
1447 tegra_dvfs_rail_is_dfll_mode(tegra_cpu_rail) ? rate :
1448 max(rate, p->dvfs->dfll_data.use_dfll_rate_min));
1452 ret = tegra_dvfs_rail_dfll_mode_set_cold(tegra_cpu_rail);
1457 /* DFLL is not selected on either side of the switch:
1458 * set target p_source equal to current clock source
1460 p_source = c->parent->parent->parent;
1462 /* Switch new parent to target clock source if necessary */
1463 if (p->parent->parent != p_source) {
1464 clk_enable(p->parent->parent);
1465 clk_enable(p->parent);
1466 p_source_old = p->parent->parent;
1467 ret = clk_set_parent(p->parent, p_source);
1469 pr_err("%s: Failed to set parent %s for %s\n",
1470 __func__, p_source->name, p->name);
1475 /* Enabling new parent scales new mode voltage rail in advanvce
1476 before the switch happens (if p_source is DFLL: open loop mode) */
1480 /* switch CPU mode */
1481 ret = tegra_cluster_control(delay, flags);
1485 pr_err("%s: Failed to switch %s mode to %s\n",
1486 __func__, c->name, p->name);
1491 * Lock DFLL now (resume closed loop VDD_CPU control).
1492 * G CPU operations are resumed on DFLL if it was the last G CPU
1493 * clock source, or if resume rate is in DFLL usage range in case
1494 * when auto-switch between PLL and DFLL is enabled.
1496 if (p_source == dfll) {
1497 if (tegra_dvfs_rail_is_dfll_mode(tegra_cpu_rail)) {
1498 tegra_clk_cfg_ex(dfll, TEGRA_CLK_DFLL_LOCK, 1);
1500 clk_set_rate(dfll, rate);
1501 tegra_clk_cfg_ex(dfll, TEGRA_CLK_DFLL_LOCK, 1);
1502 tegra_dvfs_dfll_mode_set(p->dvfs, rate);
1506 /* Disabling old parent scales old mode voltage rail */
1508 clk_disable(c->parent);
1510 clk_disable(p->parent);
1511 clk_disable(p_source_old);
1516 tegra_dvfs_rail_mode_updating(tegra_cpu_rail, false);
1520 /* Re-lock DFLL if necessary after aborted switch */
1521 if (c->parent->parent->parent == dfll) {
1522 clk_set_rate(dfll, rate);
1523 tegra_clk_cfg_ex(dfll, TEGRA_CLK_DFLL_LOCK, 1);
1526 clk_disable(p->parent);
1527 clk_disable(p_source_old);
1529 tegra_dvfs_rail_mode_updating(tegra_cpu_rail, false);
1531 pr_err("%s: aborted switch from %s to %s\n",
1532 __func__, c->parent->name, p->name);
1536 static long tegra11_cpu_cmplx_round_rate(struct clk *c,
1539 return clk_round_rate(c->parent, rate);
1542 static struct clk_ops tegra_cpu_cmplx_ops = {
1543 .init = tegra11_cpu_cmplx_clk_init,
1544 .enable = tegra11_cpu_cmplx_clk_enable,
1545 .disable = tegra11_cpu_cmplx_clk_disable,
1546 .set_rate = tegra11_cpu_cmplx_clk_set_rate,
1547 .set_parent = tegra11_cpu_cmplx_clk_set_parent,
1548 .round_rate = tegra11_cpu_cmplx_round_rate,
1551 /* virtual cop clock functions. Used to acquire the fake 'cop' clock to
1552 * reset the COP block (i.e. AVP) */
1553 static void tegra11_cop_clk_reset(struct clk *c, bool assert)
1555 unsigned long reg = assert ? RST_DEVICES_SET_L : RST_DEVICES_CLR_L;
1557 pr_debug("%s %s\n", __func__, assert ? "assert" : "deassert");
1558 clk_writel(1 << 1, reg);
1561 static struct clk_ops tegra_cop_ops = {
1562 .reset = tegra11_cop_clk_reset,
1565 /* bus clock functions */
1566 static void tegra11_bus_clk_init(struct clk *c)
1568 u32 val = clk_readl(c->reg);
1569 c->state = ((val >> c->reg_shift) & BUS_CLK_DISABLE) ? OFF : ON;
1570 c->div = ((val >> c->reg_shift) & BUS_CLK_DIV_MASK) + 1;
1574 static int tegra11_bus_clk_enable(struct clk *c)
1576 u32 val = clk_readl(c->reg);
1577 val &= ~(BUS_CLK_DISABLE << c->reg_shift);
1578 clk_writel(val, c->reg);
1582 static void tegra11_bus_clk_disable(struct clk *c)
1584 u32 val = clk_readl(c->reg);
1585 val |= BUS_CLK_DISABLE << c->reg_shift;
1586 clk_writel(val, c->reg);
1589 static int tegra11_bus_clk_set_rate(struct clk *c, unsigned long rate)
1591 u32 val = clk_readl(c->reg);
1592 unsigned long parent_rate = clk_get_rate(c->parent);
1594 for (i = 1; i <= 4; i++) {
1595 if (rate >= parent_rate / i) {
1596 val &= ~(BUS_CLK_DIV_MASK << c->reg_shift);
1597 val |= (i - 1) << c->reg_shift;
1598 clk_writel(val, c->reg);
1607 static struct clk_ops tegra_bus_ops = {
1608 .init = tegra11_bus_clk_init,
1609 .enable = tegra11_bus_clk_enable,
1610 .disable = tegra11_bus_clk_disable,
1611 .set_rate = tegra11_bus_clk_set_rate,
1614 /* Virtual system bus complex clock is used to hide the sequence of
1615 changing sclk/hclk/pclk parents and dividers to configure requested
1616 sclk target rate. */
1617 static void tegra11_sbus_cmplx_init(struct clk *c)
1621 c->max_rate = c->parent->max_rate;
1622 c->min_rate = c->parent->min_rate;
1624 /* Threshold must be an exact proper factor of low range parent,
1625 and both low/high range parents have 7.1 fractional dividers */
1626 rate = clk_get_rate(c->u.system.sclk_low->parent);
1627 if (c->u.system.threshold) {
1628 BUG_ON(c->u.system.threshold > rate) ;
1629 BUG_ON((rate % c->u.system.threshold) != 0);
1631 BUG_ON(!(c->u.system.sclk_low->flags & DIV_U71));
1632 BUG_ON(!(c->u.system.sclk_high->flags & DIV_U71));
1635 /* This special sbus round function is implemented because:
1637 * (a) sbus complex clock source is selected automatically based on rate
1639 * (b) since sbus is a shared bus, and its frequency is set to the highest
1640 * enabled shared_bus_user clock, the target rate should be rounded up divider
1641 * ladder (if max limit allows it) - for pll_div and peripheral_div common is
1642 * rounding down - special case again.
1644 * Note that final rate is trimmed (not rounded up) to avoid spiraling up in
1645 * recursive calls. Lost 1Hz is added in tegra11_sbus_cmplx_set_rate before
1646 * actually setting divider rate.
1648 static long tegra11_sbus_cmplx_round_updown(struct clk *c, unsigned long rate,
1652 unsigned long source_rate, round_rate;
1653 struct clk *new_parent;
1655 rate = max(rate, c->min_rate);
1657 new_parent = (rate <= c->u.system.threshold) ?
1658 c->u.system.sclk_low : c->u.system.sclk_high;
1659 source_rate = clk_get_rate(new_parent->parent);
1661 divider = clk_div71_get_divider(source_rate, rate,
1662 new_parent->flags, up ? ROUND_DIVIDER_DOWN : ROUND_DIVIDER_UP);
1669 round_rate = source_rate * 2 / (divider + 2);
1670 if (round_rate > c->max_rate) {
1671 divider += new_parent->flags & DIV_U71_INT ? 2 : 1;
1672 #if !DIVIDER_1_5_ALLOWED
1673 divider = max(2, divider);
1675 round_rate = source_rate * 2 / (divider + 2);
1678 if (new_parent == c->u.system.sclk_high) {
1679 /* Prevent oscillation across threshold */
1680 if (round_rate <= c->u.system.threshold)
1681 round_rate = c->u.system.threshold;
1686 static long tegra11_sbus_cmplx_round_rate(struct clk *c, unsigned long rate)
1688 return tegra11_sbus_cmplx_round_updown(c, rate, true);
1691 static int tegra11_sbus_cmplx_set_rate(struct clk *c, unsigned long rate)
1694 struct clk *new_parent;
1696 /* - select the appropriate sclk parent
1697 - keep hclk at the same rate as sclk
1698 - set pclk at 1:2 rate of hclk unless pclk minimum is violated,
1699 in the latter case switch to 1:1 ratio */
1701 if (rate >= c->u.system.pclk->min_rate * 2) {
1702 ret = clk_set_div(c->u.system.pclk, 2);
1704 pr_err("Failed to set 1 : 2 pclk divider\n");
1709 new_parent = (rate <= c->u.system.threshold) ?
1710 c->u.system.sclk_low : c->u.system.sclk_high;
1712 ret = clk_set_rate(new_parent, rate + 1);
1714 pr_err("Failed to set sclk source %s to %lu\n",
1715 new_parent->name, rate);
1719 if (new_parent != clk_get_parent(c->parent)) {
1720 ret = clk_set_parent(c->parent, new_parent);
1722 pr_err("Failed to switch sclk source to %s\n",
1728 if (rate < c->u.system.pclk->min_rate * 2) {
1729 ret = clk_set_div(c->u.system.pclk, 1);
1731 pr_err("Failed to set 1 : 1 pclk divider\n");
1739 static int tegra11_clk_sbus_update(struct clk *bus)
1741 unsigned long rate, old_rate;
1743 if (detach_shared_bus)
1746 rate = tegra11_clk_shared_bus_update(bus, NULL, NULL, NULL);
1748 old_rate = clk_get_rate_locked(bus);
1749 if (rate == old_rate)
1752 return clk_set_rate_locked(bus, rate);
1755 static struct clk_ops tegra_sbus_cmplx_ops = {
1756 .init = tegra11_sbus_cmplx_init,
1757 .set_rate = tegra11_sbus_cmplx_set_rate,
1758 .round_rate = tegra11_sbus_cmplx_round_rate,
1759 .round_rate_updown = tegra11_sbus_cmplx_round_updown,
1760 .shared_bus_update = tegra11_clk_sbus_update,
1763 /* Blink output functions */
1765 static void tegra11_blink_clk_init(struct clk *c)
1769 val = pmc_readl(PMC_CTRL);
1770 c->state = (val & PMC_CTRL_BLINK_ENB) ? ON : OFF;
1772 val = pmc_readl(c->reg);
1774 if (val & PMC_BLINK_TIMER_ENB) {
1775 unsigned int on_off;
1777 on_off = (val >> PMC_BLINK_TIMER_DATA_ON_SHIFT) &
1778 PMC_BLINK_TIMER_DATA_ON_MASK;
1779 val >>= PMC_BLINK_TIMER_DATA_OFF_SHIFT;
1780 val &= PMC_BLINK_TIMER_DATA_OFF_MASK;
1782 /* each tick in the blink timer is 4 32KHz clocks */
1783 c->div = on_off * 4;
1789 static int tegra11_blink_clk_enable(struct clk *c)
1793 val = pmc_readl(PMC_DPD_PADS_ORIDE);
1794 pmc_writel(val | PMC_DPD_PADS_ORIDE_BLINK_ENB, PMC_DPD_PADS_ORIDE);
1796 val = pmc_readl(PMC_CTRL);
1797 pmc_writel(val | PMC_CTRL_BLINK_ENB, PMC_CTRL);
1802 static void tegra11_blink_clk_disable(struct clk *c)
1806 val = pmc_readl(PMC_CTRL);
1807 pmc_writel(val & ~PMC_CTRL_BLINK_ENB, PMC_CTRL);
1809 val = pmc_readl(PMC_DPD_PADS_ORIDE);
1810 pmc_writel(val & ~PMC_DPD_PADS_ORIDE_BLINK_ENB, PMC_DPD_PADS_ORIDE);
1813 static int tegra11_blink_clk_set_rate(struct clk *c, unsigned long rate)
1815 unsigned long parent_rate = clk_get_rate(c->parent);
1816 if (rate >= parent_rate) {
1818 pmc_writel(0, c->reg);
1820 unsigned int on_off;
1823 on_off = DIV_ROUND_UP(parent_rate / 8, rate);
1824 c->div = on_off * 8;
1826 val = (on_off & PMC_BLINK_TIMER_DATA_ON_MASK) <<
1827 PMC_BLINK_TIMER_DATA_ON_SHIFT;
1828 on_off &= PMC_BLINK_TIMER_DATA_OFF_MASK;
1829 on_off <<= PMC_BLINK_TIMER_DATA_OFF_SHIFT;
1831 val |= PMC_BLINK_TIMER_ENB;
1832 pmc_writel(val, c->reg);
1838 static struct clk_ops tegra_blink_clk_ops = {
1839 .init = &tegra11_blink_clk_init,
1840 .enable = &tegra11_blink_clk_enable,
1841 .disable = &tegra11_blink_clk_disable,
1842 .set_rate = &tegra11_blink_clk_set_rate,
1846 static int tegra11_pll_clk_wait_for_lock(
1847 struct clk *c, u32 lock_reg, u32 lock_bits)
1849 #if USE_PLL_LOCK_BITS
1853 for (i = 0; i < (c->u.pll.lock_delay / PLL_PRE_LOCK_DELAY + 1); i++) {
1854 udelay(PLL_PRE_LOCK_DELAY);
1855 val = clk_readl(lock_reg);
1856 if ((val & lock_bits) == lock_bits) {
1857 udelay(PLL_POST_LOCK_DELAY);
1862 /* PLLCX lock bits may fluctuate after the lock - don't report timeout
1863 in this case (phase lock bit happens to uniquely identify PLLCX) */
1864 if (lock_bits & PLLCX_BASE_PHASE_LOCK) {
1865 pr_debug("Timed out waiting for %s lock bit ([0x%x] = 0x%x)\n",
1866 c->name, lock_reg, val);
1868 } else if ((c->flags & PLLD) &&
1869 tegra_powergate_check_clamping(TEGRA_POWERGATE_DISA)) {
1870 pr_debug("Waiting for %s lock.\n", c->name);
1872 pr_err("Timed out waiting for %s lock bit ([0x%x] = 0x%x)\n",
1873 c->name, lock_reg, val);
1877 udelay(c->u.pll.lock_delay);
1881 static void usb_plls_hw_control_enable(u32 reg)
1883 u32 val = clk_readl(reg);
1884 val |= USB_PLLS_USE_LOCKDET | USB_PLLS_SEQ_START_STATE;
1885 val &= ~USB_PLLS_ENABLE_SWCTL;
1886 val |= USB_PLLS_SEQ_START_STATE;
1887 pll_writel_delay(val, reg);
1889 val |= USB_PLLS_SEQ_ENABLE;
1890 pll_writel_delay(val, reg);
1893 static void tegra11_utmi_param_configure(struct clk *c)
1897 unsigned long main_rate =
1898 clk_get_rate(c->parent->parent);
1900 for (i = 0; i < ARRAY_SIZE(utmi_parameters); i++) {
1901 if (main_rate == utmi_parameters[i].osc_frequency) {
1906 if (i >= ARRAY_SIZE(utmi_parameters)) {
1907 pr_err("%s: Unexpected main rate %lu\n", __func__, main_rate);
1911 reg = clk_readl(UTMIP_PLL_CFG2);
1913 /* Program UTMIP PLL stable and active counts */
1914 /* [FIXME] arclk_rst.h says WRONG! This should be 1ms -> 0x50 Check! */
1915 reg &= ~UTMIP_PLL_CFG2_STABLE_COUNT(~0);
1916 reg |= UTMIP_PLL_CFG2_STABLE_COUNT(
1917 utmi_parameters[i].stable_count);
1919 reg &= ~UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(~0);
1921 reg |= UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(
1922 utmi_parameters[i].active_delay_count);
1924 /* Remove power downs from UTMIP PLL control bits */
1925 reg |= UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERUP;
1926 reg |= UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERUP;
1927 reg |= UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERUP;
1928 reg |= UTMIP_PLL_CFG2_FORCE_PD_SAMP_D_POWERUP;
1929 reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN;
1930 reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN;
1931 reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN;
1932 reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_D_POWERDOWN;
1934 clk_writel(reg, UTMIP_PLL_CFG2);
1936 /* Program UTMIP PLL delay and oscillator frequency counts */
1937 reg = clk_readl(UTMIP_PLL_CFG1);
1938 reg &= ~UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(~0);
1940 reg |= UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(
1941 utmi_parameters[i].enable_delay_count);
1943 reg &= ~UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(~0);
1944 reg |= UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(
1945 utmi_parameters[i].xtal_freq_count);
1947 /* Remove power downs from UTMIP PLL control bits */
1948 reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN;
1949 reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN;
1950 reg &= ~UTMIP_PLL_CFG1_FORCE_PLLU_POWERUP;
1951 reg &= ~UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN;
1952 clk_writel(reg, UTMIP_PLL_CFG1);
1954 /* Setup HW control of UTMIPLL */
1955 reg = clk_readl(UTMIPLL_HW_PWRDN_CFG0);
1956 reg |= UTMIPLL_HW_PWRDN_CFG0_USE_LOCKDET;
1957 reg &= ~UTMIPLL_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL;
1958 reg |= UTMIPLL_HW_PWRDN_CFG0_SEQ_START_STATE;
1959 clk_writel(reg, UTMIPLL_HW_PWRDN_CFG0);
1961 reg = clk_readl(UTMIP_PLL_CFG1);
1962 reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERUP;
1963 reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN;
1964 clk_writel(reg, UTMIP_PLL_CFG1);
1968 /* Setup SW override of UTMIPLL assuming USB2.0
1969 ports are assigned to USB2 */
1970 reg = clk_readl(UTMIPLL_HW_PWRDN_CFG0);
1971 reg |= UTMIPLL_HW_PWRDN_CFG0_IDDQ_SWCTL;
1972 reg |= UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE;
1973 clk_writel(reg, UTMIPLL_HW_PWRDN_CFG0);
1977 /* Enable HW control UTMIPLL */
1978 reg = clk_readl(UTMIPLL_HW_PWRDN_CFG0);
1979 reg |= UTMIPLL_HW_PWRDN_CFG0_SEQ_ENABLE;
1980 clk_writel(reg, UTMIPLL_HW_PWRDN_CFG0);
1983 static void tegra11_pll_clk_init(struct clk *c)
1985 u32 val = clk_readl(c->reg + PLL_BASE);
1987 c->state = (val & PLL_BASE_ENABLE) ? ON : OFF;
1989 if (c->flags & PLL_FIXED && !(val & PLL_BASE_OVERRIDE)) {
1990 const struct clk_pll_freq_table *sel;
1991 unsigned long input_rate = clk_get_rate(c->parent);
1992 c->u.pll.fixed_rate = PLLP_DEFAULT_FIXED_RATE;
1994 for (sel = c->u.pll.freq_table; sel->input_rate != 0; sel++) {
1995 if (sel->input_rate == input_rate &&
1996 sel->output_rate == c->u.pll.fixed_rate) {
1998 c->div = sel->m * sel->p;
2002 pr_err("Clock %s has unknown fixed frequency\n", c->name);
2004 } else if (val & PLL_BASE_BYPASS) {
2008 c->mul = (val & PLL_BASE_DIVN_MASK) >> PLL_BASE_DIVN_SHIFT;
2009 c->div = (val & PLL_BASE_DIVM_MASK) >> PLL_BASE_DIVM_SHIFT;
2010 if (c->flags & PLLU)
2011 c->div *= (val & PLLU_BASE_POST_DIV) ? 1 : 2;
2013 c->div *= (0x1 << ((val & PLL_BASE_DIVP_MASK) >>
2014 PLL_BASE_DIVP_SHIFT));
2017 if (c->flags & PLL_FIXED) {
2018 c->u.pll.fixed_rate = clk_get_rate_locked(c);
2021 if (c->flags & PLLU) {
2022 /* Configure UTMI PLL power management */
2023 tegra11_utmi_param_configure(c);
2025 /* Put PLLU under h/w control */
2026 usb_plls_hw_control_enable(PLLU_HW_PWRDN_CFG0);
2028 val = clk_readl(c->reg + PLL_BASE);
2029 val &= ~PLLU_BASE_OVERRIDE;
2030 clk_writel(val, c->reg + PLL_BASE);
2032 /* Set XUSB PLL pad pwr override and iddq */
2033 val = xusb_padctl_readl(XUSB_PADCTL_IOPHY_PLL0_CTL1);
2034 val |= XUSB_PADCTL_IOPHY_PLL0_CTL1_PLL_PWR_OVRD;
2035 val |= XUSB_PADCTL_IOPHY_PLL0_CTL1_PLL_IDDQ;
2036 xusb_padctl_writel(val, XUSB_PADCTL_IOPHY_PLL0_CTL1);
2040 static int tegra11_pll_clk_enable(struct clk *c)
2043 pr_debug("%s on clock %s\n", __func__, c->name);
2045 #if USE_PLL_LOCK_BITS
2046 /* toggle lock enable bit to reset lock detection circuit (couple
2047 register reads provide enough duration for reset pulse) */
2048 val = clk_readl(c->reg + PLL_MISC(c));
2049 val &= ~PLL_MISC_LOCK_ENABLE(c);
2050 clk_writel(val, c->reg + PLL_MISC(c));
2051 val = clk_readl(c->reg + PLL_MISC(c));
2052 val = clk_readl(c->reg + PLL_MISC(c));
2053 val |= PLL_MISC_LOCK_ENABLE(c);
2054 clk_writel(val, c->reg + PLL_MISC(c));
2056 val = clk_readl(c->reg + PLL_BASE);
2057 val &= ~PLL_BASE_BYPASS;
2058 val |= PLL_BASE_ENABLE;
2059 clk_writel(val, c->reg + PLL_BASE);
2061 tegra11_pll_clk_wait_for_lock(c, c->reg + PLL_BASE, PLL_BASE_LOCK);
2066 static void tegra11_pll_clk_disable(struct clk *c)
2069 pr_debug("%s on clock %s\n", __func__, c->name);
2071 val = clk_readl(c->reg);
2072 val &= ~(PLL_BASE_BYPASS | PLL_BASE_ENABLE);
2073 clk_writel(val, c->reg);
2076 static u8 get_pll_cpcon(struct clk *c, u16 n)
2078 if (c->flags & PLLD) {
2088 return c->u.pll.cpcon_default ? : OUT_OF_TABLE_CPCON;
2091 /* Special comparison frequency selection for PLLD at 12MHz refrence rate */
2092 unsigned long get_pll_cfreq_special(struct clk *c, unsigned long input_rate,
2093 unsigned long rate, unsigned long *vco)
2095 if (!(c->flags & PLLD) || (input_rate != 12000000))
2098 *vco = c->u.pll.vco_min;
2100 if (rate <= 250000000)
2102 else if (rate <= 500000000)
2108 /* Common comparison frequency selection */
2109 unsigned long get_pll_cfreq_common(struct clk *c, unsigned long input_rate,
2110 unsigned long rate, unsigned long *vco)
2112 unsigned long cfreq = 0;
2114 switch (input_rate) {
2117 cfreq = (rate <= 1000000 * 1000) ? 1000000 : 2000000;
2120 cfreq = (rate <= 1000000 * 1000) ? 1000000 : 2600000;
2124 cfreq = (rate <= 1200000 * 1000) ? 1200000 : 2400000;
2127 if (c->parent->flags & DIV_U71_FIXED) {
2128 /* PLLP_OUT1 rate is not in PLLA table */
2129 pr_warn("%s: failed %s ref/out rates %lu/%lu\n",
2130 __func__, c->name, input_rate, rate);
2131 cfreq = input_rate/(input_rate/1000000);
2134 pr_err("%s: Unexpected reference rate %lu\n",
2135 __func__, input_rate);
2139 /* Raise VCO to guarantee 0.5% accuracy, and vco min boundary */
2140 *vco = max(200 * cfreq, c->u.pll.vco_min);
2144 static int tegra11_pll_clk_set_rate(struct clk *c, unsigned long rate)
2146 u32 val, p_div, old_base;
2147 unsigned long input_rate;
2148 const struct clk_pll_freq_table *sel;
2149 struct clk_pll_freq_table cfg;
2151 pr_debug("%s: %s %lu\n", __func__, c->name, rate);
2153 if (c->flags & PLL_FIXED) {
2155 if (rate != c->u.pll.fixed_rate) {
2156 pr_err("%s: Can not change %s fixed rate %lu to %lu\n",
2157 __func__, c->name, c->u.pll.fixed_rate, rate);
2164 input_rate = clk_get_rate(c->parent);
2166 /* Check if the target rate is tabulated */
2167 for (sel = c->u.pll.freq_table; sel->input_rate != 0; sel++) {
2168 if (sel->input_rate == input_rate && sel->output_rate == rate) {
2169 if (c->flags & PLLU) {
2170 BUG_ON(sel->p < 1 || sel->p > 2);
2172 p_div = PLLU_BASE_POST_DIV;
2175 for (val = sel->p; val > 1; val >>= 1, p_div++);
2176 p_div <<= PLL_BASE_DIVP_SHIFT;
2182 /* Configure out-of-table rate */
2183 if (sel->input_rate == 0) {
2184 unsigned long cfreq, vco;
2185 BUG_ON(c->flags & PLLU);
2188 /* If available, use pll specific algorithm to select comparison
2189 frequency, and vco target */
2190 cfreq = get_pll_cfreq_special(c, input_rate, rate, &vco);
2192 cfreq = get_pll_cfreq_common(c, input_rate, rate, &vco);
2194 for (cfg.output_rate = rate; cfg.output_rate < vco; p_div++)
2195 cfg.output_rate <<= 1;
2197 cfg.p = 0x1 << p_div;
2198 cfg.m = input_rate / cfreq;
2199 cfg.n = cfg.output_rate / cfreq;
2200 cfg.cpcon = get_pll_cpcon(c, cfg.n);
2202 if ((cfg.m > (PLL_BASE_DIVM_MASK >> PLL_BASE_DIVM_SHIFT)) ||
2203 (cfg.n > (PLL_BASE_DIVN_MASK >> PLL_BASE_DIVN_SHIFT)) ||
2204 (p_div > (PLL_BASE_DIVP_MASK >> PLL_BASE_DIVP_SHIFT)) ||
2205 (cfg.output_rate > c->u.pll.vco_max)) {
2206 pr_err("%s: Failed to set %s out-of-table rate %lu\n",
2207 __func__, c->name, rate);
2210 p_div <<= PLL_BASE_DIVP_SHIFT;
2214 c->div = sel->m * sel->p;
2216 old_base = val = clk_readl(c->reg + PLL_BASE);
2217 val &= ~(PLL_BASE_DIVM_MASK | PLL_BASE_DIVN_MASK |
2218 ((c->flags & PLLU) ? PLLU_BASE_POST_DIV : PLL_BASE_DIVP_MASK));
2219 val |= (sel->m << PLL_BASE_DIVM_SHIFT) |
2220 (sel->n << PLL_BASE_DIVN_SHIFT) | p_div;
2221 if (val == old_base)
2224 if (c->state == ON) {
2225 tegra11_pll_clk_disable(c);
2226 val &= ~(PLL_BASE_BYPASS | PLL_BASE_ENABLE);
2228 clk_writel(val, c->reg + PLL_BASE);
2230 if (c->flags & PLL_HAS_CPCON) {
2231 val = clk_readl(c->reg + PLL_MISC(c));
2232 val &= ~PLL_MISC_CPCON_MASK;
2233 val |= sel->cpcon << PLL_MISC_CPCON_SHIFT;
2234 if (c->flags & (PLLU | PLLD)) {
2235 val &= ~PLL_MISC_LFCON_MASK;
2236 val |= PLLDU_LFCON << PLL_MISC_LFCON_SHIFT;
2238 clk_writel(val, c->reg + PLL_MISC(c));
2242 tegra11_pll_clk_enable(c);
2247 static struct clk_ops tegra_pll_ops = {
2248 .init = tegra11_pll_clk_init,
2249 .enable = tegra11_pll_clk_enable,
2250 .disable = tegra11_pll_clk_disable,
2251 .set_rate = tegra11_pll_clk_set_rate,
2254 static void tegra11_pllp_clk_init(struct clk *c)
2256 tegra11_pll_clk_init(c);
2257 tegra11_pllp_init_dependencies(c->u.pll.fixed_rate);
2260 #ifdef CONFIG_PM_SLEEP
2261 static void tegra11_pllp_clk_resume(struct clk *c)
2263 unsigned long rate = c->u.pll.fixed_rate;
2264 tegra11_pll_clk_init(c);
2265 BUG_ON(rate != c->u.pll.fixed_rate);
2269 static struct clk_ops tegra_pllp_ops = {
2270 .init = tegra11_pllp_clk_init,
2271 .enable = tegra11_pll_clk_enable,
2272 .disable = tegra11_pll_clk_disable,
2273 .set_rate = tegra11_pll_clk_set_rate,
2277 tegra11_plld_clk_cfg_ex(struct clk *c, enum tegra_clk_ex_param p, u32 setting)
2282 case TEGRA_CLK_PLLD_CSI_OUT_ENB:
2283 mask = PLLD_BASE_CSI_CLKENABLE | PLLD_BASE_CSI_CLKSOURCE;
2284 reg = c->reg + PLL_BASE;
2286 case TEGRA_CLK_PLLD_DSI_OUT_ENB:
2287 mask = PLLD_MISC_DSI_CLKENABLE;
2288 reg = c->reg + PLL_MISC(c);
2290 case TEGRA_CLK_PLLD_MIPI_MUX_SEL:
2291 mask = PLLD_BASE_DSI_MUX_MASK;
2292 reg = c->reg + PLL_BASE;
2298 val = clk_readl(reg);
2303 clk_writel(val, reg);
2307 static struct clk_ops tegra_plld_ops = {
2308 .init = tegra11_pll_clk_init,
2309 .enable = tegra11_pll_clk_enable,
2310 .disable = tegra11_pll_clk_disable,
2311 .set_rate = tegra11_pll_clk_set_rate,
2312 .clk_cfg_ex = tegra11_plld_clk_cfg_ex,
2316 * Dynamic ramp PLLs:
2317 * PLLC2 and PLLC3 (PLLCX)
2318 * PLLX and PLLC (PLLXC)
2320 * When scaling PLLC and PLLX, dynamic ramp is allowed for any transition that
2321 * changes NDIV only. As a matter of policy we will make sure that switching
2322 * between output rates above VCO minimum is always dynamic. The pre-requisite
2323 * for the above guarantee is the following configuration convention:
2324 * - pll configured with fixed MDIV
2325 * - when output rate is above VCO minimum PDIV = 0 (p-value = 1)
2326 * Switching between output rates below VCO minimum may or may not be dynamic,
2327 * and switching across VCO minimum is never dynamic.
2329 * PLLC2 and PLLC3 in addition to dynamic ramp mechanism have also glitchless
2330 * output dividers. However dynamic ramp without overshoot is guaranteed only
2331 * when output divisor is less or equal 8.
2333 * Of course, dynamic ramp is applied provided PLL is already enabled.
2337 * Common configuration policy for dynamic ramp PLLs:
2338 * - always set fixed M-value based on the reference rate
2339 * - always set P-value value 1:1 for output rates above VCO minimum, and
2340 * choose minimum necessary P-value for output rates below VCO minimum
2341 * - calculate N-value based on selected M and P
2343 static int pll_dyn_ramp_cfg(struct clk *c, struct clk_pll_freq_table *cfg,
2344 unsigned long rate, unsigned long input_rate, u32 *pdiv)
2351 p = DIV_ROUND_UP(c->u.pll.vco_min, rate);
2352 p = c->u.pll.round_p_to_pdiv(p, pdiv);
2353 if (IS_ERR_VALUE(p))
2356 cfg->m = PLL_FIXED_MDIV(c, input_rate);
2358 cfg->output_rate = rate * cfg->p;
2359 cfg->n = cfg->output_rate * cfg->m / input_rate;
2361 /* can use PLLCX N-divider field layout for all dynamic ramp PLLs */
2362 if ((cfg->n > (PLLCX_BASE_DIVN_MASK >> PLL_BASE_DIVN_SHIFT)) ||
2363 (cfg->output_rate > c->u.pll.vco_max))
2369 static int pll_dyn_ramp_find_cfg(struct clk *c, struct clk_pll_freq_table *cfg,
2370 unsigned long rate, unsigned long input_rate, u32 *pdiv)
2372 const struct clk_pll_freq_table *sel;
2374 /* Check if the target rate is tabulated */
2375 for (sel = c->u.pll.freq_table; sel->input_rate != 0; sel++) {
2376 if (sel->input_rate == input_rate && sel->output_rate == rate) {
2377 u32 p = c->u.pll.round_p_to_pdiv(sel->p, pdiv);
2378 BUG_ON(IS_ERR_VALUE(p));
2379 BUG_ON(sel->m != PLL_FIXED_MDIV(c, input_rate));
2385 /* Configure out-of-table rate */
2386 if (pll_dyn_ramp_cfg(c, cfg, rate, input_rate, pdiv)) {
2387 pr_err("%s: Failed to set %s out-of-table rate %lu\n",
2388 __func__, c->name, rate);
2394 static inline void pll_do_iddq(struct clk *c, u32 offs, u32 iddq_bit, bool set)
2396 u32 val = clk_readl(c->reg + offs);
2401 clk_writel_delay(val, c->reg + offs);
2405 static u8 pllcx_p[PLLCX_PDIV_MAX + 1] = {
2406 /* PDIV: 0, 1, 2, 3, 4, 5, 6, 7 */
2407 /* p: */ 1, 2, 3, 4, 6, 8, 12, 16 };
2409 static u32 pllcx_round_p_to_pdiv(u32 p, u32 *pdiv)
2414 for (i = 0; i <= PLLCX_PDIV_MAX; i++) {
2415 /* Do not use DIV3 p values - mapped to even PDIV */
2416 if (i && ((i & 0x1) == 0))
2419 if (p <= pllcx_p[i]) {
2429 static void pllcx_update_dynamic_koef(struct clk *c, unsigned long input_rate,
2432 u32 val, n_threshold;
2434 switch (input_rate) {
2449 pr_err("%s: Unexpected reference rate %lu\n",
2450 __func__, input_rate);
2455 val = clk_readl(c->reg + PLL_MISC(c));
2456 val &= ~(PLLCX_MISC_SDM_DIV_MASK | PLLCX_MISC_FILT_DIV_MASK);
2457 val |= n <= n_threshold ?
2458 PLLCX_MISC_DIV_LOW_RANGE : PLLCX_MISC_DIV_HIGH_RANGE;
2459 clk_writel(val, c->reg + PLL_MISC(c));
2462 static void pllcx_strobe(struct clk *c)
2464 u32 reg = c->reg + PLL_MISC(c);
2465 u32 val = clk_readl(reg);
2467 val |= PLLCX_MISC_STROBE;
2468 pll_writel_delay(val, reg);
2470 val &= ~PLLCX_MISC_STROBE;
2471 clk_writel(val, reg);
2474 static void pllcx_set_defaults(struct clk *c, unsigned long input_rate, u32 n)
2476 clk_writel(PLLCX_MISC_DEFAULT_VALUE, c->reg + PLL_MISC(c));
2477 clk_writel(PLLCX_MISC1_DEFAULT_VALUE, c->reg + PLL_MISCN(c, 1));
2478 clk_writel(PLLCX_MISC2_DEFAULT_VALUE, c->reg + PLL_MISCN(c, 2));
2479 clk_writel(PLLCX_MISC3_DEFAULT_VALUE, c->reg + PLL_MISCN(c, 3));
2481 pllcx_update_dynamic_koef(c, input_rate, n);
2484 static void tegra11_pllcx_clk_init(struct clk *c)
2486 unsigned long input_rate = clk_get_rate(c->parent);
2489 /* clip vco_min to exact multiple of input rate to avoid crossover
2492 DIV_ROUND_UP(c->u.pll.vco_min, input_rate) * input_rate;
2493 c->min_rate = DIV_ROUND_UP(c->u.pll.vco_min, pllcx_p[PLLCX_PDIV_MAX]);
2495 val = clk_readl(c->reg + PLL_BASE);
2496 c->state = (val & PLL_BASE_ENABLE) ? ON : OFF;
2499 * PLLCX is not a boot PLL, it should be left disabled by boot-loader,
2500 * and no enabled module clocks should use it as a source during clock
2503 BUG_ON(c->state == ON);
2505 * Most of PLLCX register fields are shadowed, and can not be read
2506 * directly from PLL h/w. Hence, actual PLLCX boot state is unknown.
2507 * Initialize PLL to default state: disabled, reset; shadow registers
2508 * loaded with default parameters; dividers are preset for half of
2509 * minimum VCO rate (the latter assured that shadowed divider settings
2510 * are within supported range).
2512 m = PLL_FIXED_MDIV(c, input_rate);
2513 n = m * c->u.pll.vco_min / input_rate;
2515 val = (m << PLL_BASE_DIVM_SHIFT) | (n << PLL_BASE_DIVN_SHIFT) |
2516 (1 << PLL_BASE_DIVP_SHIFT);
2517 clk_writel(val, c->reg + PLL_BASE); /* PLL disabled */
2519 pllcx_set_defaults(c, input_rate, n);
2525 static int tegra11_pllcx_clk_enable(struct clk *c)
2528 pr_debug("%s on clock %s\n", __func__, c->name);
2530 val = clk_readl(c->reg + PLL_BASE);
2531 val &= ~PLL_BASE_BYPASS;
2532 val |= PLL_BASE_ENABLE;
2533 pll_writel_delay(val, c->reg + PLL_BASE);
2535 val = clk_readl(c->reg + PLL_MISC(c));
2536 val &= ~PLLCX_MISC_RESET;
2537 pll_writel_delay(val, c->reg + PLL_MISC(c));
2540 tegra11_pll_clk_wait_for_lock(c, c->reg + PLL_BASE,
2541 PLL_BASE_LOCK | PLLCX_BASE_PHASE_LOCK);
2545 static void tegra11_pllcx_clk_disable(struct clk *c)
2548 pr_debug("%s on clock %s\n", __func__, c->name);
2550 val = clk_readl(c->reg);
2551 val &= ~(PLL_BASE_BYPASS | PLL_BASE_ENABLE);
2552 clk_writel(val, c->reg);
2554 val = clk_readl(c->reg + PLL_MISC(c));
2555 val |= PLLCX_MISC_RESET;
2556 pll_writel_delay(val, c->reg + PLL_MISC(c));
2559 static int tegra11_pllcx_clk_set_rate(struct clk *c, unsigned long rate)
2562 unsigned long input_rate;
2563 struct clk_pll_freq_table cfg, old_cfg;
2564 const struct clk_pll_freq_table *sel = &cfg;
2566 pr_debug("%s: %s %lu\n", __func__, c->name, rate);
2568 input_rate = clk_get_rate(c->parent);
2570 if (pll_dyn_ramp_find_cfg(c, &cfg, rate, input_rate, &pdiv))
2574 c->div = sel->m * sel->p;
2576 val = clk_readl(c->reg + PLL_BASE);
2577 PLL_BASE_PARSE(PLLCX, old_cfg, val);
2578 old_cfg.p = pllcx_p[old_cfg.p];
2580 BUG_ON(old_cfg.m != sel->m);
2581 if ((sel->n == old_cfg.n) && (sel->p == old_cfg.p))
2584 #if PLLCX_USE_DYN_RAMP
2585 if (c->state == ON && ((sel->n == old_cfg.n) ||
2586 PLLCX_IS_DYN(sel->p, old_cfg.p))) {
2588 * Dynamic ramp if PLL is enabled, and M divider is unchanged:
2589 * - Change P divider 1st if intermediate rate is below either
2591 * - Change N divider with DFS strobe - target rate is either
2592 * final new rate or below old rate
2593 * - If divider has been changed, exit without waiting for lock.
2594 * Otherwise, wait for lock and change divider.
2596 if (sel->p > old_cfg.p) {
2597 val &= ~PLLCX_BASE_DIVP_MASK;
2598 val |= pdiv << PLL_BASE_DIVP_SHIFT;
2599 clk_writel(val, c->reg + PLL_BASE);
2602 if (sel->n != old_cfg.n) {
2603 pllcx_update_dynamic_koef(c, input_rate, sel->n);
2604 val &= ~PLLCX_BASE_DIVN_MASK;
2605 val |= sel->n << PLL_BASE_DIVN_SHIFT;
2606 pll_writel_delay(val, c->reg + PLL_BASE);
2609 tegra11_pll_clk_wait_for_lock(c, c->reg + PLL_BASE,
2610 PLL_BASE_LOCK | PLLCX_BASE_PHASE_LOCK);
2613 if (sel->p < old_cfg.p) {
2614 val &= ~PLLCX_BASE_DIVP_MASK;
2615 val |= pdiv << PLL_BASE_DIVP_SHIFT;
2616 clk_writel(val, c->reg + PLL_BASE);
2622 val &= ~(PLLCX_BASE_DIVN_MASK | PLLCX_BASE_DIVP_MASK);
2623 val |= (sel->n << PLL_BASE_DIVN_SHIFT) |
2624 (pdiv << PLL_BASE_DIVP_SHIFT);
2626 if (c->state == ON) {
2627 tegra11_pllcx_clk_disable(c);
2628 val &= ~(PLL_BASE_BYPASS | PLL_BASE_ENABLE);
2630 pllcx_update_dynamic_koef(c, input_rate, sel->n);
2631 clk_writel(val, c->reg + PLL_BASE);
2633 tegra11_pllcx_clk_enable(c);
2638 #ifdef CONFIG_PM_SLEEP
2639 static void tegra11_pllcx_clk_resume_enable(struct clk *c)
2641 unsigned long rate = clk_get_rate_all_locked(c->parent);
2642 u32 val = clk_readl(c->reg + PLL_BASE);
2643 enum clk_state state = c->state;
2645 if (val & PLL_BASE_ENABLE)
2646 return; /* already resumed */
2648 /* Restore input divider */
2649 val &= ~PLLCX_BASE_DIVM_MASK;
2650 val |= PLL_FIXED_MDIV(c, rate) << PLL_BASE_DIVM_SHIFT;
2651 clk_writel(val, c->reg + PLL_BASE);
2653 /* temporarily sync h/w and s/w states, final sync happens
2654 in tegra_clk_resume later */
2656 pllcx_set_defaults(c, rate, c->mul);
2658 rate = clk_get_rate_all_locked(c) + 1;
2659 tegra11_pllcx_clk_set_rate(c, rate);
2660 tegra11_pllcx_clk_enable(c);
2665 static struct clk_ops tegra_pllcx_ops = {
2666 .init = tegra11_pllcx_clk_init,
2667 .enable = tegra11_pllcx_clk_enable,
2668 .disable = tegra11_pllcx_clk_disable,
2669 .set_rate = tegra11_pllcx_clk_set_rate,
2673 /* non-monotonic mapping below is not a typo */
2674 static u8 pllxc_p[PLLXC_PDIV_MAX + 1] = {
2675 /* PDIV: 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 */
2676 /* p: */ 1, 2, 3, 4, 5, 6, 8, 10, 12, 16, 12, 16, 20, 24, 32 };
2678 static u32 pllxc_round_p_to_pdiv(u32 p, u32 *pdiv)
2680 if (!p || (p > PLLXC_SW_PDIV_MAX + 1))
2688 static void pllxc_get_dyn_steps(struct clk *c, unsigned long input_rate,
2689 u32 *step_a, u32 *step_b)
2691 switch (input_rate) {
2707 pr_err("%s: Unexpected reference rate %lu\n",
2708 __func__, input_rate);
2713 static void pllx_set_defaults(struct clk *c, unsigned long input_rate)
2718 /* Only s/w dyn ramp control is supported */
2719 val = clk_readl(PLLX_HW_CTRL_CFG);
2720 BUG_ON(!(val & PLLX_HW_CTRL_CFG_SWCTRL));
2722 pllxc_get_dyn_steps(c, input_rate, &step_a, &step_b);
2723 val = step_a << PLLX_MISC2_DYNRAMP_STEPA_SHIFT;
2724 val |= step_b << PLLX_MISC2_DYNRAMP_STEPB_SHIFT;
2726 /* Get ready dyn ramp state machine, disable lock override */
2727 clk_writel(val, c->reg + PLL_MISCN(c, 2));
2729 /* Enable outputs to CPUs and configure lock */
2731 #if USE_PLL_LOCK_BITS
2732 val |= PLL_MISC_LOCK_ENABLE(c);
2734 clk_writel(val, c->reg + PLL_MISC(c));
2736 /* Check/set IDDQ */
2737 val = clk_readl(c->reg + PLL_MISCN(c, 3));
2739 BUG_ON(val & PLLX_MISC3_IDDQ);
2741 val |= PLLX_MISC3_IDDQ;
2742 clk_writel(val, c->reg + PLL_MISCN(c, 3));
2746 static void pllc_set_defaults(struct clk *c, unsigned long input_rate)
2751 /* Get ready dyn ramp state machine */
2752 pllxc_get_dyn_steps(c, input_rate, &step_a, &step_b);
2753 val = step_a << PLLC_MISC1_DYNRAMP_STEPA_SHIFT;
2754 val |= step_b << PLLC_MISC1_DYNRAMP_STEPB_SHIFT;
2755 clk_writel(val, c->reg + PLL_MISCN(c, 1));
2757 /* Configure lock and check/set IDDQ */
2758 val = clk_readl(c->reg + PLL_BASE);
2759 val &= ~PLLC_BASE_LOCK_OVERRIDE;
2760 clk_writel(val, c->reg + PLL_BASE);
2762 val = clk_readl(c->reg + PLL_MISC(c));
2763 #if USE_PLL_LOCK_BITS
2764 val |= PLLC_MISC_LOCK_ENABLE;
2766 val &= ~PLLC_MISC_LOCK_ENABLE;
2768 clk_writel(val, c->reg + PLL_MISC(c));
2770 if (c->state == ON) {
2771 BUG_ON(val & PLLC_MISC_IDDQ);
2773 val |= PLLC_MISC_IDDQ;
2774 clk_writel(val, c->reg + PLL_MISC(c));
2778 static void tegra11_pllxc_clk_init(struct clk *c)
2780 unsigned long input_rate = clk_get_rate(c->parent);
2783 /* clip vco_min to exact multiple of input rate to avoid crossover
2786 DIV_ROUND_UP(c->u.pll.vco_min, input_rate) * input_rate;
2788 DIV_ROUND_UP(c->u.pll.vco_min, pllxc_p[PLLXC_SW_PDIV_MAX]);
2790 val = clk_readl(c->reg + PLL_BASE);
2791 c->state = (val & PLL_BASE_ENABLE) ? ON : OFF;
2793 m = (val & PLLXC_BASE_DIVM_MASK) >> PLL_BASE_DIVM_SHIFT;
2794 p = (val & PLLXC_BASE_DIVP_MASK) >> PLL_BASE_DIVP_SHIFT;
2795 BUG_ON(p > PLLXC_PDIV_MAX);
2799 c->mul = (val & PLLXC_BASE_DIVN_MASK) >> PLL_BASE_DIVN_SHIFT;
2801 if (c->flags & PLLX)
2802 pllx_set_defaults(c, input_rate);
2804 pllc_set_defaults(c, input_rate);
2807 static int tegra11_pllxc_clk_enable(struct clk *c)
2810 pr_debug("%s on clock %s\n", __func__, c->name);
2812 if (c->flags & PLLX)
2813 pll_do_iddq(c, PLL_MISCN(c, 3), PLLX_MISC3_IDDQ, false);
2815 pll_do_iddq(c, PLL_MISC(c), PLLC_MISC_IDDQ, false);
2817 val = clk_readl(c->reg + PLL_BASE);
2818 val |= PLL_BASE_ENABLE;
2819 clk_writel(val, c->reg + PLL_BASE);
2821 tegra11_pll_clk_wait_for_lock(c, c->reg + PLL_BASE, PLL_BASE_LOCK);
2826 static void tegra11_pllxc_clk_disable(struct clk *c)
2829 pr_debug("%s on clock %s\n", __func__, c->name);
2831 val = clk_readl(c->reg + PLL_BASE);
2832 val &= ~PLL_BASE_ENABLE;
2833 clk_writel(val, c->reg + PLL_BASE);
2835 if (c->flags & PLLX)
2836 pll_do_iddq(c, PLL_MISCN(c, 3), PLLX_MISC3_IDDQ, true);
2838 pll_do_iddq(c, PLL_MISC(c), PLLC_MISC_IDDQ, true);
2842 #define PLLXC_DYN_RAMP(pll_misc, reg) \
2844 u32 misc = clk_readl((reg)); \
2846 misc &= ~pll_misc##_NDIV_NEW_MASK; \
2847 misc |= sel->n << pll_misc##_NDIV_NEW_SHIFT; \
2848 pll_writel_delay(misc, (reg)); \
2850 misc |= pll_misc##_EN_DYNRAMP; \
2851 clk_writel(misc, (reg)); \
2852 tegra11_pll_clk_wait_for_lock(c, (reg), \
2853 pll_misc##_DYNRAMP_DONE); \
2855 val &= ~PLLXC_BASE_DIVN_MASK; \
2856 val |= sel->n << PLL_BASE_DIVN_SHIFT; \
2857 pll_writel_delay(val, c->reg + PLL_BASE); \
2859 misc &= ~pll_misc##_EN_DYNRAMP; \
2860 pll_writel_delay(misc, (reg)); \
2863 static int tegra11_pllxc_clk_set_rate(struct clk *c, unsigned long rate)
2866 unsigned long input_rate;
2867 struct clk_pll_freq_table cfg, old_cfg;
2868 const struct clk_pll_freq_table *sel = &cfg;
2870 pr_debug("%s: %s %lu\n", __func__, c->name, rate);
2872 input_rate = clk_get_rate(c->parent);
2874 if (pll_dyn_ramp_find_cfg(c, &cfg, rate, input_rate, &pdiv))
2878 c->div = sel->m * sel->p;
2880 val = clk_readl(c->reg + PLL_BASE);
2881 PLL_BASE_PARSE(PLLXC, old_cfg, val);
2882 old_cfg.p = pllxc_p[old_cfg.p];
2884 if ((sel->m == old_cfg.m) && (sel->n == old_cfg.n) &&
2885 (sel->p == old_cfg.p))
2888 #if PLLXC_USE_DYN_RAMP
2890 * Dynamic ramp can be used if M, P dividers are unchanged
2891 * (coveres superset of conventional dynamic ramps)
2893 if ((c->state == ON) && (sel->m == old_cfg.m) &&
2894 (sel->p == old_cfg.p)) {
2896 if (c->flags & PLLX) {
2897 u32 reg = c->reg + PLL_MISCN(c, 2);
2898 PLLXC_DYN_RAMP(PLLX_MISC2, reg);
2900 u32 reg = c->reg + PLL_MISCN(c, 1);
2901 PLLXC_DYN_RAMP(PLLC_MISC1, reg);
2907 if (c->state == ON) {
2908 /* Use "ENABLE" pulse without placing PLL into IDDQ */
2909 val &= ~PLL_BASE_ENABLE;
2910 pll_writel_delay(val, c->reg + PLL_BASE);
2913 val &= ~(PLLXC_BASE_DIVM_MASK |
2914 PLLXC_BASE_DIVN_MASK | PLLXC_BASE_DIVP_MASK);
2915 val |= (sel->m << PLL_BASE_DIVM_SHIFT) |
2916 (sel->n << PLL_BASE_DIVN_SHIFT) | (pdiv << PLL_BASE_DIVP_SHIFT);
2917 clk_writel(val, c->reg + PLL_BASE);
2919 if (c->state == ON) {
2920 val |= PLL_BASE_ENABLE;
2921 clk_writel(val, c->reg + PLL_BASE);
2922 tegra11_pll_clk_wait_for_lock(c, c->reg + PLL_BASE,
2928 #ifdef CONFIG_PM_SLEEP
2929 static void tegra11_pllxc_clk_resume_enable(struct clk *c)
2931 unsigned long rate = clk_get_rate_all_locked(c->parent);
2932 enum clk_state state = c->state;
2934 if (clk_readl(c->reg + PLL_BASE) & PLL_BASE_ENABLE)
2935 return; /* already resumed */
2937 /* temporarily sync h/w and s/w states, final sync happens
2938 in tegra_clk_resume later */
2940 if (c->flags & PLLX)
2941 pllx_set_defaults(c, rate);
2943 pllc_set_defaults(c, rate);
2945 rate = clk_get_rate_all_locked(c) + 1;
2946 tegra11_pllxc_clk_set_rate(c, rate);
2947 tegra11_pllxc_clk_enable(c);
2952 static struct clk_ops tegra_pllxc_ops = {
2953 .init = tegra11_pllxc_clk_init,
2954 .enable = tegra11_pllxc_clk_enable,
2955 .disable = tegra11_pllxc_clk_disable,
2956 .set_rate = tegra11_pllxc_clk_set_rate,
2960 /* FIXME: pllm suspend/resume */
2962 static u32 pllm_round_p_to_pdiv(u32 p, u32 *pdiv)
2972 static void pllm_set_defaults(struct clk *c, unsigned long input_rate)
2974 u32 val = clk_readl(c->reg + PLL_MISC(c));
2976 val &= ~PLLM_MISC_LOCK_OVERRIDE;
2977 #if USE_PLL_LOCK_BITS
2978 val &= ~PLLM_MISC_LOCK_DISABLE;
2980 val |= PLLM_MISC_LOCK_DISABLE;
2984 val |= PLLM_MISC_IDDQ;
2986 BUG_ON(val & PLLM_MISC_IDDQ);
2988 clk_writel(val, c->reg + PLL_MISC(c));
2991 static void tegra11_pllm_clk_init(struct clk *c)
2993 unsigned long input_rate = clk_get_rate(c->parent);
2996 /* clip vco_min to exact multiple of input rate to avoid crossover
2999 DIV_ROUND_UP(c->u.pll.vco_min, input_rate) * input_rate;
3001 DIV_ROUND_UP(c->u.pll.vco_min, 2);
3003 val = pmc_readl(PMC_PLLP_WB0_OVERRIDE);
3004 if (val & PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE) {
3005 c->state = (val & PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE) ? ON : OFF;
3006 val = pmc_readl(PMC_PLLM_WB0_OVERRIDE_2);
3007 p = (val & PMC_PLLM_WB0_OVERRIDE_2_DIVP_MASK) ? 2 : 1;
3009 val = pmc_readl(PMC_PLLM_WB0_OVERRIDE);
3011 val = clk_readl(c->reg + PLL_BASE);
3012 c->state = (val & PLL_BASE_ENABLE) ? ON : OFF;
3013 p = (val & PLLM_BASE_DIVP_MASK) ? 2 : 1;
3016 m = (val & PLLM_BASE_DIVM_MASK) >> PLL_BASE_DIVM_SHIFT;
3017 BUG_ON(m != PLL_FIXED_MDIV(c, input_rate));
3019 c->mul = (val & PLLM_BASE_DIVN_MASK) >> PLL_BASE_DIVN_SHIFT;
3021 pllm_set_defaults(c, input_rate);
3024 static int tegra11_pllm_clk_enable(struct clk *c)
3027 pr_debug("%s on clock %s\n", __func__, c->name);
3029 pll_do_iddq(c, PLL_MISC(c), PLLM_MISC_IDDQ, false);
3031 /* Just enable both base and override - one would work */
3032 val = clk_readl(c->reg + PLL_BASE);
3033 val |= PLL_BASE_ENABLE;
3034 clk_writel(val, c->reg + PLL_BASE);
3036 val = pmc_readl(PMC_PLLP_WB0_OVERRIDE);
3037 val |= PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE;
3038 pmc_writel(val, PMC_PLLP_WB0_OVERRIDE);
3039 val = pmc_readl(PMC_PLLP_WB0_OVERRIDE);
3041 tegra11_pll_clk_wait_for_lock(c, c->reg + PLL_BASE, PLL_BASE_LOCK);
3045 static void tegra11_pllm_clk_disable(struct clk *c)
3048 pr_debug("%s on clock %s\n", __func__, c->name);
3050 /* Just disable both base and override - one would work */
3051 val = pmc_readl(PMC_PLLP_WB0_OVERRIDE);
3052 val &= ~PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE;
3053 pmc_writel(val, PMC_PLLP_WB0_OVERRIDE);
3054 val = pmc_readl(PMC_PLLP_WB0_OVERRIDE);
3056 val = clk_readl(c->reg + PLL_BASE);
3057 val &= ~PLL_BASE_ENABLE;
3058 clk_writel(val, c->reg + PLL_BASE);
3060 pll_do_iddq(c, PLL_MISC(c), PLLM_MISC_IDDQ, true);
3063 static int tegra11_pllm_clk_set_rate(struct clk *c, unsigned long rate)
3066 unsigned long input_rate;
3067 struct clk_pll_freq_table cfg;
3068 const struct clk_pll_freq_table *sel = &cfg;
3070 pr_debug("%s: %s %lu\n", __func__, c->name, rate);
3072 if (c->state == ON) {
3073 if (rate != clk_get_rate_locked(c)) {
3074 pr_err("%s: Can not change memory %s rate in flight\n",
3081 input_rate = clk_get_rate(c->parent);
3083 if (pll_dyn_ramp_find_cfg(c, &cfg, rate, input_rate, &pdiv))
3087 c->div = sel->m * sel->p;
3089 val = pmc_readl(PMC_PLLP_WB0_OVERRIDE);
3090 if (val & PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE) {
3091 val = pmc_readl(PMC_PLLM_WB0_OVERRIDE_2);
3092 val = pdiv ? (val | PMC_PLLM_WB0_OVERRIDE_2_DIVP_MASK) :
3093 (val & ~PMC_PLLM_WB0_OVERRIDE_2_DIVP_MASK);
3094 pmc_writel(val, PMC_PLLM_WB0_OVERRIDE_2);
3096 val = pmc_readl(PMC_PLLM_WB0_OVERRIDE);
3097 val &= ~(PLLM_BASE_DIVM_MASK | PLLM_BASE_DIVN_MASK);
3098 val |= (sel->m << PLL_BASE_DIVM_SHIFT) |
3099 (sel->n << PLL_BASE_DIVN_SHIFT);
3100 pmc_writel(val, PMC_PLLM_WB0_OVERRIDE);
3102 val = clk_readl(c->reg + PLL_BASE);
3103 val &= ~(PLLM_BASE_DIVM_MASK | PLLM_BASE_DIVN_MASK |
3104 PLLM_BASE_DIVP_MASK);
3105 val |= (sel->m << PLL_BASE_DIVM_SHIFT) |
3106 (sel->n << PLL_BASE_DIVN_SHIFT) |
3107 (pdiv ? PLLM_BASE_DIVP_MASK : 0);
3108 clk_writel(val, c->reg + PLL_BASE);
3114 static struct clk_ops tegra_pllm_ops = {
3115 .init = tegra11_pllm_clk_init,
3116 .enable = tegra11_pllm_clk_enable,
3117 .disable = tegra11_pllm_clk_disable,
3118 .set_rate = tegra11_pllm_clk_set_rate,
3122 /* non-monotonic mapping below is not a typo */
3123 static u8 pllre_p[PLLRE_PDIV_MAX + 1] = {
3124 /* PDIV: 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 */
3125 /* p: */ 1, 2, 3, 4, 5, 6, 8, 10, 12, 16, 12, 16, 20, 24, 32 };
3127 static u32 pllre_round_p_to_pdiv(u32 p, u32 *pdiv)
3129 if (!p || (p > PLLRE_SW_PDIV_MAX + 1))
3137 static void pllre_set_defaults(struct clk *c, unsigned long input_rate)
3139 u32 val = clk_readl(c->reg + PLL_MISC(c));
3141 val &= ~PLLRE_MISC_LOCK_OVERRIDE;
3142 #if USE_PLL_LOCK_BITS
3143 val |= PLLRE_MISC_LOCK_ENABLE;
3145 val &= ~PLLRE_MISC_LOCK_ENABLE;
3149 val |= PLLRE_MISC_IDDQ;
3151 BUG_ON(val & PLLRE_MISC_IDDQ);
3153 clk_writel(val, c->reg + PLL_MISC(c));
3156 static void tegra11_pllre_clk_init(struct clk *c)
3158 unsigned long input_rate = clk_get_rate(c->parent);
3161 /* clip vco_min to exact multiple of input rate to avoid crossover
3164 DIV_ROUND_UP(c->u.pll.vco_min, input_rate) * input_rate;
3165 c->min_rate = c->u.pll.vco_min;
3167 val = clk_readl(c->reg + PLL_BASE);
3168 c->state = (val & PLL_BASE_ENABLE) ? ON : OFF;
3171 /* overwrite h/w por state with min setting */
3172 m = PLL_FIXED_MDIV(c, input_rate);
3173 val = (m << PLL_BASE_DIVM_SHIFT) |
3174 (c->min_rate / input_rate << PLL_BASE_DIVN_SHIFT);
3175 clk_writel(val, c->reg + PLL_BASE);
3178 m = (val & PLLRE_BASE_DIVM_MASK) >> PLL_BASE_DIVM_SHIFT;
3179 BUG_ON(m != PLL_FIXED_MDIV(c, input_rate));
3182 c->mul = (val & PLLRE_BASE_DIVN_MASK) >> PLL_BASE_DIVN_SHIFT;
3184 pllre_set_defaults(c, input_rate);
3187 static int tegra11_pllre_clk_enable(struct clk *c)
3190 pr_debug("%s on clock %s\n", __func__, c->name);
3192 pll_do_iddq(c, PLL_MISC(c), PLLRE_MISC_IDDQ, false);
3194 val = clk_readl(c->reg + PLL_BASE);
3195 val |= PLL_BASE_ENABLE;
3196 clk_writel(val, c->reg + PLL_BASE);
3198 tegra11_pll_clk_wait_for_lock(c, c->reg + PLL_MISC(c), PLLRE_MISC_LOCK);
3202 static void tegra11_pllre_clk_disable(struct clk *c)
3205 pr_debug("%s on clock %s\n", __func__, c->name);
3207 val = clk_readl(c->reg + PLL_BASE);
3208 val &= ~PLL_BASE_ENABLE;
3209 clk_writel(val, c->reg + PLL_BASE);
3211 pll_do_iddq(c, PLL_MISC(c), PLLRE_MISC_IDDQ, true);
3214 static int tegra11_pllre_clk_set_rate(struct clk *c, unsigned long rate)
3217 unsigned long input_rate;
3218 struct clk_pll_freq_table cfg;
3220 pr_debug("%s: %s %lu\n", __func__, c->name, rate);
3222 if (rate < c->min_rate) {
3223 pr_err("%s: Failed to set %s rate %lu\n",
3224 __func__, c->name, rate);
3228 input_rate = clk_get_rate(c->parent);
3229 cfg.m = PLL_FIXED_MDIV(c, input_rate);
3230 cfg.n = rate * cfg.m / input_rate;
3235 val = old_base = clk_readl(c->reg + PLL_BASE);
3236 val &= ~(PLLRE_BASE_DIVM_MASK | PLLRE_BASE_DIVN_MASK);
3237 val |= (cfg.m << PLL_BASE_DIVM_SHIFT) | (cfg.n << PLL_BASE_DIVN_SHIFT);
3238 if (val == old_base)
3241 if (c->state == ON) {
3242 /* Use "ENABLE" pulse without placing PLL into IDDQ */
3243 val &= ~PLL_BASE_ENABLE;
3244 old_base &= ~PLL_BASE_ENABLE;
3245 pll_writel_delay(old_base, c->reg + PLL_BASE);
3248 clk_writel(val, c->reg + PLL_BASE);
3250 if (c->state == ON) {
3251 val |= PLL_BASE_ENABLE;
3252 clk_writel(val, c->reg + PLL_BASE);
3253 tegra11_pll_clk_wait_for_lock(
3254 c, c->reg + PLL_MISC(c), PLLRE_MISC_LOCK);
3259 static struct clk_ops tegra_pllre_ops = {
3260 .init = tegra11_pllre_clk_init,
3261 .enable = tegra11_pllre_clk_enable,
3262 .disable = tegra11_pllre_clk_disable,
3263 .set_rate = tegra11_pllre_clk_set_rate,
3266 static void tegra11_pllre_out_clk_init(struct clk *c)
3270 val = clk_readl(c->reg);
3271 p = (val & PLLRE_BASE_DIVP_MASK) >> PLLRE_BASE_DIVP_SHIFT;
3272 BUG_ON(p > PLLRE_PDIV_MAX);
3277 c->state = c->parent->state;
3280 static int tegra11_pllre_out_clk_enable(struct clk *c)
3285 static void tegra11_pllre_out_clk_disable(struct clk *c)
3289 static int tegra11_pllre_out_clk_set_rate(struct clk *c, unsigned long rate)
3292 unsigned long input_rate, flags;
3294 pr_debug("%s: %s %lu\n", __func__, c->name, rate);
3296 clk_lock_save(c->parent, &flags);
3297 input_rate = clk_get_rate_locked(c->parent);
3299 p = DIV_ROUND_UP(input_rate, rate);
3300 p = c->parent->u.pll.round_p_to_pdiv(p, &pdiv);
3301 if (IS_ERR_VALUE(p)) {
3302 pr_err("%s: Failed to set %s rate %lu\n",
3303 __func__, c->name, rate);
3304 clk_unlock_restore(c->parent, &flags);
3309 val = clk_readl(c->reg);
3310 val &= ~PLLRE_BASE_DIVP_MASK;
3311 val |= pdiv << PLLRE_BASE_DIVP_SHIFT;
3312 clk_writel(val, c->reg);
3314 clk_unlock_restore(c->parent, &flags);
3318 static struct clk_ops tegra_pllre_out_ops = {
3319 .init = tegra11_pllre_out_clk_init,
3320 .enable = tegra11_pllre_out_clk_enable,
3321 .disable = tegra11_pllre_out_clk_disable,
3322 .set_rate = tegra11_pllre_out_clk_set_rate,
3325 #ifdef CONFIG_PM_SLEEP
3326 /* Resume both pllre_vco and pllre_out */
3327 static void tegra11_pllre_clk_resume_enable(struct clk *c)
3330 u32 val = clk_readl(c->reg + PLL_BASE);
3331 unsigned long rate = clk_get_rate_all_locked(c->parent->parent);
3332 enum clk_state state = c->parent->state;
3334 if (val & PLL_BASE_ENABLE)
3335 return; /* already resumed */
3337 /* temporarily sync h/w and s/w states, final sync happens
3338 in tegra_clk_resume later */
3339 c->parent->state = OFF;
3340 pllre_set_defaults(c->parent, rate);
3342 /* restore PLLRE VCO feedback loop (m, n) */
3343 rate = clk_get_rate_all_locked(c->parent) + 1;
3344 tegra11_pllre_clk_set_rate(c->parent, rate);
3346 /* restore PLLRE post-divider */
3347 c->parent->u.pll.round_p_to_pdiv(c->div, &pdiv);
3348 val = clk_readl(c->reg);
3349 val &= ~PLLRE_BASE_DIVP_MASK;
3350 val |= pdiv << PLLRE_BASE_DIVP_SHIFT;
3351 clk_writel(val, c->reg);
3353 tegra11_pllre_clk_enable(c->parent);
3354 c->parent->state = state;
3358 /* non-monotonic mapping below is not a typo */
3359 static u8 plle_p[PLLE_CMLDIV_MAX + 1] = {
3360 /* CMLDIV: 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 */
3361 /* p: */ 1, 2, 3, 4, 5, 6, 8, 10, 12, 16, 12, 16, 20, 24, 32 };
3363 static inline void select_pll_e_input(u32 aux_reg)
3365 #if USE_PLLE_INPUT_PLLRE
3366 aux_reg |= PLLE_AUX_PLLRE_SEL;
3368 aux_reg &= ~(PLLE_AUX_PLLRE_SEL | PLLE_AUX_PLLP_SEL);
3370 clk_writel(aux_reg, PLLE_AUX);
3373 static void tegra11_plle_clk_init(struct clk *c)
3376 struct clk *pll_ref = tegra_get_clock_by_name("pll_ref");
3377 struct clk *re_vco = tegra_get_clock_by_name("pll_re_vco");
3378 struct clk *pllp = tegra_get_clock_by_name("pllp");
3379 #if USE_PLLE_INPUT_PLLRE
3380 struct clk *ref = re_vco;
3382 struct clk *ref = pll_ref;
3386 val = clk_readl(c->reg + PLL_BASE);
3387 c->state = (val & PLL_BASE_ENABLE) ? ON : OFF;
3388 c->mul = (val & PLLE_BASE_DIVN_MASK) >> PLL_BASE_DIVN_SHIFT;
3389 c->div = (val & PLLE_BASE_DIVM_MASK) >> PLL_BASE_DIVM_SHIFT;
3390 p = (val & PLLE_BASE_DIVCML_MASK) >> PLLE_BASE_DIVCML_SHIFT;
3391 c->div *= plle_p[p];
3393 val = clk_readl(PLLE_AUX);
3394 c->parent = (val & PLLE_AUX_PLLRE_SEL) ? re_vco :
3395 (val & PLLE_AUX_PLLP_SEL) ? pllp : pll_ref;
3396 if (c->parent != ref) {
3397 if (c->state == ON) {
3398 WARN(1, "%s: pll_e is left enabled with %s input\n",
3399 __func__, c->parent->name);
3402 select_pll_e_input(val);
3407 static void tegra11_plle_clk_disable(struct clk *c)
3410 pr_debug("%s on clock %s\n", __func__, c->name);
3412 /* FIXME: do we need to restore other s/w controls ? */
3413 val = clk_readl(c->reg + PLL_BASE);
3414 val &= ~PLL_BASE_ENABLE;
3415 clk_writel(val, c->reg + PLL_BASE);
3417 val = clk_readl(c->reg + PLL_MISC(c));
3418 val |= PLLE_MISC_IDDQ_SW_CTRL | PLLE_MISC_IDDQ_SW_VALUE;
3419 pll_writel_delay(val, c->reg + PLL_MISC(c));
3422 static int tegra11_plle_clk_enable(struct clk *c)
3425 const struct clk_pll_freq_table *sel;
3426 unsigned long rate = c->u.pll.fixed_rate;
3427 unsigned long input_rate = clk_get_rate(c->parent);
3429 if (c->state == ON) {
3430 /* BL left plle enabled - don't change configuartion */
3431 pr_warn("%s: pll_e is already enabled\n", __func__);
3435 for (sel = c->u.pll.freq_table; sel->input_rate != 0; sel++) {
3436 if (sel->input_rate == input_rate && sel->output_rate == rate)
3440 if (sel->input_rate == 0) {
3441 pr_err("%s: %s input rate %lu is out-of-table\n",
3442 __func__, c->name, input_rate);
3446 /* setup locking configuration, s/w control of IDDQ and enable modes,
3447 take pll out of IDDQ via s/w control, setup VREG */
3448 val = clk_readl(c->reg + PLL_BASE);
3449 val &= ~PLLE_BASE_LOCK_OVERRIDE;
3450 clk_writel(val, c->reg + PLL_BASE);
3452 val = clk_readl(c->reg + PLL_MISC(c));
3453 val |= PLLE_MISC_LOCK_ENABLE;
3454 val |= PLLE_MISC_IDDQ_SW_CTRL;
3455 val &= ~PLLE_MISC_IDDQ_SW_VALUE;
3456 val |= PLLE_MISC_PLLE_PTS;
3457 val |= PLLE_MISC_VREG_BG_CTRL_MASK | PLLE_MISC_VREG_CTRL_MASK;
3458 clk_writel(val, c->reg + PLL_MISC(c));
3461 /* configure dividers, disable SS */
3462 val = clk_readl(PLLE_SS_CTRL);
3463 val |= PLLE_SS_DISABLE;
3464 clk_writel(val, PLLE_SS_CTRL);
3466 val = clk_readl(c->reg + PLL_BASE);
3467 val &= ~(PLLE_BASE_DIVM_MASK | PLLE_BASE_DIVN_MASK |
3468 PLLE_BASE_DIVCML_MASK);
3469 val |= (sel->m << PLL_BASE_DIVM_SHIFT) |
3470 (sel->n << PLL_BASE_DIVN_SHIFT) |
3471 (sel->cpcon << PLLE_BASE_DIVCML_SHIFT);
3472 pll_writel_delay(val, c->reg + PLL_BASE);
3474 c->div = sel->m * sel->p;
3476 /* enable and lock pll */
3477 val |= PLL_BASE_ENABLE;
3478 clk_writel(val, c->reg + PLL_BASE);
3479 tegra11_pll_clk_wait_for_lock(
3480 c, c->reg + PLL_MISC(c), PLLE_MISC_LOCK);
3482 val = clk_readl(PLLE_SS_CTRL);
3483 val &= ~(PLLE_SS_CNTL_CENTER | PLLE_SS_CNTL_INVERT);
3484 val &= ~PLLE_SS_COEFFICIENTS_MASK;
3485 val |= PLLE_SS_COEFFICIENTS_VAL;
3486 clk_writel(val, PLLE_SS_CTRL);
3487 val &= ~(PLLE_SS_CNTL_SSC_BYP | PLLE_SS_CNTL_BYPASS_SS);
3488 pll_writel_delay(val, PLLE_SS_CTRL);
3489 val &= ~PLLE_SS_CNTL_INTERP_RESET;
3490 pll_writel_delay(val, PLLE_SS_CTRL);
3493 /* switch pll under h/w control */
3494 val = clk_readl(c->reg + PLL_MISC(c));
3495 val &= ~PLLE_MISC_IDDQ_SW_CTRL;
3496 clk_writel(val, c->reg + PLL_MISC(c));
3498 val = clk_readl(PLLE_AUX);
3499 val |= PLLE_AUX_USE_LOCKDET | PLLE_AUX_SEQ_START_STATE;
3500 val &= ~(PLLE_AUX_ENABLE_SWCTL | PLLE_AUX_SS_SWCTL);
3501 pll_writel_delay(val, PLLE_AUX);
3502 val |= PLLE_AUX_SEQ_ENABLE;
3503 pll_writel_delay(val, PLLE_AUX);
3505 /* clear XUSB PLL pad pwr override and iddq */
3506 val = xusb_padctl_readl(XUSB_PADCTL_IOPHY_PLL0_CTL1);
3507 val &= ~XUSB_PADCTL_IOPHY_PLL0_CTL1_PLL_PWR_OVRD;
3508 val &= ~XUSB_PADCTL_IOPHY_PLL0_CTL1_PLL_IDDQ;
3509 xusb_padctl_writel(val, XUSB_PADCTL_IOPHY_PLL0_CTL1);
3511 /* enable hw control of xusb brick pll */
3512 usb_plls_hw_control_enable(XUSBIO_PLL_CFG0);
3517 #ifdef CONFIG_PM_SLEEP
3518 static void tegra11_plle_clk_resume(struct clk *c)
3520 u32 val = clk_readl(c->reg + PLL_BASE);
3521 if (val & PLL_BASE_ENABLE)
3522 return; /* already resumed */
3524 /* Restore parent */
3525 val = clk_readl(PLLE_AUX);
3526 select_pll_e_input(val);
3530 static struct clk_ops tegra_plle_ops = {
3531 .init = tegra11_plle_clk_init,
3532 .enable = tegra11_plle_clk_enable,
3533 .disable = tegra11_plle_clk_disable,
3537 * Tegra11 includes dynamic frequency lock loop (DFLL) with automatic voltage
3538 * control as possible CPU clock source. It is included in the Tegra11 clock
3539 * tree as "complex PLL" with standard Tegra clock framework APIs. However,
3540 * DFLL locking logic h/w access APIs are separated in the tegra_cl_dvfs.c
3541 * module. Hence, DFLL operations, with the exception of initialization, are
3542 * basically cl-dvfs wrappers.
3545 /* DFLL operations */
3546 #ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS
3547 static void tune_cpu_trimmers(bool trim_high)
3550 clk_writel(0, CPU_FINETRIM_SELECT);
3551 clk_writel(0, CPU_FINETRIM_DR);
3552 clk_writel(0, CPU_FINETRIM_R);
3554 clk_writel(0x3F, CPU_FINETRIM_SELECT);
3555 clk_writel(0x3F, CPU_FINETRIM_DR);
3556 clk_writel(0xFFF, CPU_FINETRIM_R);
3559 clk_readl(CPU_FINETRIM_R);
3563 static void __init tegra11_dfll_cpu_late_init(struct clk *c)
3565 #ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS
3567 struct clk *cpu = tegra_get_clock_by_name("cpu_g");
3569 if (!cpu || !cpu->dvfs) {
3570 pr_err("%s: CPU dvfs is not present\n", __func__);
3573 if (cpu->dvfs->speedo_id > 0) /* A01P and above parts */
3574 tegra_dvfs_set_dfll_tune_trimmers(cpu->dvfs, tune_cpu_trimmers);
3576 #ifdef CONFIG_TEGRA_FPGA_PLATFORM
3577 u32 netlist, patchid;
3578 tegra_get_netlist_revision(&netlist, &patchid);
3580 pr_err("%s: CL-DVFS is not available on net %d\n",
3585 /* release dfll clock source reset, init cl_dvfs control logic, and
3586 move dfll to initialized state, so it can be used as CPU source */
3587 tegra_periph_reset_deassert(c);
3588 ret = tegra_init_cl_dvfs();
3591 c->u.dfll.cl_dvfs = platform_get_drvdata(&tegra_cl_dvfs_device);
3593 use_dfll = CONFIG_TEGRA_USE_DFLL_RANGE;
3594 tegra_dvfs_set_dfll_range(cpu->dvfs, use_dfll);
3595 tegra_cl_dvfs_debug_init(c);
3596 pr_info("Tegra CPU DFLL is initialized\n");
3601 static void tegra11_dfll_clk_init(struct clk *c)
3603 c->ops->init = tegra11_dfll_cpu_late_init;
3606 static int tegra11_dfll_clk_enable(struct clk *c)
3608 return tegra_cl_dvfs_enable(c->u.dfll.cl_dvfs);
3611 static void tegra11_dfll_clk_disable(struct clk *c)
3613 tegra_cl_dvfs_disable(c->u.dfll.cl_dvfs);
3616 static int tegra11_dfll_clk_set_rate(struct clk *c, unsigned long rate)
3618 int ret = tegra_cl_dvfs_request_rate(c->u.dfll.cl_dvfs, rate);
3621 c->rate = tegra_cl_dvfs_request_get(c->u.dfll.cl_dvfs);
3626 static void tegra11_dfll_clk_reset(struct clk *c, bool assert)
3628 u32 val = assert ? DFLL_BASE_RESET : 0;
3629 clk_writel_delay(val, c->reg);
3633 tegra11_dfll_clk_cfg_ex(struct clk *c, enum tegra_clk_ex_param p, u32 setting)
3635 if (p == TEGRA_CLK_DFLL_LOCK)
3636 return setting ? tegra_cl_dvfs_lock(c->u.dfll.cl_dvfs) :
3637 tegra_cl_dvfs_unlock(c->u.dfll.cl_dvfs);
3641 #ifdef CONFIG_PM_SLEEP
3642 static void tegra11_dfll_clk_resume(struct clk *c)
3644 if (!(clk_readl(c->reg) & DFLL_BASE_RESET))
3645 return; /* already resumed */
3647 if (c->state != UNINITIALIZED) {
3648 tegra_periph_reset_deassert(c);
3649 tegra_cl_dvfs_resume(c->u.dfll.cl_dvfs);
3654 static struct clk_ops tegra_dfll_ops = {
3655 .init = tegra11_dfll_clk_init,
3656 .enable = tegra11_dfll_clk_enable,
3657 .disable = tegra11_dfll_clk_disable,
3658 .set_rate = tegra11_dfll_clk_set_rate,
3659 .reset = tegra11_dfll_clk_reset,
3660 .clk_cfg_ex = tegra11_dfll_clk_cfg_ex,
3663 /* DFLL sysfs interface */
3664 static int tegra11_use_dfll_cb(const char *arg, const struct kernel_param *kp)
3667 unsigned long c_flags, p_flags;
3668 unsigned int old_use_dfll;
3669 struct clk *c = tegra_get_clock_by_name("cpu");
3670 struct clk *dfll = tegra_get_clock_by_name("dfll_cpu");
3672 if (!c->parent || !c->parent->dvfs || !dfll)
3675 clk_lock_save(c, &c_flags);
3676 if (dfll->state == UNINITIALIZED) {
3677 pr_err("%s: DFLL is not initialized\n", __func__);
3678 clk_unlock_restore(c, &c_flags);
3681 if (c->parent->u.cpu.mode == MODE_LP) {
3682 pr_err("%s: DFLL is not used on LP CPU\n", __func__);
3683 clk_unlock_restore(c, &c_flags);
3687 clk_lock_save(c->parent, &p_flags);
3688 old_use_dfll = use_dfll;
3689 param_set_int(arg, kp);
3691 if (use_dfll != old_use_dfll) {
3692 ret = tegra_dvfs_set_dfll_range(c->parent->dvfs, use_dfll);
3694 use_dfll = old_use_dfll;
3696 ret = clk_set_rate_locked(c->parent,
3697 clk_get_rate_locked(c->parent));
3699 use_dfll = old_use_dfll;
3700 tegra_dvfs_set_dfll_range(
3701 c->parent->dvfs, use_dfll);
3705 clk_unlock_restore(c->parent, &p_flags);
3706 clk_unlock_restore(c, &c_flags);
3707 tegra_recalculate_cpu_edp_limits();
3711 static struct kernel_param_ops tegra11_use_dfll_ops = {
3712 .set = tegra11_use_dfll_cb,
3713 .get = param_get_int,
3715 module_param_cb(use_dfll, &tegra11_use_dfll_ops, &use_dfll, 0644);
3718 /* Clock divider ops (non-atomic shared register access) */
3719 static DEFINE_SPINLOCK(pll_div_lock);
3721 static int tegra11_pll_div_clk_set_rate(struct clk *c, unsigned long rate);
3722 static void tegra11_pll_div_clk_init(struct clk *c)
3724 if (c->flags & DIV_U71) {
3726 if (c->parent->state == OFF)
3729 val = clk_readl(c->reg);
3730 val >>= c->reg_shift;
3731 c->state = (val & PLL_OUT_CLKEN) ? ON : OFF;
3732 if (!(val & PLL_OUT_RESET_DISABLE))
3735 if (c->u.pll_div.default_rate) {
3736 int ret = tegra11_pll_div_clk_set_rate(
3737 c, c->u.pll_div.default_rate);
3741 divu71 = (val & PLL_OUT_RATIO_MASK) >> PLL_OUT_RATIO_SHIFT;
3742 c->div = (divu71 + 2);
3744 } else if (c->flags & DIV_2) {
3746 if (c->flags & (PLLD | PLLX)) {
3752 } else if (c->flags & PLLU) {
3753 u32 val = clk_readl(c->reg);
3754 c->state = val & (0x1 << c->reg_shift) ? ON : OFF;
3762 static int tegra11_pll_div_clk_enable(struct clk *c)
3766 unsigned long flags;
3768 pr_debug("%s: %s\n", __func__, c->name);
3769 if (c->flags & DIV_U71) {
3770 spin_lock_irqsave(&pll_div_lock, flags);
3771 val = clk_readl(c->reg);
3772 new_val = val >> c->reg_shift;
3775 new_val |= PLL_OUT_CLKEN | PLL_OUT_RESET_DISABLE;
3777 val &= ~(0xFFFF << c->reg_shift);
3778 val |= new_val << c->reg_shift;
3779 clk_writel_delay(val, c->reg);
3780 spin_unlock_irqrestore(&pll_div_lock, flags);
3782 } else if (c->flags & DIV_2) {
3784 } else if (c->flags & PLLU) {
3785 clk_lock_save(c->parent, &flags);
3786 val = clk_readl(c->reg) | (0x1 << c->reg_shift);
3787 clk_writel_delay(val, c->reg);
3788 clk_unlock_restore(c->parent, &flags);
3794 static void tegra11_pll_div_clk_disable(struct clk *c)
3798 unsigned long flags;
3800 pr_debug("%s: %s\n", __func__, c->name);
3801 if (c->flags & DIV_U71) {
3802 spin_lock_irqsave(&pll_div_lock, flags);
3803 val = clk_readl(c->reg);
3804 new_val = val >> c->reg_shift;
3807 new_val &= ~(PLL_OUT_CLKEN | PLL_OUT_RESET_DISABLE);
3809 val &= ~(0xFFFF << c->reg_shift);
3810 val |= new_val << c->reg_shift;
3811 clk_writel_delay(val, c->reg);
3812 spin_unlock_irqrestore(&pll_div_lock, flags);
3813 } else if (c->flags & PLLU) {
3814 clk_lock_save(c->parent, &flags);
3815 val = clk_readl(c->reg) & (~(0x1 << c->reg_shift));
3816 clk_writel_delay(val, c->reg);
3817 clk_unlock_restore(c->parent, &flags);
3821 static int tegra11_pll_div_clk_set_rate(struct clk *c, unsigned long rate)
3826 unsigned long parent_rate = clk_get_rate(c->parent);
3827 unsigned long flags;
3829 pr_debug("%s: %s %lu\n", __func__, c->name, rate);
3830 if (c->flags & DIV_U71) {
3831 divider_u71 = clk_div71_get_divider(
3832 parent_rate, rate, c->flags, ROUND_DIVIDER_UP);
3833 if (divider_u71 >= 0) {
3834 spin_lock_irqsave(&pll_div_lock, flags);
3835 val = clk_readl(c->reg);
3836 new_val = val >> c->reg_shift;
3838 if (c->flags & DIV_U71_FIXED)
3839 new_val |= PLL_OUT_OVERRIDE;
3840 new_val &= ~PLL_OUT_RATIO_MASK;
3841 new_val |= divider_u71 << PLL_OUT_RATIO_SHIFT;
3843 val &= ~(0xFFFF << c->reg_shift);
3844 val |= new_val << c->reg_shift;
3845 clk_writel_delay(val, c->reg);
3846 c->div = divider_u71 + 2;
3848 spin_unlock_irqrestore(&pll_div_lock, flags);
3851 } else if (c->flags & DIV_2)
3852 return clk_set_rate(c->parent, rate * 2);
3857 static long tegra11_pll_div_clk_round_rate(struct clk *c, unsigned long rate)
3860 unsigned long parent_rate = clk_get_rate(c->parent);
3861 pr_debug("%s: %s %lu\n", __func__, c->name, rate);
3863 if (c->flags & DIV_U71) {
3864 divider = clk_div71_get_divider(
3865 parent_rate, rate, c->flags, ROUND_DIVIDER_UP);
3868 return DIV_ROUND_UP(parent_rate * 2, divider + 2);
3869 } else if (c->flags & DIV_2)
3870 /* no rounding - fixed DIV_2 dividers pass rate to parent PLL */
3876 static struct clk_ops tegra_pll_div_ops = {
3877 .init = tegra11_pll_div_clk_init,
3878 .enable = tegra11_pll_div_clk_enable,
3879 .disable = tegra11_pll_div_clk_disable,
3880 .set_rate = tegra11_pll_div_clk_set_rate,
3881 .round_rate = tegra11_pll_div_clk_round_rate,
3884 /* Periph clk ops */
3885 static inline u32 periph_clk_source_mask(struct clk *c)
3887 if (c->u.periph.src_mask)
3888 return c->u.periph.src_mask;
3889 else if (c->flags & MUX8)
3891 else if (c->flags & MUX_PWM)
3893 else if (c->flags & MUX_CLK_OUT)
3894 return 3 << (c->u.periph.clk_num + 4);
3895 else if (c->flags & PLLD)
3896 return PLLD_BASE_DSI_MUX_MASK;
3901 static inline u32 periph_clk_source_shift(struct clk *c)
3903 if (c->u.periph.src_shift)
3904 return c->u.periph.src_shift;
3905 else if (c->flags & MUX8)
3907 else if (c->flags & MUX_PWM)
3909 else if (c->flags & MUX_CLK_OUT)
3910 return c->u.periph.clk_num + 4;
3911 else if (c->flags & PLLD)
3912 return PLLD_BASE_DSI_MUX_SHIFT;
3917 static void tegra11_periph_clk_init(struct clk *c)
3919 u32 val = clk_readl(c->reg);
3920 const struct clk_mux_sel *mux = 0;
3921 const struct clk_mux_sel *sel;
3922 if (c->flags & MUX) {
3923 for (sel = c->inputs; sel->input != NULL; sel++) {
3924 if (((val & periph_clk_source_mask(c)) >>
3925 periph_clk_source_shift(c)) == sel->value)
3930 c->parent = mux->input;
3932 if (c->flags & PLLU) {
3933 /* for xusb_hs clock enforce SS div2 source */
3934 val &= ~periph_clk_source_mask(c);
3935 clk_writel_delay(val, c->reg);
3937 c->parent = c->inputs[0].input;
3940 /* if peripheral is left under reset - enforce safe rate */
3941 if (!(c->flags & PERIPH_NO_RESET) &&
3942 (clk_readl(PERIPH_CLK_TO_RST_REG(c)) & PERIPH_CLK_TO_BIT(c))) {
3943 tegra_periph_clk_safe_rate_init(c);
3944 val = clk_readl(c->reg);
3947 if (c->flags & DIV_U71) {
3948 u32 divu71 = val & PERIPH_CLK_SOURCE_DIVU71_MASK;
3949 if (c->flags & DIV_U71_IDLE) {
3950 val &= ~(PERIPH_CLK_SOURCE_DIVU71_MASK <<
3951 PERIPH_CLK_SOURCE_DIVIDLE_SHIFT);
3952 val |= (PERIPH_CLK_SOURCE_DIVIDLE_VAL <<
3953 PERIPH_CLK_SOURCE_DIVIDLE_SHIFT);
3954 clk_writel(val, c->reg);
3956 c->div = divu71 + 2;
3958 } else if (c->flags & DIV_U151) {
3959 u32 divu151 = val & PERIPH_CLK_SOURCE_DIVU16_MASK;
3960 if ((c->flags & DIV_U151_UART) &&
3961 (!(val & PERIPH_CLK_UART_DIV_ENB))) {
3964 c->div = divu151 + 2;
3966 } else if (c->flags & DIV_U16) {
3967 u32 divu16 = val & PERIPH_CLK_SOURCE_DIVU16_MASK;
3968 c->div = divu16 + 1;
3975 if (c->flags & PERIPH_NO_ENB) {
3976 c->state = c->parent->state;
3982 if (!(clk_readl(PERIPH_CLK_TO_ENB_REG(c)) & PERIPH_CLK_TO_BIT(c)))
3984 if (!(c->flags & PERIPH_NO_RESET))
3985 if (clk_readl(PERIPH_CLK_TO_RST_REG(c)) & PERIPH_CLK_TO_BIT(c))
3989 static int tegra11_periph_clk_enable(struct clk *c)
3991 unsigned long flags;
3992 pr_debug("%s on clock %s\n", __func__, c->name);
3994 if (c->flags & PERIPH_NO_ENB)
3997 spin_lock_irqsave(&periph_refcount_lock, flags);
3999 tegra_periph_clk_enable_refcount[c->u.periph.clk_num]++;
4000 if (tegra_periph_clk_enable_refcount[c->u.periph.clk_num] > 1) {
4001 spin_unlock_irqrestore(&periph_refcount_lock, flags);
4005 clk_writel_delay(PERIPH_CLK_TO_BIT(c), PERIPH_CLK_TO_ENB_SET_REG(c));
4006 if (!(c->flags & PERIPH_NO_RESET) && !(c->flags & PERIPH_MANUAL_RESET)) {
4007 if (clk_readl(PERIPH_CLK_TO_RST_REG(c)) & PERIPH_CLK_TO_BIT(c)) {
4008 udelay(RESET_PROPAGATION_DELAY);
4009 clk_writel(PERIPH_CLK_TO_BIT(c), PERIPH_CLK_TO_RST_CLR_REG(c));
4012 spin_unlock_irqrestore(&periph_refcount_lock, flags);
4016 static void tegra11_periph_clk_disable(struct clk *c)
4018 unsigned long val, flags;
4019 pr_debug("%s on clock %s\n", __func__, c->name);
4021 if (c->flags & PERIPH_NO_ENB)
4024 spin_lock_irqsave(&periph_refcount_lock, flags);
4027 tegra_periph_clk_enable_refcount[c->u.periph.clk_num]--;
4029 if (tegra_periph_clk_enable_refcount[c->u.periph.clk_num] == 0) {
4030 /* If peripheral is in the APB bus then read the APB bus to
4031 * flush the write operation in apb bus. This will avoid the
4032 * peripheral access after disabling clock*/
4033 if (c->flags & PERIPH_ON_APB)
4034 val = tegra_read_chipid();
4037 PERIPH_CLK_TO_BIT(c), PERIPH_CLK_TO_ENB_CLR_REG(c));
4039 spin_unlock_irqrestore(&periph_refcount_lock, flags);
4042 static void tegra11_periph_clk_reset(struct clk *c, bool assert)
4045 pr_debug("%s %s on clock %s\n", __func__,
4046 assert ? "assert" : "deassert", c->name);
4048 if (c->flags & PERIPH_NO_ENB)
4051 if (!(c->flags & PERIPH_NO_RESET)) {
4053 /* If peripheral is in the APB bus then read the APB
4054 * bus to flush the write operation in apb bus. This
4055 * will avoid the peripheral access after disabling
4057 if (c->flags & PERIPH_ON_APB)
4058 val = tegra_read_chipid();
4060 clk_writel(PERIPH_CLK_TO_BIT(c),
4061 PERIPH_CLK_TO_RST_SET_REG(c));
4063 clk_writel(PERIPH_CLK_TO_BIT(c),
4064 PERIPH_CLK_TO_RST_CLR_REG(c));
4068 static int tegra11_periph_clk_set_parent(struct clk *c, struct clk *p)
4071 const struct clk_mux_sel *sel;
4072 pr_debug("%s: %s %s\n", __func__, c->name, p->name);
4074 if (!(c->flags & MUX))
4075 return (p == c->parent) ? 0 : (-EINVAL);
4077 for (sel = c->inputs; sel->input != NULL; sel++) {
4078 if (sel->input == p) {
4079 val = clk_readl(c->reg);
4080 val &= ~periph_clk_source_mask(c);
4081 val |= (sel->value << periph_clk_source_shift(c));
4086 clk_writel_delay(val, c->reg);
4088 if (c->refcnt && c->parent)
4089 clk_disable(c->parent);
4099 static int tegra11_periph_clk_set_rate(struct clk *c, unsigned long rate)
4103 unsigned long parent_rate = clk_get_rate(c->parent);
4105 if (c->flags & DIV_U71) {
4106 divider = clk_div71_get_divider(
4107 parent_rate, rate, c->flags, ROUND_DIVIDER_UP);
4109 val = clk_readl(c->reg);
4110 val &= ~PERIPH_CLK_SOURCE_DIVU71_MASK;
4112 clk_writel_delay(val, c->reg);
4113 c->div = divider + 2;
4117 } else if (c->flags & DIV_U151) {
4118 divider = clk_div151_get_divider(
4119 parent_rate, rate, c->flags, ROUND_DIVIDER_UP);
4121 val = clk_readl(c->reg);
4122 val &= ~PERIPH_CLK_SOURCE_DIVU16_MASK;
4124 if (c->flags & DIV_U151_UART) {
4126 val |= PERIPH_CLK_UART_DIV_ENB;
4128 val &= ~PERIPH_CLK_UART_DIV_ENB;
4130 clk_writel_delay(val, c->reg);
4131 c->div = divider + 2;
4135 } else if (c->flags & DIV_U16) {
4136 divider = clk_div16_get_divider(parent_rate, rate);
4138 val = clk_readl(c->reg);
4139 val &= ~PERIPH_CLK_SOURCE_DIVU16_MASK;
4141 clk_writel_delay(val, c->reg);
4142 c->div = divider + 1;
4146 } else if (parent_rate <= rate) {
4154 static long tegra11_periph_clk_round_rate(struct clk *c,
4158 unsigned long parent_rate = clk_get_rate(c->parent);
4159 pr_debug("%s: %s %lu\n", __func__, c->name, rate);
4161 if (c->flags & DIV_U71) {
4162 divider = clk_div71_get_divider(
4163 parent_rate, rate, c->flags, ROUND_DIVIDER_UP);
4167 return DIV_ROUND_UP(parent_rate * 2, divider + 2);
4168 } else if (c->flags & DIV_U151) {
4169 divider = clk_div151_get_divider(
4170 parent_rate, rate, c->flags, ROUND_DIVIDER_UP);
4174 return DIV_ROUND_UP(parent_rate * 2, divider + 2);
4175 } else if (c->flags & DIV_U16) {
4176 divider = clk_div16_get_divider(parent_rate, rate);
4179 return DIV_ROUND_UP(parent_rate, divider + 1);
4184 static struct clk_ops tegra_periph_clk_ops = {
4185 .init = &tegra11_periph_clk_init,
4186 .enable = &tegra11_periph_clk_enable,
4187 .disable = &tegra11_periph_clk_disable,
4188 .set_parent = &tegra11_periph_clk_set_parent,
4189 .set_rate = &tegra11_periph_clk_set_rate,
4190 .round_rate = &tegra11_periph_clk_round_rate,
4191 .reset = &tegra11_periph_clk_reset,
4194 /* 1x shared bus ops */
4195 static long tegra11_1xbus_round_updown(struct clk *c, unsigned long rate,
4199 unsigned long source_rate, round_rate;
4200 struct clk *new_parent;
4202 rate = max(rate, c->min_rate);
4204 new_parent = (rate <= c->u.periph.threshold) ?
4205 c->u.periph.pll_low : c->u.periph.pll_high;
4206 source_rate = clk_get_rate(new_parent);
4208 divider = clk_div71_get_divider(source_rate, rate, c->flags,
4209 up ? ROUND_DIVIDER_DOWN : ROUND_DIVIDER_UP);
4214 round_rate = source_rate * 2 / (divider + 2);
4216 if (round_rate > c->max_rate) {
4217 divider += c->flags & DIV_U71_INT ? 2 : 1;
4218 #if !DIVIDER_1_5_ALLOWED
4219 divider = max(2, divider);
4221 round_rate = source_rate * 2 / (divider + 2);
4224 if (new_parent == c->u.periph.pll_high) {
4225 /* Prevent oscillation across threshold */
4226 if (round_rate <= c->u.periph.threshold)
4227 round_rate = c->u.periph.threshold;
4232 static long tegra11_1xbus_round_rate(struct clk *c, unsigned long rate)
4234 return tegra11_1xbus_round_updown(c, rate, true);
4237 static int tegra11_1xbus_set_rate(struct clk *c, unsigned long rate)
4239 /* Compensate rate truncating during rounding */
4240 return tegra11_periph_clk_set_rate(c, rate + 1);
4243 static int tegra11_clk_1xbus_update(struct clk *c)
4246 struct clk *new_parent;
4247 unsigned long rate, old_rate;
4249 if (detach_shared_bus)
4252 rate = tegra11_clk_shared_bus_update(c, NULL, NULL, NULL);
4254 old_rate = clk_get_rate_locked(c);
4255 pr_debug("\n1xbus %s: rate %lu on parent %s: new request %lu\n",
4256 c->name, old_rate, c->parent->name, rate);
4257 if (rate == old_rate)
4260 if (!c->u.periph.min_div_low || !c->u.periph.min_div_high) {
4261 unsigned long r, m = c->max_rate;
4262 r = clk_get_rate(c->u.periph.pll_low);
4263 c->u.periph.min_div_low = DIV_ROUND_UP(r, m) * c->mul;
4264 r = clk_get_rate(c->u.periph.pll_high);
4265 c->u.periph.min_div_high = DIV_ROUND_UP(r, m) * c->mul;
4268 new_parent = (rate <= c->u.periph.threshold) ?
4269 c->u.periph.pll_low : c->u.periph.pll_high;
4272 * The transition procedure below is guaranteed to switch to the target
4273 * parent/rate without violation of max clock limits. It would attempt
4274 * to switch without dip in bus rate if it is possible, but this cannot
4275 * be guaranteed (example: switch from 408 MHz : 1 to 624 MHz : 2 with
4276 * maximum bus limit 408 MHz will be executed as 408 => 204 => 312 MHz,
4277 * and there is no way to avoid rate dip in this case).
4279 if (new_parent != c->parent) {
4280 int interim_div = 0;
4281 /* Switching to pll_high may over-clock bus if current divider
4282 is too small - increase divider to safe value */
4283 if ((new_parent == c->u.periph.pll_high) &&
4284 (c->div < c->u.periph.min_div_high))
4285 interim_div = c->u.periph.min_div_high;
4287 /* Switching to pll_low may dip down rate if current divider
4288 is too big - decrease divider as much as we can */
4289 if ((new_parent == c->u.periph.pll_low) &&
4290 (c->div > c->u.periph.min_div_low))
4291 interim_div = c->u.periph.min_div_low;
4294 u64 interim_rate = old_rate * c->div;
4295 do_div(interim_rate, interim_div);
4296 ret = clk_set_rate_locked(c, interim_rate);
4298 pr_err("Failed to set %s rate to %lu\n",
4299 c->name, (unsigned long)interim_rate);
4302 pr_debug("1xbus %s: rate %lu on parent %s\n", c->name,
4303 clk_get_rate_locked(c), c->parent->name);
4306 ret = clk_set_parent_locked(c, new_parent);
4308 pr_err("Failed to set %s parent %s\n",
4309 c->name, new_parent->name);
4313 old_rate = clk_get_rate_locked(c);
4314 pr_debug("1xbus %s: rate %lu on parent %s\n", c->name,
4315 old_rate, c->parent->name);
4316 if (rate == old_rate)
4320 ret = clk_set_rate_locked(c, rate);
4322 pr_err("Failed to set %s rate to %lu\n", c->name, rate);
4325 pr_debug("1xbus %s: rate %lu on parent %s\n", c->name,
4326 clk_get_rate_locked(c), c->parent->name);
4331 static struct clk_ops tegra_1xbus_clk_ops = {
4332 .init = &tegra11_periph_clk_init,
4333 .enable = &tegra11_periph_clk_enable,
4334 .disable = &tegra11_periph_clk_disable,
4335 .set_parent = &tegra11_periph_clk_set_parent,
4336 .set_rate = &tegra11_1xbus_set_rate,
4337 .round_rate = &tegra11_1xbus_round_rate,
4338 .reset = &tegra11_periph_clk_reset,
4339 .shared_bus_update = &tegra11_clk_1xbus_update,
4342 /* msenc clock propagation WAR for bug 1005168 */
4343 static int tegra11_msenc_clk_enable(struct clk *c)
4345 int ret = tegra11_periph_clk_enable(c);
4349 clk_writel(0, LVL2_CLK_GATE_OVRE);
4350 clk_writel(0x00400000, LVL2_CLK_GATE_OVRE);
4352 clk_writel(0, LVL2_CLK_GATE_OVRE);
4356 static struct clk_ops tegra_msenc_clk_ops = {
4357 .init = &tegra11_periph_clk_init,
4358 .enable = &tegra11_msenc_clk_enable,
4359 .disable = &tegra11_periph_clk_disable,
4360 .set_parent = &tegra11_periph_clk_set_parent,
4361 .set_rate = &tegra11_periph_clk_set_rate,
4362 .round_rate = &tegra11_periph_clk_round_rate,
4363 .reset = &tegra11_periph_clk_reset,
4365 /* Periph extended clock configuration ops */
4367 tegra11_vi_clk_cfg_ex(struct clk *c, enum tegra_clk_ex_param p, u32 setting)
4369 if (p == TEGRA_CLK_VI_INP_SEL) {
4370 u32 val = clk_readl(c->reg);
4371 val &= ~PERIPH_CLK_VI_SEL_EX_MASK;
4372 val |= (setting << PERIPH_CLK_VI_SEL_EX_SHIFT) &
4373 PERIPH_CLK_VI_SEL_EX_MASK;
4374 clk_writel(val, c->reg);
4380 static struct clk_ops tegra_vi_clk_ops = {
4381 .init = &tegra11_periph_clk_init,
4382 .enable = &tegra11_periph_clk_enable,
4383 .disable = &tegra11_periph_clk_disable,
4384 .set_parent = &tegra11_periph_clk_set_parent,
4385 .set_rate = &tegra11_periph_clk_set_rate,
4386 .round_rate = &tegra11_periph_clk_round_rate,
4387 .clk_cfg_ex = &tegra11_vi_clk_cfg_ex,
4388 .reset = &tegra11_periph_clk_reset,
4392 tegra11_nand_clk_cfg_ex(struct clk *c, enum tegra_clk_ex_param p, u32 setting)
4394 if (p == TEGRA_CLK_NAND_PAD_DIV2_ENB) {
4395 u32 val = clk_readl(c->reg);
4397 val |= PERIPH_CLK_NAND_DIV_EX_ENB;
4399 val &= ~PERIPH_CLK_NAND_DIV_EX_ENB;
4400 clk_writel(val, c->reg);
4406 static struct clk_ops tegra_nand_clk_ops = {
4407 .init = &tegra11_periph_clk_init,
4408 .enable = &tegra11_periph_clk_enable,
4409 .disable = &tegra11_periph_clk_disable,
4410 .set_parent = &tegra11_periph_clk_set_parent,
4411 .set_rate = &tegra11_periph_clk_set_rate,
4412 .round_rate = &tegra11_periph_clk_round_rate,
4413 .clk_cfg_ex = &tegra11_nand_clk_cfg_ex,
4414 .reset = &tegra11_periph_clk_reset,
4419 tegra11_dtv_clk_cfg_ex(struct clk *c, enum tegra_clk_ex_param p, u32 setting)
4421 if (p == TEGRA_CLK_DTV_INVERT) {
4422 u32 val = clk_readl(c->reg);
4424 val |= PERIPH_CLK_DTV_POLARITY_INV;
4426 val &= ~PERIPH_CLK_DTV_POLARITY_INV;
4427 clk_writel(val, c->reg);
4433 static struct clk_ops tegra_dtv_clk_ops = {
4434 .init = &tegra11_periph_clk_init,
4435 .enable = &tegra11_periph_clk_enable,
4436 .disable = &tegra11_periph_clk_disable,
4437 .set_parent = &tegra11_periph_clk_set_parent,
4438 .set_rate = &tegra11_periph_clk_set_rate,
4439 .round_rate = &tegra11_periph_clk_round_rate,
4440 .clk_cfg_ex = &tegra11_dtv_clk_cfg_ex,
4441 .reset = &tegra11_periph_clk_reset,
4444 static int tegra11_dsi_clk_set_parent(struct clk *c, struct clk *p)
4446 const struct clk_mux_sel *sel;
4447 struct clk *d = tegra_get_clock_by_name("pll_d");
4448 if (c->reg != d->reg)
4449 d = tegra_get_clock_by_name("pll_d2");
4451 pr_debug("%s: %s %s\n", __func__, c->name, p->name);
4453 for (sel = c->inputs; sel->input != NULL; sel++) {
4454 if (sel->input == p) {
4458 /* The DSI parent selection bit is in PLLD base
4459 register - can not do direct r-m-w, must be
4460 protected by PLLD lock */
4462 d, TEGRA_CLK_PLLD_MIPI_MUX_SEL, sel->value);
4464 if (c->refcnt && c->parent)
4465 clk_disable(c->parent);
4475 static struct clk_ops tegra_dsi_clk_ops = {
4476 .init = &tegra11_periph_clk_init,
4477 .enable = &tegra11_periph_clk_enable,
4478 .disable = &tegra11_periph_clk_disable,
4479 .set_parent = &tegra11_dsi_clk_set_parent,
4480 .set_rate = &tegra11_periph_clk_set_rate,
4481 .round_rate = &tegra11_periph_clk_round_rate,
4482 .reset = &tegra11_periph_clk_reset,
4485 /* xusb common clock gate - enabled on init and never disabled */
4486 static void tegra11_xusb_gate_clk_init(struct clk *c)
4488 tegra11_periph_clk_enable(c);
4491 static struct clk_ops tegra_xusb_gate_clk_ops = {
4492 .init = tegra11_xusb_gate_clk_init,
4495 /* pciex clock support only reset function */
4496 static struct clk_ops tegra_pciex_clk_ops = {
4497 .reset = tegra11_periph_clk_reset,
4500 /* Output clock ops */
4502 static DEFINE_SPINLOCK(clk_out_lock);
4504 static void tegra11_clk_out_init(struct clk *c)
4506 const struct clk_mux_sel *mux = 0;
4507 const struct clk_mux_sel *sel;
4508 u32 val = pmc_readl(c->reg);
4510 c->state = (val & (0x1 << c->u.periph.clk_num)) ? ON : OFF;
4514 for (sel = c->inputs; sel->input != NULL; sel++) {
4515 if (((val & periph_clk_source_mask(c)) >>
4516 periph_clk_source_shift(c)) == sel->value)
4520 c->parent = mux->input;
4523 static int tegra11_clk_out_enable(struct clk *c)
4526 unsigned long flags;
4528 pr_debug("%s on clock %s\n", __func__, c->name);
4530 spin_lock_irqsave(&clk_out_lock, flags);
4531 val = pmc_readl(c->reg);
4532 val |= (0x1 << c->u.periph.clk_num);
4533 pmc_writel(val, c->reg);
4534 spin_unlock_irqrestore(&clk_out_lock, flags);
4539 static void tegra11_clk_out_disable(struct clk *c)
4542 unsigned long flags;
4544 pr_debug("%s on clock %s\n", __func__, c->name);
4546 spin_lock_irqsave(&clk_out_lock, flags);
4547 val = pmc_readl(c->reg);
4548 val &= ~(0x1 << c->u.periph.clk_num);
4549 pmc_writel(val, c->reg);
4550 spin_unlock_irqrestore(&clk_out_lock, flags);
4553 static int tegra11_clk_out_set_parent(struct clk *c, struct clk *p)
4556 unsigned long flags;
4557 const struct clk_mux_sel *sel;
4559 pr_debug("%s: %s %s\n", __func__, c->name, p->name);
4561 for (sel = c->inputs; sel->input != NULL; sel++) {
4562 if (sel->input == p) {
4566 spin_lock_irqsave(&clk_out_lock, flags);
4567 val = pmc_readl(c->reg);
4568 val &= ~periph_clk_source_mask(c);
4569 val |= (sel->value << periph_clk_source_shift(c));
4570 pmc_writel(val, c->reg);
4571 spin_unlock_irqrestore(&clk_out_lock, flags);
4573 if (c->refcnt && c->parent)
4574 clk_disable(c->parent);
4583 static struct clk_ops tegra_clk_out_ops = {
4584 .init = &tegra11_clk_out_init,
4585 .enable = &tegra11_clk_out_enable,
4586 .disable = &tegra11_clk_out_disable,
4587 .set_parent = &tegra11_clk_out_set_parent,
4591 /* External memory controller clock ops */
4592 static void tegra11_emc_clk_init(struct clk *c)
4594 tegra11_periph_clk_init(c);
4595 tegra_emc_dram_type_init(c);
4598 static long tegra11_emc_clk_round_updown(struct clk *c, unsigned long rate,
4601 unsigned long new_rate = max(rate, c->min_rate);
4603 new_rate = tegra_emc_round_rate_updown(new_rate, up);
4604 if (IS_ERR_VALUE(new_rate))
4605 new_rate = c->max_rate;
4610 static long tegra11_emc_clk_round_rate(struct clk *c, unsigned long rate)
4612 return tegra11_emc_clk_round_updown(c, rate, true);
4615 static int tegra11_emc_clk_set_rate(struct clk *c, unsigned long rate)
4621 /* The tegra11x memory controller has an interlock with the clock
4622 * block that allows memory shadowed registers to be updated,
4623 * and then transfer them to the main registers at the same
4624 * time as the clock update without glitches. During clock change
4625 * operation both clock parent and divider may change simultaneously
4626 * to achieve requested rate. */
4627 p = tegra_emc_predict_parent(rate, &div_value);
4628 div_value += 2; /* emc has fractional DIV_U71 divider */
4629 if (IS_ERR_OR_NULL(p)) {
4630 pr_err("%s: Failed to predict emc parent for rate %lu\n",
4635 if (p == c->parent) {
4636 if (div_value == c->div)
4638 } else if (c->refcnt)
4641 ret = tegra_emc_set_rate(rate);
4645 if (p != c->parent) {
4646 if(c->refcnt && c->parent)
4647 clk_disable(c->parent);
4655 static int tegra11_clk_emc_bus_update(struct clk *bus)
4657 struct clk *p = NULL;
4658 unsigned long rate, old_rate, parent_rate, backup_rate;
4660 if (detach_shared_bus)
4663 rate = tegra11_clk_shared_bus_update(bus, NULL, NULL, NULL);
4665 old_rate = clk_get_rate_locked(bus);
4666 if (rate == old_rate)
4669 if (!tegra_emc_is_parent_ready(rate, &p, &parent_rate, &backup_rate)) {
4670 if (bus->parent == p) {
4671 /* need backup to re-lock current parent */
4673 if (IS_ERR_VALUE(backup_rate)) {
4674 pr_err("%s: No backup for %s rate %lu\n",
4675 __func__, bus->name, rate);
4679 /* set volatge for backup rate if going up */
4680 if (backup_rate > old_rate) {
4681 ret = tegra_dvfs_set_rate(bus, backup_rate);
4683 pr_err("%s: dvfs failed on %s rate %lu\n",
4684 __func__, bus->name, backup_rate);
4689 trace_clock_set_rate(bus->name, backup_rate, 0);
4690 ret = bus->ops->set_rate(bus, backup_rate);
4692 pr_err("%s: Failed to backup %s for rate %lu\n",
4693 __func__, bus->name, rate);
4696 clk_rate_change_notify(bus, backup_rate);
4699 pr_err("%s: %s has other than emc child\n",
4704 if (clk_set_rate(p, parent_rate)) {
4705 pr_err("%s: Failed to set %s rate %lu\n",
4706 __func__, p->name, parent_rate);
4711 return clk_set_rate_locked(bus, rate);
4714 static struct clk_ops tegra_emc_clk_ops = {
4715 .init = &tegra11_emc_clk_init,
4716 .enable = &tegra11_periph_clk_enable,
4717 .disable = &tegra11_periph_clk_disable,
4718 .set_rate = &tegra11_emc_clk_set_rate,
4719 .round_rate = &tegra11_emc_clk_round_rate,
4720 .round_rate_updown = &tegra11_emc_clk_round_updown,
4721 .reset = &tegra11_periph_clk_reset,
4722 .shared_bus_update = &tegra11_clk_emc_bus_update,
4725 /* Clock doubler ops (non-atomic shared register access) */
4726 static DEFINE_SPINLOCK(doubler_lock);
4728 static void tegra11_clk_double_init(struct clk *c)
4730 u32 val = clk_readl(c->reg);
4731 c->mul = val & (0x1 << c->reg_shift) ? 1 : 2;
4734 if (!(clk_readl(PERIPH_CLK_TO_ENB_REG(c)) & PERIPH_CLK_TO_BIT(c)))
4738 static int tegra11_clk_double_set_rate(struct clk *c, unsigned long rate)
4741 unsigned long parent_rate = clk_get_rate(c->parent);
4742 unsigned long flags;
4744 if (rate == parent_rate) {
4745 spin_lock_irqsave(&doubler_lock, flags);
4746 val = clk_readl(c->reg) | (0x1 << c->reg_shift);
4747 clk_writel(val, c->reg);
4750 spin_unlock_irqrestore(&doubler_lock, flags);
4752 } else if (rate == 2 * parent_rate) {
4753 spin_lock_irqsave(&doubler_lock, flags);
4754 val = clk_readl(c->reg) & (~(0x1 << c->reg_shift));
4755 clk_writel(val, c->reg);
4758 spin_unlock_irqrestore(&doubler_lock, flags);
4764 static struct clk_ops tegra_clk_double_ops = {
4765 .init = &tegra11_clk_double_init,
4766 .enable = &tegra11_periph_clk_enable,
4767 .disable = &tegra11_periph_clk_disable,
4768 .set_rate = &tegra11_clk_double_set_rate,
4771 /* Audio sync clock ops */
4772 static int tegra11_sync_source_set_rate(struct clk *c, unsigned long rate)
4778 static struct clk_ops tegra_sync_source_ops = {
4779 .set_rate = &tegra11_sync_source_set_rate,
4782 static void tegra11_audio_sync_clk_init(struct clk *c)
4785 const struct clk_mux_sel *sel;
4786 u32 val = clk_readl(c->reg);
4787 c->state = (val & AUDIO_SYNC_DISABLE_BIT) ? OFF : ON;
4788 source = val & AUDIO_SYNC_SOURCE_MASK;
4789 for (sel = c->inputs; sel->input != NULL; sel++)
4790 if (sel->value == source)
4792 BUG_ON(sel->input == NULL);
4793 c->parent = sel->input;
4796 static int tegra11_audio_sync_clk_enable(struct clk *c)
4798 u32 val = clk_readl(c->reg);
4799 clk_writel((val & (~AUDIO_SYNC_DISABLE_BIT)), c->reg);
4803 static void tegra11_audio_sync_clk_disable(struct clk *c)
4805 u32 val = clk_readl(c->reg);
4806 clk_writel((val | AUDIO_SYNC_DISABLE_BIT), c->reg);
4809 static int tegra11_audio_sync_clk_set_parent(struct clk *c, struct clk *p)
4812 const struct clk_mux_sel *sel;
4813 for (sel = c->inputs; sel->input != NULL; sel++) {
4814 if (sel->input == p) {
4815 val = clk_readl(c->reg);
4816 val &= ~AUDIO_SYNC_SOURCE_MASK;
4822 clk_writel(val, c->reg);
4824 if (c->refcnt && c->parent)
4825 clk_disable(c->parent);
4835 static struct clk_ops tegra_audio_sync_clk_ops = {
4836 .init = tegra11_audio_sync_clk_init,
4837 .enable = tegra11_audio_sync_clk_enable,
4838 .disable = tegra11_audio_sync_clk_disable,
4839 .set_parent = tegra11_audio_sync_clk_set_parent,
4845 * Some clocks require dynamic re-locking of source PLL in order to
4846 * achieve frequency scaling granularity that matches characterized
4847 * core voltage steps. The cbus clock creates a shared bus that
4848 * provides a virtual root for such clocks to hide and synchronize
4849 * parent PLL re-locking as well as backup operations.
4852 static void tegra11_clk_cbus_init(struct clk *c)
4858 static int tegra11_clk_cbus_enable(struct clk *c)
4863 /* select 5 steps below top rate as fine granularity region */
4864 #define CBUS_FINE_GRANULARITY 12000000 /* 12 MHz */
4865 #define CBUS_FINE_GRANULARITY_RANGE (5 * CBUS_FINE_GRANULARITY)
4867 static long tegra11_clk_cbus_round_updown(struct clk *c, unsigned long rate,
4874 c->min_rate = c->parent->min_rate;
4875 rate = max(rate, c->min_rate);
4879 /* update min now, since no dvfs table was available during init
4880 (skip placeholder entries set to 1 kHz) */
4882 for (i = 0; i < (c->dvfs->num_freqs - 1); i++) {
4883 if (c->dvfs->freqs[i] > 1 * c->dvfs->freqs_mult) {
4884 c->min_rate = c->dvfs->freqs[i];
4888 BUG_ON(!c->min_rate);
4890 rate = max(rate, c->min_rate);
4892 /* for top rates in fine granularity region don't clip to dvfs table */
4893 n = c->dvfs->num_freqs;
4894 if ((n >= 2) && (c->dvfs->millivolts[n-1] <= c->dvfs->max_millivolts) &&
4895 (rate > c->dvfs->freqs[n-2])) {
4896 unsigned long threshold = max(c->dvfs->freqs[n-1],
4897 c->dvfs->freqs[n-2] + CBUS_FINE_GRANULARITY_RANGE);
4898 threshold -= CBUS_FINE_GRANULARITY_RANGE;
4900 if (rate <= threshold)
4901 return up ? threshold : c->dvfs->freqs[n-2];
4903 rate = (up ? DIV_ROUND_UP(rate, CBUS_FINE_GRANULARITY) :
4904 rate / CBUS_FINE_GRANULARITY) * CBUS_FINE_GRANULARITY;
4905 rate = clamp(rate, threshold, c->dvfs->freqs[n-1]);
4909 /* clip rate to dvfs table steps */
4910 for (i = 0; ; i++) {
4911 unsigned long f = c->dvfs->freqs[i];
4912 int mv = c->dvfs->millivolts[i];
4913 if ((f >= rate) || (mv >= c->dvfs->max_millivolts) ||
4914 ((i + 1) >= c->dvfs->num_freqs)) {
4915 if (!up && i && (f > rate))
4920 return c->dvfs->freqs[i];
4923 static long tegra11_clk_cbus_round_rate(struct clk *c, unsigned long rate)
4925 return tegra11_clk_cbus_round_updown(c, rate, true);
4928 static int cbus_switch_one(struct clk *c, struct clk *p, u32 div, bool abort)
4932 /* set new divider if it is bigger than the current one */
4933 if (c->div < c->mul * div) {
4934 ret = clk_set_div(c, div);
4936 pr_err("%s: failed to set %s clock divider %u: %d\n",
4937 __func__, c->name, div, ret);
4943 if (c->parent != p) {
4944 ret = clk_set_parent(c, p);
4946 pr_err("%s: failed to set %s clock parent %s: %d\n",
4947 __func__, c->name, p->name, ret);
4953 /* set new divider if it is smaller than the current one */
4954 if (c->div > c->mul * div) {
4955 ret = clk_set_div(c, div);
4957 pr_err("%s: failed to set %s clock divider %u: %d\n",
4958 __func__, c->name, div, ret);
4964 static int cbus_backup(struct clk *c)
4969 list_for_each_entry(user, &c->shared_bus_list,
4970 u.shared_bus_user.node) {
4971 struct clk *client = user->u.shared_bus_user.client;
4972 if (client && (client->state == ON) &&
4973 (client->parent == c->parent)) {
4974 ret = cbus_switch_one(client,
4975 c->shared_bus_backup.input,
4976 c->shared_bus_backup.value *
4985 static int cbus_dvfs_set_rate(struct clk *c, unsigned long rate)
4990 list_for_each_entry(user, &c->shared_bus_list,
4991 u.shared_bus_user.node) {
4992 struct clk *client = user->u.shared_bus_user.client;
4993 if (client && client->refcnt && (client->parent == c->parent)) {
4994 ret = tegra_dvfs_set_rate(c, rate);
5002 static void cbus_restore(struct clk *c)
5006 list_for_each_entry(user, &c->shared_bus_list,
5007 u.shared_bus_user.node) {
5008 if (user->u.shared_bus_user.client)
5009 cbus_switch_one(user->u.shared_bus_user.client,
5010 c->parent, c->div * user->div, false);
5014 static int get_next_backup_div(struct clk *c, unsigned long rate)
5017 unsigned long backup_rate = clk_get_rate(c->shared_bus_backup.input);
5019 rate = max(rate, clk_get_rate_locked(c));
5020 rate = rate - (rate >> 2); /* 25% margin for backup rate */
5021 if ((u64)rate * div < backup_rate)
5022 div = DIV_ROUND_UP(backup_rate, rate);
5028 static int tegra11_clk_cbus_set_rate(struct clk *c, unsigned long rate)
5036 ret = clk_enable(c->parent);
5038 pr_err("%s: failed to enable %s clock: %d\n",
5039 __func__, c->name, ret);
5043 dramp = tegra11_is_dyn_ramp(c->parent, rate * c->div, false);
5045 c->shared_bus_backup.value = get_next_backup_div(c, rate);
5046 ret = cbus_backup(c);
5051 ret = clk_set_rate(c->parent, rate * c->div);
5053 pr_err("%s: failed to set %s clock rate %lu: %d\n",
5054 __func__, c->name, rate, ret);
5058 /* Safe voltage setting is taken care of by cbus clock dvfs; the call
5059 * below only records requirements for each enabled client.
5062 ret = cbus_dvfs_set_rate(c, rate);
5067 clk_disable(c->parent);
5071 static inline void cbus_move_enabled_user(
5072 struct clk *user, struct clk *dst, struct clk *src)
5075 list_move_tail(&user->u.shared_bus_user.node, &dst->shared_bus_list);
5077 clk_reparent(user, dst);
5080 #ifdef CONFIG_TEGRA_DYNAMIC_CBUS
5081 static int tegra11_clk_cbus_update(struct clk *bus)
5084 struct clk *slow = NULL;
5085 struct clk *top = NULL;
5087 unsigned long old_rate;
5088 unsigned long ceiling;
5090 if (detach_shared_bus)
5093 rate = tegra11_clk_shared_bus_update(bus, &top, &slow, &ceiling);
5095 /* use dvfs table of the slowest enabled client as cbus dvfs table */
5096 if (bus->dvfs && slow && (slow != bus->u.cbus.slow_user)) {
5098 unsigned long *dest = &bus->dvfs->freqs[0];
5099 unsigned long *src =
5100 &slow->u.shared_bus_user.client->dvfs->freqs[0];
5102 for (i = 0; i < bus->dvfs->num_freqs; i++)
5103 dest[i] = src[i] * slow->div;
5105 memcpy(dest, src, sizeof(*dest) * bus->dvfs->num_freqs);
5108 /* update bus state variables and rate */
5109 bus->u.cbus.slow_user = slow;
5110 bus->u.cbus.top_user = top;
5112 rate = tegra11_clk_cap_shared_bus(bus, rate, ceiling);
5113 mv = tegra_dvfs_predict_millivolts(bus, rate);
5114 if (IS_ERR_VALUE(mv))
5118 mv -= bus->dvfs->cur_millivolts;
5119 if (bus->refcnt && (mv > 0)) {
5120 ret = tegra_dvfs_set_rate(bus, rate);
5126 old_rate = clk_get_rate_locked(bus);
5127 if (IS_ENABLED(CONFIG_TEGRA_MIGRATE_CBUS_USERS) || (old_rate != rate)) {
5128 ret = bus->ops->set_rate(bus, rate);
5134 if (bus->refcnt && (mv <= 0)) {
5135 ret = tegra_dvfs_set_rate(bus, rate);
5141 clk_rate_change_notify(bus, rate);
5145 static int tegra11_clk_cbus_update(struct clk *bus)
5147 unsigned long rate, old_rate;
5149 if (detach_shared_bus)
5152 rate = tegra11_clk_shared_bus_update(bus, NULL, NULL, NULL);
5154 old_rate = clk_get_rate_locked(bus);
5155 if (rate == old_rate)
5158 return clk_set_rate_locked(bus, rate);
5162 static int tegra11_clk_cbus_migrate_users(struct clk *user)
5164 #ifdef CONFIG_TEGRA_MIGRATE_CBUS_USERS
5165 struct clk *src_bus, *dst_bus, *top_user, *c;
5166 struct list_head *pos, *n;
5168 if (!user->u.shared_bus_user.client || !user->inputs)
5171 /* Dual cbus on Tegra11 */
5172 src_bus = user->inputs[0].input;
5173 dst_bus = user->inputs[1].input;
5175 if (!src_bus->u.cbus.top_user && !dst_bus->u.cbus.top_user)
5178 /* Make sure top user on the source bus is requesting highest rate */
5179 if (!src_bus->u.cbus.top_user || (dst_bus->u.cbus.top_user &&
5180 bus_user_request_is_lower(src_bus->u.cbus.top_user,
5181 dst_bus->u.cbus.top_user)))
5182 swap(src_bus, dst_bus);
5184 /* If top user is the slow one on its own (source) bus, do nothing */
5185 top_user = src_bus->u.cbus.top_user;
5186 BUG_ON(!top_user->u.shared_bus_user.client);
5187 if (!bus_user_is_slower(src_bus->u.cbus.slow_user, top_user))
5190 /* If source bus top user is slower than all users on destination bus,
5191 move top user; otherwise move all users slower than the top one */
5192 if (!dst_bus->u.cbus.slow_user ||
5193 !bus_user_is_slower(dst_bus->u.cbus.slow_user, top_user)) {
5194 cbus_move_enabled_user(top_user, dst_bus, src_bus);
5196 list_for_each_safe(pos, n, &src_bus->shared_bus_list) {
5197 c = list_entry(pos, struct clk, u.shared_bus_user.node);
5198 if (c->u.shared_bus_user.enabled &&
5199 c->u.shared_bus_user.client &&
5200 bus_user_is_slower(c, top_user))
5201 cbus_move_enabled_user(c, dst_bus, src_bus);
5205 /* Update destination bus 1st (move clients), then source */
5206 tegra_clk_shared_bus_update(dst_bus);
5207 tegra_clk_shared_bus_update(src_bus);
5212 static struct clk_ops tegra_clk_cbus_ops = {
5213 .init = tegra11_clk_cbus_init,
5214 .enable = tegra11_clk_cbus_enable,
5215 .set_rate = tegra11_clk_cbus_set_rate,
5216 .round_rate = tegra11_clk_cbus_round_rate,
5217 .round_rate_updown = tegra11_clk_cbus_round_updown,
5218 .shared_bus_update = tegra11_clk_cbus_update,
5221 /* shared bus ops */
5223 * Some clocks may have multiple downstream users that need to request a
5224 * higher clock rate. Shared bus clocks provide a unique shared_bus_user
5225 * clock to each user. The frequency of the bus is set to the highest
5226 * enabled shared_bus_user clock, with a minimum value set by the
5229 * Optionally shared bus may support users migration. Since shared bus and
5230 * its * children (users) have reversed rate relations: user rates determine
5231 * bus rate, * switching user from one parent/bus to another may change rates
5232 * of both parents. Therefore we need a cross-bus lock on top of individual
5233 * user and bus locks. For now, limit bus switch support to cbus only if
5234 * CONFIG_TEGRA_MIGRATE_CBUS_USERS is set.
5237 static unsigned long tegra11_clk_shared_bus_update(struct clk *bus,
5238 struct clk **bus_top, struct clk **bus_slow, unsigned long *rate_cap)
5241 struct clk *slow = NULL;
5242 struct clk *top = NULL;
5244 unsigned long override_rate = 0;
5245 unsigned long top_rate = 0;
5246 unsigned long rate = bus->min_rate;
5247 unsigned long bw = 0;
5248 unsigned long iso_bw = 0;
5249 unsigned long ceiling = bus->max_rate;
5250 unsigned long ceiling_but_iso = bus->max_rate;
5251 u32 usage_flags = 0;
5253 list_for_each_entry(c, &bus->shared_bus_list,
5254 u.shared_bus_user.node) {
5256 * Ignore requests from disabled floor and bw users, and from
5257 * auto-users riding the bus. Always honor ceiling users, even
5258 * if they are disabled - we do not want to keep enabled parent
5259 * bus just because ceiling is set.
5261 if (c->u.shared_bus_user.enabled ||
5262 (c->u.shared_bus_user.mode == SHARED_CEILING) ||
5263 (c->u.shared_bus_user.mode == SHARED_CEILING_BUT_ISO)) {
5264 unsigned long request_rate = c->u.shared_bus_user.rate *
5266 usage_flags |= c->u.shared_bus_user.usage_flag;
5268 switch (c->u.shared_bus_user.mode) {
5270 iso_bw += request_rate;
5271 if (iso_bw > bus->max_rate)
5272 iso_bw = bus->max_rate;
5276 if (bw > bus->max_rate)
5279 case SHARED_CEILING_BUT_ISO:
5281 min(request_rate, ceiling_but_iso);
5283 case SHARED_CEILING:
5284 ceiling = min(request_rate, ceiling);
5286 case SHARED_OVERRIDE:
5287 if (override_rate == 0)
5288 override_rate = request_rate;
5294 rate = max(request_rate, rate);
5295 if (c->u.shared_bus_user.client
5297 if (top_rate < request_rate) {
5298 top_rate = request_rate;
5300 } else if ((top_rate == request_rate) &&
5301 bus_user_is_slower(c, top)) {
5306 if (c->u.shared_bus_user.client &&
5307 (!slow || bus_user_is_slower(c, slow)))
5312 if (bus->flags & PERIPH_EMC_ENB)
5313 bw = tegra_emc_apply_efficiency(
5314 bw, iso_bw, bus->max_rate, usage_flags, NULL);
5316 rate = override_rate ? : max(rate, bw);
5317 ceiling = min(ceiling, ceiling_but_iso);
5318 ceiling = override_rate ? bus->max_rate : ceiling;
5320 if (bus_top && bus_slow && rate_cap) {
5321 /* If dynamic bus dvfs table, let the caller to complete
5322 rounding and aggregation */
5325 *rate_cap = ceiling;
5327 /* If satic bus dvfs table, complete rounding and aggregation */
5328 rate = tegra11_clk_cap_shared_bus(bus, rate, ceiling);
5334 static unsigned long tegra11_clk_cap_shared_bus(struct clk *bus,
5335 unsigned long rate, unsigned long ceiling)
5337 if (bus->ops && bus->ops->round_rate_updown)
5338 ceiling = bus->ops->round_rate_updown(bus, ceiling, false);
5340 rate = min(rate, ceiling);
5342 if (bus->ops && bus->ops->round_rate)
5343 rate = bus->ops->round_rate(bus, rate);
5348 static int tegra_clk_shared_bus_migrate_users(struct clk *user)
5350 if (detach_shared_bus)
5353 /* Only cbus migration is supported */
5354 if (user->flags & PERIPH_ON_CBUS)
5355 return tegra11_clk_cbus_migrate_users(user);
5359 static void tegra_clk_shared_bus_user_init(struct clk *c)
5361 c->max_rate = c->parent->max_rate;
5362 c->u.shared_bus_user.rate = c->parent->max_rate;
5366 if ((c->u.shared_bus_user.mode == SHARED_CEILING) ||
5367 (c->u.shared_bus_user.mode == SHARED_CEILING_BUT_ISO)) {
5372 if (c->u.shared_bus_user.client_id) {
5373 c->u.shared_bus_user.client =
5374 tegra_get_clock_by_name(c->u.shared_bus_user.client_id);
5375 if (!c->u.shared_bus_user.client) {
5376 pr_err("%s: could not find clk %s\n", __func__,
5377 c->u.shared_bus_user.client_id);
5380 c->u.shared_bus_user.client->flags |=
5381 c->parent->flags & PERIPH_ON_CBUS;
5382 c->flags |= c->parent->flags & PERIPH_ON_CBUS;
5383 c->div = c->u.shared_bus_user.client_div ? : 1;
5387 list_add_tail(&c->u.shared_bus_user.node,
5388 &c->parent->shared_bus_list);
5391 static int tegra_clk_shared_bus_user_set_parent(struct clk *c, struct clk *p)
5394 const struct clk_mux_sel *sel;
5396 if (detach_shared_bus)
5402 if (!(c->inputs && c->cross_clk_mutex && clk_cansleep(c)))
5405 for (sel = c->inputs; sel->input != NULL; sel++) {
5406 if (sel->input == p)
5415 list_move_tail(&c->u.shared_bus_user.node, &p->shared_bus_list);
5416 ret = tegra_clk_shared_bus_update(p);
5418 list_move_tail(&c->u.shared_bus_user.node,
5419 &c->parent->shared_bus_list);
5420 tegra_clk_shared_bus_update(c->parent);
5425 tegra_clk_shared_bus_update(c->parent);
5428 clk_disable(c->parent);
5435 static int tegra_clk_shared_bus_user_set_rate(struct clk *c, unsigned long rate)
5439 c->u.shared_bus_user.rate = rate;
5440 ret = tegra_clk_shared_bus_update(c->parent);
5442 if (!ret && c->cross_clk_mutex && clk_cansleep(c))
5443 tegra_clk_shared_bus_migrate_users(c);
5448 static long tegra_clk_shared_bus_user_round_rate(
5449 struct clk *c, unsigned long rate)
5451 /* Defer rounding requests until aggregated. BW users must not be
5452 rounded at all, others just clipped to bus range (some clients
5453 may use round api to find limits) */
5454 if ((c->u.shared_bus_user.mode != SHARED_BW) &&
5455 (c->u.shared_bus_user.mode != SHARED_ISO_BW)) {
5459 if (rate > c->parent->max_rate)
5460 rate = c->parent->max_rate;
5461 else if (rate < c->parent->min_rate)
5462 rate = c->parent->min_rate;
5470 static int tegra_clk_shared_bus_user_enable(struct clk *c)
5474 c->u.shared_bus_user.enabled = true;
5475 ret = tegra_clk_shared_bus_update(c->parent);
5476 if (!ret && c->u.shared_bus_user.client)
5477 ret = clk_enable(c->u.shared_bus_user.client);
5479 if (!ret && c->cross_clk_mutex && clk_cansleep(c))
5480 tegra_clk_shared_bus_migrate_users(c);
5485 static void tegra_clk_shared_bus_user_disable(struct clk *c)
5487 if (c->u.shared_bus_user.client)
5488 clk_disable(c->u.shared_bus_user.client);
5489 c->u.shared_bus_user.enabled = false;
5490 tegra_clk_shared_bus_update(c->parent);
5492 if (c->cross_clk_mutex && clk_cansleep(c))
5493 tegra_clk_shared_bus_migrate_users(c);
5496 static void tegra_clk_shared_bus_user_reset(struct clk *c, bool assert)
5498 if (c->u.shared_bus_user.client) {
5499 if (c->u.shared_bus_user.client->ops &&
5500 c->u.shared_bus_user.client->ops->reset)
5501 c->u.shared_bus_user.client->ops->reset(
5502 c->u.shared_bus_user.client, assert);
5506 static struct clk_ops tegra_clk_shared_bus_user_ops = {
5507 .init = tegra_clk_shared_bus_user_init,
5508 .enable = tegra_clk_shared_bus_user_enable,
5509 .disable = tegra_clk_shared_bus_user_disable,
5510 .set_parent = tegra_clk_shared_bus_user_set_parent,
5511 .set_rate = tegra_clk_shared_bus_user_set_rate,
5512 .round_rate = tegra_clk_shared_bus_user_round_rate,
5513 .reset = tegra_clk_shared_bus_user_reset,
5516 /* coupled gate ops */
5518 * Some clocks may have common enable/disable control, but run at different
5519 * rates, and have different dvfs tables. Coupled gate clock synchronize
5520 * enable/disable operations for such clocks.
5523 static int tegra11_clk_coupled_gate_enable(struct clk *c)
5526 const struct clk_mux_sel *sel;
5529 pr_debug("%s on clock %s\n", __func__, c->name);
5531 for (sel = c->inputs; sel->input != NULL; sel++) {
5532 if (sel->input == c->parent)
5535 ret = clk_enable(sel->input);
5537 while(sel != c->inputs) {
5539 if (sel->input == c->parent)
5541 clk_disable(sel->input);
5547 return tegra11_periph_clk_enable(c);
5550 static void tegra11_clk_coupled_gate_disable(struct clk *c)
5552 const struct clk_mux_sel *sel;
5555 pr_debug("%s on clock %s\n", __func__, c->name);
5557 tegra11_periph_clk_disable(c);
5559 if (!c->refcnt) /* happens only on boot clean-up: don't propagate */
5562 for (sel = c->inputs; sel->input != NULL; sel++) {
5563 if (sel->input == c->parent)
5566 if (sel->input->set) /* enforce coupling after boot only */
5567 clk_disable(sel->input);
5571 static struct clk_ops tegra_clk_coupled_gate_ops = {
5572 .init = tegra11_periph_clk_init,
5573 .enable = tegra11_clk_coupled_gate_enable,
5574 .disable = tegra11_clk_coupled_gate_disable,
5575 .reset = &tegra11_periph_clk_reset,
5579 /* Clock definitions */
5580 static struct clk tegra_clk_32k = {
5587 static struct clk tegra_clk_m = {
5589 .flags = ENABLE_ON_INIT,
5590 .ops = &tegra_clk_m_ops,
5593 .max_rate = 48000000,
5596 static struct clk tegra_clk_m_div2 = {
5597 .name = "clk_m_div2",
5598 .ops = &tegra_clk_m_div_ops,
5599 .parent = &tegra_clk_m,
5603 .max_rate = 24000000,
5606 static struct clk tegra_clk_m_div4 = {
5607 .name = "clk_m_div4",
5608 .ops = &tegra_clk_m_div_ops,
5609 .parent = &tegra_clk_m,
5613 .max_rate = 12000000,
5616 static struct clk tegra_pll_ref = {
5618 .flags = ENABLE_ON_INIT,
5619 .ops = &tegra_pll_ref_ops,
5620 .parent = &tegra_clk_m,
5621 .max_rate = 26000000,
5624 static struct clk_pll_freq_table tegra_pll_c_freq_table[] = {
5625 { 12000000, 624000000, 104, 1, 2},
5626 { 12000000, 600000000, 100, 1, 2},
5627 { 13000000, 600000000, 92, 1, 2}, /* actual: 598.0 MHz */
5628 { 16800000, 600000000, 71, 1, 2}, /* actual: 596.4 MHz */
5629 { 19200000, 600000000, 62, 1, 2}, /* actual: 595.2 MHz */
5630 { 26000000, 600000000, 92, 2, 2}, /* actual: 598.0 MHz */
5631 { 0, 0, 0, 0, 0, 0 },
5634 static struct clk tegra_pll_c = {
5636 .ops = &tegra_pllxc_ops,
5638 .parent = &tegra_pll_ref,
5639 .max_rate = 1400000000,
5641 .input_min = 12000000,
5642 .input_max = 800000000,
5644 .cf_max = 19200000, /* s/w policy, h/w capability 50 MHz */
5645 .vco_min = 600000000,
5646 .vco_max = 1400000000,
5647 .freq_table = tegra_pll_c_freq_table,
5649 .misc1 = 0x88 - 0x80,
5650 .round_p_to_pdiv = pllxc_round_p_to_pdiv,
5654 static struct clk tegra_pll_c_out1 = {
5655 .name = "pll_c_out1",
5656 .ops = &tegra_pll_div_ops,
5657 #ifdef CONFIG_TEGRA_DUAL_CBUS
5658 .flags = DIV_U71 | DIV_U71_INT,
5660 .flags = DIV_U71 | DIV_U71_INT | PERIPH_ON_CBUS,
5662 .parent = &tegra_pll_c,
5665 .max_rate = 700000000,
5668 static struct clk_pll_freq_table tegra_pll_cx_freq_table[] = {
5669 { 12000000, 600000000, 100, 1, 2},
5670 { 13000000, 600000000, 92, 1, 2}, /* actual: 598.0 MHz */
5671 { 16800000, 600000000, 71, 1, 2}, /* actual: 596.4 MHz */
5672 { 19200000, 600000000, 62, 1, 2}, /* actual: 595.2 MHz */
5673 { 26000000, 600000000, 92, 2, 2}, /* actual: 598.0 MHz */
5674 { 0, 0, 0, 0, 0, 0 },
5677 static struct clk tegra_pll_c2 = {
5679 .ops = &tegra_pllcx_ops,
5680 .flags = PLL_ALT_MISC_REG,
5682 .parent = &tegra_pll_ref,
5683 .max_rate = 1200000000,
5685 .input_min = 12000000,
5686 .input_max = 48000000,
5689 .vco_min = 624000000,
5690 .vco_max = 1248000000,
5691 .freq_table = tegra_pll_cx_freq_table,
5693 .misc1 = 0x4f0 - 0x4e8,
5694 .round_p_to_pdiv = pllcx_round_p_to_pdiv,
5698 static struct clk tegra_pll_c3 = {
5700 .ops = &tegra_pllcx_ops,
5701 .flags = PLL_ALT_MISC_REG,
5703 .parent = &tegra_pll_ref,
5704 .max_rate = 1200000000,
5706 .input_min = 12000000,
5707 .input_max = 48000000,
5710 .vco_min = 624000000,
5711 .vco_max = 1248000000,
5712 .freq_table = tegra_pll_cx_freq_table,
5714 .misc1 = 0x504 - 0x4fc,
5715 .round_p_to_pdiv = pllcx_round_p_to_pdiv,
5719 static struct clk_pll_freq_table tegra_pll_m_freq_table[] = {
5720 { 12000000, 800000000, 66, 1, 1}, /* actual: 792.0 MHz */
5721 { 13000000, 800000000, 61, 1, 1}, /* actual: 793.0 MHz */
5722 { 16800000, 800000000, 47, 1, 1}, /* actual: 789.6 MHz */
5723 { 19200000, 800000000, 41, 1, 1}, /* actual: 787.2 MHz */
5724 { 26000000, 800000000, 61, 2, 1}, /* actual: 793.0 MHz */
5725 { 0, 0, 0, 0, 0, 0 },
5728 static struct clk tegra_pll_m = {
5731 .ops = &tegra_pllm_ops,
5733 .parent = &tegra_pll_ref,
5734 .max_rate = 1066000000,
5736 .input_min = 12000000,
5737 .input_max = 500000000,
5739 .cf_max = 19200000, /* s/w policy, h/w capability 50 MHz */
5740 .vco_min = 400000000,
5741 .vco_max = 1066000000,
5742 .freq_table = tegra_pll_m_freq_table,
5744 .misc1 = 0x98 - 0x90,
5745 .round_p_to_pdiv = pllm_round_p_to_pdiv,
5749 static struct clk tegra_pll_m_out1 = {
5750 .name = "pll_m_out1",
5751 .ops = &tegra_pll_div_ops,
5752 .flags = DIV_U71 | DIV_U71_INT,
5753 .parent = &tegra_pll_m,
5756 .max_rate = 1066000000,
5759 static struct clk_pll_freq_table tegra_pll_p_freq_table[] = {
5760 { 12000000, 216000000, 432, 12, 2, 8},
5761 { 13000000, 216000000, 432, 13, 2, 8},
5762 { 16800000, 216000000, 360, 14, 2, 8},
5763 { 19200000, 216000000, 360, 16, 2, 8},
5764 { 26000000, 216000000, 432, 26, 2, 8},
5765 { 0, 0, 0, 0, 0, 0 },
5768 static struct clk tegra_pll_p = {
5770 .flags = ENABLE_ON_INIT | PLL_FIXED | PLL_HAS_CPCON,
5771 .ops = &tegra_pllp_ops,
5773 .parent = &tegra_pll_ref,
5774 .max_rate = 432000000,
5776 .input_min = 2000000,
5777 .input_max = 31000000,
5780 .vco_min = 200000000,
5781 .vco_max = 700000000,
5782 .freq_table = tegra_pll_p_freq_table,
5787 static struct clk tegra_pll_p_out1 = {
5788 .name = "pll_p_out1",
5789 .ops = &tegra_pll_div_ops,
5790 .flags = DIV_U71 | DIV_U71_FIXED,
5791 .parent = &tegra_pll_p,
5794 .max_rate = 432000000,
5797 static struct clk tegra_pll_p_out2 = {
5798 .name = "pll_p_out2",
5799 .ops = &tegra_pll_div_ops,
5800 .flags = DIV_U71 | DIV_U71_FIXED | DIV_U71_INT,
5801 .parent = &tegra_pll_p,
5804 .max_rate = 432000000,
5807 static struct clk tegra_pll_p_out3 = {
5808 .name = "pll_p_out3",
5809 .ops = &tegra_pll_div_ops,
5810 .flags = DIV_U71 | DIV_U71_FIXED,
5811 .parent = &tegra_pll_p,
5814 .max_rate = 432000000,
5817 static struct clk tegra_pll_p_out4 = {
5818 .name = "pll_p_out4",
5819 .ops = &tegra_pll_div_ops,
5820 .flags = DIV_U71 | DIV_U71_FIXED,
5821 .parent = &tegra_pll_p,
5824 .max_rate = 432000000,
5827 static struct clk_pll_freq_table tegra_pll_a_freq_table[] = {
5828 { 9600000, 282240000, 147, 5, 1, 4},
5829 { 9600000, 368640000, 192, 5, 1, 4},
5830 { 9600000, 240000000, 200, 8, 1, 8},
5832 { 28800000, 282240000, 245, 25, 1, 8},
5833 { 28800000, 368640000, 320, 25, 1, 8},
5834 { 28800000, 240000000, 200, 24, 1, 8},
5835 { 0, 0, 0, 0, 0, 0 },
5838 static struct clk tegra_pll_a = {
5840 .flags = PLL_HAS_CPCON,
5841 .ops = &tegra_pll_ops,
5843 .parent = &tegra_pll_p_out1,
5844 .max_rate = 700000000,
5846 .input_min = 2000000,
5847 .input_max = 31000000,
5850 .vco_min = 200000000,
5851 .vco_max = 700000000,
5852 .freq_table = tegra_pll_a_freq_table,
5857 static struct clk tegra_pll_a_out0 = {
5858 .name = "pll_a_out0",
5859 .ops = &tegra_pll_div_ops,
5861 .parent = &tegra_pll_a,
5864 .max_rate = 100000000,
5867 static struct clk_pll_freq_table tegra_pll_d_freq_table[] = {
5868 { 12000000, 216000000, 864, 12, 4, 12},
5869 { 13000000, 216000000, 864, 13, 4, 12},
5870 { 16800000, 216000000, 720, 14, 4, 12},
5871 { 19200000, 216000000, 720, 16, 4, 12},
5872 { 26000000, 216000000, 864, 26, 4, 12},
5874 { 12000000, 594000000, 99, 1, 2, 15},
5875 { 13000000, 594000000, 594, 13, 1, 12},
5876 { 16800000, 594000000, 495, 14, 1, 12},
5877 { 19200000, 594000000, 495, 16, 1, 12},
5878 { 26000000, 594000000, 594, 26, 1, 12},
5880 { 12000000, 1000000000, 1000, 12, 1, 12},
5881 { 13000000, 1000000000, 1000, 13, 1, 12},
5882 { 19200000, 1000000000, 625, 12, 1, 12},
5883 { 26000000, 1000000000, 1000, 26, 1, 12},
5885 { 0, 0, 0, 0, 0, 0 },
5888 static struct clk tegra_pll_d = {
5890 .flags = PLL_HAS_CPCON | PLLD,
5891 .ops = &tegra_plld_ops,
5893 .parent = &tegra_pll_ref,
5894 .max_rate = 1000000000,
5896 .input_min = 2000000,
5897 .input_max = 40000000,
5900 .vco_min = 500000000,
5901 .vco_max = 1000000000,
5902 .freq_table = tegra_pll_d_freq_table,
5907 static struct clk tegra_pll_d_out0 = {
5908 .name = "pll_d_out0",
5909 .ops = &tegra_pll_div_ops,
5910 .flags = DIV_2 | PLLD,
5911 .parent = &tegra_pll_d,
5912 .max_rate = 500000000,
5915 static struct clk tegra_pll_d2 = {
5917 .flags = PLL_HAS_CPCON | PLL_ALT_MISC_REG | PLLD,
5918 .ops = &tegra_plld_ops,
5920 .parent = &tegra_pll_ref,
5921 .max_rate = 1000000000,
5923 .input_min = 2000000,
5924 .input_max = 40000000,
5927 .vco_min = 500000000,
5928 .vco_max = 1000000000,
5929 .freq_table = tegra_pll_d_freq_table,
5934 static struct clk tegra_pll_d2_out0 = {
5935 .name = "pll_d2_out0",
5936 .ops = &tegra_pll_div_ops,
5937 .flags = DIV_2 | PLLD,
5938 .parent = &tegra_pll_d2,
5939 .max_rate = 500000000,
5942 static struct clk_pll_freq_table tegra_pll_u_freq_table[] = {
5943 { 12000000, 480000000, 960, 12, 2, 12},
5944 { 13000000, 480000000, 960, 13, 2, 12},
5945 { 16800000, 480000000, 400, 7, 2, 5},
5946 { 19200000, 480000000, 200, 4, 2, 3},
5947 { 26000000, 480000000, 960, 26, 2, 12},
5948 { 0, 0, 0, 0, 0, 0 },
5951 static struct clk tegra_pll_u = {
5953 .flags = PLL_HAS_CPCON | PLLU,
5954 .ops = &tegra_pll_ops,
5956 .parent = &tegra_pll_ref,
5957 .max_rate = 480000000,
5959 .input_min = 2000000,
5960 .input_max = 40000000,
5963 .vco_min = 480000000,
5964 .vco_max = 960000000,
5965 .freq_table = tegra_pll_u_freq_table,
5967 .cpcon_default = 12,
5971 static struct clk tegra_pll_u_480M = {
5972 .name = "pll_u_480M",
5974 .ops = &tegra_pll_div_ops,
5977 .parent = &tegra_pll_u,
5980 .max_rate = 480000000,
5983 static struct clk tegra_pll_u_60M = {
5984 .name = "pll_u_60M",
5986 .ops = &tegra_pll_div_ops,
5989 .parent = &tegra_pll_u,
5992 .max_rate = 60000000,
5995 static struct clk tegra_pll_u_48M = {
5996 .name = "pll_u_48M",
5998 .ops = &tegra_pll_div_ops,
6001 .parent = &tegra_pll_u,
6004 .max_rate = 48000000,
6007 static struct clk tegra_pll_u_12M = {
6008 .name = "pll_u_12M",
6010 .ops = &tegra_pll_div_ops,
6013 .parent = &tegra_pll_u,
6016 .max_rate = 12000000,
6019 static struct clk_pll_freq_table tegra_pll_x_freq_table[] = {
6021 { 12000000, 1000000000, 83, 1, 1}, /* actual: 996.0 MHz */
6022 { 13000000, 1000000000, 76, 1, 1}, /* actual: 988.0 MHz */
6023 { 16800000, 1000000000, 59, 1, 1}, /* actual: 991.2 MHz */
6024 { 19200000, 1000000000, 52, 1, 1}, /* actual: 998.4 MHz */
6025 { 26000000, 1000000000, 76, 2, 1}, /* actual: 988.0 MHz */
6027 { 0, 0, 0, 0, 0, 0 },
6030 static struct clk tegra_pll_x = {
6032 .flags = PLL_ALT_MISC_REG | PLLX,
6033 .ops = &tegra_pllxc_ops,
6035 .parent = &tegra_pll_ref,
6036 .max_rate = 1800000000,
6038 .input_min = 12000000,
6039 .input_max = 800000000,
6041 .cf_max = 19200000, /* s/w policy, h/w capability 50 MHz */
6042 .vco_min = 700000000,
6043 .vco_max = 2400000000U,
6044 .freq_table = tegra_pll_x_freq_table,
6046 .misc1 = 0x510 - 0xe0,
6047 .round_p_to_pdiv = pllxc_round_p_to_pdiv,
6051 static struct clk tegra_pll_x_out0 = {
6052 .name = "pll_x_out0",
6053 .ops = &tegra_pll_div_ops,
6054 .flags = DIV_2 | PLLX,
6055 .parent = &tegra_pll_x,
6056 .max_rate = 700000000,
6059 static struct clk tegra_dfll_cpu = {
6062 .ops = &tegra_dfll_ops,
6064 .max_rate = 2000000000,
6067 static struct clk tegra_pll_re_vco = {
6068 .name = "pll_re_vco",
6069 .flags = PLL_ALT_MISC_REG,
6070 .ops = &tegra_pllre_ops,
6072 .parent = &tegra_pll_ref,
6073 .max_rate = 672000000,
6075 .input_min = 12000000,
6076 .input_max = 1000000000,
6078 .cf_max = 19200000, /* s/w policy, h/w capability 38 MHz */
6079 .vco_min = 300000000,
6080 .vco_max = 672000000,
6082 .round_p_to_pdiv = pllre_round_p_to_pdiv,
6086 static struct clk tegra_pll_re_out = {
6087 .name = "pll_re_out",
6088 .ops = &tegra_pllre_out_ops,
6089 .parent = &tegra_pll_re_vco,
6091 .max_rate = 672000000,
6094 static struct clk_pll_freq_table tegra_pll_e_freq_table[] = {
6095 /* PLLE special case: use cpcon field to store cml divider value */
6096 { 336000000, 100000000, 100, 21, 16, 11},
6097 { 312000000, 100000000, 200, 26, 24, 13},
6098 { 12000000, 100000000, 200, 1, 24, 13},
6099 { 0, 0, 0, 0, 0, 0 },
6102 static struct clk tegra_pll_e = {
6104 .flags = PLL_ALT_MISC_REG,
6105 .ops = &tegra_plle_ops,
6107 .max_rate = 100000000,
6109 .input_min = 12000000,
6110 .input_max = 1000000000,
6113 .vco_min = 1600000000,
6114 .vco_max = 2400000000U,
6115 .freq_table = tegra_pll_e_freq_table,
6117 .fixed_rate = 100000000,
6121 static struct clk tegra_pciex_clk = {
6123 .parent = &tegra_pll_e,
6124 .ops = &tegra_pciex_clk_ops,
6125 .max_rate = 100000000,
6131 /* Audio sync clocks */
6132 #define SYNC_SOURCE(_id, _dev) \
6134 .name = #_id "_sync", \
6137 .con_id = "ext_audio_sync", \
6140 .max_rate = 24000000, \
6141 .ops = &tegra_sync_source_ops \
6143 static struct clk tegra_sync_source_list[] = {
6144 SYNC_SOURCE(spdif_in, tegra30-spdif),
6145 SYNC_SOURCE(i2s0, tegra30-i2s.0),
6146 SYNC_SOURCE(i2s1, tegra30-i2s.1),
6147 SYNC_SOURCE(i2s2, tegra30-i2s.2),
6148 SYNC_SOURCE(i2s3, tegra30-i2s.3),
6149 SYNC_SOURCE(i2s4, tegra30-i2s.4),
6150 SYNC_SOURCE(vimclk, vimclk),
6153 static struct clk_mux_sel mux_d_audio_clk[] = {
6154 { .input = &tegra_pll_a_out0, .value = 0},
6155 { .input = &tegra_pll_p, .value = 0x8000},
6156 { .input = &tegra_clk_m, .value = 0xc000},
6157 { .input = &tegra_sync_source_list[0], .value = 0xE000},
6158 { .input = &tegra_sync_source_list[1], .value = 0xE001},
6159 { .input = &tegra_sync_source_list[2], .value = 0xE002},
6160 { .input = &tegra_sync_source_list[3], .value = 0xE003},
6161 { .input = &tegra_sync_source_list[4], .value = 0xE004},
6162 { .input = &tegra_sync_source_list[5], .value = 0xE005},
6163 { .input = &tegra_pll_a_out0, .value = 0xE006},
6164 { .input = &tegra_sync_source_list[6], .value = 0xE007},
6168 static struct clk_mux_sel mux_audio_sync_clk[] =
6170 { .input = &tegra_sync_source_list[0], .value = 0},
6171 { .input = &tegra_sync_source_list[1], .value = 1},
6172 { .input = &tegra_sync_source_list[2], .value = 2},
6173 { .input = &tegra_sync_source_list[3], .value = 3},
6174 { .input = &tegra_sync_source_list[4], .value = 4},
6175 { .input = &tegra_sync_source_list[5], .value = 5},
6176 { .input = &tegra_pll_a_out0, .value = 6},
6177 { .input = &tegra_sync_source_list[6], .value = 7},
6181 #define AUDIO_SYNC_CLK(_id, _dev, _index) \
6186 .con_id = "audio_sync", \
6188 .inputs = mux_audio_sync_clk, \
6189 .reg = 0x4A0 + (_index) * 4, \
6190 .max_rate = 24000000, \
6191 .ops = &tegra_audio_sync_clk_ops \
6193 static struct clk tegra_clk_audio_list[] = {
6194 AUDIO_SYNC_CLK(audio0, tegra30-i2s.0, 0),
6195 AUDIO_SYNC_CLK(audio1, tegra30-i2s.1, 1),
6196 AUDIO_SYNC_CLK(audio2, tegra30-i2s.2, 2),
6197 AUDIO_SYNC_CLK(audio3, tegra30-i2s.3, 3),
6198 AUDIO_SYNC_CLK(audio4, tegra30-i2s.4, 4),
6199 AUDIO_SYNC_CLK(audio, tegra30-spdif, 5), /* SPDIF */
6202 #define AUDIO_SYNC_2X_CLK(_id, _dev, _index) \
6204 .name = #_id "_2x", \
6207 .con_id = "audio_sync_2x" \
6209 .flags = PERIPH_NO_RESET, \
6210 .max_rate = 48000000, \
6211 .ops = &tegra_clk_double_ops, \
6213 .reg_shift = 24 + (_index), \
6214 .parent = &tegra_clk_audio_list[(_index)], \
6216 .clk_num = 113 + (_index), \
6219 static struct clk tegra_clk_audio_2x_list[] = {
6220 AUDIO_SYNC_2X_CLK(audio0, tegra30-i2s.0, 0),
6221 AUDIO_SYNC_2X_CLK(audio1, tegra30-i2s.1, 1),
6222 AUDIO_SYNC_2X_CLK(audio2, tegra30-i2s.2, 2),
6223 AUDIO_SYNC_2X_CLK(audio3, tegra30-i2s.3, 3),
6224 AUDIO_SYNC_2X_CLK(audio4, tegra30-i2s.4, 4),
6225 AUDIO_SYNC_2X_CLK(audio, tegra30-spdif, 5), /* SPDIF */
6228 #define MUX_I2S_SPDIF(_id, _index) \
6229 static struct clk_mux_sel mux_pllaout0_##_id##_2x_pllp_clkm[] = { \
6230 {.input = &tegra_pll_a_out0, .value = 0}, \
6231 {.input = &tegra_clk_audio_2x_list[(_index)], .value = 1}, \
6232 {.input = &tegra_pll_p, .value = 2}, \
6233 {.input = &tegra_clk_m, .value = 3}, \
6236 MUX_I2S_SPDIF(audio0, 0);
6237 MUX_I2S_SPDIF(audio1, 1);
6238 MUX_I2S_SPDIF(audio2, 2);
6239 MUX_I2S_SPDIF(audio3, 3);
6240 MUX_I2S_SPDIF(audio4, 4);
6241 MUX_I2S_SPDIF(audio, 5); /* SPDIF */
6243 /* External clock outputs (through PMC) */
6244 #define MUX_EXTERN_OUT(_id) \
6245 static struct clk_mux_sel mux_clkm_clkm2_clkm4_extern##_id[] = { \
6246 {.input = &tegra_clk_m, .value = 0}, \
6247 {.input = &tegra_clk_m_div2, .value = 1}, \
6248 {.input = &tegra_clk_m_div4, .value = 2}, \
6249 {.input = NULL, .value = 3}, /* placeholder */ \
6256 static struct clk_mux_sel *mux_extern_out_list[] = {
6257 mux_clkm_clkm2_clkm4_extern1,
6258 mux_clkm_clkm2_clkm4_extern2,
6259 mux_clkm_clkm2_clkm4_extern3,
6262 #define CLK_OUT_CLK(_id, _max_rate) \
6264 .name = "clk_out_" #_id, \
6266 .dev_id = "clk_out_" #_id, \
6267 .con_id = "extern" #_id, \
6269 .ops = &tegra_clk_out_ops, \
6271 .inputs = mux_clkm_clkm2_clkm4_extern##_id, \
6272 .flags = MUX_CLK_OUT, \
6273 .max_rate = _max_rate, \
6275 .clk_num = (_id - 1) * 8 + 2, \
6278 static struct clk tegra_clk_out_list[] = {
6279 CLK_OUT_CLK(1, 12288000),
6280 CLK_OUT_CLK(2, 40800000),
6281 CLK_OUT_CLK(3, 12288000),
6284 /* called after peripheral external clocks are initialized */
6285 static void init_clk_out_mux(void)
6290 /* output clock con_id is the name of peripheral
6291 external clock connected to input 3 of the output mux */
6292 for (i = 0; i < ARRAY_SIZE(tegra_clk_out_list); i++) {
6293 c = tegra_get_clock_by_name(
6294 tegra_clk_out_list[i].lookup.con_id);
6296 pr_err("%s: could not find clk %s\n", __func__,
6297 tegra_clk_out_list[i].lookup.con_id);
6298 mux_extern_out_list[i][3].input = c;
6302 /* Peripheral muxes */
6303 static struct clk_mux_sel mux_cclk_g[] = {
6304 { .input = &tegra_clk_m, .value = 0},
6305 { .input = &tegra_pll_c, .value = 1},
6306 { .input = &tegra_clk_32k, .value = 2},
6307 { .input = &tegra_pll_m, .value = 3},
6308 { .input = &tegra_pll_p, .value = 4},
6309 { .input = &tegra_pll_p_out4, .value = 5},
6310 /* { .input = &tegra_pll_c2, .value = 6}, - no use on tegra11x */
6311 /* { .input = &tegra_clk_c3, .value = 7}, - no use on tegra11x */
6312 { .input = &tegra_pll_x, .value = 8},
6313 { .input = &tegra_dfll_cpu, .value = 15},
6317 static struct clk_mux_sel mux_cclk_lp[] = {
6318 { .input = &tegra_clk_m, .value = 0},
6319 { .input = &tegra_pll_c, .value = 1},
6320 { .input = &tegra_clk_32k, .value = 2},
6321 { .input = &tegra_pll_m, .value = 3},
6322 { .input = &tegra_pll_p, .value = 4},
6323 { .input = &tegra_pll_p_out4, .value = 5},
6324 /* { .input = &tegra_pll_c2, .value = 6}, - no use on tegra11x */
6325 /* { .input = &tegra_clk_c3, .value = 7}, - no use on tegra11x */
6326 { .input = &tegra_pll_x_out0, .value = 8},
6327 { .input = &tegra_pll_x, .value = 8 | SUPER_LP_DIV2_BYPASS},
6331 static struct clk_mux_sel mux_sclk[] = {
6332 { .input = &tegra_clk_m, .value = 0},
6333 { .input = &tegra_pll_c_out1, .value = 1},
6334 { .input = &tegra_pll_p_out4, .value = 2},
6335 { .input = &tegra_pll_p, .value = 3},
6336 { .input = &tegra_pll_p_out2, .value = 4},
6337 /* { .input = &tegra_clk_d, .value = 5}, - no use on tegra11x */
6338 { .input = &tegra_clk_32k, .value = 6},
6339 { .input = &tegra_pll_m_out1, .value = 7},
6343 static struct clk tegra_clk_cclk_g = {
6345 .flags = DIV_U71 | DIV_U71_INT | MUX,
6346 .inputs = mux_cclk_g,
6348 .ops = &tegra_super_ops,
6349 .max_rate = 2000000000,
6352 static struct clk tegra_clk_cclk_lp = {
6354 .flags = DIV_2 | DIV_U71 | DIV_U71_INT | MUX,
6355 .inputs = mux_cclk_lp,
6357 .ops = &tegra_super_ops,
6358 .max_rate = 816000000,
6361 static struct clk tegra_clk_sclk = {
6365 .ops = &tegra_super_ops,
6366 .max_rate = 384000000,
6367 .min_rate = 12000000,
6370 static struct clk tegra_clk_virtual_cpu_g = {
6372 .parent = &tegra_clk_cclk_g,
6373 .ops = &tegra_cpu_ops,
6374 .max_rate = 2000000000,
6376 .main = &tegra_pll_x,
6377 .backup = &tegra_pll_p_out4,
6378 .dynamic = &tegra_dfll_cpu,
6383 static struct clk tegra_clk_virtual_cpu_lp = {
6385 .parent = &tegra_clk_cclk_lp,
6386 .ops = &tegra_cpu_ops,
6387 .max_rate = 816000000,
6389 .main = &tegra_pll_x,
6390 .backup = &tegra_pll_p_out4,
6395 static struct clk_mux_sel mux_cpu_cmplx[] = {
6396 { .input = &tegra_clk_virtual_cpu_g, .value = 0},
6397 { .input = &tegra_clk_virtual_cpu_lp, .value = 1},
6401 static struct clk tegra_clk_cpu_cmplx = {
6403 .inputs = mux_cpu_cmplx,
6404 .ops = &tegra_cpu_cmplx_ops,
6405 .max_rate = 2000000000,
6408 static struct clk tegra_clk_cop = {
6410 .parent = &tegra_clk_sclk,
6411 .ops = &tegra_cop_ops,
6412 .max_rate = 384000000,
6415 static struct clk tegra_clk_hclk = {
6418 .parent = &tegra_clk_sclk,
6421 .ops = &tegra_bus_ops,
6422 .max_rate = 384000000,
6423 .min_rate = 12000000,
6426 static struct clk tegra_clk_pclk = {
6429 .parent = &tegra_clk_hclk,
6432 .ops = &tegra_bus_ops,
6433 .max_rate = 192000000,
6434 .min_rate = 12000000,
6437 static struct raw_notifier_head sbus_rate_change_nh;
6439 static struct clk tegra_clk_sbus_cmplx = {
6441 .parent = &tegra_clk_sclk,
6442 .ops = &tegra_sbus_cmplx_ops,
6444 .pclk = &tegra_clk_pclk,
6445 .hclk = &tegra_clk_hclk,
6446 .sclk_low = &tegra_pll_p_out2,
6447 #ifdef CONFIG_TEGRA_PLLM_SCALED
6448 .sclk_high = &tegra_pll_c_out1,
6450 .sclk_high = &tegra_pll_m_out1,
6453 .rate_change_nh = &sbus_rate_change_nh,
6456 static struct clk tegra_clk_blink = {
6458 .parent = &tegra_clk_32k,
6460 .ops = &tegra_blink_clk_ops,
6465 /* Multimedia modules muxes */
6466 static struct clk_mux_sel mux_pllm_pllc2_c_c3_pllp_plla[] = {
6467 { .input = &tegra_pll_m, .value = 0},
6468 { .input = &tegra_pll_c2, .value = 1},
6469 { .input = &tegra_pll_c, .value = 2},
6470 { .input = &tegra_pll_c3, .value = 3},
6471 { .input = &tegra_pll_p, .value = 4},
6472 { .input = &tegra_pll_a_out0, .value = 6},
6476 static struct clk_mux_sel mux_pllm_pllc_pllp_plla[] = {
6477 { .input = &tegra_pll_m, .value = 0},
6478 { .input = &tegra_pll_c, .value = 1},
6479 { .input = &tegra_pll_p, .value = 2},
6480 { .input = &tegra_pll_a_out0, .value = 3},
6484 static struct clk_mux_sel mux_plla_pllc_pllp_clkm[] = {
6485 { .input = &tegra_pll_a_out0, .value = 0},
6486 { .input = &tegra_pll_c, .value = 1},
6487 { .input = &tegra_pll_p, .value = 2},
6488 { .input = &tegra_clk_m, .value = 3},
6493 /* FIXME: add EMC latency mux */
6494 static struct clk_mux_sel mux_pllm_pllc_pllp_clkm[] = {
6495 { .input = &tegra_pll_m, .value = 0},
6496 { .input = &tegra_pll_c, .value = 1},
6497 { .input = &tegra_pll_p, .value = 2},
6498 { .input = &tegra_clk_m, .value = 3},
6499 { .input = &tegra_pll_m, .value = 4}, /* low jitter PLLM input */
6504 /* Display subsystem muxes */
6505 static struct clk_mux_sel mux_pllp_pllm_plld_plla_pllc_plld2_clkm[] = {
6506 {.input = &tegra_pll_p, .value = 0},
6507 {.input = &tegra_pll_m, .value = 1},
6508 {.input = &tegra_pll_d_out0, .value = 2},
6509 {.input = &tegra_pll_a_out0, .value = 3},
6510 {.input = &tegra_pll_c, .value = 4},
6511 {.input = &tegra_pll_d2_out0, .value = 5},
6512 {.input = &tegra_clk_m, .value = 6},
6516 static struct clk_mux_sel mux_plld_out0_plld2_out0[] = {
6517 { .input = &tegra_pll_d_out0, .value = 0},
6518 { .input = &tegra_pll_d2_out0, .value = 1},
6522 static struct clk_mux_sel mux_pllp_pllc_clkm[] = {
6523 {.input = &tegra_pll_p, .value = 0},
6524 {.input = &tegra_pll_c, .value = 1},
6525 {.input = &tegra_clk_m, .value = 3},
6529 /* Peripheral muxes */
6530 static struct clk_mux_sel mux_pllp_pllc2_c_c3_pllm_clkm[] = {
6531 { .input = &tegra_pll_p, .value = 0},
6532 { .input = &tegra_pll_c2, .value = 1},
6533 { .input = &tegra_pll_c, .value = 2},
6534 { .input = &tegra_pll_c3, .value = 3},
6535 { .input = &tegra_pll_m, .value = 4},
6536 { .input = &tegra_clk_m, .value = 6},
6540 static struct clk_mux_sel mux_pllp_pllc_pllm_clkm[] = {
6541 { .input = &tegra_pll_p, .value = 0},
6542 { .input = &tegra_pll_c, .value = 1},
6543 { .input = &tegra_pll_m, .value = 2},
6544 { .input = &tegra_clk_m, .value = 3},
6548 static struct clk_mux_sel mux_pllp_pllc_pllm[] = {
6549 {.input = &tegra_pll_p, .value = 0},
6550 {.input = &tegra_pll_c, .value = 1},
6551 {.input = &tegra_pll_m, .value = 2},
6555 static struct clk_mux_sel mux_pllp_clkm[] = {
6556 { .input = &tegra_pll_p, .value = 0},
6557 { .input = &tegra_clk_m, .value = 3},
6561 static struct clk_mux_sel mux_pllp_pllc_clk32_clkm[] = {
6562 {.input = &tegra_pll_p, .value = 0},
6563 {.input = &tegra_pll_c, .value = 1},
6564 {.input = &tegra_clk_32k, .value = 2},
6565 {.input = &tegra_clk_m, .value = 3},
6569 static struct clk_mux_sel mux_pllp_pllc_clkm_clk32[] = {
6570 {.input = &tegra_pll_p, .value = 0},
6571 {.input = &tegra_pll_c, .value = 1},
6572 {.input = &tegra_clk_m, .value = 2},
6573 {.input = &tegra_clk_32k, .value = 3},
6577 static struct clk_mux_sel mux_plla_clk32_pllp_clkm_plle[] = {
6578 { .input = &tegra_pll_a_out0, .value = 0},
6579 { .input = &tegra_clk_32k, .value = 1},
6580 { .input = &tegra_pll_p, .value = 2},
6581 { .input = &tegra_clk_m, .value = 3},
6582 { .input = &tegra_pll_e, .value = 4},
6586 static struct clk_mux_sel mux_clkm_pllp_pllc_pllre[] = {
6587 { .input = &tegra_clk_m, .value = 0},
6588 { .input = &tegra_pll_p, .value = 1},
6589 { .input = &tegra_pll_c, .value = 3},
6590 { .input = &tegra_pll_re_vco, .value = 5},
6594 static struct clk_mux_sel mux_clkm_48M_pllp_480M[] = {
6595 { .input = &tegra_clk_m, .value = 0},
6596 { .input = &tegra_pll_u_48M, .value = 1},
6597 { .input = &tegra_pll_p, .value = 2},
6598 { .input = &tegra_pll_u_480M, .value = 3},
6602 static struct clk_mux_sel mux_clkm_pllre_clk32_480M_pllc_ref[] = {
6603 { .input = &tegra_clk_m, .value = 0},
6604 { .input = &tegra_pll_re_vco, .value = 1},
6605 { .input = &tegra_clk_32k, .value = 2},
6606 { .input = &tegra_pll_u_480M, .value = 3},
6607 { .input = &tegra_pll_c, .value = 4},
6608 { .input = &tegra_pll_ref, .value = 7},
6612 /* Single clock source ("fake") muxes */
6613 static struct clk_mux_sel mux_clk_m[] = {
6614 { .input = &tegra_clk_m, .value = 0},
6618 static struct clk_mux_sel mux_pllp_out3[] = {
6619 { .input = &tegra_pll_p_out3, .value = 0},
6623 static struct clk_mux_sel mux_clk_32k[] = {
6624 { .input = &tegra_clk_32k, .value = 0},
6628 static struct raw_notifier_head emc_rate_change_nh;
6630 static struct clk tegra_clk_emc = {
6632 .ops = &tegra_emc_clk_ops,
6634 .max_rate = 1066000000,
6635 .min_rate = 12750000,
6636 .inputs = mux_pllm_pllc_pllp_clkm,
6637 .flags = MUX | MUX8 | DIV_U71 | PERIPH_EMC_ENB,
6641 .rate_change_nh = &emc_rate_change_nh,
6644 static struct raw_notifier_head host1x_rate_change_nh;
6646 static struct clk tegra_clk_host1x = {
6651 .ops = &tegra_1xbus_clk_ops,
6653 .inputs = mux_pllm_pllc_pllp_plla,
6654 .flags = MUX | DIV_U71 | DIV_U71_INT,
6655 .max_rate = 384000000,
6656 .min_rate = 12000000,
6659 .pll_low = &tegra_pll_p,
6660 #ifdef CONFIG_TEGRA_PLLM_SCALED
6661 .pll_high = &tegra_pll_c,
6663 .pll_high = &tegra_pll_m,
6666 .rate_change_nh = &host1x_rate_change_nh,
6669 #ifdef CONFIG_TEGRA_DUAL_CBUS
6671 static struct raw_notifier_head c2bus_rate_change_nh;
6672 static struct raw_notifier_head c3bus_rate_change_nh;
6674 static struct clk tegra_clk_c2bus = {
6676 .parent = &tegra_pll_c2,
6677 .ops = &tegra_clk_cbus_ops,
6678 .max_rate = 864000000,
6681 .flags = PERIPH_ON_CBUS,
6682 .shared_bus_backup = {
6683 .input = &tegra_pll_p,
6685 .rate_change_nh = &c2bus_rate_change_nh,
6687 static struct clk tegra_clk_c3bus = {
6689 .parent = &tegra_pll_c3,
6690 .ops = &tegra_clk_cbus_ops,
6691 .max_rate = 700000000,
6694 .flags = PERIPH_ON_CBUS,
6695 .shared_bus_backup = {
6696 .input = &tegra_pll_p,
6698 .rate_change_nh = &c3bus_rate_change_nh,
6701 #ifdef CONFIG_TEGRA_MIGRATE_CBUS_USERS
6702 static DEFINE_MUTEX(cbus_mutex);
6703 #define CROSS_CBUS_MUTEX (&cbus_mutex)
6705 #define CROSS_CBUS_MUTEX NULL
6709 static struct clk_mux_sel mux_clk_cbus[] = {
6710 { .input = &tegra_clk_c2bus, .value = 0},
6711 { .input = &tegra_clk_c3bus, .value = 1},
6715 #define DUAL_CBUS_CLK(_name, _dev, _con, _parent, _id, _div, _mode)\
6722 .ops = &tegra_clk_shared_bus_user_ops, \
6723 .parent = _parent, \
6724 .inputs = mux_clk_cbus, \
6726 .u.shared_bus_user = { \
6728 .client_div = _div, \
6731 .cross_clk_mutex = CROSS_CBUS_MUTEX, \
6736 static struct raw_notifier_head cbus_rate_change_nh;
6738 static struct clk tegra_clk_cbus = {
6740 .parent = &tegra_pll_c,
6741 .ops = &tegra_clk_cbus_ops,
6742 .max_rate = 700000000,
6745 .flags = PERIPH_ON_CBUS,
6746 .shared_bus_backup = {
6747 .input = &tegra_pll_p,
6749 .rate_change_nh = &cbus_rate_change_nh,
6753 static void tegra11_camera_mclk_init(struct clk *c)
6757 c->parent = tegra_get_clock_by_name("vi_sensor");
6758 c->max_rate = c->parent->max_rate;
6761 static int tegra11_camera_mclk_set_rate(struct clk *c, unsigned long rate)
6763 return clk_set_rate(c->parent, rate);
6766 static struct clk_ops tegra_camera_mclk_ops = {
6767 .init = tegra11_camera_mclk_init,
6768 .enable = tegra11_periph_clk_enable,
6769 .disable = tegra11_periph_clk_disable,
6770 .set_rate = tegra11_camera_mclk_set_rate,
6773 static struct clk tegra_camera_mclk = {
6775 .ops = &tegra_camera_mclk_ops,
6777 .clk_num = 92, /* csus */
6779 .flags = PERIPH_NO_RESET,
6782 #define PERIPH_CLK(_name, _dev, _con, _clk_num, _reg, _max, _inputs, _flags) \
6789 .ops = &tegra_periph_clk_ops, \
6791 .inputs = _inputs, \
6795 .clk_num = _clk_num, \
6799 #define PERIPH_CLK_EX(_name, _dev, _con, _clk_num, _reg, _max, _inputs, \
6809 .inputs = _inputs, \
6813 .clk_num = _clk_num, \
6817 #define D_AUDIO_CLK(_name, _dev, _con, _clk_num, _reg, _max, _inputs, _flags) \
6824 .ops = &tegra_periph_clk_ops, \
6826 .inputs = _inputs, \
6830 .clk_num = _clk_num, \
6831 .src_mask = 0xE01F << 16, \
6836 #define SHARED_CLK(_name, _dev, _con, _parent, _id, _div, _mode)\
6843 .ops = &tegra_clk_shared_bus_user_ops, \
6844 .parent = _parent, \
6845 .u.shared_bus_user = { \
6847 .client_div = _div, \
6851 #define SHARED_EMC_CLK(_name, _dev, _con, _parent, _id, _div, _mode, _flag)\
6858 .ops = &tegra_clk_shared_bus_user_ops, \
6859 .parent = _parent, \
6860 .u.shared_bus_user = { \
6862 .client_div = _div, \
6864 .usage_flag = _flag, \
6868 struct clk tegra_list_clks[] = {
6869 PERIPH_CLK("apbdma", "tegra-apbdma", NULL, 34, 0, 26000000, mux_clk_m, 0),
6870 PERIPH_CLK("rtc", "rtc-tegra", NULL, 4, 0, 32768, mux_clk_32k, PERIPH_NO_RESET | PERIPH_ON_APB),
6871 PERIPH_CLK("kbc", "tegra-kbc", NULL, 36, 0, 32768, mux_clk_32k, PERIPH_NO_RESET | PERIPH_ON_APB),
6872 PERIPH_CLK("timer", "timer", NULL, 5, 0, 26000000, mux_clk_m, 0),
6873 PERIPH_CLK("kfuse", "kfuse-tegra", NULL, 40, 0, 26000000, mux_clk_m, PERIPH_ON_APB),
6874 PERIPH_CLK("fuse", "fuse-tegra", "fuse", 39, 0, 26000000, mux_clk_m, PERIPH_ON_APB),
6875 PERIPH_CLK("fuse_burn", "fuse-tegra", "fuse_burn", 39, 0, 26000000, mux_clk_m, PERIPH_ON_APB),
6876 PERIPH_CLK("apbif", "tegra30-ahub", "apbif", 107, 0, 26000000, mux_clk_m, PERIPH_ON_APB),
6877 PERIPH_CLK("i2s0", "tegra30-i2s.0", NULL, 30, 0x1d8, 24576000, mux_pllaout0_audio0_2x_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
6878 PERIPH_CLK("i2s1", "tegra30-i2s.1", NULL, 11, 0x100, 24576000, mux_pllaout0_audio1_2x_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
6879 PERIPH_CLK("i2s2", "tegra30-i2s.2", NULL, 18, 0x104, 24576000, mux_pllaout0_audio2_2x_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
6880 PERIPH_CLK("i2s3", "tegra30-i2s.3", NULL, 101, 0x3bc, 24576000, mux_pllaout0_audio3_2x_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
6881 PERIPH_CLK("i2s4", "tegra30-i2s.4", NULL, 102, 0x3c0, 24576000, mux_pllaout0_audio4_2x_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
6882 PERIPH_CLK("spdif_out", "tegra30-spdif", "spdif_out", 10, 0x108, 24576000, mux_pllaout0_audio_2x_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
6883 PERIPH_CLK("spdif_in", "tegra30-spdif", "spdif_in", 10, 0x10c, 100000000, mux_pllp_pllc_pllm, MUX | DIV_U71 | PERIPH_ON_APB),
6884 PERIPH_CLK("pwm", "tegra-pwm", NULL, 17, 0x110, 48000000, mux_pllp_pllc_clk32_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
6885 D_AUDIO_CLK("d_audio", "tegra30-ahub", "d_audio", 106, 0x3d0, 48000000, mux_d_audio_clk, MUX | DIV_U71 | PERIPH_ON_APB),
6886 D_AUDIO_CLK("dam0", "tegra30-dam.0", NULL, 108, 0x3d8, 19910000, mux_d_audio_clk, MUX | DIV_U71 | PERIPH_ON_APB),
6887 D_AUDIO_CLK("dam1", "tegra30-dam.1", NULL, 109, 0x3dc, 19910000, mux_d_audio_clk, MUX | DIV_U71 | PERIPH_ON_APB),
6888 D_AUDIO_CLK("dam2", "tegra30-dam.2", NULL, 110, 0x3e0, 19910000, mux_d_audio_clk, MUX | DIV_U71 | PERIPH_ON_APB),
6889 PERIPH_CLK("adx", "adx", NULL, 154, 0x638, 24730000, mux_plla_pllc_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
6890 PERIPH_CLK("amx", "amx", NULL, 153, 0x63c, 24730000, mux_plla_pllc_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
6891 PERIPH_CLK("hda", "tegra30-hda", "hda", 125, 0x428, 48000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
6892 PERIPH_CLK("hda2codec_2x", "tegra30-hda", "hda2codec", 111, 0x3e4, 48000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
6893 PERIPH_CLK("hda2hdmi", "tegra30-hda", "hda2hdmi", 128, 0, 48000000, mux_clk_m, PERIPH_ON_APB),
6894 PERIPH_CLK("sbc1", "spi-tegra114.0", NULL, 41, 0x134, 52000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
6895 PERIPH_CLK("sbc2", "spi-tegra114.1", NULL, 44, 0x118, 52000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
6896 PERIPH_CLK("sbc3", "spi-tegra114.2", NULL, 46, 0x11c, 52000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
6897 PERIPH_CLK("sbc4", "spi-tegra114.3", NULL, 68, 0x1b4, 52000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
6898 PERIPH_CLK("sbc5", "spi-tegra114.4", NULL, 104, 0x3c8, 52000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
6899 PERIPH_CLK("sbc6", "spi-tegra114.5", NULL, 105, 0x3cc, 52000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
6900 PERIPH_CLK_EX("ndflash", "tegra_nand", NULL, 13, 0x160, 240000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB, &tegra_nand_clk_ops),
6901 PERIPH_CLK("ndspeed", "tegra_nand_speed", NULL, 80, 0x3f8, 240000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
6902 PERIPH_CLK("vfir", "vfir", NULL, 7, 0x168, 72000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
6903 PERIPH_CLK("sdmmc1", "sdhci-tegra.0", NULL, 14, 0x150, 208000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
6904 PERIPH_CLK("sdmmc2", "sdhci-tegra.1", NULL, 9, 0x154, 102000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
6905 PERIPH_CLK("sdmmc3", "sdhci-tegra.2", NULL, 69, 0x1bc, 208000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
6906 PERIPH_CLK("sdmmc4", "sdhci-tegra.3", NULL, 15, 0x164, 200000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
6907 PERIPH_CLK("vcp", "tegra-avp", "vcp", 29, 0, 250000000, mux_clk_m, 0),
6908 PERIPH_CLK("bsea", "tegra-avp", "bsea", 62, 0, 250000000, mux_clk_m, 0),
6909 PERIPH_CLK("bsev", "tegra-aes", "bsev", 63, 0, 250000000, mux_clk_m, 0),
6910 PERIPH_CLK("cec", "tegra_cec", NULL, 136, 0, 250000000, mux_clk_m, PERIPH_ON_APB),
6911 PERIPH_CLK("vde", "vde", NULL, 61, 0x1c8, 600000000, mux_pllp_pllc2_c_c3_pllm_clkm, MUX | MUX8 | DIV_U71 | DIV_U71_INT),
6912 PERIPH_CLK("csite", "csite", NULL, 73, 0x1d4, 144000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
6913 PERIPH_CLK("la", "la", NULL, 76, 0x1f8, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
6914 PERIPH_CLK("trace", "trace", NULL, 77, 0x634, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
6915 PERIPH_CLK("owr", "tegra_w1", NULL, 71, 0x1cc, 12000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
6916 PERIPH_CLK("nor", "tegra-nor", NULL, 42, 0x1d0, 127000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
6917 PERIPH_CLK("mipi", "mipi", NULL, 50, 0x174, 60000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
6918 PERIPH_CLK("i2c1", "tegra11-i2c.0", "div-clk", 12, 0x124, 136000000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB),
6919 PERIPH_CLK("i2c2", "tegra11-i2c.1", "div-clk", 54, 0x198, 136000000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB),
6920 PERIPH_CLK("i2c3", "tegra11-i2c.2", "div-clk", 67, 0x1b8, 136000000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB),
6921 PERIPH_CLK("i2c4", "tegra11-i2c.3", "div-clk", 103, 0x3c4, 136000000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB),
6922 PERIPH_CLK("i2c5", "tegra11-i2c.4", "div-clk", 47, 0x128, 64000000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB),
6923 PERIPH_CLK("mipi-cal", "mipi-cal", NULL, 56, 0, 60000000, mux_clk_m, PERIPH_ON_APB),
6924 PERIPH_CLK("mipi-cal-fixed", "mipi-cal-fixed", NULL, 0, 0, 108000000, mux_pllp_out3, PERIPH_NO_ENB),
6925 PERIPH_CLK("uarta", "serial-tegra.0", NULL, 6, 0x178, 800000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U151 | DIV_U151_UART | PERIPH_ON_APB),
6926 PERIPH_CLK("uartb", "serial-tegra.1", NULL, 7, 0x17c, 800000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U151 | DIV_U151_UART | PERIPH_ON_APB),
6927 PERIPH_CLK("uartc", "serial-tegra.2", NULL, 55, 0x1a0, 800000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U151 | DIV_U151_UART | PERIPH_ON_APB),
6928 PERIPH_CLK("uartd", "serial-tegra.3", NULL, 65, 0x1c0, 800000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U151 | DIV_U151_UART | PERIPH_ON_APB),
6929 PERIPH_CLK("uarte", "tegra_uart.4", NULL, 66, 0x1c4, 800000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U151 | DIV_U151_UART | PERIPH_ON_APB),
6930 PERIPH_CLK("3d", "3d", NULL, 24, 0x158, 864000000, mux_pllm_pllc2_c_c3_pllp_plla, MUX | MUX8 | DIV_U71 | DIV_U71_INT | DIV_U71_IDLE | PERIPH_MANUAL_RESET),
6931 PERIPH_CLK("2d", "2d", NULL, 21, 0x15c, 864000000, mux_pllm_pllc2_c_c3_pllp_plla, MUX | MUX8 | DIV_U71 | DIV_U71_INT | DIV_U71_IDLE),
6932 PERIPH_CLK_EX("vi", "vi", "vi", 20, 0x148, 425000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | DIV_U71_INT, &tegra_vi_clk_ops),
6933 PERIPH_CLK("vi_sensor", NULL, "vi_sensor", 20, 0x1a8, 150000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | PERIPH_NO_RESET),
6934 PERIPH_CLK("epp", "epp", NULL, 19, 0x16c, 864000000, mux_pllm_pllc2_c_c3_pllp_plla, MUX | MUX8 | DIV_U71 | DIV_U71_INT),
6935 PERIPH_CLK_EX("msenc", "msenc", NULL, 91, 0x1f0, 600000000, mux_pllm_pllc2_c_c3_pllp_plla, MUX | MUX8 | DIV_U71 | DIV_U71_INT, &tegra_msenc_clk_ops),
6936 PERIPH_CLK("tsec", "tsec", NULL, 83, 0x1f4, 600000000, mux_pllp_pllc2_c_c3_pllm_clkm, MUX | MUX8 | DIV_U71 | DIV_U71_INT),
6937 PERIPH_CLK_EX("dtv", "dtv", NULL, 79, 0x1dc, 250000000, mux_clk_m, PERIPH_ON_APB, &tegra_dtv_clk_ops),
6938 PERIPH_CLK("hdmi", "hdmi", NULL, 51, 0x18c, 297000000, mux_pllp_pllm_plld_plla_pllc_plld2_clkm, MUX | MUX8 | DIV_U71),
6939 PERIPH_CLK("disp1", "tegradc.0", NULL, 27, 0x138, 600000000, mux_pllp_pllm_plld_plla_pllc_plld2_clkm, MUX | MUX8),
6940 PERIPH_CLK("disp2", "tegradc.1", NULL, 26, 0x13c, 600000000, mux_pllp_pllm_plld_plla_pllc_plld2_clkm, MUX | MUX8),
6941 PERIPH_CLK("usbd", "tegra-udc.0", NULL, 22, 0, 480000000, mux_clk_m, 0),
6942 PERIPH_CLK("usb2", "tegra-ehci.1", NULL, 58, 0, 480000000, mux_clk_m, 0),
6943 PERIPH_CLK("usb3", "tegra-ehci.2", NULL, 59, 0, 480000000, mux_clk_m, 0),
6944 PERIPH_CLK_EX("dsia", "tegradc.0", "dsia", 48, 0xd0, 500000000, mux_plld_out0_plld2_out0, MUX | PLLD, &tegra_dsi_clk_ops),
6945 PERIPH_CLK_EX("dsib", "tegradc.1", "dsib", 82, 0x4b8, 500000000, mux_plld_out0_plld2_out0, MUX | PLLD, &tegra_dsi_clk_ops),
6946 PERIPH_CLK("dsi1-fixed", "tegradc.0", "dsi-fixed", 0, 0, 108000000, mux_pllp_out3, PERIPH_NO_ENB),
6947 PERIPH_CLK("dsi2-fixed", "tegradc.1", "dsi-fixed", 0, 0, 108000000, mux_pllp_out3, PERIPH_NO_ENB),
6948 PERIPH_CLK("csi", "vi", "csi", 52, 0, 102000000, mux_pllp_out3, 0),
6949 PERIPH_CLK("isp", "vi", "isp", 23, 0, 150000000, mux_clk_m, 0), /* same frequency as VI */
6950 PERIPH_CLK("csus", "vi", "csus", 92, 0, 150000000, mux_clk_m, PERIPH_NO_RESET),
6951 PERIPH_CLK("cilab", "vi", "cilab", 144, 0x614, 102000000, mux_pllp_pllc_clkm, MUX | DIV_U71),
6952 PERIPH_CLK("cilcd", "vi", "cilcd", 145, 0x618, 102000000, mux_pllp_pllc_clkm, MUX | DIV_U71),
6953 PERIPH_CLK("cile", "vi", "cile", 146, 0x61c, 102000000, mux_pllp_pllc_clkm, MUX | DIV_U71),
6954 PERIPH_CLK("dsialp", "tegradc.0", "dsialp", 147, 0x620, 102000000, mux_pllp_pllc_clkm, MUX | DIV_U71),
6955 PERIPH_CLK("dsiblp", "tegradc.1", "dsiblp", 148, 0x624, 102000000, mux_pllp_pllc_clkm, MUX | DIV_U71),
6957 PERIPH_CLK("tsensor", "tegra-tsensor", NULL, 100, 0x3b8, 12000000, mux_pllp_pllc_clkm_clk32, MUX | DIV_U71 | PERIPH_ON_APB),
6958 PERIPH_CLK("actmon", "actmon", NULL, 119, 0x3e8, 216000000, mux_pllp_pllc_clk32_clkm, MUX | DIV_U71),
6959 PERIPH_CLK("extern1", "extern1", NULL, 120, 0x3ec, 216000000, mux_plla_clk32_pllp_clkm_plle, MUX | MUX8 | DIV_U71),
6960 PERIPH_CLK("extern2", "extern2", NULL, 121, 0x3f0, 216000000, mux_plla_clk32_pllp_clkm_plle, MUX | MUX8 | DIV_U71),
6961 PERIPH_CLK("extern3", "extern3", NULL, 122, 0x3f4, 216000000, mux_plla_clk32_pllp_clkm_plle, MUX | MUX8 | DIV_U71),
6962 PERIPH_CLK("i2cslow", "i2cslow", NULL, 81, 0x3fc, 26000000, mux_pllp_pllc_clk32_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
6963 PERIPH_CLK("pcie", "tegra-pcie", "pcie", 70, 0, 250000000, mux_clk_m, 0),
6964 PERIPH_CLK("afi", "tegra-pcie", "afi", 72, 0, 250000000, mux_clk_m, 0),
6965 PERIPH_CLK("se", "se", NULL, 127, 0x42c, 600000000, mux_pllp_pllc2_c_c3_pllm_clkm, MUX | MUX8 | DIV_U71 | DIV_U71_INT | PERIPH_ON_APB),
6966 PERIPH_CLK("mselect", "mselect", NULL, 99, 0x3b4, 102000000, mux_pllp_clkm, MUX | DIV_U71 | DIV_U71_INT),
6967 PERIPH_CLK("cl_dvfs_ref", "tegra_cl_dvfs", "ref", 155, 0x62c, 54000000, mux_pllp_clkm, MUX | DIV_U71 | DIV_U71_INT | PERIPH_ON_APB),
6968 PERIPH_CLK("cl_dvfs_soc", "tegra_cl_dvfs", "soc", 155, 0x630, 54000000, mux_pllp_clkm, MUX | DIV_U71 | DIV_U71_INT | PERIPH_ON_APB),
6969 PERIPH_CLK("soc_therm", "soc_therm", NULL, 78, 0x644, 136000000, mux_pllm_pllc_pllp_plla, MUX | MUX8 | DIV_U71 | PERIPH_ON_APB),
6971 PERIPH_CLK("dds", "dds", NULL, 150, 0, 26000000, mux_clk_m, PERIPH_ON_APB),
6972 PERIPH_CLK("dp2", "dp2", NULL, 152, 0, 26000000, mux_clk_m, PERIPH_ON_APB),
6974 SHARED_CLK("avp.sclk", "tegra-avp", "sclk", &tegra_clk_sbus_cmplx, NULL, 0, 0),
6975 SHARED_CLK("bsea.sclk", "tegra-aes", "sclk", &tegra_clk_sbus_cmplx, NULL, 0, 0),
6976 SHARED_CLK("usbd.sclk", "tegra-udc.0", "sclk", &tegra_clk_sbus_cmplx, NULL, 0, 0),
6977 SHARED_CLK("usb1.sclk", "tegra-ehci.0", "sclk", &tegra_clk_sbus_cmplx, NULL, 0, 0),
6978 SHARED_CLK("usb2.sclk", "tegra-ehci.1", "sclk", &tegra_clk_sbus_cmplx, NULL, 0, 0),
6979 SHARED_CLK("usb3.sclk", "tegra-ehci.2", "sclk", &tegra_clk_sbus_cmplx, NULL, 0, 0),
6980 SHARED_CLK("sdmmc3.sclk", "sdhci-tegra.2", "sclk", &tegra_clk_sbus_cmplx, NULL, 0, 0),
6981 SHARED_CLK("sdmmc4.sclk", "sdhci-tegra.3", "sclk", &tegra_clk_sbus_cmplx, NULL, 0, 0),
6982 SHARED_CLK("wake.sclk", "wake_sclk", "sclk", &tegra_clk_sbus_cmplx, NULL, 0, 0),
6983 SHARED_CLK("camera.sclk", "vi", "sclk", &tegra_clk_sbus_cmplx, NULL, 0, 0),
6984 SHARED_CLK("mon.avp", "tegra_actmon", "avp", &tegra_clk_sbus_cmplx, NULL, 0, 0),
6985 SHARED_CLK("cap.sclk", "cap_sclk", NULL, &tegra_clk_sbus_cmplx, NULL, 0, SHARED_CEILING),
6986 SHARED_CLK("cap.throttle.sclk", "cap_throttle", NULL, &tegra_clk_sbus_cmplx, NULL, 0, SHARED_CEILING),
6987 SHARED_CLK("floor.sclk", "floor_sclk", NULL, &tegra_clk_sbus_cmplx, NULL, 0, 0),
6988 SHARED_CLK("override.sclk", "override_sclk", NULL, &tegra_clk_sbus_cmplx, NULL, 0, SHARED_OVERRIDE),
6990 SHARED_EMC_CLK("avp.emc", "tegra-avp", "emc", &tegra_clk_emc, NULL, 0, 0, 0),
6991 SHARED_EMC_CLK("disp1.emc", "tegradc.0", "emc", &tegra_clk_emc,
6992 NULL, 0, SHARED_ISO_BW, BIT(EMC_USER_DC1)),
6993 SHARED_EMC_CLK("disp2.emc", "tegradc.1", "emc", &tegra_clk_emc,
6994 NULL, 0, SHARED_ISO_BW, BIT(EMC_USER_DC2)),
6995 SHARED_EMC_CLK("mon_cpu.emc", "tegra_mon", "cpu_emc",
6996 &tegra_clk_emc, NULL, 0, 0, 0),
6997 SHARED_EMC_CLK("hdmi.emc", "hdmi", "emc", &tegra_clk_emc, NULL, 0, 0, 0),
6998 SHARED_EMC_CLK("usbd.emc", "tegra-udc.0", "emc", &tegra_clk_emc, NULL, 0, 0, 0),
6999 SHARED_EMC_CLK("usb1.emc", "tegra-ehci.0", "emc", &tegra_clk_emc, NULL, 0, 0, 0),
7000 SHARED_EMC_CLK("usb2.emc", "tegra-ehci.1", "emc", &tegra_clk_emc, NULL, 0, 0, 0),
7001 SHARED_EMC_CLK("usb3.emc", "tegra-ehci.2", "emc", &tegra_clk_emc, NULL, 0, 0, 0),
7002 SHARED_EMC_CLK("mon.emc", "tegra_actmon", "emc", &tegra_clk_emc, NULL, 0, 0, 0),
7003 SHARED_EMC_CLK("cap.emc", "cap.emc", NULL, &tegra_clk_emc, NULL, 0, SHARED_CEILING, 0),
7004 SHARED_EMC_CLK("cap.throttle.emc", "cap_throttle", NULL, &tegra_clk_emc, NULL, 0, SHARED_CEILING, 0),
7005 SHARED_EMC_CLK("3d.emc", "tegra_gr3d", "emc", &tegra_clk_emc, NULL, 0, 0, BIT(EMC_USER_3D)),
7006 SHARED_EMC_CLK("2d.emc", "tegra_gr2d", "emc", &tegra_clk_emc, NULL, 0, 0, BIT(EMC_USER_2D)),
7007 SHARED_EMC_CLK("msenc.emc", "tegra_msenc", "emc", &tegra_clk_emc, NULL, 0, SHARED_BW, BIT(EMC_USER_MSENC)),
7008 SHARED_EMC_CLK("tsec.emc", "tegra_tsec", "emc", &tegra_clk_emc, NULL, 0, 0, 0),
7009 SHARED_EMC_CLK("sdmmc3.emc", "sdhci-tegra.2", "emc", &tegra_clk_emc, NULL, 0, 0, 0),
7010 SHARED_EMC_CLK("sdmmc4.emc", "sdhci-tegra.3", "emc", &tegra_clk_emc, NULL, 0, 0, 0),
7011 SHARED_EMC_CLK("camera.emc", "vi", "emc", &tegra_clk_emc, NULL, 0, SHARED_ISO_BW, BIT(EMC_USER_VI)),
7012 SHARED_EMC_CLK("iso.emc", "iso", "emc", &tegra_clk_emc, NULL, 0, 0, 0),
7013 SHARED_EMC_CLK("floor.emc", "floor.emc", NULL, &tegra_clk_emc, NULL, 0, 0, 0),
7014 SHARED_EMC_CLK("override.emc", "override.emc", NULL, &tegra_clk_emc, NULL, 0, SHARED_OVERRIDE, 0),
7015 SHARED_EMC_CLK("edp.emc", "edp.emc", NULL, &tegra_clk_emc, NULL, 0, SHARED_CEILING, 0),
7016 SHARED_EMC_CLK("battery.emc", "battery_edp", "emc", &tegra_clk_emc, NULL, 0, SHARED_CEILING, 0),
7017 SHARED_EMC_CLK("floor.profile.emc", "profile.emc", NULL, &tegra_clk_emc, NULL, 0, 0, 0),
7019 #ifdef CONFIG_TEGRA_DUAL_CBUS
7020 DUAL_CBUS_CLK("3d.cbus", "tegra_gr3d", "gr3d", &tegra_clk_c2bus, "3d", 0, 0),
7021 DUAL_CBUS_CLK("2d.cbus", "tegra_gr2d", "gr2d", &tegra_clk_c2bus, "2d", 0, 0),
7022 DUAL_CBUS_CLK("epp.cbus", "tegra_gr2d", "epp", &tegra_clk_c2bus, "epp", 0, 0),
7023 SHARED_CLK("cap.c2bus", "cap.c2bus", NULL, &tegra_clk_c2bus, NULL, 0, SHARED_CEILING),
7024 SHARED_CLK("cap.throttle.c2bus", "cap_throttle", NULL, &tegra_clk_c2bus, NULL, 0, SHARED_CEILING),
7025 SHARED_CLK("floor.c2bus", "floor.c2bus", NULL, &tegra_clk_c2bus, NULL, 0, 0),
7026 SHARED_CLK("override.c2bus", "override.c2bus", NULL, &tegra_clk_c2bus, NULL, 0, SHARED_OVERRIDE),
7027 SHARED_CLK("edp.c2bus", "edp.c2bus", NULL, &tegra_clk_c2bus, NULL, 0, SHARED_CEILING),
7028 SHARED_CLK("battery.c2bus", "battery_edp", "gpu", &tegra_clk_c2bus, NULL, 0, SHARED_CEILING),
7029 SHARED_CLK("cap.profile.c2bus", "profile.c2bus", NULL, &tegra_clk_c2bus, NULL, 0, SHARED_CEILING),
7030 SHARED_CLK("floor.profile.c2bus", "profile.c2bus", NULL, &tegra_clk_c2bus, NULL, 0, 0),
7032 DUAL_CBUS_CLK("msenc.cbus", "tegra_msenc", "msenc", &tegra_clk_c3bus, "msenc", 0, 0),
7033 DUAL_CBUS_CLK("tsec.cbus", "tegra_tsec", "tsec", &tegra_clk_c3bus, "tsec", 0, 0),
7034 DUAL_CBUS_CLK("vde.cbus", "tegra-avp", "vde", &tegra_clk_c3bus, "vde", 0, 0),
7035 DUAL_CBUS_CLK("se.cbus", "tegra11-se", NULL, &tegra_clk_c3bus, "se", 0, 0),
7036 SHARED_CLK("cap.c3bus", "cap.c3bus", NULL, &tegra_clk_c3bus, NULL, 0, SHARED_CEILING),
7037 SHARED_CLK("cap.throttle.c3bus", "cap_throttle", NULL, &tegra_clk_c3bus, NULL, 0, SHARED_CEILING),
7038 SHARED_CLK("floor.c3bus", "floor.c3bus", NULL, &tegra_clk_c3bus, NULL, 0, 0),
7039 SHARED_CLK("override.c3bus", "override.c3bus", NULL, &tegra_clk_c3bus, NULL, 0, SHARED_OVERRIDE),
7041 SHARED_CLK("3d.cbus", "tegra_gr3d", "gr3d", &tegra_clk_cbus, "3d", 0, 0),
7042 SHARED_CLK("2d.cbus", "tegra_gr2d", "gr2d", &tegra_clk_cbus, "2d", 0, 0),
7043 SHARED_CLK("epp.cbus", "tegra_gr2d", "epp", &tegra_clk_cbus, "epp", 0, 0),
7044 SHARED_CLK("msenc.cbus","tegra_msenc", "msenc",&tegra_clk_cbus, "msenc", 0, 0),
7045 SHARED_CLK("tsec.cbus", "tegra_tsec", "tsec", &tegra_clk_cbus, "tsec", 0, 0),
7046 SHARED_CLK("vde.cbus", "tegra-avp", "vde", &tegra_clk_cbus, "vde", 0, 0),
7047 SHARED_CLK("se.cbus", "tegra11-se", NULL, &tegra_clk_cbus, "se", 0, 0),
7048 SHARED_CLK("cap.cbus", "cap.cbus", NULL, &tegra_clk_cbus, NULL, 0, SHARED_CEILING),
7049 SHARED_CLK("cap.throttle.cbus", "cap_throttle", NULL, &tegra_clk_cbus, NULL, 0, SHARED_CEILING),
7050 SHARED_CLK("floor.cbus", "floor.cbus", NULL, &tegra_clk_cbus, NULL, 0, 0),
7051 SHARED_CLK("override.cbus", "override.cbus", NULL, &tegra_clk_cbus, NULL, 0, SHARED_OVERRIDE),
7052 SHARED_CLK("edp.cbus", "edp.cbus", NULL, &tegra_clk_cbus, NULL, 0, SHARED_CEILING),
7053 SHARED_CLK("battery.cbus", "battery_edp", "gpu", &tegra_clk_cbus, NULL, 0, SHARED_CEILING),
7054 SHARED_CLK("cap.profile.cbus", "profile.cbus", NULL, &tegra_clk_cbus, NULL, 0, SHARED_CEILING),
7055 SHARED_CLK("floor.profile.cbus", "profile.cbus", NULL, &tegra_clk_cbus, NULL, 0, 0),
7057 SHARED_CLK("nv.host1x", "tegra_host1x", "host1x", &tegra_clk_host1x, NULL, 0, 0),
7058 SHARED_CLK("vi.host1x", "tegra_vi", "host1x", &tegra_clk_host1x, NULL, 0, 0),
7059 SHARED_CLK("cap.host1x", "cap.host1x", NULL, &tegra_clk_host1x, NULL, 0, SHARED_CEILING),
7060 SHARED_CLK("floor.host1x", "floor.host1x", NULL, &tegra_clk_host1x, NULL, 0, 0),
7061 SHARED_CLK("override.host1x", "override.host1x", NULL, &tegra_clk_host1x, NULL, 0, SHARED_OVERRIDE),
7062 SHARED_CLK("floor.profile.host1x", "profile.host1x", NULL, &tegra_clk_host1x, NULL, 0, 0),
7064 SHARED_CLK("sbc1.sclk", "spi_tegra.0", "sclk", &tegra_clk_sbus_cmplx, NULL, 0, 0),
7065 SHARED_CLK("sbc2.sclk", "spi_tegra.1", "sclk", &tegra_clk_sbus_cmplx, NULL, 0, 0),
7066 SHARED_CLK("sbc3.sclk", "spi_tegra.2", "sclk", &tegra_clk_sbus_cmplx, NULL, 0, 0),
7067 SHARED_CLK("sbc4.sclk", "spi_tegra.3", "sclk", &tegra_clk_sbus_cmplx, NULL, 0, 0),
7068 SHARED_CLK("sbc5.sclk", "spi_tegra.4", "sclk", &tegra_clk_sbus_cmplx, NULL, 0, 0),
7069 SHARED_CLK("sbc6.sclk", "spi_tegra.5", "sclk", &tegra_clk_sbus_cmplx, NULL, 0, 0),
7074 #define XUSB_ID "tegra-xhci"
7076 static struct clk tegra_clk_xusb_gate = {
7077 .name = "xusb_gate",
7078 .flags = ENABLE_ON_INIT | PERIPH_NO_RESET,
7079 .ops = &tegra_xusb_gate_clk_ops,
7081 .max_rate = 48000000,
7087 static struct clk tegra_xusb_source_clks[] = {
7088 PERIPH_CLK("xusb_host_src", XUSB_ID, "host_src", 143, 0x600, 120000000, mux_clkm_pllp_pllc_pllre, MUX | MUX8 | DIV_U71 | DIV_U71_INT | PERIPH_NO_RESET | PERIPH_ON_APB),
7089 PERIPH_CLK("xusb_falcon_src", XUSB_ID, "falcon_src", 143, 0x604, 350000000, mux_clkm_pllp_pllc_pllre, MUX | MUX8 | DIV_U71 | DIV_U71_INT | PERIPH_NO_RESET),
7090 PERIPH_CLK("xusb_fs_src", XUSB_ID, "fs_src", 143, 0x608, 48000000, mux_clkm_48M_pllp_480M, MUX | DIV_U71 | DIV_U71_INT | PERIPH_NO_RESET),
7091 PERIPH_CLK("xusb_ss_src", XUSB_ID, "ss_src", 143, 0x610, 122400000, mux_clkm_pllre_clk32_480M_pllc_ref, MUX | MUX8 | DIV_U71 | DIV_U71_INT | PERIPH_NO_RESET),
7092 PERIPH_CLK("xusb_dev_src", XUSB_ID, "dev_src", 95, 0x60c, 120000000, mux_clkm_pllp_pllc_pllre, MUX | MUX8 | DIV_U71 | DIV_U71_INT | PERIPH_NO_RESET | PERIPH_ON_APB),
7093 SHARED_EMC_CLK("xusb.emc", XUSB_ID, "emc", &tegra_clk_emc, NULL, 0, SHARED_BW, 0),
7096 static struct clk tegra_xusb_ss_div2 = {
7097 .name = "xusb_ss_div2",
7098 .ops = &tegra_clk_m_div_ops,
7099 .parent = &tegra_xusb_source_clks[3],
7103 .max_rate = 61200000,
7106 static struct clk_mux_sel mux_ss_div2_pllu_60M[] = {
7107 { .input = &tegra_xusb_ss_div2, .value = 0},
7108 { .input = &tegra_pll_u_60M, .value = 1},
7112 static struct clk tegra_xusb_hs_src = {
7113 .name = "xusb_hs_src",
7118 .ops = &tegra_periph_clk_ops,
7120 .inputs = mux_ss_div2_pllu_60M,
7121 .flags = PLLU | PERIPH_NO_ENB,
7122 .max_rate = 61200000,
7124 .src_mask = 0x1 << 25,
7129 static struct clk_mux_sel mux_xusb_host[] = {
7130 { .input = &tegra_xusb_source_clks[0], .value = 0},
7131 { .input = &tegra_xusb_source_clks[1], .value = 1},
7132 { .input = &tegra_xusb_source_clks[2], .value = 2},
7133 { .input = &tegra_xusb_hs_src, .value = 5},
7137 static struct clk_mux_sel mux_xusb_ss[] = {
7138 { .input = &tegra_xusb_source_clks[3], .value = 3},
7139 { .input = &tegra_xusb_source_clks[0], .value = 0},
7140 { .input = &tegra_xusb_source_clks[1], .value = 1},
7144 static struct clk_mux_sel mux_xusb_dev[] = {
7145 { .input = &tegra_xusb_source_clks[4], .value = 4},
7146 { .input = &tegra_xusb_source_clks[2], .value = 2},
7147 { .input = &tegra_xusb_source_clks[3], .value = 3},
7151 static struct clk tegra_xusb_coupled_clks[] = {
7152 PERIPH_CLK_EX("xusb_host", XUSB_ID, "host", 89, 0, 350000000, mux_xusb_host, 0, &tegra_clk_coupled_gate_ops),
7153 PERIPH_CLK_EX("xusb_ss", XUSB_ID, "ss", 156, 0, 350000000, mux_xusb_ss, 0, &tegra_clk_coupled_gate_ops),
7154 PERIPH_CLK_EX("xusb_dev", XUSB_ID, "dev", 95, 0, 120000000, mux_xusb_dev, 0, &tegra_clk_coupled_gate_ops),
7157 #define CLK_DUPLICATE(_name, _dev, _con) \
7166 /* Some clocks may be used by different drivers depending on the board
7167 * configuration. List those here to register them twice in the clock lookup
7168 * table under two names.
7170 struct clk_duplicate tegra_clk_duplicates[] = {
7171 CLK_DUPLICATE("uarta", "serial8250.0", NULL),
7172 CLK_DUPLICATE("uartb", "serial8250.1", NULL),
7173 CLK_DUPLICATE("uartc", "serial8250.2", NULL),
7174 CLK_DUPLICATE("uartd", "serial8250.3", NULL),
7175 CLK_DUPLICATE("uarte", "serial8250.4", NULL),
7176 CLK_DUPLICATE("usbd", XUSB_ID, "utmip-pad"),
7177 CLK_DUPLICATE("usbd", "utmip-pad", NULL),
7178 CLK_DUPLICATE("usbd", "tegra-ehci.0", NULL),
7179 CLK_DUPLICATE("usbd", "tegra-otg", NULL),
7180 CLK_DUPLICATE("disp1", "tegra_dc_dsi_vs1.0", NULL),
7181 CLK_DUPLICATE("disp1.emc", "tegra_dc_dsi_vs1.0", "emc"),
7182 CLK_DUPLICATE("disp1", "tegra_dc_dsi_vs1.1", NULL),
7183 CLK_DUPLICATE("disp1.emc", "tegra_dc_dsi_vs1.1", "emc"),
7184 CLK_DUPLICATE("hdmi", "tegradc.0", "hdmi"),
7185 CLK_DUPLICATE("hdmi", "tegradc.1", "hdmi"),
7186 CLK_DUPLICATE("dsib", "tegradc.0", "dsib"),
7187 CLK_DUPLICATE("dsia", "tegradc.1", "dsia"),
7188 CLK_DUPLICATE("dsiblp", "tegradc.0", "dsiblp"),
7189 CLK_DUPLICATE("dsialp", "tegradc.1", "dsialp"),
7190 CLK_DUPLICATE("dsia", "tegra_dc_dsi_vs1.0", "dsia"),
7191 CLK_DUPLICATE("dsia", "tegra_dc_dsi_vs1.1", "dsia"),
7192 CLK_DUPLICATE("dsialp", "tegra_dc_dsi_vs1.0", "dsialp"),
7193 CLK_DUPLICATE("dsialp", "tegra_dc_dsi_vs1.1", "dsialp"),
7194 CLK_DUPLICATE("dsi1-fixed", "tegra_dc_dsi_vs1.0", "dsi-fixed"),
7195 CLK_DUPLICATE("dsi1-fixed", "tegra_dc_dsi_vs1.1", "dsi-fixed"),
7196 CLK_DUPLICATE("cop", "tegra-avp", "cop"),
7197 CLK_DUPLICATE("bsev", "tegra-avp", "bsev"),
7198 CLK_DUPLICATE("cop", "nvavp", "cop"),
7199 CLK_DUPLICATE("bsev", "nvavp", "bsev"),
7200 CLK_DUPLICATE("vde", "tegra-aes", "vde"),
7201 CLK_DUPLICATE("bsea", "tegra-aes", "bsea"),
7202 CLK_DUPLICATE("bsea", "nvavp", "bsea"),
7203 CLK_DUPLICATE("pciex", "tegra_pcie", "pciex"),
7204 CLK_DUPLICATE("clk_m", NULL, "apb_pclk"),
7205 CLK_DUPLICATE("i2c1", "tegra-i2c-slave.0", NULL),
7206 CLK_DUPLICATE("i2c2", "tegra-i2c-slave.1", NULL),
7207 CLK_DUPLICATE("i2c3", "tegra-i2c-slave.2", NULL),
7208 CLK_DUPLICATE("i2c4", "tegra-i2c-slave.3", NULL),
7209 CLK_DUPLICATE("i2c5", "tegra-i2c-slave.4", NULL),
7210 CLK_DUPLICATE("cl_dvfs_soc", "tegra11-i2c.4", NULL),
7211 CLK_DUPLICATE("cl_dvfs_ref", "tegra11-i2c.4", NULL),
7212 CLK_DUPLICATE("sbc1", "tegra11-spi-slave.0", NULL),
7213 CLK_DUPLICATE("sbc2", "tegra11-spi-slave.1", NULL),
7214 CLK_DUPLICATE("sbc3", "tegra11-spi-slave.2", NULL),
7215 CLK_DUPLICATE("sbc4", "tegra11-spi-slave.3", NULL),
7216 CLK_DUPLICATE("sbc5", "tegra11-spi-slave.4", NULL),
7217 CLK_DUPLICATE("sbc6", "tegra11-spi-slave.5", NULL),
7218 CLK_DUPLICATE("vcp", "nvavp", "vcp"),
7219 CLK_DUPLICATE("avp.sclk", "nvavp", "sclk"),
7220 CLK_DUPLICATE("avp.emc", "nvavp", "emc"),
7221 CLK_DUPLICATE("vde.cbus", "nvavp", "vde"),
7222 CLK_DUPLICATE("i2c5", "tegra_cl_dvfs", "i2c"),
7223 CLK_DUPLICATE("cpu_g", "tegra_cl_dvfs", "safe_dvfs"),
7224 CLK_DUPLICATE("epp.cbus", "tegra_isp", "epp"),
7225 CLK_DUPLICATE("i2s0", NULL, "i2s0"),
7226 CLK_DUPLICATE("i2s1", NULL, "i2s1"),
7227 CLK_DUPLICATE("i2s2", NULL, "i2s2"),
7228 CLK_DUPLICATE("i2s3", NULL, "i2s3"),
7229 CLK_DUPLICATE("i2s4", NULL, "i2s4"),
7230 CLK_DUPLICATE("dam0", NULL, "dam0"),
7231 CLK_DUPLICATE("dam1", NULL, "dam1"),
7232 CLK_DUPLICATE("dam2", NULL, "dam2"),
7233 CLK_DUPLICATE("spdif_in", NULL, "spdif_in"),
7234 CLK_DUPLICATE("mclk", NULL, "default_mclk"),
7237 struct clk *tegra_ptr_clks[] = {
7260 &tegra_clk_xusb_gate,
7278 &tegra_clk_virtual_cpu_g,
7279 &tegra_clk_virtual_cpu_lp,
7280 &tegra_clk_cpu_cmplx,
7283 &tegra_clk_sbus_cmplx,
7286 #ifdef CONFIG_TEGRA_DUAL_CBUS
7294 /* Return true from this function if the target rate can be locked without
7295 switching pll clients to back-up source */
7296 static bool tegra11_is_dyn_ramp(
7297 struct clk *c, unsigned long rate, bool from_vco_min)
7299 #if PLLCX_USE_DYN_RAMP
7300 /* PLLC2, PLLC3 support dynamic ramp only when output divider <= 8 */
7301 if ((c == &tegra_pll_c2) || (c == &tegra_pll_c3)) {
7302 struct clk_pll_freq_table cfg, old_cfg;
7303 unsigned long input_rate = clk_get_rate(c->parent);
7305 u32 val = clk_readl(c->reg + PLL_BASE);
7306 PLL_BASE_PARSE(PLLCX, old_cfg, val);
7307 old_cfg.p = pllcx_p[old_cfg.p];
7309 if (!pll_dyn_ramp_find_cfg(c, &cfg, rate, input_rate, NULL)) {
7310 if ((cfg.n == old_cfg.n) ||
7311 PLLCX_IS_DYN(cfg.p, old_cfg.p))
7317 #if PLLXC_USE_DYN_RAMP
7318 /* PPLX, PLLC support dynamic ramp when changing NDIV only */
7319 if ((c == &tegra_pll_x) || (c == &tegra_pll_c)) {
7320 struct clk_pll_freq_table cfg, old_cfg;
7321 unsigned long input_rate = clk_get_rate(c->parent);
7324 old_cfg.m = PLL_FIXED_MDIV(c, input_rate);
7327 u32 val = clk_readl(c->reg + PLL_BASE);
7328 PLL_BASE_PARSE(PLLXC, old_cfg, val);
7329 old_cfg.p = pllxc_p[old_cfg.p];
7332 if (!pll_dyn_ramp_find_cfg(c, &cfg, rate, input_rate, NULL)) {
7333 if ((cfg.m == old_cfg.m) && (cfg.p == old_cfg.p))
7342 * Backup pll is used as transitional CPU clock source while main pll is
7343 * relocking; in addition all CPU rates below backup level are sourced from
7344 * backup pll only. Target backup levels for each CPU mode are selected high
7345 * enough to avoid voltage droop when CPU clock is switched between backup and
7346 * main plls. Actual backup rates will be rounded to match backup source fixed
7347 * frequency. Backup rates are also used as stay-on-backup thresholds, and must
7348 * be kept the same in G and LP mode (will need to add a separate stay-on-backup
7349 * parameter to allow different backup rates if necessary).
7351 * Sbus threshold must be exact factor of pll_p rate.
7353 #define CPU_G_BACKUP_RATE_TARGET 200000000
7354 #define CPU_LP_BACKUP_RATE_TARGET 200000000
7356 static void tegra11_pllp_init_dependencies(unsigned long pllp_rate)
7359 unsigned long backup_rate;
7361 switch (pllp_rate) {
7363 tegra_pll_p_out1.u.pll_div.default_rate = 28800000;
7364 tegra_pll_p_out3.u.pll_div.default_rate = 72000000;
7365 tegra_clk_sbus_cmplx.u.system.threshold = 108000000;
7366 tegra_clk_host1x.u.periph.threshold = 108000000;
7369 tegra_pll_p_out1.u.pll_div.default_rate = 9600000;
7370 tegra_pll_p_out3.u.pll_div.default_rate = 102000000;
7371 tegra_clk_sbus_cmplx.u.system.threshold = 204000000;
7372 tegra_clk_host1x.u.periph.threshold = 204000000;
7375 tegra_pll_p_out1.u.pll_div.default_rate = 4800000;
7376 tegra_pll_p_out3.u.pll_div.default_rate = 102000000;
7377 tegra_clk_sbus_cmplx.u.system.threshold = 204000000;
7378 tegra_clk_host1x.u.periph.threshold = 204000000;
7381 pr_err("tegra: PLLP rate: %lu is not supported\n", pllp_rate);
7384 pr_info("tegra: PLLP fixed rate: %lu\n", pllp_rate);
7386 div = pllp_rate / CPU_G_BACKUP_RATE_TARGET;
7387 backup_rate = pllp_rate / div;
7388 tegra_clk_virtual_cpu_g.u.cpu.backup_rate = backup_rate;
7390 div = pllp_rate / CPU_LP_BACKUP_RATE_TARGET;
7391 backup_rate = pllp_rate / div;
7392 tegra_clk_virtual_cpu_lp.u.cpu.backup_rate = backup_rate;
7395 static void tegra11_init_one_clock(struct clk *c)
7398 INIT_LIST_HEAD(&c->shared_bus_list);
7399 if (!c->lookup.dev_id && !c->lookup.con_id)
7400 c->lookup.con_id = c->name;
7402 clkdev_add(&c->lookup);
7405 /* Direct access to CPU clock sources fot CPU idle driver */
7406 int tegra11_cpu_g_idle_rate_exchange(unsigned long *rate)
7409 struct clk *dfll = tegra_clk_cpu_cmplx.parent->u.cpu.dynamic;
7410 unsigned long old_rate, new_rate, flags;
7412 if (!dfll || !tegra_dvfs_rail_is_dfll_mode(tegra_cpu_rail))
7415 /* Clipping min to oscillator rate is pretty much arbitrary */
7416 new_rate = max(*rate, tegra_clk_m.rate);
7418 clk_lock_save(dfll, &flags);
7420 old_rate = clk_get_rate_locked(dfll);
7422 if (new_rate != old_rate)
7423 ret = clk_set_rate_locked(dfll, new_rate);
7425 clk_unlock_restore(dfll, &flags);
7429 int tegra11_cpu_lp_idle_rate_exchange(unsigned long *rate)
7432 struct clk *backup = tegra_clk_cpu_cmplx.parent->u.cpu.backup;
7433 unsigned long old_rate, flags;
7434 unsigned long new_rate = min(
7435 *rate, tegra_clk_cpu_cmplx.parent->u.cpu.backup_rate);
7437 clk_lock_save(backup, &flags);
7439 old_rate = clk_get_rate_locked(backup);
7441 if (new_rate != old_rate)
7442 ret = clk_set_rate_locked(backup, new_rate);
7444 clk_unlock_restore(backup, &flags);
7448 void tegra_edp_throttle_cpu_now(u8 factor)
7450 /* empty definition for tegra11 */
7454 bool tegra_clk_is_parent_allowed(struct clk *c, struct clk *p)
7457 * Most of the Tegra11 multimedia and peripheral muxes include pll_c2
7458 * and pll_c3 as possible inputs. However, per clock policy these plls
7459 * are allowed to be used only by handful devices aggregated on cbus.
7460 * For all others, instead of enforcing policy at run-time in this
7461 * function, we simply stripped out pll_c2 and pll_c3 options from the
7462 * respective muxes statically.
7466 * In configuration with dual cbus pll_c can be used as a scaled clock
7467 * source for EMC only when pll_m is fixed, or as a general fixed rate
7468 * clock source for EMC and other peripherals if pll_m is scaled. In
7469 * configuration with single cbus pll_c can be used as a scaled cbus
7470 * clock source only. No direct use for pll_c by super clocks.
7472 if ((p == &tegra_pll_c) && (c != &tegra_pll_c_out1)) {
7473 if (c->ops == &tegra_super_ops)
7475 #ifdef CONFIG_TEGRA_DUAL_CBUS
7476 #ifndef CONFIG_TEGRA_PLLM_SCALED
7477 return c->flags & PERIPH_EMC_ENB;
7480 return c->flags & PERIPH_ON_CBUS;
7485 * In any configuration pll_m must not be used as a clock source for
7486 * cbus modules. If pll_m is scaled it can be used as EMC source only.
7487 * Otherwise fixed rate pll_m can be used as clock source for EMC and
7488 * other peripherals. No direct use for pll_m by super clocks.
7490 if ((p == &tegra_pll_m) && (c != &tegra_pll_m_out1)) {
7491 if (c->ops == &tegra_super_ops)
7494 if (c->flags & PERIPH_ON_CBUS)
7496 #ifdef CONFIG_TEGRA_PLLM_SCALED
7497 return c->flags & PERIPH_EMC_ENB;
7503 /* Internal LA may request some clocks to be enabled on init via TRANSACTION
7504 SCRATCH register settings */
7505 void __init tegra11x_clk_init_la(void)
7508 u32 reg = readl(misc_gp_base + MISC_GP_TRANSACTOR_SCRATCH_0);
7510 if (!(reg & MISC_GP_TRANSACTOR_SCRATCH_LA_ENABLE))
7513 c = tegra_get_clock_by_name("la");
7514 if (WARN(!c, "%s: could not find la clk\n", __func__))
7518 if (reg & MISC_GP_TRANSACTOR_SCRATCH_DDS_ENABLE) {
7519 c = tegra_get_clock_by_name("dds");
7520 if (WARN(!c, "%s: could not find la clk\n", __func__))
7524 if (reg & MISC_GP_TRANSACTOR_SCRATCH_DP2_ENABLE) {
7525 c = tegra_get_clock_by_name("dp2");
7526 if (WARN(!c, "%s: could not find la clk\n", __func__))
7530 c = tegra_get_clock_by_name("hdmi");
7531 if (WARN(!c, "%s: could not find la clk\n", __func__))
7537 #ifdef CONFIG_CPU_FREQ
7540 * Frequency table index must be sequential starting at 0 and frequencies
7541 * must be ascending.
7543 #define CPU_FREQ_STEP 102000 /* 102MHz cpu_g table step */
7544 #define CPU_FREQ_TABLE_MAX_SIZE (2 * MAX_DVFS_FREQS + 1)
7546 static struct cpufreq_frequency_table freq_table[CPU_FREQ_TABLE_MAX_SIZE];
7547 static struct tegra_cpufreq_table_data freq_table_data;
7549 struct tegra_cpufreq_table_data *tegra_cpufreq_table_get(void)
7552 bool g_vmin_done = false;
7553 unsigned int freq, lp_backup_freq, g_vmin_freq, g_start_freq, max_freq;
7554 struct clk *cpu_clk_g = tegra_get_clock_by_name("cpu_g");
7555 struct clk *cpu_clk_lp = tegra_get_clock_by_name("cpu_lp");
7557 /* Initialize once */
7558 if (freq_table_data.freq_table)
7559 return &freq_table_data;
7562 for (i = 0; i < CPU_FREQ_TABLE_MAX_SIZE; i++) {
7563 freq_table[i].index = i;
7564 freq_table[i].frequency = CPUFREQ_TABLE_END;
7567 lp_backup_freq = cpu_clk_lp->u.cpu.backup_rate / 1000;
7568 if (!lp_backup_freq) {
7569 WARN(1, "%s: cannot make cpufreq table: no LP CPU backup rate\n",
7573 if (!cpu_clk_lp->dvfs) {
7574 WARN(1, "%s: cannot make cpufreq table: no LP CPU dvfs\n",
7578 if (!cpu_clk_g->dvfs) {
7579 WARN(1, "%s: cannot make cpufreq table: no G CPU dvfs\n",
7583 g_vmin_freq = cpu_clk_g->dvfs->freqs[0] / 1000;
7584 if (g_vmin_freq <= lp_backup_freq) {
7585 WARN(1, "%s: cannot make cpufreq table: LP CPU backup rate"
7586 " exceeds G CPU rate at Vmin\n", __func__);
7590 /* Start with backup frequencies */
7592 freq = lp_backup_freq;
7593 freq_table[i++].frequency = freq/4;
7594 freq_table[i++].frequency = freq/2;
7595 freq_table[i++].frequency = freq;
7597 /* Throttle low index at backup level*/
7598 freq_table_data.throttle_lowest_index = i - 1;
7601 * Next, set table steps along LP CPU dvfs ladder, but make sure G CPU
7602 * dvfs rate at minimum voltage is not missed (if it happens to be below
7605 max_freq = cpu_clk_lp->max_rate / 1000;
7606 for (j = 0; j < cpu_clk_lp->dvfs->num_freqs; j++) {
7607 freq = cpu_clk_lp->dvfs->freqs[j] / 1000;
7608 if (freq <= lp_backup_freq)
7611 if (!g_vmin_done && (freq >= g_vmin_freq)) {
7613 if (freq > g_vmin_freq)
7614 freq_table[i++].frequency = g_vmin_freq;
7616 freq_table[i++].frequency = freq;
7618 if (freq == max_freq)
7622 /* Set G CPU min rate at least one table step below LP maximum */
7623 cpu_clk_g->min_rate = min(freq_table[i-2].frequency, g_vmin_freq)*1000;
7625 /* Suspend index at max LP CPU */
7626 freq_table_data.suspend_index = i - 1;
7628 /* Fill in "hole" (if any) between LP CPU maximum rate and G CPU dvfs
7629 ladder rate at minimum voltage */
7630 if (freq < g_vmin_freq) {
7631 int n = (g_vmin_freq - freq) / CPU_FREQ_STEP;
7632 for (j = 0; j <= n; j++) {
7633 freq = g_vmin_freq - CPU_FREQ_STEP * (n - j);
7634 freq_table[i++].frequency = freq;
7638 /* Now, step along the rest of G CPU dvfs ladder */
7639 g_start_freq = freq;
7640 max_freq = cpu_clk_g->max_rate / 1000;
7641 for (j = 0; j < cpu_clk_g->dvfs->num_freqs; j++) {
7642 freq = cpu_clk_g->dvfs->freqs[j] / 1000;
7643 if (freq > g_start_freq)
7644 freq_table[i++].frequency = freq;
7645 if (freq == max_freq)
7649 /* Throttle high index one step below maximum */
7650 BUG_ON(i >= CPU_FREQ_TABLE_MAX_SIZE);
7651 freq_table_data.throttle_highest_index = i - 2;
7652 freq_table_data.freq_table = freq_table;
7653 return &freq_table_data;
7656 unsigned long tegra_emc_to_cpu_ratio(unsigned long cpu_rate)
7658 static unsigned long emc_max_rate;
7660 if (emc_max_rate == 0)
7661 emc_max_rate = clk_round_rate(
7662 tegra_get_clock_by_name("emc"), ULONG_MAX);
7664 /* Vote on memory bus frequency based on cpu frequency;
7665 cpu rate is in kHz, emc rate is in Hz */
7666 if (cpu_rate >= 1500000)
7667 return emc_max_rate; /* cpu >= 1.5GHz, emc max */
7668 else if (cpu_rate >= 975000)
7669 return 400000000; /* cpu >= 975 MHz, emc 400 MHz */
7670 else if (cpu_rate >= 725000)
7671 return 200000000; /* cpu >= 725 MHz, emc 200 MHz */
7672 else if (cpu_rate >= 500000)
7673 return 100000000; /* cpu >= 500 MHz, emc 100 MHz */
7674 else if (cpu_rate >= 275000)
7675 return 50000000; /* cpu >= 275 MHz, emc 50 MHz */
7677 return 0; /* emc min */
7680 int tegra_update_mselect_rate(unsigned long cpu_rate)
7682 static struct clk *mselect = NULL;
7684 unsigned long mselect_rate;
7687 mselect = tegra_get_clock_by_name("mselect");
7692 /* Vote on mselect frequency based on cpu frequency:
7693 keep mselect at half of cpu rate up to 102 MHz;
7694 cpu rate is in kHz, mselect rate is in Hz */
7695 mselect_rate = DIV_ROUND_UP(cpu_rate, 2) * 1000;
7696 mselect_rate = min(mselect_rate, 102000000UL);
7698 if (mselect_rate != clk_get_rate(mselect))
7699 return clk_set_rate(mselect, mselect_rate);
7705 #ifdef CONFIG_PM_SLEEP
7706 static u32 clk_rst_suspend[RST_DEVICES_NUM + CLK_OUT_ENB_NUM +
7707 PERIPH_CLK_SOURCE_NUM + 25];
7709 static int tegra11_clk_suspend(void)
7712 u32 *ctx = clk_rst_suspend;
7714 *ctx++ = clk_readl(OSC_CTRL) & OSC_CTRL_MASK;
7715 *ctx++ = clk_readl(CPU_SOFTRST_CTRL);
7716 *ctx++ = clk_readl(CPU_SOFTRST_CTRL1);
7717 *ctx++ = clk_readl(CPU_SOFTRST_CTRL2);
7719 *ctx++ = clk_readl(tegra_pll_p_out1.reg);
7720 *ctx++ = clk_readl(tegra_pll_p_out3.reg);
7722 *ctx++ = clk_readl(tegra_pll_a.reg + PLL_BASE);
7723 *ctx++ = clk_readl(tegra_pll_a.reg + PLL_MISC(&tegra_pll_a));
7724 *ctx++ = clk_readl(tegra_pll_d.reg + PLL_BASE);
7725 *ctx++ = clk_readl(tegra_pll_d.reg + PLL_MISC(&tegra_pll_d));
7726 *ctx++ = clk_readl(tegra_pll_d2.reg + PLL_BASE);
7727 *ctx++ = clk_readl(tegra_pll_d2.reg + PLL_MISC(&tegra_pll_d2));
7729 *ctx++ = clk_readl(tegra_pll_m_out1.reg);
7730 *ctx++ = clk_readl(tegra_pll_a_out0.reg);
7731 *ctx++ = clk_readl(tegra_pll_c_out1.reg);
7733 *ctx++ = clk_readl(tegra_clk_cclk_lp.reg);
7734 *ctx++ = clk_readl(tegra_clk_cclk_lp.reg + SUPER_CLK_DIVIDER);
7736 *ctx++ = clk_readl(tegra_clk_sclk.reg);
7737 *ctx++ = clk_readl(tegra_clk_sclk.reg + SUPER_CLK_DIVIDER);
7738 *ctx++ = clk_readl(tegra_clk_pclk.reg);
7740 for (off = PERIPH_CLK_SOURCE_I2S1; off <= PERIPH_CLK_SOURCE_OSC;
7742 if (off == PERIPH_CLK_SOURCE_EMC)
7744 *ctx++ = clk_readl(off);
7746 for (off = PERIPH_CLK_SOURCE_G3D2; off <= PERIPH_CLK_SOURCE_SE;
7748 *ctx++ = clk_readl(off);
7750 for (off = AUDIO_DLY_CLK; off <= AUDIO_SYNC_CLK_SPDIF; off+=4) {
7751 *ctx++ = clk_readl(off);
7753 for (off = PERIPH_CLK_SOURCE_XUSB_HOST;
7754 off <= PERIPH_CLK_SOURCE_SOC_THERM; off += 4)
7755 *ctx++ = clk_readl(off);
7757 *ctx++ = clk_readl(RST_DEVICES_L);
7758 *ctx++ = clk_readl(RST_DEVICES_H);
7759 *ctx++ = clk_readl(RST_DEVICES_U);
7760 *ctx++ = clk_readl(RST_DEVICES_V);
7761 *ctx++ = clk_readl(RST_DEVICES_W);
7762 *ctx++ = clk_readl(RST_DEVICES_X);
7764 *ctx++ = clk_readl(CLK_OUT_ENB_L);
7765 *ctx++ = clk_readl(CLK_OUT_ENB_H);
7766 *ctx++ = clk_readl(CLK_OUT_ENB_U);
7767 *ctx++ = clk_readl(CLK_OUT_ENB_V);
7768 *ctx++ = clk_readl(CLK_OUT_ENB_W);
7769 *ctx++ = clk_readl(CLK_OUT_ENB_X);
7771 *ctx++ = clk_readl(tegra_clk_cclk_g.reg);
7772 *ctx++ = clk_readl(tegra_clk_cclk_g.reg + SUPER_CLK_DIVIDER);
7774 *ctx++ = clk_readl(SPARE_REG);
7775 *ctx++ = clk_readl(MISC_CLK_ENB);
7776 *ctx++ = clk_readl(CLK_MASK_ARM);
7781 static void tegra11_clk_resume(void)
7784 const u32 *ctx = clk_rst_suspend;
7789 u32 pll_p_out12, pll_p_out34;
7790 u32 pll_a_out0, pll_m_out1, pll_c_out1;
7793 /* FIXME: OSC_CTRL already restored by warm boot code? */
7794 val = clk_readl(OSC_CTRL) & ~OSC_CTRL_MASK;
7796 clk_writel(val, OSC_CTRL);
7797 clk_writel(*ctx++, CPU_SOFTRST_CTRL);
7798 clk_writel(*ctx++, CPU_SOFTRST_CTRL1);
7799 clk_writel(*ctx++, CPU_SOFTRST_CTRL2);
7801 /* Since we are going to reset devices and switch clock sources in this
7802 * function, plls and secondary dividers is required to be enabled. The
7803 * actual value will be restored back later. Note that boot plls: pllm,
7804 * pllp, and pllu are already configured and enabled
7806 val = PLL_OUT_CLKEN | PLL_OUT_RESET_DISABLE;
7808 pll_p_out12 = *ctx++;
7809 clk_writel(pll_p_out12 | val, tegra_pll_p_out1.reg);
7810 pll_p_out34 = *ctx++;
7811 clk_writel(pll_p_out34 | val, tegra_pll_p_out3.reg);
7813 tegra11_pllcx_clk_resume_enable(&tegra_pll_c2);
7814 tegra11_pllcx_clk_resume_enable(&tegra_pll_c3);
7815 tegra11_pllxc_clk_resume_enable(&tegra_pll_c);
7816 tegra11_pllxc_clk_resume_enable(&tegra_pll_x);
7817 tegra11_pllre_clk_resume_enable(&tegra_pll_re_out);
7820 clk_writel(*ctx++, tegra_pll_a.reg + PLL_MISC(&tegra_pll_a));
7821 clk_writel(plla_base | PLL_BASE_ENABLE, tegra_pll_a.reg + PLL_BASE);
7824 clk_writel(*ctx++, tegra_pll_d.reg + PLL_MISC(&tegra_pll_d));
7825 clk_writel(plld_base | PLL_BASE_ENABLE, tegra_pll_d.reg + PLL_BASE);
7827 plld2_base = *ctx++;
7828 clk_writel(*ctx++, tegra_pll_d2.reg + PLL_MISC(&tegra_pll_d2));
7829 clk_writel(plld2_base | PLL_BASE_ENABLE, tegra_pll_d2.reg + PLL_BASE);
7833 val = PLL_OUT_CLKEN | PLL_OUT_RESET_DISABLE;
7834 pll_m_out1 = *ctx++;
7835 clk_writel(pll_m_out1 | val, tegra_pll_m_out1.reg);
7836 pll_a_out0 = *ctx++;
7837 clk_writel(pll_a_out0 | val, tegra_pll_a_out0.reg);
7838 pll_c_out1 = *ctx++;
7839 clk_writel(pll_c_out1 | val, tegra_pll_c_out1.reg);
7842 tegra11_super_clk_resume(&tegra_clk_cclk_lp,
7843 tegra_clk_virtual_cpu_lp.u.cpu.backup, val);
7844 clk_writel(*ctx++, tegra_clk_cclk_lp.reg + SUPER_CLK_DIVIDER);
7846 clk_writel(*ctx++, tegra_clk_sclk.reg);
7847 clk_writel(*ctx++, tegra_clk_sclk.reg + SUPER_CLK_DIVIDER);
7848 clk_writel(*ctx++, tegra_clk_pclk.reg);
7850 /* enable all clocks before configuring clock sources */
7851 clk_writel(0xfdfffff1ul, CLK_OUT_ENB_L);
7852 clk_writel(0xffddfff7ul, CLK_OUT_ENB_H);
7853 clk_writel(0xfbfffbfeul, CLK_OUT_ENB_U);
7854 clk_writel(0xfffffffful, CLK_OUT_ENB_V);
7855 clk_writel(0xff7ffffful, CLK_OUT_ENB_W);
7858 for (off = PERIPH_CLK_SOURCE_I2S1; off <= PERIPH_CLK_SOURCE_OSC;
7860 if (off == PERIPH_CLK_SOURCE_EMC)
7862 clk_writel(*ctx++, off);
7864 for (off = PERIPH_CLK_SOURCE_G3D2; off <= PERIPH_CLK_SOURCE_SE;
7866 clk_writel(*ctx++, off);
7868 for (off = AUDIO_DLY_CLK; off <= AUDIO_SYNC_CLK_SPDIF; off+=4) {
7869 clk_writel(*ctx++, off);
7871 for (off = PERIPH_CLK_SOURCE_XUSB_HOST;
7872 off <= PERIPH_CLK_SOURCE_SOC_THERM; off += 4)
7873 clk_writel(*ctx++, off);
7875 udelay(RESET_PROPAGATION_DELAY);
7877 clk_writel(*ctx++, RST_DEVICES_L);
7878 clk_writel(*ctx++, RST_DEVICES_H);
7879 clk_writel(*ctx++, RST_DEVICES_U);
7880 clk_writel(*ctx++, RST_DEVICES_V);
7881 clk_writel(*ctx++, RST_DEVICES_W);
7882 clk_writel(*ctx++, RST_DEVICES_X);
7885 clk_writel(*ctx++, CLK_OUT_ENB_L);
7886 clk_writel(*ctx++, CLK_OUT_ENB_H);
7887 clk_writel(*ctx++, CLK_OUT_ENB_U);
7889 /* For LP0 resume, clk to lpcpu is required to be on */
7891 val |= CLK_OUT_ENB_V_CLK_ENB_CPULP_EN;
7892 clk_writel(val, CLK_OUT_ENB_V);
7894 clk_writel(*ctx++, CLK_OUT_ENB_W);
7895 clk_writel(*ctx++, CLK_OUT_ENB_X);
7898 /* DFLL resume after cl_dvfs and i2c5 clocks are resumed */
7899 tegra11_dfll_clk_resume(&tegra_dfll_cpu);
7901 /* CPU G clock restored after DFLL and PLLs */
7902 clk_writel(*ctx++, tegra_clk_cclk_g.reg);
7903 clk_writel(*ctx++, tegra_clk_cclk_g.reg + SUPER_CLK_DIVIDER);
7905 clk_writel(*ctx++, SPARE_REG);
7906 clk_writel(*ctx++, MISC_CLK_ENB);
7907 clk_writel(*ctx++, CLK_MASK_ARM);
7909 /* Restore back the actual pll and secondary divider values */
7910 clk_writel(pll_p_out12, tegra_pll_p_out1.reg);
7911 clk_writel(pll_p_out34, tegra_pll_p_out3.reg);
7914 if (p->state == OFF)
7915 tegra11_pllcx_clk_disable(p);
7917 if (p->state == OFF)
7918 tegra11_pllcx_clk_disable(p);
7920 if (p->state == OFF)
7921 tegra11_pllxc_clk_disable(p);
7923 if (p->state == OFF)
7924 tegra11_pllxc_clk_disable(p);
7925 p = &tegra_pll_re_vco;
7926 if (p->state == OFF)
7927 tegra11_pllre_clk_disable(p);
7929 clk_writel(plla_base, tegra_pll_a.reg + PLL_BASE);
7930 clk_writel(plld_base, tegra_pll_d.reg + PLL_BASE);
7931 clk_writel(plld2_base, tegra_pll_d2.reg + PLL_BASE);
7933 clk_writel(pll_m_out1, tegra_pll_m_out1.reg);
7934 clk_writel(pll_a_out0, tegra_pll_a_out0.reg);
7935 clk_writel(pll_c_out1, tegra_pll_c_out1.reg);
7937 /* Since EMC clock is not restored, and may not preserve parent across
7938 suspend, update current state, and mark EMC DFS as out of sync */
7939 p = tegra_clk_emc.parent;
7940 tegra11_periph_clk_init(&tegra_clk_emc);
7942 /* Turn Off pll_m if it was OFF before suspend, and emc was not switched
7943 to pll_m across suspend; re-init pll_m to sync s/w and h/w states */
7944 if ((tegra_pll_m.state == OFF) &&
7945 (&tegra_pll_m != tegra_clk_emc.parent))
7946 tegra11_pllm_clk_disable(&tegra_pll_m);
7947 tegra11_pllm_clk_init(&tegra_pll_m);
7949 if (p != tegra_clk_emc.parent) {
7950 pr_debug("EMC parent(refcount) across suspend: %s(%d) : %s(%d)",
7951 p->name, p->refcnt, tegra_clk_emc.parent->name,
7952 tegra_clk_emc.parent->refcnt);
7954 /* emc switched to the new parent by low level code, but ref
7955 count and s/w state need to be updated */
7957 clk_enable(tegra_clk_emc.parent);
7958 tegra_dvfs_set_rate(&tegra_clk_emc,
7959 clk_get_rate_all_locked(&tegra_clk_emc));
7961 tegra_emc_timing_invalidate();
7963 tegra11_pll_clk_init(&tegra_pll_u); /* Re-init utmi parameters */
7964 tegra11_plle_clk_resume(&tegra_pll_e); /* Restore plle parent as pll_re_vco */
7965 tegra11_pllp_clk_resume(&tegra_pll_p); /* Fire a bug if not restored */
7968 static struct syscore_ops tegra_clk_syscore_ops = {
7969 .suspend = tegra11_clk_suspend,
7970 .resume = tegra11_clk_resume,
7971 .save = tegra11_clk_suspend,
7972 .restore = tegra11_clk_resume,
7976 /* Tegra11 CPU clock and reset control functions */
7977 static void tegra11_wait_cpu_in_reset(u32 cpu)
7982 reg = readl(reg_clk_base +
7983 TEGRA30_CLK_RST_CONTROLLER_CPU_CMPLX_STATUS);
7985 } while (!(reg & (1 << cpu))); /* check CPU been reset or not */
7990 static void tegra11_put_cpu_in_reset(u32 cpu)
7992 writel(CPU_RESET(cpu),
7993 reg_clk_base + TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET);
7997 static void tegra11_cpu_out_of_reset(u32 cpu)
7999 writel(CPU_RESET(cpu),
8000 reg_clk_base + TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR);
8004 static void tegra11_enable_cpu_clock(u32 cpu)
8008 writel(CPU_CLOCK(cpu),
8009 reg_clk_base + TEGRA30_CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR);
8010 reg = readl(reg_clk_base +
8011 TEGRA30_CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR);
8013 static void tegra11_disable_cpu_clock(u32 cpu)
8017 static struct tegra_cpu_car_ops tegra11_cpu_car_ops = {
8018 .wait_for_reset = tegra11_wait_cpu_in_reset,
8019 .put_in_reset = tegra11_put_cpu_in_reset,
8020 .out_of_reset = tegra11_cpu_out_of_reset,
8021 .enable_clock = tegra11_enable_cpu_clock,
8022 .disable_clock = tegra11_disable_cpu_clock,
8025 static void __init tegra11_cpu_car_ops_init(void)
8027 tegra_cpu_car_ops = &tegra11_cpu_car_ops;
8030 static void tegra11_init_xusb_clocks(void)
8034 for (i = 0; i < ARRAY_SIZE(tegra_xusb_source_clks); i++)
8035 tegra11_init_one_clock(&tegra_xusb_source_clks[i]);
8037 tegra11_init_one_clock(&tegra_xusb_ss_div2);
8038 tegra11_init_one_clock(&tegra_xusb_hs_src);
8040 for (i = 0; i < ARRAY_SIZE(tegra_xusb_coupled_clks); i++)
8041 tegra11_init_one_clock(&tegra_xusb_coupled_clks[i]);
8044 void __init tegra11x_init_clocks(void)
8049 for (i = 0; i < ARRAY_SIZE(tegra_ptr_clks); i++)
8050 tegra11_init_one_clock(tegra_ptr_clks[i]);
8052 for (i = 0; i < ARRAY_SIZE(tegra_list_clks); i++)
8053 tegra11_init_one_clock(&tegra_list_clks[i]);
8055 tegra11_init_one_clock(&tegra_camera_mclk);
8057 for (i = 0; i < ARRAY_SIZE(tegra_sync_source_list); i++)
8058 tegra11_init_one_clock(&tegra_sync_source_list[i]);
8059 for (i = 0; i < ARRAY_SIZE(tegra_clk_audio_list); i++)
8060 tegra11_init_one_clock(&tegra_clk_audio_list[i]);
8061 for (i = 0; i < ARRAY_SIZE(tegra_clk_audio_2x_list); i++)
8062 tegra11_init_one_clock(&tegra_clk_audio_2x_list[i]);
8065 for (i = 0; i < ARRAY_SIZE(tegra_clk_out_list); i++)
8066 tegra11_init_one_clock(&tegra_clk_out_list[i]);
8068 tegra11_init_xusb_clocks();
8070 for (i = 0; i < ARRAY_SIZE(tegra_clk_duplicates); i++) {
8071 c = tegra_get_clock_by_name(tegra_clk_duplicates[i].name);
8073 pr_err("%s: Unknown duplicate clock %s\n", __func__,
8074 tegra_clk_duplicates[i].name);
8078 tegra_clk_duplicates[i].lookup.clk = c;
8079 clkdev_add(&tegra_clk_duplicates[i].lookup);
8082 /* Initialize to default */
8083 tegra_init_cpu_edp_limits(0);
8085 tegra11_cpu_car_ops_init();
8087 #ifdef CONFIG_PM_SLEEP
8088 register_syscore_ops(&tegra_clk_syscore_ops);
8093 static int __init tegra11x_clk_late_init(void)
8095 clk_disable(&tegra_pll_re_vco);
8098 late_initcall(tegra11x_clk_late_init);