a30dabfc603e287b5ae5d8fa525dad534558580e
[linux-3.10.git] / arch / arm / mach-tegra / sleep-t30.S
1 /*
2  * Copyright (c) 2012, NVIDIA Corporation. All rights reserved.
3  *
4  * This program is free software; you can redistribute it and/or modify it
5  * under the terms and conditions of the GNU General Public License,
6  * version 2, as published by the Free Software Foundation.
7  *
8  * This program is distributed in the hope it will be useful, but WITHOUT
9  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
11  * more details.
12  *
13  * You should have received a copy of the GNU General Public License
14  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
15  */
16
17 #include <linux/const.h>
18 #include <linux/init.h>
19 #include <linux/linkage.h>
20
21 #include <asm/assembler.h>
22 #include <asm/cache.h>
23 #include <asm/domain.h>
24 #include <asm/memory.h>
25 #include <asm/page.h>
26 #include <asm/ptrace.h>
27 #include <asm/asm-offsets.h>
28 #include <asm/glue-cache.h>
29 #include <asm/glue-proc.h>
30 #include <asm/cp15.h>
31
32 #include "sleep.h"
33 #include "flowctrl.h"
34
35 #define EMC_CFG                         0xc
36 #define EMC_ADR_CFG                     0x10
37 #define EMC_TIMING_CONTROL              0x28
38 #define EMC_REFRESH                     0x70
39 #define EMC_NOP                         0xdc
40 #define EMC_SELF_REF                    0xe0
41 #define EMC_MRW                         0xe8
42 #define EMC_REQ_CTRL                    0x2b0
43 #define EMC_EMC_STATUS                  0x2b4
44 #define EMC_FBIO_CFG5                   0x104
45 #define EMC_AUTO_CAL_CONFIG             0x2a4
46 #define EMC_AUTO_CAL_INTERVAL           0x2a8
47 #define EMC_AUTO_CAL_STATUS             0x2ac
48 #define EMC_CFG_DIG_DLL                 0x2bc
49 #define EMC_ZCAL_INTERVAL               0x2e0
50 #define EMC_ZQ_CAL                      0x2ec
51 #define EMC_XM2VTTGENPADCTRL            0x310
52 #define EMC_XM2VTTGENPADCTRL2           0x314
53
54 #define PMC_CTRL                        0x0
55 #define PMC_CTRL_SIDE_EFFECT_LP0        (1 << 14)  /* enter LP0 when CPU pwr gated */
56
57 #define PMC_PWRGATE_TOGGLE              0x30
58 #define PMC_REMOVE_CLAMPING_CMD         0x34
59 #define PMC_PWRGATE_STATUS              0x38
60
61 #define PMC_PWRGATE_PARTID_L2C          (0x5)
62
63 #define PMC_IO_DPD_REQ                  0x1b8
64 #define PMC_IO_DPD_STATUS               0x1bc
65
66 #define CLK_RESET_CCLK_BURST            0x20
67 #define CLK_RESET_CCLK_DIVIDER          0x24
68 #define CLK_RESET_SCLK_BURST            0x28
69 #define CLK_RESET_SCLK_DIVIDER          0x2c
70
71 #define CLK_RESET_PLLC_BASE             0x80
72 #define CLK_RESET_PLLM_BASE             0x90
73 #define CLK_RESET_PLLP_BASE             0xa0
74 #define CLK_RESET_PLLA_BASE             0xb0
75 #define CLK_RESET_PLLX_BASE             0xe0
76
77 #define CLK_RESET_PLLC_MISC             0x8c
78 #define CLK_RESET_PLLM_MISC             0x9c
79 #define CLK_RESET_PLLP_MISC             0xac
80 #define CLK_RESET_PLLA_MISC             0xbc
81 #define CLK_RESET_PLLX_MISC             0xe4
82
83 #define CLK_RESET_PLLP_OUTA             0xa4
84 #define CLK_RESET_PLLP_OUTB             0xa8
85
86 #define PMC_PLLP_WB0_OVERRIDE           0xf8
87
88 #define CLK_RESET_CLK_SOURCE_MSELECT    0x3b4
89
90 #define MSELECT_CLKM                    (0x3 << 30)
91
92 #define USE_PLL_LOCK_BITS 0
93 #define USE_PLLP_ON_SLEEP_ENTRY 0
94
95 #define TEGRA30_POWER_HOTPLUG_SHUTDOWN  (1 << 27) /* Hotplug shutdown */
96
97 .macro emc_device_mask, rd, base
98         ldr     \rd, [\base, #EMC_ADR_CFG]
99         tst     \rd, #(0x3<<24)
100         moveq   \rd, #(0x1<<8)          @ just 1 device
101         movne   \rd, #(0x3<<8)          @ 2 devices
102 .endm
103
104 .macro emc_timing_update, rd, base
105         mov     \rd, #1
106         str     \rd, [\base, #EMC_TIMING_CONTROL]
107 1001:
108         ldr     \rd, [\base, #EMC_EMC_STATUS]
109         tst     \rd, #(0x1<<23)         @ wait until EMC_STATUS_TIMING_UPDATE_STALLED is clear
110         bne     1001b
111 .endm
112
113 #if defined(CONFIG_HOTPLUG_CPU) || defined(CONFIG_PM_SLEEP)
114 /*
115  * tegra30_hotplug_shutdown(void)
116  *
117  * Powergates the current CPU.
118  * Should never return.
119  */
120 ENTRY(tegra30_hotplug_shutdown)
121         mov     r6, lr
122         bl      tegra_cpu_exit_coherency
123
124         /* Powergate this CPU */
125         mov     r0, #TEGRA30_POWER_HOTPLUG_SHUTDOWN
126         bl      tegra30_cpu_shutdown
127         mov     pc, r6                  @ should never get here
128 ENDPROC(tegra30_hotplug_shutdown)
129
130 /*
131  * tegra30_cpu_shutdown(unsigned long flags)
132  *
133  * Puts the current CPU in wait-for-event mode on the flow controller
134  * and powergates it -- flags (in R0) indicate the request type.
135  * Must never be called for CPU 0.
136  *
137  * corrupts r0-r4, r12
138  */
139 ENTRY(tegra30_cpu_shutdown)
140         cpu_id  r3
141         cmp     r3, #0
142         moveq   pc, lr          @ Must never be called for CPU 0
143
144         ldr     r12, =TEGRA_FLOW_CTRL_VIRT
145         cpu_to_csr_reg r1, r3
146         add     r1, r1, r12     @ virtual CSR address for this CPU
147         cpu_to_halt_reg r2, r3
148         add     r2, r2, r12     @ virtual HALT_EVENTS address for this CPU
149
150         /*
151          * Clear this CPU's "event" and "interrupt" flags and power gate
152          * it when halting but not before it is in the "WFE" state.
153          */
154         movw    r12, \
155                 FLOW_CTRL_CSR_INTR_FLAG | FLOW_CTRL_CSR_EVENT_FLAG | \
156                 FLOW_CTRL_CSR_ENABLE
157         mov     r4, #(1 << 4)
158         orr     r12, r12, r4, lsl r3
159         str     r12, [r1]
160
161         /* Halt this CPU. */
162         mov     r3, #0x400
163 delay_1:
164         subs    r3, r3, #1                      @ delay as a part of wfe war.
165         bge     delay_1;
166         cpsid   a                               @ disable imprecise aborts.
167         ldr     r3, [r1]                        @ read CSR
168         str     r3, [r1]                        @ clear CSR
169         tst     r0, #TEGRA30_POWER_HOTPLUG_SHUTDOWN
170         moveq   r3, #FLOW_CTRL_WAIT_FOR_INTERRUPT       @ For LP2
171         movne   r3, #FLOW_CTRL_WAITEVENT                @ For hotplug
172         str     r3, [r2]
173         ldr     r0, [r2]
174         b       wfe_war
175
176 __cpu_reset_again:
177         dsb
178         .align 5
179         wfe                                     @ CPU should be power gated here
180 wfe_war:
181         b       __cpu_reset_again
182
183         /*
184          * 38 nop's, which fills reset of wfe cache line and
185          * 4 more cachelines with nop
186          */
187         .rept 38
188         nop
189         .endr
190         b       .                               @ should never get here
191
192 ENDPROC(tegra30_cpu_shutdown)
193 #endif
194
195 #ifdef CONFIG_PM_SLEEP
196 /*
197  * tegra3_sleep_core(unsigned long v2p)
198  *
199  * enters suspend in LP0 or LP1 by turning off the mmu and jumping to
200  * tegra3_tear_down_core in IRAM
201  */
202 ENTRY(tegra3_sleep_core)
203         mov     r12, pc                 @ return here is via r12
204         b       tegra_cpu_save
205
206         /* preload all the address literals that are needed for the
207          * CPU power-gating process, to avoid loads from SDRAM (which are
208          * not supported once SDRAM is put into self-refresh.
209          * LP0 / LP1 use physical address, since the MMU needs to be
210          * disabled before putting SDRAM into self-refresh to avoid
211          * memory access due to page table walks */
212         mov32   r4, TEGRA_PMC_BASE
213         mov32   r5, TEGRA_CLK_RESET_BASE
214         mov32   r6, TEGRA_FLOW_CTRL_BASE
215         mov32   r7, TEGRA_TMRUS_BASE
216
217         mov32   r1, tegra3_tear_down_core
218         mov32   r2, tegra3_iram_start
219         sub     r1, r1, r2
220         mov32   r2, TEGRA_IRAM_CODE_AREA
221         add     r1, r1, r2
222         b       tegra_turn_off_mmu
223 ENDPROC(tegra3_sleep_core)
224
225 /*
226  * tegra3_sleep_cpu_secondary(unsigned long v2p)
227  *
228  * Enters LP2 on secondary CPU by exiting coherency and powergating the CPU.
229  */
230 ENTRY(tegra3_sleep_cpu_secondary)
231         mov     r12, pc                         @ return here is via r12
232         b       tegra_cpu_save
233
234         /* Powergate this CPU. */
235         mov     r0, #0                          @ power mode flags (!hotplug)
236         bl      tegra30_cpu_shutdown
237         b       .                               @ should never get here
238 ENDPROC(tegra3_sleep_cpu_secondary)
239
240 /*
241  * tegra3_tear_down_cpu
242  *
243  * Switches the CPU cluster to PLL-P and enters sleep.
244  */
245 ENTRY(tegra3_tear_down_cpu)
246         mov32   r4, TEGRA_PMC_BASE
247         mov32   r5, TEGRA_CLK_RESET_BASE
248         mov32   r6, TEGRA_FLOW_CTRL_BASE
249         mov32   r7, TEGRA_TMRUS_BASE
250 #if USE_PLLP_ON_SLEEP_ENTRY
251         bl      tegra_cpu_pllp
252 #endif
253         b       tegra3_enter_sleep
254 ENDPROC(tegra3_tear_down_cpu)
255
256 /* START OF ROUTINES COPIED TO IRAM */
257         .align L1_CACHE_SHIFT
258         .globl tegra3_iram_start
259 tegra3_iram_start:
260
261 /*
262  * tegra3_lp1_reset
263  *
264  * reset vector for LP1 restore; copied into IRAM during suspend.
265  * brings the system back up to a safe starting point (SDRAM out of
266  * self-refresh, PLLC, PLLM and PLLP reenabled, CPU running on PLLP,
267  * system clock running on the same PLL that it suspended at), and
268  * jumps to tegra_lp2_startup to restore PLLX and virtual addressing.
269  * physical address of tegra_lp2_startup expected to be stored in
270  * PMC_SCRATCH41
271  *
272  * NOTE: THIS *MUST* BE RELOCATED TO TEGRA_IRAM_CODE_AREA AND MUST BE FIRST.
273  */
274 .macro pll_enable, rd, car, base, misc
275         ldr     \rd, [\car, #\base]
276         tst     \rd, #(1<<30)
277         orreq   \rd, \rd, #(1<<30)
278         streq   \rd, [\car, #\base]
279 #if USE_PLL_LOCK_BITS
280         ldr     \rd, [\car, #\misc]
281         orr     \rd, \rd, #(1<<18)
282         str     \rd, [\car, #\misc]
283 #endif
284 .endm
285
286 ENTRY(tegra3_lp1_reset)
287         /* the CPU and system bus are running at 32KHz and executing from
288          * IRAM when this code is executed; immediately switch to CLKM and
289          * enable PLLP, PLLM, PLLC, PLLA and PLLX. */
290         mov32   r0, TEGRA_CLK_RESET_BASE
291
292         mov     r1, #(1<<28)
293         str     r1, [r0, #CLK_RESET_SCLK_BURST]
294         str     r1, [r0, #CLK_RESET_CCLK_BURST]
295         mov     r1, #0
296         str     r1, [r0, #CLK_RESET_SCLK_DIVIDER]
297         str     r1, [r0, #CLK_RESET_CCLK_DIVIDER]
298
299         /* enable PLLM via PMC */
300         mov32   r2, TEGRA_PMC_BASE
301         ldr     r1, [r2, #PMC_PLLP_WB0_OVERRIDE]
302         orr     r1, r1, #(1<<12)
303         str     r1, [r2, #PMC_PLLP_WB0_OVERRIDE]
304
305         pll_enable r1, r0, CLK_RESET_PLLP_BASE, CLK_RESET_PLLP_MISC
306         pll_enable r1, r0, CLK_RESET_PLLA_BASE, CLK_RESET_PLLA_MISC
307         pll_enable r1, r0, CLK_RESET_PLLC_BASE, CLK_RESET_PLLC_MISC
308         pll_enable r1, r0, CLK_RESET_PLLX_BASE, CLK_RESET_PLLX_MISC
309         mov32   r7, TEGRA_TMRUS_BASE
310         ldr     r1, [r7]
311
312 #if USE_PLL_LOCK_BITS
313         pll_locked r1, r0, CLK_RESET_PLLM_BASE
314         pll_locked r1, r0, CLK_RESET_PLLP_BASE
315         pll_locked r1, r0, CLK_RESET_PLLA_BASE
316         pll_locked r1, r0, CLK_RESET_PLLC_BASE
317         pll_locked r1, r0, CLK_RESET_PLLX_BASE
318 #else
319         add     r1, r1, #0xff   @ 255uS delay for PLL stabilization
320         wait_until r1, r7, r3
321 #endif
322         add     r5, pc, #tegra3_sdram_pad_save-(.+8)    @ r5 reserved for pad base
323
324         ldr     r4, [r5, #0x18]
325         str     r4, [r0, #CLK_RESET_CLK_SOURCE_MSELECT]
326
327         ldr     r4, [r5, #0x1C]
328         str     r4, [r0, #CLK_RESET_SCLK_BURST]
329
330         mov32   r4, ((1<<28) | (8))     @ burst policy is PLLX
331         str     r4, [r0, #CLK_RESET_CCLK_BURST]
332
333 #if defined (CONFIG_CACHE_L2X0)
334         /* power up L2 */
335         ldr     r0, [r2, #PMC_PWRGATE_STATUS]
336         tst     r0, #(1<<PMC_PWRGATE_PARTID_L2C)
337         bne     powerup_l2_done
338         movw    r0, #(1<<8) | PMC_PWRGATE_PARTID_L2C
339         str     r0, [r2, #PMC_PWRGATE_TOGGLE]
340 powerup_l2_wait:
341         ldr     r0, [r2, #PMC_PWRGATE_STATUS]
342         tst     r0, #(1<<PMC_PWRGATE_PARTID_L2C)
343         beq     powerup_l2_wait
344 powerup_l2_done:
345         mov     r0, #PMC_PWRGATE_PARTID_L2C
346         str     r0, [r2, #PMC_REMOVE_CLAMPING_CMD]
347 #endif
348
349         mov32   r0, TEGRA_EMC_BASE                      @ r0 reserved for emc base
350
351         ldr     r1, [r5, #0x14] @ PMC_IO_DPD_STATUS
352         mvn     r1, r1
353         bic     r1, r1, #(0x1<<31)
354         orr     r1, r1, #(0x1<<30)
355         str     r1, [r2, #PMC_IO_DPD_REQ]
356         ldr     r1, [r5, #0xC]
357         str     r1, [r0, #EMC_XM2VTTGENPADCTRL]
358         ldr     r1, [r5, #0x10]
359         str     r1, [r0, #EMC_XM2VTTGENPADCTRL2]
360         ldr     r1, [r5, #0x8]
361         str     r1, [r0, #EMC_AUTO_CAL_INTERVAL]
362
363         ldr     r1, [r0, #EMC_CFG_DIG_DLL]
364         orr     r1, r1, #(0x1<<30)              @ set DLL_RESET
365         str     r1, [r0, #EMC_CFG_DIG_DLL]
366
367         emc_timing_update r1, r0
368
369         ldr     r1, [r0, #EMC_AUTO_CAL_CONFIG]
370         orr     r1, r1, #(0x1<<31)              @ set AUTO_CAL_ACTIVE
371         str     r1, [r0, #EMC_AUTO_CAL_CONFIG]
372
373 emc_wait_audo_cal_onetime:
374         ldr     r1, [r0, #EMC_AUTO_CAL_STATUS]
375         tst     r1, #(0x1<<31)          @ wait until AUTO_CAL_ACTIVE is clear
376         bne     emc_wait_audo_cal_onetime
377
378         ldr     r1, [r0, #EMC_CFG]
379         bic     r1, r1, #(1<<31)        @ disable DRAM_CLK_STOP
380         str     r1, [r0, #EMC_CFG]
381
382         mov     r1, #0
383         str     r1, [r0, #EMC_SELF_REF] @ take DRAM out of self refresh
384         mov     r1, #1
385         str     r1, [r0, #EMC_NOP]
386         str     r1, [r0, #EMC_NOP]
387         str     r1, [r0, #EMC_REFRESH]
388
389         emc_device_mask r1, r0
390
391 exit_selfrefresh_loop:
392         ldr     r2, [r0, #EMC_EMC_STATUS]
393         ands    r2, r2, r1
394         bne     exit_selfrefresh_loop
395
396         lsr     r1, r1, #8              @ devSel, bit0:dev0 bit1:dev1
397
398         mov32   r7, TEGRA_TMRUS_BASE
399         ldr     r2, [r0, #EMC_FBIO_CFG5]
400
401         and     r2, r2, #3
402         cmp     r2, #2
403         beq     emc_lpddr2
404
405         mov32   r2, 0x80000011
406         str     r2, [r0, #EMC_ZQ_CAL]
407         ldr     r2, [r7]
408         add     r2, r2, #10
409         wait_until r2, r7, r3
410
411         tst     r1, #2
412         beq zcal_done
413
414         mov32   r2, 0x40000011
415         str     r2, [r0, #EMC_ZQ_CAL]
416         ldr     r2, [r7]
417         add     r2, r2, #10
418         wait_until r2, r7, r3
419         b zcal_done
420
421 emc_lpddr2:
422
423         mov32   r2, 0x800A00AB
424         str     r2, [r0, #EMC_MRW]
425         ldr     r2, [r7]
426         add     r2, r2, #1
427         wait_until r2, r7, r3
428
429         tst     r1, #2
430         beq zcal_done
431
432         mov32   r2, 0x400A00AB
433         str     r2, [r0, #EMC_MRW]
434         ldr     r2, [r7]
435         add     r2, r2, #1
436         wait_until r2, r7, r3
437
438 zcal_done:
439
440         mov     r1, #0
441         str     r1, [r0, #EMC_REQ_CTRL]
442         ldr     r1, [r5, #0x4]
443         str     r1, [r0, #EMC_ZCAL_INTERVAL]
444         ldr     r1, [r5, #0x0]
445         str     r1, [r0, #EMC_CFG]
446
447         mov32   r0, TEGRA_PMC_BASE
448         ldr     r0, [r0, #PMC_SCRATCH41]
449         mov     pc, r0
450 ENDPROC(tegra3_lp1_reset)
451
452         .align  L1_CACHE_SHIFT
453         .type   tegra3_sdram_pad_save, %object
454 tegra3_sdram_pad_save:
455         .word   0
456         .word   0
457         .word   0
458         .word   0
459         .word   0
460         .word   0
461         .word   0
462         .word   0
463
464 tegra3_sdram_pad_address:
465         .word   TEGRA_EMC_BASE + EMC_CFG                                @0x0
466         .word   TEGRA_EMC_BASE + EMC_ZCAL_INTERVAL                      @0x4
467         .word   TEGRA_EMC_BASE + EMC_AUTO_CAL_INTERVAL                  @0x8
468         .word   TEGRA_EMC_BASE + EMC_XM2VTTGENPADCTRL                   @0xc
469         .word   TEGRA_EMC_BASE + EMC_XM2VTTGENPADCTRL2                  @0x10
470         .word   TEGRA_PMC_BASE + PMC_IO_DPD_STATUS                      @0x14
471         .word   TEGRA_CLK_RESET_BASE + CLK_RESET_CLK_SOURCE_MSELECT     @0x18
472         .word   TEGRA_CLK_RESET_BASE + CLK_RESET_SCLK_BURST             @0x1c
473
474 tegra3_sdram_pad_size:
475         .word   tegra3_sdram_pad_address - tegra3_sdram_pad_save
476
477 /*
478  * tegra3_tear_down_core
479  *
480  * copied into and executed from IRAM
481  * puts memory in self-refresh for LP0 and LP1
482  */
483 tegra3_tear_down_core:
484         bl      tegra3_sdram_self_refresh
485         bl      tegra3_cpu_clk32k
486         b       tegra3_enter_sleep
487
488 /*
489  * tegra3_cpu_clk32k
490  *
491  * In LP0 and LP1 all plls will be turned off.  Switch the CPU and system clock
492  * to the 32khz clock (clks)
493  * r4 = TEGRA_PMC_BASE
494  * r5 = TEGRA_CLK_RESET_BASE
495  * r6 = TEGRA_FLOW_CTRL_BASE
496  * r7 = TEGRA_TMRUS_BASE
497  */
498 tegra3_cpu_clk32k:
499         /* start by jumping to clkm to safely disable PLLs, then jump
500          * to clks */
501         mov     r0, #(1 << 28)
502         str     r0, [r5, #CLK_RESET_SCLK_BURST]
503         str     r0, [r5, #CLK_RESET_CCLK_BURST]
504         mov     r0, #0
505         str     r0, [r5, #CLK_RESET_CCLK_DIVIDER]
506         str     r0, [r5, #CLK_RESET_SCLK_DIVIDER]
507
508         /* switch the clock source for mselect to be CLK_M */
509         ldr     r0, [r5, #CLK_RESET_CLK_SOURCE_MSELECT]
510         orr     r0, r0, #MSELECT_CLKM
511         str     r0, [r5, #CLK_RESET_CLK_SOURCE_MSELECT]
512
513         /* 2 us delay between changing sclk and disabling PLLs */
514         wait_for_us r1, r7, r9
515         add     r1, r1, #2
516         wait_until r1, r7, r9
517
518 #if 1
519         /* switch to CLKS */
520         mov     r0, #0  /* burst policy = 32KHz */
521         str     r0, [r5, #CLK_RESET_SCLK_BURST]
522 #endif
523
524         /* disable PLLM via PMC in LP1 */
525         ldr     r0, [r4, #PMC_CTRL]
526         tst     r0, #PMC_CTRL_SIDE_EFFECT_LP0
527         bne     enable_pllm_lp0
528         /* disable PLLM via PMC in LP0 and LP1 states */
529         ldr     r0, [r4, #PMC_PLLP_WB0_OVERRIDE]
530         bic     r0, r0, #(1<<12)
531         str     r0, [r4, #PMC_PLLP_WB0_OVERRIDE]
532         b       powerdown_pll_pcx
533
534 enable_pllm_lp0:
535         /* enable PLLM via PMC in LP0 */
536         ldr     r0, [r4, #PMC_PLLP_WB0_OVERRIDE]
537         orr     r0, r0, #((1<<12) | (1 << 11))
538         str     r0, [r4, #PMC_PLLP_WB0_OVERRIDE]
539
540 powerdown_pll_pcx:
541         /* disable PLLP, PLLA, PLLC, and PLLX in LP0 and LP1 states */
542         ldr     r0, [r5, #CLK_RESET_PLLP_BASE]
543         bic     r0, r0, #(1<<30)
544         str     r0, [r5, #CLK_RESET_PLLP_BASE]
545         ldr     r0, [r5, #CLK_RESET_PLLA_BASE]
546         bic     r0, r0, #(1<<30)
547         str     r0, [r5, #CLK_RESET_PLLA_BASE]
548         ldr     r0, [r5, #CLK_RESET_PLLC_BASE]
549         bic     r0, r0, #(1<<30)
550         str     r0, [r5, #CLK_RESET_PLLC_BASE]
551         ldr     r0, [r5, #CLK_RESET_PLLX_BASE]
552         bic     r0, r0, #(1<<30)
553         str     r0, [r5, #CLK_RESET_PLLX_BASE]
554
555         mov     pc, lr
556
557 /*
558  * tegra3_enter_sleep
559  *
560  * uses flow controller to enter sleep state
561  * executes from IRAM with SDRAM in selfrefresh when target state is LP0 or LP1
562  * executes from SDRAM with target state is LP2
563  * r4 = TEGRA_PMC_BASE
564  * r5 = TEGRA_CLK_RESET_BASE
565  * r6 = TEGRA_FLOW_CTRL_BASE
566  * r7 = TEGRA_TMRUS_BASE
567  */
568 tegra3_enter_sleep:
569         ldr     r1, [r7]
570         str     r1, [r4, #PMC_SCRATCH38]
571         dsb
572         cpu_id  r1
573
574         cpu_to_csr_reg  r2, r1
575         ldr     r0, [r6, r2]
576         orr     r0, r0, #FLOW_CTRL_CSR_INTR_FLAG | FLOW_CTRL_CSR_EVENT_FLAG
577         orr     r0, r0, #FLOW_CTRL_CSR_ENABLE
578         str     r0, [r6, r2]
579
580         mov     r0, #FLOW_CTRL_WAIT_FOR_INTERRUPT
581         orr     r0, r0, #FLOW_CTRL_HALT_CPU_IRQ | FLOW_CTRL_HALT_CPU_FIQ
582         cpu_to_halt_reg r2, r1
583         str     r0, [r6, r2]
584         dsb
585         ldr     r0, [r6, r2] /* memory barrier */
586
587 halted:
588         isb
589         dsb
590         wfi     /* CPU should be power gated here */
591
592         /* !!!FIXME!!! Implement halt failure handler */
593         b       halted
594
595 /*
596  * tegra3_sdram_self_refresh
597  *
598  * called with MMU off and caches disabled
599  * puts sdram in self refresh
600  * must execute from IRAM
601  * r4 = TEGRA_PMC_BASE
602  * r5 = TEGRA_CLK_RESET_BASE
603  * r6 = TEGRA_FLOW_CTRL_BASE
604  * r7 = TEGRA_TMRUS_BASE
605  */
606
607 tegra3_sdram_self_refresh:
608
609         adr     r2, tegra3_sdram_pad_address
610         adr     r8, tegra3_sdram_pad_save
611         mov     r9, #0
612
613 padsave:
614         ldr     r0, [r2, r9]                    @ r0 is emc register address
615
616         ldr     r1, [r0]
617         str     r1, [r8, r9]                    @ save emc register
618
619         add     r9, r9, #4
620         ldr     r0, tegra3_sdram_pad_size
621         cmp     r0, r9
622         bne     padsave
623 padsave_done:
624
625         dsb
626
627         mov32   r0, TEGRA_EMC_BASE                      @ r0 reserved for emc base
628
629         mov     r1, #0
630         str     r1, [r0, #EMC_ZCAL_INTERVAL]
631         str     r1, [r0, #EMC_AUTO_CAL_INTERVAL]
632         ldr     r1, [r0, #EMC_CFG]
633         bic     r1, r1, #(1<<28)
634         str     r1, [r0, #EMC_CFG]              @ disable DYN_SELF_REF
635
636         emc_timing_update r1, r0
637
638         ldr     r1, [r7]
639         add     r1, r1, #5
640         wait_until r1, r7, r2
641
642 emc_wait_audo_cal:
643         ldr     r1, [r0, #EMC_AUTO_CAL_STATUS]
644         tst     r1, #(0x1<<31)          @ wait until AUTO_CAL_ACTIVE is clear
645         bne     emc_wait_audo_cal
646
647         mov     r1, #3
648         str     r1, [r0, #EMC_REQ_CTRL]         @ stall incoming DRAM requests
649
650 emcidle:
651         ldr     r1, [r0, #EMC_EMC_STATUS]
652         tst     r1, #4
653         beq     emcidle
654
655         mov     r1, #1
656         str     r1, [r0, #EMC_SELF_REF]
657
658         emc_device_mask r1, r0
659
660 emcself:
661         ldr     r2, [r0, #EMC_EMC_STATUS]
662         and     r2, r2, r1
663         cmp     r2, r1
664         bne     emcself                         @ loop until DDR in self-refresh
665
666         ldr     r1, [r0, #EMC_XM2VTTGENPADCTRL]
667         mov32   r2, 0xF8F8FFFF          @ clear XM2VTTGEN_DRVUP and XM2VTTGEN_DRVDN
668         and     r1, r1, r2
669         str     r1, [r0, #EMC_XM2VTTGENPADCTRL]
670         ldr     r1, [r0, #EMC_XM2VTTGENPADCTRL2]
671         orr     r1, r1, #7                      @ set E_NO_VTTGEN
672         str     r1, [r0, #EMC_XM2VTTGENPADCTRL2]
673
674         emc_timing_update r1, r0
675
676         ldr     r1, [r4, #PMC_CTRL]
677         tst     r1, #PMC_CTRL_SIDE_EFFECT_LP0
678         bne     pmc_io_dpd_skip
679         mov32   r1, 0x8EC00000
680         str     r1, [r4, #PMC_IO_DPD_REQ]
681 pmc_io_dpd_skip:
682
683         dsb
684
685         mov     pc, lr
686
687         .ltorg
688 /* dummy symbol for end of IRAM */
689         .align L1_CACHE_SHIFT
690         .globl tegra3_iram_end
691 tegra3_iram_end:
692         b       .
693 #endif