33b7be3824c5ccc964172bdbe84b718a695646bd
[linux-3.10.git] / arch / arm / mach-tegra / sleep-t30.S
1 /*
2  * Copyright (c) 2012, NVIDIA Corporation. All rights reserved.
3  *
4  * This program is free software; you can redistribute it and/or modify it
5  * under the terms and conditions of the GNU General Public License,
6  * version 2, as published by the Free Software Foundation.
7  *
8  * This program is distributed in the hope it will be useful, but WITHOUT
9  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
11  * more details.
12  *
13  * You should have received a copy of the GNU General Public License
14  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
15  */
16
17 #include <linux/const.h>
18 #include <linux/init.h>
19 #include <linux/linkage.h>
20
21 #include <asm/assembler.h>
22 #include <asm/cache.h>
23 #include <asm/domain.h>
24 #include <asm/memory.h>
25 #include <asm/page.h>
26 #include <asm/ptrace.h>
27 #include <asm/asm-offsets.h>
28 #include <asm/glue-cache.h>
29 #include <asm/glue-proc.h>
30 #include <asm/cp15.h>
31
32 #include "sleep.h"
33 #include "flowctrl.h"
34 #include "clock.h"
35
36 #define EMC_CFG                         0xc
37 #define EMC_ADR_CFG                     0x10
38 #define EMC_TIMING_CONTROL              0x28
39 #define EMC_REFRESH                     0x70
40 #define EMC_NOP                         0xdc
41 #define EMC_SELF_REF                    0xe0
42 #define EMC_MRW                         0xe8
43 #define EMC_REQ_CTRL                    0x2b0
44 #define EMC_EMC_STATUS                  0x2b4
45 #define EMC_FBIO_CFG5                   0x104
46 #define EMC_AUTO_CAL_CONFIG             0x2a4
47 #define EMC_AUTO_CAL_INTERVAL           0x2a8
48 #define EMC_AUTO_CAL_STATUS             0x2ac
49 #define EMC_CFG_DIG_DLL                 0x2bc
50 #define EMC_ZCAL_INTERVAL               0x2e0
51 #define EMC_ZQ_CAL                      0x2ec
52 #define EMC_XM2VTTGENPADCTRL            0x310
53 #define EMC_XM2VTTGENPADCTRL2           0x314
54
55 #define PMC_CTRL                        0x0
56 #define PMC_CTRL_SIDE_EFFECT_LP0        (1 << 14)  /* enter LP0 when CPU pwr gated */
57
58 #define PMC_PWRGATE_TOGGLE              0x30
59 #define PMC_REMOVE_CLAMPING_CMD         0x34
60 #define PMC_PWRGATE_STATUS              0x38
61
62 #define PMC_PWRGATE_PARTID_L2C          (0x5)
63
64 #define PMC_IO_DPD_REQ                  0x1b8
65 #define PMC_IO_DPD_STATUS               0x1bc
66
67 #define CLK_RESET_CCLK_BURST            0x20
68 #define CLK_RESET_CCLK_DIVIDER          0x24
69 #define CLK_RESET_SCLK_BURST            0x28
70 #define CLK_RESET_SCLK_DIVIDER          0x2c
71
72 #define CLK_RESET_PLLC_BASE             0x80
73 #define CLK_RESET_PLLM_BASE             0x90
74 #define CLK_RESET_PLLP_BASE             0xa0
75 #define CLK_RESET_PLLA_BASE             0xb0
76 #define CLK_RESET_PLLX_BASE             0xe0
77
78 #define CLK_RESET_PLLC_MISC             0x8c
79 #define CLK_RESET_PLLM_MISC             0x9c
80 #define CLK_RESET_PLLP_MISC             0xac
81 #define CLK_RESET_PLLA_MISC             0xbc
82 #define CLK_RESET_PLLX_MISC             0xe4
83
84 #define CLK_RESET_PLLP_OUTA             0xa4
85 #define CLK_RESET_PLLP_OUTB             0xa8
86
87 #define PMC_PLLP_WB0_OVERRIDE           0xf8
88
89 #define CLK_RESET_CLK_SOURCE_MSELECT    0x3b4
90
91 #define MSELECT_CLKM                    (0x3 << 30)
92
93 #if USE_PLL_LOCK_BITS
94 #define LOCK_DELAY              PLL_POST_LOCK_DELAY
95 #else
96 #define LOCK_DELAY              0xff /* 255uS delay for PLL stabilization */
97 #endif
98
99 #define USE_PLLP_ON_SLEEP_ENTRY 0
100
101 #define TEGRA30_POWER_HOTPLUG_SHUTDOWN  (1 << 27) /* Hotplug shutdown */
102
103 .macro emc_device_mask, rd, base
104         ldr     \rd, [\base, #EMC_ADR_CFG]
105         tst     \rd, #0x1
106         moveq   \rd, #(0x1<<8)          @ just 1 device
107         movne   \rd, #(0x3<<8)          @ 2 devices
108 .endm
109
110 .macro emc_timing_update, rd, base
111         mov     \rd, #1
112         str     \rd, [\base, #EMC_TIMING_CONTROL]
113 1001:
114         ldr     \rd, [\base, #EMC_EMC_STATUS]
115         tst     \rd, #(0x1<<23)         @ wait until EMC_STATUS_TIMING_UPDATE_STALLED is clear
116         bne     1001b
117 .endm
118
119 #if defined(CONFIG_HOTPLUG_CPU) || defined(CONFIG_PM_SLEEP)
120 /*
121  * tegra30_hotplug_shutdown(void)
122  *
123  * Powergates the current CPU.
124  * Should never return.
125  */
126 ENTRY(tegra30_hotplug_shutdown)
127         mov     r6, lr
128         bl      tegra_cpu_exit_coherency
129
130         /* Powergate this CPU */
131         mov     r0, #TEGRA30_POWER_HOTPLUG_SHUTDOWN
132         bl      tegra30_cpu_shutdown
133         mov     pc, r6                  @ should never get here
134 ENDPROC(tegra30_hotplug_shutdown)
135
136 /*
137  * tegra30_cpu_shutdown(unsigned long flags)
138  *
139  * Puts the current CPU in wait-for-event mode on the flow controller
140  * and powergates it -- flags (in R0) indicate the request type.
141  * Must never be called for CPU 0.
142  *
143  * corrupts r0-r4, r12
144  */
145 ENTRY(tegra30_cpu_shutdown)
146         cpu_id  r3
147         cmp     r3, #0
148         moveq   pc, lr          @ Must never be called for CPU 0
149
150         ldr     r12, =TEGRA_FLOW_CTRL_VIRT
151         cpu_to_csr_reg r1, r3
152         add     r1, r1, r12     @ virtual CSR address for this CPU
153         cpu_to_halt_reg r2, r3
154         add     r2, r2, r12     @ virtual HALT_EVENTS address for this CPU
155
156         /*
157          * Clear this CPU's "event" and "interrupt" flags and power gate
158          * it when halting but not before it is in the "WFE" state.
159          */
160         movw    r12, \
161                 FLOW_CTRL_CSR_INTR_FLAG | FLOW_CTRL_CSR_EVENT_FLAG | \
162                 FLOW_CTRL_CSR_ENABLE
163         mov     r4, #(1 << 4)
164         orr     r12, r12, r4, lsl r3
165         str     r12, [r1]
166
167         /* Halt this CPU. */
168         mov     r3, #0x400
169 delay_1:
170         subs    r3, r3, #1                      @ delay as a part of wfe war.
171         bge     delay_1;
172         cpsid   a                               @ disable imprecise aborts.
173         ldr     r3, [r1]                        @ read CSR
174         str     r3, [r1]                        @ clear CSR
175         tst     r0, #TEGRA30_POWER_HOTPLUG_SHUTDOWN
176         moveq   r3, #FLOW_CTRL_WAIT_FOR_INTERRUPT       @ For LP2
177         movne   r3, #FLOW_CTRL_WAITEVENT                @ For hotplug
178         str     r3, [r2]
179         ldr     r0, [r2]
180         b       wfe_war
181
182 __cpu_reset_again:
183         dsb
184         .align 5
185         wfe                                     @ CPU should be power gated here
186 wfe_war:
187         b       __cpu_reset_again
188
189         /*
190          * 38 nop's, which fills reset of wfe cache line and
191          * 4 more cachelines with nop
192          */
193         .rept 38
194         nop
195         .endr
196         b       .                               @ should never get here
197
198 ENDPROC(tegra30_cpu_shutdown)
199 #endif
200
201 #ifdef CONFIG_PM_SLEEP
202 /*
203  * tegra3_sleep_core_finish(unsigned long int)
204  *
205  * enters suspend in LP0 or LP1 by turning off the mmu and jumping to
206  * tegra3_tear_down_core in IRAM
207  */
208 ENTRY(tegra3_sleep_core_finish)
209         bl      tegra_cpu_exit_coherency
210
211         /* preload all the address literals that are needed for the
212          * CPU power-gating process, to avoid loads from SDRAM (which are
213          * not supported once SDRAM is put into self-refresh.
214          * LP0 / LP1 use physical address, since the MMU needs to be
215          * disabled before putting SDRAM into self-refresh to avoid
216          * memory access due to page table walks */
217         mov32   r4, TEGRA_PMC_BASE
218         mov32   r5, TEGRA_CLK_RESET_BASE
219         mov32   r6, TEGRA_FLOW_CTRL_BASE
220         mov32   r7, TEGRA_TMRUS_BASE
221
222         mov32   r1, tegra3_tear_down_core
223         mov32   r2, tegra3_iram_start
224         sub     r1, r1, r2
225         mov32   r2, TEGRA_IRAM_CODE_AREA
226         add     r1, r1, r2
227         b       tegra_turn_off_mmu
228 ENDPROC(tegra3_sleep_core_finish)
229
230 /*
231  * tegra3_sleep_cpu_secondary_finish(unsigned long v2p)
232  *
233  * Enters LP2 on secondary CPU by exiting coherency and powergating the CPU.
234  */
235 ENTRY(tegra3_sleep_cpu_secondary_finish)
236         mov     r6, lr
237
238         dsb
239 #ifdef MULTI_CACHE
240         mov32   r10, cpu_cache
241         mov     lr, pc
242         ldr     pc, [r10, #CACHE_FLUSH_KERN_ALL]
243 #else
244         bl      __cpuc_flush_kern_all
245 #endif
246
247         bl      tegra_cpu_exit_coherency
248
249         /* Powergate this CPU. */
250         mov     r0, #0                          @ power mode flags (!hotplug)
251         bl      tegra30_cpu_shutdown
252         mov     r0, #1                          @ never return here
253         mov     pc, r6
254 ENDPROC(tegra3_sleep_cpu_secondary_finish)
255
256 /*
257  * tegra3_tear_down_cpu
258  *
259  * Switches the CPU cluster to PLL-P and enters sleep.
260  */
261 ENTRY(tegra3_tear_down_cpu)
262         mov32   r4, TEGRA_PMC_BASE
263         mov32   r5, TEGRA_CLK_RESET_BASE
264         mov32   r6, TEGRA_FLOW_CTRL_BASE
265         mov32   r7, TEGRA_TMRUS_BASE
266 #if USE_PLLP_ON_SLEEP_ENTRY
267         bl      tegra_cpu_pllp
268 #endif
269         b       tegra3_enter_sleep
270 ENDPROC(tegra3_tear_down_cpu)
271
272 /* START OF ROUTINES COPIED TO IRAM */
273         .align L1_CACHE_SHIFT
274         .globl tegra3_iram_start
275 tegra3_iram_start:
276
277 /*
278  * tegra3_lp1_reset
279  *
280  * reset vector for LP1 restore; copied into IRAM during suspend.
281  * brings the system back up to a safe starting point (SDRAM out of
282  * self-refresh, PLLC, PLLM and PLLP reenabled, CPU running on PLLP,
283  * system clock running on the same PLL that it suspended at), and
284  * jumps to tegra_lp2_startup to restore PLLX and virtual addressing.
285  * physical address of tegra_lp2_startup expected to be stored in
286  * PMC_SCRATCH41
287  *
288  * NOTE: THIS *MUST* BE RELOCATED TO TEGRA_IRAM_CODE_AREA AND MUST BE FIRST.
289  */
290 .macro pll_enable, rd, car, base, misc
291         ldr     \rd, [\car, #\base]
292         tst     \rd, #(1<<30)
293         orreq   \rd, \rd, #(1<<30)
294         streq   \rd, [\car, #\base]
295 #if USE_PLL_LOCK_BITS
296         ldr     \rd, [\car, #\misc]
297         orr     \rd, \rd, #(1<<18)
298         str     \rd, [\car, #\misc]
299 #endif
300 .endm
301
302 .macro pll_locked, rd, car, base
303 #if USE_PLL_LOCK_BITS
304 1:
305         ldr     \rd, [\car, #\base]
306         tst     \rd, #(1<<27)
307         beq     1b
308 #endif
309 .endm
310
311 ENTRY(tegra3_lp1_reset)
312         /* the CPU and system bus are running at 32KHz and executing from
313          * IRAM when this code is executed; immediately switch to CLKM and
314          * enable PLLP, PLLM, PLLC, PLLA and PLLX. */
315         mov32   r0, TEGRA_CLK_RESET_BASE
316 #ifndef CONFIG_TRUSTED_FOUNDATIONS
317         /* secure code handles 32KHz to CLKM/OSC clock switch */
318         mov     r1, #(1<<28)
319         str     r1, [r0, #CLK_RESET_SCLK_BURST]
320         str     r1, [r0, #CLK_RESET_CCLK_BURST]
321         mov     r1, #0
322         str     r1, [r0, #CLK_RESET_SCLK_DIVIDER]
323         str     r1, [r0, #CLK_RESET_CCLK_DIVIDER]
324 #endif
325         /* enable PLLM via PMC */
326         mov32   r2, TEGRA_PMC_BASE
327         ldr     r1, [r2, #PMC_PLLP_WB0_OVERRIDE]
328         orr     r1, r1, #(1<<12)
329         str     r1, [r2, #PMC_PLLP_WB0_OVERRIDE]
330
331         pll_enable r1, r0, CLK_RESET_PLLM_BASE, CLK_RESET_PLLM_MISC
332         pll_enable r1, r0, CLK_RESET_PLLP_BASE, CLK_RESET_PLLP_MISC
333         pll_enable r1, r0, CLK_RESET_PLLA_BASE, CLK_RESET_PLLA_MISC
334         pll_enable r1, r0, CLK_RESET_PLLC_BASE, CLK_RESET_PLLC_MISC
335         pll_enable r1, r0, CLK_RESET_PLLX_BASE, CLK_RESET_PLLX_MISC
336
337         pll_locked r1, r0, CLK_RESET_PLLM_BASE
338         pll_locked r1, r0, CLK_RESET_PLLP_BASE
339         pll_locked r1, r0, CLK_RESET_PLLA_BASE
340         pll_locked r1, r0, CLK_RESET_PLLC_BASE
341         pll_locked r1, r0, CLK_RESET_PLLX_BASE
342
343         mov32   r7, TEGRA_TMRUS_BASE
344         ldr     r1, [r7]
345         add     r1, r1, #LOCK_DELAY
346         wait_until r1, r7, r3
347
348         add     r5, pc, #tegra3_sdram_pad_save-(.+8)    @ r5 reserved for pad base
349
350         ldr     r4, [r5, #0x18]
351         str     r4, [r0, #CLK_RESET_CLK_SOURCE_MSELECT]
352
353         ldr     r4, [r5, #0x1C]
354         str     r4, [r0, #CLK_RESET_SCLK_BURST]
355
356         mov32   r4, ((1<<28) | (8))     @ burst policy is PLLX
357         str     r4, [r0, #CLK_RESET_CCLK_BURST]
358
359 #if defined (CONFIG_CACHE_L2X0)
360         /* power up L2 */
361         ldr     r0, [r2, #PMC_PWRGATE_STATUS]
362         tst     r0, #(1<<PMC_PWRGATE_PARTID_L2C)
363         bne     powerup_l2_done
364         movw    r0, #(1<<8) | PMC_PWRGATE_PARTID_L2C
365         str     r0, [r2, #PMC_PWRGATE_TOGGLE]
366 powerup_l2_wait:
367         ldr     r0, [r2, #PMC_PWRGATE_STATUS]
368         tst     r0, #(1<<PMC_PWRGATE_PARTID_L2C)
369         beq     powerup_l2_wait
370 powerup_l2_done:
371         mov     r0, #PMC_PWRGATE_PARTID_L2C
372         str     r0, [r2, #PMC_REMOVE_CLAMPING_CMD]
373 #endif
374
375         mov32   r0, TEGRA_EMC_BASE                      @ r0 reserved for emc base
376
377         ldr     r1, [r5, #0x14] @ PMC_IO_DPD_STATUS
378         mvn     r1, r1
379         bic     r1, r1, #(0x1<<31)
380         orr     r1, r1, #(0x1<<30)
381         str     r1, [r2, #PMC_IO_DPD_REQ]
382         ldr     r1, [r5, #0xC]
383         str     r1, [r0, #EMC_XM2VTTGENPADCTRL]
384         ldr     r1, [r5, #0x10]
385         str     r1, [r0, #EMC_XM2VTTGENPADCTRL2]
386         ldr     r1, [r5, #0x8]
387         str     r1, [r0, #EMC_AUTO_CAL_INTERVAL]
388
389         ldr     r1, [r0, #EMC_CFG_DIG_DLL]
390         orr     r1, r1, #(0x1<<30)              @ set DLL_RESET
391         str     r1, [r0, #EMC_CFG_DIG_DLL]
392
393         emc_timing_update r1, r0
394
395         ldr     r1, [r0, #EMC_AUTO_CAL_CONFIG]
396         orr     r1, r1, #(0x1<<31)              @ set AUTO_CAL_ACTIVE
397         str     r1, [r0, #EMC_AUTO_CAL_CONFIG]
398
399 emc_wait_audo_cal_onetime:
400         ldr     r1, [r0, #EMC_AUTO_CAL_STATUS]
401         tst     r1, #(0x1<<31)          @ wait until AUTO_CAL_ACTIVE is clear
402         bne     emc_wait_audo_cal_onetime
403
404         ldr     r1, [r0, #EMC_CFG]
405         bic     r1, r1, #(1<<31)        @ disable DRAM_CLK_STOP
406         str     r1, [r0, #EMC_CFG]
407
408         mov     r1, #0
409         str     r1, [r0, #EMC_SELF_REF] @ take DRAM out of self refresh
410         mov     r1, #1
411         str     r1, [r0, #EMC_NOP]
412         str     r1, [r0, #EMC_NOP]
413         str     r1, [r0, #EMC_REFRESH]
414
415         emc_device_mask r1, r0
416
417 exit_selfrefresh_loop:
418         ldr     r2, [r0, #EMC_EMC_STATUS]
419         ands    r2, r2, r1
420         bne     exit_selfrefresh_loop
421
422         lsr     r1, r1, #8              @ devSel, bit0:dev0 bit1:dev1
423
424         mov32   r7, TEGRA_TMRUS_BASE
425         ldr     r2, [r0, #EMC_FBIO_CFG5]
426
427         and     r2, r2, #3
428         cmp     r2, #2
429         beq     emc_lpddr2
430
431         mov32   r2, 0x80000011
432         str     r2, [r0, #EMC_ZQ_CAL]
433         ldr     r2, [r7]
434         add     r2, r2, #10
435         wait_until r2, r7, r3
436
437         tst     r1, #2
438         beq zcal_done
439
440         mov32   r2, 0x40000011
441         str     r2, [r0, #EMC_ZQ_CAL]
442         ldr     r2, [r7]
443         add     r2, r2, #10
444         wait_until r2, r7, r3
445         b zcal_done
446
447 emc_lpddr2:
448
449         mov32   r2, 0x800A00AB
450         str     r2, [r0, #EMC_MRW]
451         ldr     r2, [r7]
452         add     r2, r2, #1
453         wait_until r2, r7, r3
454
455         tst     r1, #2
456         beq zcal_done
457
458         mov32   r2, 0x400A00AB
459         str     r2, [r0, #EMC_MRW]
460         ldr     r2, [r7]
461         add     r2, r2, #1
462         wait_until r2, r7, r3
463
464 zcal_done:
465
466         mov     r1, #0
467         str     r1, [r0, #EMC_REQ_CTRL]
468         ldr     r1, [r5, #0x4]
469         str     r1, [r0, #EMC_ZCAL_INTERVAL]
470         ldr     r1, [r5, #0x0]
471         str     r1, [r0, #EMC_CFG]
472
473         mov32   r0, TEGRA_PMC_BASE
474         ldr     r0, [r0, #PMC_SCRATCH41]
475         mov     pc, r0
476 ENDPROC(tegra3_lp1_reset)
477
478         .align  L1_CACHE_SHIFT
479         .type   tegra3_sdram_pad_save, %object
480 tegra3_sdram_pad_save:
481         .word   0
482         .word   0
483         .word   0
484         .word   0
485         .word   0
486         .word   0
487         .word   0
488         .word   0
489
490 tegra3_sdram_pad_address:
491         .word   TEGRA_EMC_BASE + EMC_CFG                                @0x0
492         .word   TEGRA_EMC_BASE + EMC_ZCAL_INTERVAL                      @0x4
493         .word   TEGRA_EMC_BASE + EMC_AUTO_CAL_INTERVAL                  @0x8
494         .word   TEGRA_EMC_BASE + EMC_XM2VTTGENPADCTRL                   @0xc
495         .word   TEGRA_EMC_BASE + EMC_XM2VTTGENPADCTRL2                  @0x10
496         .word   TEGRA_PMC_BASE + PMC_IO_DPD_STATUS                      @0x14
497         .word   TEGRA_CLK_RESET_BASE + CLK_RESET_CLK_SOURCE_MSELECT     @0x18
498         .word   TEGRA_CLK_RESET_BASE + CLK_RESET_SCLK_BURST             @0x1c
499
500 tegra3_sdram_pad_size:
501         .word   tegra3_sdram_pad_address - tegra3_sdram_pad_save
502
503 /*
504  * tegra3_tear_down_core
505  *
506  * copied into and executed from IRAM
507  * puts memory in self-refresh for LP0 and LP1
508  */
509 tegra3_tear_down_core:
510         bl      tegra3_sdram_self_refresh
511         bl      tegra3_cpu_clk32k
512         b       tegra3_enter_sleep
513
514 /*
515  * tegra3_cpu_clk32k
516  *
517  * In LP0 and LP1 all plls will be turned off.  Switch the CPU and system clock
518  * to the 32khz clock (clks)
519  * r4 = TEGRA_PMC_BASE
520  * r5 = TEGRA_CLK_RESET_BASE
521  * r6 = TEGRA_FLOW_CTRL_BASE
522  * r7 = TEGRA_TMRUS_BASE
523  */
524 tegra3_cpu_clk32k:
525         ldr     r0, [r4, #PMC_CTRL]
526         tst     r0, #PMC_CTRL_SIDE_EFFECT_LP0
527         beq     lp1_clocks_prepare
528
529         /* enable PLLM via PMC in LP0 */
530         ldr     r0, [r4, #PMC_PLLP_WB0_OVERRIDE]
531         orr     r0, r0, #((1 << 12) | (1 << 11))
532         str     r0, [r4, #PMC_PLLP_WB0_OVERRIDE]
533         mov     pc, lr
534
535         /* start by jumping to clkm to safely disable PLLs, then jump
536          * to clks */
537 lp1_clocks_prepare:
538         mov     r0, #(1 << 28)
539         str     r0, [r5, #CLK_RESET_SCLK_BURST]
540         str     r0, [r5, #CLK_RESET_CCLK_BURST]
541         mov     r0, #0
542         str     r0, [r5, #CLK_RESET_CCLK_DIVIDER]
543         str     r0, [r5, #CLK_RESET_SCLK_DIVIDER]
544
545         /* switch the clock source for mselect to be CLK_M */
546         ldr     r0, [r5, #CLK_RESET_CLK_SOURCE_MSELECT]
547         orr     r0, r0, #MSELECT_CLKM
548         str     r0, [r5, #CLK_RESET_CLK_SOURCE_MSELECT]
549
550         /* 2 us delay between changing sclk and disabling PLLs */
551         wait_for_us r1, r7, r9
552         add     r1, r1, #2
553         wait_until r1, r7, r9
554
555         /* switch to CLKS */
556         mov     r0, #0  /* burst policy = 32KHz */
557         str     r0, [r5, #CLK_RESET_SCLK_BURST]
558
559         /* disable PLLM via PMC in LP1 */
560         ldr     r0, [r4, #PMC_PLLP_WB0_OVERRIDE]
561         bic     r0, r0, #(1 << 12)
562         str     r0, [r4, #PMC_PLLP_WB0_OVERRIDE]
563         b       powerdown_pll_pcx
564
565 powerdown_pll_pcx:
566         ldr     r11, [r4, #PMC_SCRATCH37]       @ load the LP1 flags
567         tst     r11, #TEGRA_POWER_LP1_AUDIO     @ check if voice call is going on
568         bne     powerdown_pll_cx                @ if yes, do not turn off pll-p/pll-a
569
570         ldr     r0, [r5, #CLK_RESET_PLLP_BASE]
571         bic     r0, r0, #(1<<30)
572         str     r0, [r5, #CLK_RESET_PLLP_BASE]
573         ldr     r0, [r5, #CLK_RESET_PLLA_BASE]
574         bic     r0, r0, #(1<<30)
575         str     r0, [r5, #CLK_RESET_PLLA_BASE]
576
577 powerdown_pll_cx:
578         ldr     r0, [r5, #CLK_RESET_PLLC_BASE]
579         bic     r0, r0, #(1<<30)
580         str     r0, [r5, #CLK_RESET_PLLC_BASE]
581         ldr     r0, [r5, #CLK_RESET_PLLX_BASE]
582         bic     r0, r0, #(1<<30)
583         str     r0, [r5, #CLK_RESET_PLLX_BASE]
584
585         mov     pc, lr
586
587 /*
588  * tegra3_enter_sleep
589  *
590  * uses flow controller to enter sleep state
591  * executes from IRAM with SDRAM in selfrefresh when target state is LP0 or LP1
592  * executes from SDRAM with target state is LP2
593  * r4 = TEGRA_PMC_BASE
594  * r5 = TEGRA_CLK_RESET_BASE
595  * r6 = TEGRA_FLOW_CTRL_BASE
596  * r7 = TEGRA_TMRUS_BASE
597  */
598 tegra3_enter_sleep:
599         ldr     r1, [r7]
600         str     r1, [r4, #PMC_SCRATCH38]
601         dsb
602         cpu_id  r1
603
604         cpu_to_csr_reg  r2, r1
605         ldr     r0, [r6, r2]
606         orr     r0, r0, #FLOW_CTRL_CSR_INTR_FLAG | FLOW_CTRL_CSR_EVENT_FLAG
607         orr     r0, r0, #FLOW_CTRL_CSR_ENABLE
608         str     r0, [r6, r2]
609
610         mov     r0, #FLOW_CTRL_WAIT_FOR_INTERRUPT
611         orr     r0, r0, #FLOW_CTRL_HALT_CPU_IRQ | FLOW_CTRL_HALT_CPU_FIQ
612         cpu_to_halt_reg r2, r1
613         str     r0, [r6, r2]
614         dsb
615         ldr     r0, [r6, r2] /* memory barrier */
616
617 halted:
618         isb
619         dsb
620         wfi     /* CPU should be power gated here */
621
622         /* !!!FIXME!!! Implement halt failure handler */
623         b       halted
624
625 /*
626  * tegra3_sdram_self_refresh
627  *
628  * called with MMU off and caches disabled
629  * puts sdram in self refresh
630  * must execute from IRAM
631  * r4 = TEGRA_PMC_BASE
632  * r5 = TEGRA_CLK_RESET_BASE
633  * r6 = TEGRA_FLOW_CTRL_BASE
634  * r7 = TEGRA_TMRUS_BASE
635  */
636
637 tegra3_sdram_self_refresh:
638
639         adr     r2, tegra3_sdram_pad_address
640         adr     r8, tegra3_sdram_pad_save
641         mov     r9, #0
642
643 padsave:
644         ldr     r0, [r2, r9]                    @ r0 is emc register address
645
646         ldr     r1, [r0]
647         str     r1, [r8, r9]                    @ save emc register
648
649         add     r9, r9, #4
650         ldr     r0, tegra3_sdram_pad_size
651         cmp     r0, r9
652         bne     padsave
653 padsave_done:
654
655         dsb
656
657         mov32   r0, TEGRA_EMC_BASE                      @ r0 reserved for emc base
658
659         mov     r1, #0
660         str     r1, [r0, #EMC_ZCAL_INTERVAL]
661         str     r1, [r0, #EMC_AUTO_CAL_INTERVAL]
662         ldr     r1, [r0, #EMC_CFG]
663         bic     r1, r1, #(1<<28)
664         str     r1, [r0, #EMC_CFG]              @ disable DYN_SELF_REF
665
666         emc_timing_update r1, r0
667
668         ldr     r1, [r7]
669         add     r1, r1, #5
670         wait_until r1, r7, r2
671
672 emc_wait_audo_cal:
673         ldr     r1, [r0, #EMC_AUTO_CAL_STATUS]
674         tst     r1, #(0x1<<31)          @ wait until AUTO_CAL_ACTIVE is clear
675         bne     emc_wait_audo_cal
676
677         mov     r1, #3
678         str     r1, [r0, #EMC_REQ_CTRL]         @ stall incoming DRAM requests
679
680 emcidle:
681         ldr     r1, [r0, #EMC_EMC_STATUS]
682         tst     r1, #4
683         beq     emcidle
684
685         mov     r1, #1
686         str     r1, [r0, #EMC_SELF_REF]
687
688         emc_device_mask r1, r0
689
690 emcself:
691         ldr     r2, [r0, #EMC_EMC_STATUS]
692         and     r2, r2, r1
693         cmp     r2, r1
694         bne     emcself                         @ loop until DDR in self-refresh
695
696         ldr     r1, [r0, #EMC_XM2VTTGENPADCTRL]
697         mov32   r2, 0xF8F8FFFF          @ clear XM2VTTGEN_DRVUP and XM2VTTGEN_DRVDN
698         and     r1, r1, r2
699         str     r1, [r0, #EMC_XM2VTTGENPADCTRL]
700         ldr     r1, [r0, #EMC_XM2VTTGENPADCTRL2]
701         orr     r1, r1, #7                      @ set E_NO_VTTGEN
702         str     r1, [r0, #EMC_XM2VTTGENPADCTRL2]
703
704         emc_timing_update r1, r0
705
706         ldr     r1, [r4, #PMC_CTRL]
707         tst     r1, #PMC_CTRL_SIDE_EFFECT_LP0
708         bne     pmc_io_dpd_skip
709         mov32   r1, 0x8EC00000
710         str     r1, [r4, #PMC_IO_DPD_REQ]
711 pmc_io_dpd_skip:
712
713         dsb
714
715         mov     pc, lr
716
717         .ltorg
718 /* dummy symbol for end of IRAM */
719         .align L1_CACHE_SHIFT
720         .globl tegra3_iram_end
721 tegra3_iram_end:
722         b       .
723 #endif