arm: tegra: poll CLAMP_STATUS
[linux-3.10.git] / arch / arm / mach-tegra / powergate.c
1 /*
2  * arch/arm/mach-tegra/powergate.c
3  *
4  * Copyright (c) 2010 Google, Inc
5  * Copyright (c) 2011 - 2013, NVIDIA CORPORATION.  All rights reserved.
6  *
7  * Author:
8  *      Colin Cross <ccross@google.com>
9  *
10  * This software is licensed under the terms of the GNU General Public
11  * License version 2, as published by the Free Software Foundation, and
12  * may be copied, distributed, and modified under those terms.
13  *
14  * This program is distributed in the hope that it will be useful,
15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
17  * GNU General Public License for more details.
18  *
19  */
20
21 #include <linux/kernel.h>
22 #include <linux/module.h>
23 #include <linux/clk.h>
24 #include <linux/clk/tegra.h>
25 #include <linux/string.h>
26 #include <linux/debugfs.h>
27 #include <linux/delay.h>
28 #include <linux/err.h>
29 #include <linux/init.h>
30 #include <linux/io.h>
31 #include <linux/seq_file.h>
32 #include <linux/spinlock.h>
33 #include <linux/clk/tegra.h>
34 #include <linux/tegra-powergate.h>
35 #include <linux/tegra-soc.h>
36 #include <trace/events/power.h>
37 #include <asm/atomic.h>
38
39 #include "clock.h"
40 #include "fuse.h"
41 #include "iomap.h"
42 #include "powergate-priv.h"
43
44 static struct powergate_ops *pg_ops;
45
46 static spinlock_t *tegra_get_powergate_lock(void)
47 {
48         if (pg_ops && pg_ops->get_powergate_lock)
49                 return pg_ops->get_powergate_lock();
50         else
51                 WARN_ON_ONCE("This SOC does not export powergate lock");
52
53         return NULL;
54 }
55
56 int tegra_powergate_set(int id, bool new_state)
57 {
58         bool status;
59         unsigned long flags;
60         spinlock_t *lock;
61
62         /* 10us timeout for toggle operation if it takes affect*/
63         int toggle_timeout = 10;
64
65         /* 100 * 10 = 1000us timeout for toggle command to take affect in case
66            of contention with h/w initiated CPU power gating */
67         int contention_timeout = 100;
68
69         if (tegra_cpu_is_asim())
70                 return 0;
71
72         lock = tegra_get_powergate_lock();
73
74         spin_lock_irqsave(lock, flags);
75
76         status = !!(pmc_read(PWRGATE_STATUS) & (1 << id));
77
78         if (status == new_state) {
79                 spin_unlock_irqrestore(lock, flags);
80                 return 0;
81         }
82
83         if (TEGRA_IS_CPU_POWERGATE_ID(id)) {
84                 /* CPU ungated in s/w only during boot/resume with outer
85                    waiting loop and no contention from other CPUs */
86                 pmc_write(PWRGATE_TOGGLE_START | id, PWRGATE_TOGGLE);
87                 spin_unlock_irqrestore(lock, flags);
88                 return 0;
89         }
90
91         pmc_write(PWRGATE_TOGGLE_START | id, PWRGATE_TOGGLE);
92         do {
93                 do {
94                         udelay(1);
95                         status = !!(pmc_read(PWRGATE_STATUS) & (1 << id));
96
97                         toggle_timeout--;
98                 } while ((status != new_state) && (toggle_timeout > 0));
99
100                 contention_timeout--;
101         } while ((status != new_state) && (contention_timeout > 0));
102
103         spin_unlock_irqrestore(lock, flags);
104
105         if (status != new_state) {
106                 WARN(1, "Could not set powergate %d to %d", id, new_state);
107                 return -EBUSY;
108         }
109
110         trace_power_domain_target(tegra_powergate_get_name(id), new_state,
111                         raw_smp_processor_id());
112
113         return 0;
114 }
115
116 int is_partition_clk_disabled(struct powergate_partition_info *pg_info)
117 {
118         u32 idx;
119         struct clk *clk;
120         struct partition_clk_info *clk_info;
121         int ret = 0;
122
123         for (idx = 0; idx < MAX_CLK_EN_NUM; idx++) {
124                 clk_info = &pg_info->clk_info[idx];
125                 clk = clk_info->clk_ptr;
126
127                 if (!clk)
128                         break;
129
130                 if (clk_info->clk_type != RST_ONLY) {
131                         if (tegra_is_clk_enabled(clk)) {
132                                 ret = -1;
133                                 break;
134                         }
135                 }
136         }
137
138         return ret;
139 }
140
141 int powergate_module(int id)
142 {
143         if (!pg_ops) {
144                 pr_info("This SOC doesn't support powergating\n");
145                 return -EINVAL;
146         }
147
148         if (id < 0 || id >= pg_ops->num_powerdomains)
149                 return -EINVAL;
150
151         tegra_powergate_mc_flush(id);
152
153         return tegra_powergate_set(id, false);
154 }
155
156 int unpowergate_module(int id)
157 {
158         if (!pg_ops) {
159                 pr_info("This SOC doesn't support powergating\n");
160                 return -EINVAL;
161         }
162
163         if (id < 0 || id >= pg_ops->num_powerdomains)
164                 return -EINVAL;
165
166         return tegra_powergate_set(id, true);
167 }
168
169 int partition_clk_enable(struct powergate_partition_info *pg_info)
170 {
171         int ret;
172         u32 idx;
173         struct clk *clk;
174         struct partition_clk_info *clk_info;
175
176         for (idx = 0; idx < MAX_CLK_EN_NUM; idx++) {
177                 clk_info = &pg_info->clk_info[idx];
178                 clk = clk_info->clk_ptr;
179                 if (!clk)
180                         break;
181
182                 if (clk_info->clk_type != RST_ONLY) {
183                         ret = tegra_clk_prepare_enable(clk);
184                         if (ret)
185                                 goto err_clk_en;
186                 }
187         }
188
189         return 0;
190
191 err_clk_en:
192         WARN(1, "Could not enable clk %s, error %d", clk->name, ret);
193         while (idx--) {
194                 clk_info = &pg_info->clk_info[idx];
195                 if (clk_info->clk_type != RST_ONLY)
196                         tegra_clk_disable_unprepare(clk_info->clk_ptr);
197         }
198
199         return ret;
200 }
201
202 void partition_clk_disable(struct powergate_partition_info *pg_info)
203 {
204         u32 idx;
205         struct clk *clk;
206         struct partition_clk_info *clk_info;
207
208         for (idx = 0; idx < MAX_CLK_EN_NUM; idx++) {
209                 clk_info = &pg_info->clk_info[idx];
210                 clk = clk_info->clk_ptr;
211
212                 if (!clk)
213                         break;
214
215                 if (clk_info->clk_type != RST_ONLY)
216                         tegra_clk_disable_unprepare(clk);
217         }
218 }
219
220 void get_clk_info(struct powergate_partition_info *pg_info)
221 {
222         int idx;
223
224         for (idx = 0; idx < MAX_CLK_EN_NUM; idx++) {
225                 if (!pg_info->clk_info[idx].clk_name)
226                         break;
227
228                 pg_info->clk_info[idx].clk_ptr = tegra_get_clock_by_name(
229                         pg_info->clk_info[idx].clk_name);
230         }
231 }
232
233 void powergate_partition_assert_reset(struct powergate_partition_info *pg_info)
234 {
235         u32 idx;
236         struct clk *clk_ptr;
237         struct partition_clk_info *clk_info;
238
239         for (idx = 0; idx < MAX_CLK_EN_NUM; idx++) {
240                 clk_info = &pg_info->clk_info[idx];
241                 clk_ptr = clk_info->clk_ptr;
242
243                 if (!clk_ptr)
244                         break;
245
246                 if (clk_info->clk_type != CLK_ONLY)
247                         tegra_periph_reset_assert(clk_ptr);
248         }
249 }
250
251 void powergate_partition_deassert_reset(struct powergate_partition_info *pg_info)
252 {
253         u32 idx;
254         struct clk *clk_ptr;
255         struct partition_clk_info *clk_info;
256
257         for (idx = 0; idx < MAX_CLK_EN_NUM; idx++) {
258                 clk_info = &pg_info->clk_info[idx];
259                 clk_ptr = clk_info->clk_ptr;
260
261                 if (!clk_ptr)
262                         break;
263
264                 if (clk_info->clk_type != CLK_ONLY)
265                         tegra_periph_reset_deassert(clk_ptr);
266         }
267 }
268
269 int tegra_powergate_reset_module(struct powergate_partition_info *pg_info)
270 {
271         int ret;
272
273         powergate_partition_assert_reset(pg_info);
274
275         udelay(10);
276
277         ret = partition_clk_enable(pg_info);
278         if (ret)
279                 return ret;
280
281         udelay(10);
282
283         powergate_partition_deassert_reset(pg_info);
284
285         partition_clk_disable(pg_info);
286
287         return 0;
288 }
289
290 bool tegra_powergate_check_clamping(int id)
291 {
292         if (!pg_ops || !pg_ops->powergate_check_clamping) {
293                 pr_info("This SOC can't check clamping status\n");
294                 return -EINVAL;
295         }
296
297         if (id < 0 || id >= pg_ops->num_powerdomains)
298                 return -EINVAL;
299
300         return pg_ops->powergate_check_clamping(id);
301 }
302
303 int tegra_powergate_remove_clamping(int id)
304 {
305         u32 mask;
306         int contention_timeout = 100;
307
308         if (!pg_ops) {
309                 pr_info("This SOC doesn't support powergating\n");
310                 return -EINVAL;
311         }
312
313         if (id < 0 || id >= pg_ops->num_powerdomains)
314                 return -EINVAL;
315
316         /*
317          * PCIE and VDE clamping masks are swapped with respect to their
318          * partition ids
319          */
320         if (id ==  TEGRA_POWERGATE_VDEC)
321                 mask = (1 << TEGRA_POWERGATE_PCIE);
322         else if (id == TEGRA_POWERGATE_PCIE)
323                 mask = (1 << TEGRA_POWERGATE_VDEC);
324         else
325                 mask = (1 << id);
326
327         pmc_write(mask, REMOVE_CLAMPING);
328         /* Wait until clamp is removed */
329         do {
330                 udelay(1);
331                 contention_timeout--;
332         } while ((contention_timeout > 0)
333                         && (pmc_read(PWRGATE_CLAMP_STATUS) & mask));
334
335         WARN(contention_timeout <= 0, "Couldn't remove clamping");
336
337         return 0;
338 }
339
340 static inline bool tegra_powergate_check_skip_list(int id)
341 {
342         return pg_ops->powergate_skip ?
343                 pg_ops->powergate_skip(id) : false;
344 }
345
346 /* EXTERNALY VISIBLE APIS */
347
348 bool tegra_powergate_is_powered(int id)
349 {
350         u32 status;
351
352         if (!pg_ops) {
353                 pr_info("This SOC doesn't support powergating\n");
354                 return -EINVAL;
355         }
356
357         if (id < 0 || id >= pg_ops->num_powerdomains)
358                 return -EINVAL;
359
360         if (pg_ops->powergate_is_powered)
361                 return pg_ops->powergate_is_powered(id);
362         else
363                 status = pmc_read(PWRGATE_STATUS) & (1 << id);
364
365         status = pmc_read(PWRGATE_STATUS) & (1 << id);
366
367         return !!status;
368 }
369 EXPORT_SYMBOL(tegra_powergate_is_powered);
370
371 int tegra_cpu_powergate_id(int cpuid)
372 {
373         if (!pg_ops) {
374                 pr_info("This SOC doesn't support powergating\n");
375                 return -EINVAL;
376         }
377
378         if (cpuid < 0 || cpuid >= pg_ops->num_cpu_domains) {
379                 pr_info("%s: invalid powergate id\n", __func__);
380                 return -EINVAL;
381         }
382
383         if (pg_ops->cpu_domains)
384                 return pg_ops->cpu_domains[cpuid];
385         else
386                 WARN_ON_ONCE("This SOC does not support CPU powergate\n");
387
388         return -EINVAL;
389 }
390 EXPORT_SYMBOL(tegra_cpu_powergate_id);
391
392 int tegra_powergate_partition(int id)
393 {
394         if (!pg_ops) {
395                 pr_info("This SOC doesn't support powergating\n");
396                 return -EINVAL;
397         }
398
399         if (id < 0 || id >= pg_ops->num_powerdomains) {
400                 pr_info("%s: invalid powergate id\n", __func__);
401                 return -EINVAL;
402         }
403
404         if (tegra_powergate_check_skip_list(id))
405                 printk_once("%s: %s is in powergate skip list\n", __func__,
406                         tegra_powergate_get_name(id));
407
408         if (pg_ops->powergate_partition)
409                 return pg_ops->powergate_partition(id);
410         else
411                 WARN_ON_ONCE("This SOC doesn't support powergating");
412
413         return -EINVAL;
414 }
415 EXPORT_SYMBOL(tegra_powergate_partition);
416
417 int tegra_unpowergate_partition(int id)
418 {
419         if (!pg_ops) {
420                 pr_info("This SOC doesn't support powergating\n");
421                 return -EINVAL;
422         }
423
424         if (id < 0 || id >= pg_ops->num_powerdomains) {
425                 pr_info("%s: invalid powergate id\n", __func__);
426                 return -EINVAL;
427         }
428
429         if (tegra_powergate_check_skip_list(id))
430                 printk_once("%s: %s is in powergate skip list\n", __func__,
431                         tegra_powergate_get_name(id));
432
433         if (pg_ops->unpowergate_partition)
434                 return pg_ops->unpowergate_partition(id);
435         else
436                 WARN_ON_ONCE("This SOC doesn't support un-powergating");
437
438         return -EINVAL;
439 }
440 EXPORT_SYMBOL(tegra_unpowergate_partition);
441
442 int tegra_powergate_partition_with_clk_off(int id)
443 {
444         if (!pg_ops) {
445                 pr_info("This SOC doesn't support powergating\n");
446                 return -EINVAL;
447         }
448
449         if (id < 0 || id >= pg_ops->num_powerdomains) {
450                 pr_info("%s: invalid powergate id\n", __func__);
451                 return -EINVAL;
452         }
453
454         if (tegra_powergate_check_skip_list(id))
455                 printk_once("%s: %s is in powergate skip list\n", __func__,
456                         tegra_powergate_get_name(id));
457
458         if (pg_ops->powergate_partition_with_clk_off)
459                 return pg_ops->powergate_partition_with_clk_off(id);
460         else
461                 WARN_ON_ONCE("This SOC doesn't support powergating with clk off");
462
463         return -EINVAL;
464 }
465 EXPORT_SYMBOL(tegra_powergate_partition_with_clk_off);
466
467 int tegra_unpowergate_partition_with_clk_on(int id)
468 {
469         if (!pg_ops) {
470                 pr_info("This SOC doesn't support powergating\n");
471                 return -EINVAL;
472         }
473
474         if (id < 0 || id >= pg_ops->num_powerdomains) {
475                 pr_info("%s: invalid powergate id\n", __func__);
476                 return -EINVAL;
477         }
478
479         if (tegra_powergate_check_skip_list(id))
480                 printk_once("%s: %s is in powergate skip list\n", __func__,
481                         tegra_powergate_get_name(id));
482
483         if (pg_ops->unpowergate_partition_with_clk_on)
484                 return pg_ops->unpowergate_partition_with_clk_on(id);
485         else
486                 WARN_ON_ONCE("This SOC doesn't support power un-gating with clk on");
487
488         return -EINVAL;
489 }
490 EXPORT_SYMBOL(tegra_unpowergate_partition_with_clk_on);
491
492 int tegra_powergate_mc_enable(int id)
493 {
494         if (!pg_ops) {
495                 pr_info("This SOC doesn't support powergating\n");
496                 return -EINVAL;
497         }
498
499         if (id < 0 || id >= pg_ops->num_powerdomains) {
500                 pr_info("%s: invalid powergate id\n", __func__);
501                 return -EINVAL;
502         }
503
504         if (pg_ops->powergate_mc_enable)
505                 return pg_ops->powergate_mc_enable(id);
506         else
507                 WARN_ON_ONCE("This SOC does not support powergate mc enable");
508
509         return -EINVAL;
510 }
511 EXPORT_SYMBOL(tegra_powergate_mc_enable);
512
513 int tegra_powergate_mc_disable(int id)
514 {
515         if (!pg_ops) {
516                 pr_info("This SOC doesn't support powergating\n");
517                 return -EINVAL;
518         }
519
520         if (id < 0 || id >= pg_ops->num_powerdomains) {
521                 pr_info("%s: invalid powergate id\n", __func__);
522                 return -EINVAL;
523         }
524
525         if (pg_ops->powergate_mc_disable)
526                 return pg_ops->powergate_mc_disable(id);
527         else
528                 WARN_ON_ONCE("This SOC does not support powergate mc disable");
529
530         return -EINVAL;
531 }
532 EXPORT_SYMBOL(tegra_powergate_mc_disable);
533
534 int tegra_powergate_mc_flush(int id)
535 {
536         if (!pg_ops) {
537                 pr_info("This SOC doesn't support powergating\n");
538                 return -EINVAL;
539         }
540
541         if (id < 0 || id >= pg_ops->num_powerdomains) {
542                 pr_info("%s: invalid powergate id\n", __func__);
543                 return -EINVAL;
544         }
545
546         if (pg_ops->powergate_mc_flush)
547                 return pg_ops->powergate_mc_flush(id);
548         else
549                 WARN_ON_ONCE("This SOC does not support powergate mc flush");
550
551         return -EINVAL;
552 }
553 EXPORT_SYMBOL(tegra_powergate_mc_flush);
554
555 int tegra_powergate_mc_flush_done(int id)
556 {
557         if (!pg_ops) {
558                 pr_info("This SOC doesn't support powergating\n");
559                 return -EINVAL;
560         }
561
562         if (id < 0 || id >= pg_ops->num_powerdomains) {
563                 pr_info("%s: invalid powergate id\n", __func__);
564                 return -EINVAL;
565         }
566
567         if (pg_ops->powergate_mc_flush_done)
568                 return pg_ops->powergate_mc_flush_done(id);
569         else
570                 WARN_ON_ONCE("This SOC does not support powergate mc flush done");
571
572         return -EINVAL;
573 }
574 EXPORT_SYMBOL(tegra_powergate_mc_flush_done);
575
576 const char *tegra_powergate_get_name(int id)
577 {
578         if (!pg_ops) {
579                 pr_info("This SOC doesn't support powergating\n");
580                 return NULL;
581         }
582
583         if (id < 0 || id >= pg_ops->num_powerdomains) {
584                 pr_info("invalid powergate id\n");
585                 return "invalid";
586         }
587
588         if (pg_ops->get_powergate_domain_name)
589                 return pg_ops->get_powergate_domain_name(id);
590         else
591                 WARN_ON_ONCE("This SOC does not support CPU powergate");
592
593         return "invalid";
594 }
595 EXPORT_SYMBOL(tegra_powergate_get_name);
596
597 int tegra_powergate_init_refcount(void)
598 {
599         if ((!pg_ops) || (!pg_ops->powergate_init_refcount))
600                 return 0;
601
602         return pg_ops->powergate_init_refcount();
603 }
604
605 int __init tegra_powergate_init(void)
606 {
607         switch (tegra_chip_id) {
608                 case TEGRA_CHIPID_TEGRA2:
609                         pg_ops = tegra2_powergate_init_chip_support();
610                         break;
611
612                 case TEGRA_CHIPID_TEGRA3:
613                         pg_ops = tegra3_powergate_init_chip_support();
614                         break;
615
616                 case TEGRA_CHIPID_TEGRA11:
617                         pg_ops = tegra11x_powergate_init_chip_support();
618                         break;
619
620                 case TEGRA_CHIPID_TEGRA14:
621                         pg_ops = tegra14x_powergate_init_chip_support();
622                         break;
623
624                 case TEGRA_CHIPID_TEGRA12:
625                         pg_ops = tegra12x_powergate_init_chip_support();
626                         break;
627
628                 default:
629                         pg_ops = NULL;
630                         pr_info("%s: Unknown Tegra variant. Disabling powergate\n", __func__);
631                         break;
632         }
633
634         tegra_powergate_init_refcount();
635
636         pr_info("%s: DONE\n", __func__);
637
638         return (pg_ops ? 0 : -EINVAL);
639 }
640
641 #ifdef CONFIG_DEBUG_FS
642
643 static int powergate_show(struct seq_file *s, void *data)
644 {
645         int i;
646         const char *name;
647         bool is_pg_skip;
648
649         if (!pg_ops) {
650                 seq_printf(s, "This SOC doesn't support powergating\n");
651                 return -EINVAL;
652         }
653
654         seq_printf(s, " powergate powered\n");
655         seq_printf(s, "------------------\n");
656
657         for (i = 0; i < pg_ops->num_powerdomains; i++) {
658                 name = tegra_powergate_get_name(i);
659                 if (name) {
660                         is_pg_skip = tegra_powergate_check_skip_list(i);
661                         seq_printf(s, " %9s %7s\n", name,
662                                 (is_pg_skip ? "skip" : \
663                                 (tegra_powergate_is_powered(i) ? \
664                                 "yes" : "no")));
665                 }
666         }
667
668         return 0;
669 }
670
671 static int powergate_open(struct inode *inode, struct file *file)
672 {
673         return single_open(file, powergate_show, inode->i_private);
674 }
675
676 static const struct file_operations powergate_fops = {
677         .open           = powergate_open,
678         .read           = seq_read,
679         .llseek         = seq_lseek,
680         .release        = single_release,
681 };
682
683 int __init tegra_powergate_debugfs_init(void)
684 {
685         struct dentry *d;
686
687         d = debugfs_create_file("powergate", S_IRUGO, NULL, NULL,
688                 &powergate_fops);
689         if (!d)
690                 return -ENOMEM;
691
692         return 0;
693 }
694
695 #endif