arch/arm/mach-tegra/powergate.c

   1 /*
   2  * arch/arm/mach-tegra/powergate.c
   3  *
   4  * Copyright (c) 2010 Google, Inc
   5  * Copyright (c) 2011 - 2013, NVIDIA CORPORATION.  All rights reserved.
   6  *
   7  * Author:
   8  *      Colin Cross <ccross@google.com>
   9  *
  10  * This software is licensed under the terms of the GNU General Public
  11  * License version 2, as published by the Free Software Foundation, and
  12  * may be copied, distributed, and modified under those terms.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  */
  20
  21 #include <linux/kernel.h>
  22 #include <linux/module.h>
  23 #include <linux/clk.h>
  24 #include <linux/clk/tegra.h>
  25 #include <linux/string.h>
  26 #include <linux/debugfs.h>
  27 #include <linux/delay.h>
  28 #include <linux/err.h>
  29 #include <linux/init.h>
  30 #include <linux/io.h>
  31 #include <linux/seq_file.h>
  32 #include <linux/spinlock.h>
  33 #include <linux/clk/tegra.h>
  34 #include <linux/tegra-powergate.h>
  35 #include <linux/tegra-soc.h>
  36 #include <trace/events/power.h>
  37 #include <asm/atomic.h>
  38
  39 #include "clock.h"
  40 #include "fuse.h"
  41 #include "iomap.h"
  42 #include "powergate-priv.h"
  43
  44 static struct powergate_ops *pg_ops;
  45
  46 static spinlock_t *tegra_get_powergate_lock(void)
  47 {
  48         if (pg_ops && pg_ops->get_powergate_lock)
  49                 return pg_ops->get_powergate_lock();
  50         else
  51                 WARN_ON_ONCE("This SOC does not export powergate lock");
  52
  53         return NULL;
  54 }
  55
  56 int tegra_powergate_set(int id, bool new_state)
  57 {
  58         bool status;
  59         unsigned long flags;
  60         spinlock_t *lock;
  61
  62         if (tegra_cpu_is_asim())
  63                 return 0;
  64
  65         lock = tegra_get_powergate_lock();
  66         /* 10us timeout for toggle operation if it takes affect*/
  67         int toggle_timeout = 10;
  68
  69         /* 100 * 10 = 1000us timeout for toggle command to take affect in case
  70            of contention with h/w initiated CPU power gating */
  71         int contention_timeout = 100;
  72
  73         spin_lock_irqsave(lock, flags);
  74
  75         status = !!(pmc_read(PWRGATE_STATUS) & (1 << id));
  76
  77         if (status == new_state) {
  78                 spin_unlock_irqrestore(lock, flags);
  79                 return 0;
  80         }
  81
  82         if (TEGRA_IS_CPU_POWERGATE_ID(id)) {
  83                 /* CPU ungated in s/w only during boot/resume with outer
  84                    waiting loop and no contention from other CPUs */
  85                 pmc_write(PWRGATE_TOGGLE_START | id, PWRGATE_TOGGLE);
  86                 spin_unlock_irqrestore(lock, flags);
  87                 return 0;
  88         }
  89
  90         pmc_write(PWRGATE_TOGGLE_START | id, PWRGATE_TOGGLE);
  91         do {
  92                 do {
  93                         udelay(1);
  94                         status = !!(pmc_read(PWRGATE_STATUS) & (1 << id));
  95
  96                         toggle_timeout--;
  97                 } while ((status != new_state) && (toggle_timeout > 0));
  98
  99                 contention_timeout--;
 100         } while ((status != new_state) && (contention_timeout > 0));
 101
 102         spin_unlock_irqrestore(lock, flags);
 103
 104         if (status != new_state) {
 105                 WARN(1, "Could not set powergate %d to %d", id, new_state);
 106                 return -EBUSY;
 107         }
 108
 109         trace_power_domain_target(tegra_powergate_get_name(id), new_state,
 110                         raw_smp_processor_id());
 111
 112         return 0;
 113 }
 114
 115 int is_partition_clk_disabled(struct powergate_partition_info *pg_info)
 116 {
 117         u32 idx;
 118         struct clk *clk;
 119         struct partition_clk_info *clk_info;
 120         int ret = 0;
 121
 122         for (idx = 0; idx < MAX_CLK_EN_NUM; idx++) {
 123                 clk_info = &pg_info->clk_info[idx];
 124                 clk = clk_info->clk_ptr;
 125
 126                 if (!clk)
 127                         break;
 128
 129                 if (clk_info->clk_type != RST_ONLY) {
 130                         if (tegra_is_clk_enabled(clk)) {
 131                                 ret = -1;
 132                                 break;
 133                         }
 134                 }
 135         }
 136
 137         return ret;
 138 }
 139
 140 int powergate_module(int id)
 141 {
 142         if (!pg_ops) {
 143                 pr_info("This SOC doesn't support powergating\n");
 144                 return -EINVAL;
 145         }
 146
 147         if (id < 0 || id >= pg_ops->num_powerdomains)
 148                 return -EINVAL;
 149
 150         tegra_powergate_mc_flush(id);
 151
 152         return tegra_powergate_set(id, false);
 153 }
 154
 155 int unpowergate_module(int id)
 156 {
 157         if (!pg_ops) {
 158                 pr_info("This SOC doesn't support powergating\n");
 159                 return -EINVAL;
 160         }
 161
 162         if (id < 0 || id >= pg_ops->num_powerdomains)
 163                 return -EINVAL;
 164
 165         return tegra_powergate_set(id, true);
 166 }
 167
 168 int partition_clk_enable(struct powergate_partition_info *pg_info)
 169 {
 170         int ret;
 171         u32 idx;
 172         struct clk *clk;
 173         struct partition_clk_info *clk_info;
 174
 175         for (idx = 0; idx < MAX_CLK_EN_NUM; idx++) {
 176                 clk_info = &pg_info->clk_info[idx];
 177                 clk = clk_info->clk_ptr;
 178                 if (!clk)
 179                         break;
 180
 181                 if (clk_info->clk_type != RST_ONLY) {
 182                         ret = tegra_clk_prepare_enable(clk);
 183                         if (ret)
 184                                 goto err_clk_en;
 185                 }
 186         }
 187
 188         return 0;
 189
 190 err_clk_en:
 191         WARN(1, "Could not enable clk %s, error %d", clk->name, ret);
 192         while (idx--) {
 193                 clk_info = &pg_info->clk_info[idx];
 194                 if (clk_info->clk_type != RST_ONLY)
 195                         tegra_clk_disable_unprepare(clk_info->clk_ptr);
 196         }
 197
 198         return ret;
 199 }
 200
 201 void partition_clk_disable(struct powergate_partition_info *pg_info)
 202 {
 203         u32 idx;
 204         struct clk *clk;
 205         struct partition_clk_info *clk_info;
 206
 207         for (idx = 0; idx < MAX_CLK_EN_NUM; idx++) {
 208                 clk_info = &pg_info->clk_info[idx];
 209                 clk = clk_info->clk_ptr;
 210
 211                 if (!clk)
 212                         break;
 213
 214                 if (clk_info->clk_type != RST_ONLY)
 215                         tegra_clk_disable_unprepare(clk);
 216         }
 217 }
 218
 219 void get_clk_info(struct powergate_partition_info *pg_info)
 220 {
 221         int idx;
 222
 223         for (idx = 0; idx < MAX_CLK_EN_NUM; idx++) {
 224                 if (!pg_info->clk_info[idx].clk_name)
 225                         break;
 226
 227                 pg_info->clk_info[idx].clk_ptr = tegra_get_clock_by_name(
 228                         pg_info->clk_info[idx].clk_name);
 229         }
 230 }
 231
 232 void powergate_partition_assert_reset(struct powergate_partition_info *pg_info)
 233 {
 234         u32 idx;
 235         struct clk *clk_ptr;
 236         struct partition_clk_info *clk_info;
 237
 238         for (idx = 0; idx < MAX_CLK_EN_NUM; idx++) {
 239                 clk_info = &pg_info->clk_info[idx];
 240                 clk_ptr = clk_info->clk_ptr;
 241
 242                 if (!clk_ptr)
 243                         break;
 244
 245                 if (clk_info->clk_type != CLK_ONLY)
 246                         tegra_periph_reset_assert(clk_ptr);
 247         }
 248 }
 249
 250 void powergate_partition_deassert_reset(struct powergate_partition_info *pg_info)
 251 {
 252         u32 idx;
 253         struct clk *clk_ptr;
 254         struct partition_clk_info *clk_info;
 255
 256         for (idx = 0; idx < MAX_CLK_EN_NUM; idx++) {
 257                 clk_info = &pg_info->clk_info[idx];
 258                 clk_ptr = clk_info->clk_ptr;
 259
 260                 if (!clk_ptr)
 261                         break;
 262
 263                 if (clk_info->clk_type != CLK_ONLY)
 264                         tegra_periph_reset_deassert(clk_ptr);
 265         }
 266 }
 267
 268 int tegra_powergate_reset_module(struct powergate_partition_info *pg_info)
 269 {
 270         int ret;
 271
 272         powergate_partition_assert_reset(pg_info);
 273
 274         udelay(10);
 275
 276         ret = partition_clk_enable(pg_info);
 277         if (ret)
 278                 return ret;
 279
 280         udelay(10);
 281
 282         powergate_partition_deassert_reset(pg_info);
 283
 284         partition_clk_disable(pg_info);
 285
 286         return 0;
 287 }
 288
 289 bool tegra_powergate_check_clamping(int id)
 290 {
 291         if (!pg_ops || !pg_ops->powergate_check_clamping) {
 292                 pr_info("This SOC can't check clamping status\n");
 293                 return -EINVAL;
 294         }
 295
 296         if (id < 0 || id >= pg_ops->num_powerdomains)
 297                 return -EINVAL;
 298
 299         return pg_ops->powergate_check_clamping(id);
 300 }
 301
 302 int tegra_powergate_remove_clamping(int id)
 303 {
 304         u32 mask;
 305         int contention_timeout = 100;
 306
 307         if (!pg_ops) {
 308                 pr_info("This SOC doesn't support powergating\n");
 309                 return -EINVAL;
 310         }
 311
 312         if (id < 0 || id >= pg_ops->num_powerdomains)
 313                 return -EINVAL;
 314
 315         /*
 316          * PCIE and VDE clamping masks are swapped with respect to their
 317          * partition ids
 318          */
 319         if (id ==  TEGRA_POWERGATE_VDEC)
 320                 mask = (1 << TEGRA_POWERGATE_PCIE);
 321         else if (id == TEGRA_POWERGATE_PCIE)
 322                 mask = (1 << TEGRA_POWERGATE_VDEC);
 323         else
 324                 mask = (1 << id);
 325
 326         pmc_write(mask, REMOVE_CLAMPING);
 327         /* Wait until clamp is removed */
 328         do {
 329                 udelay(1);
 330                 contention_timeout--;
 331         } while ((contention_timeout > 0)
 332                         && (pmc_read(REMOVE_CLAMPING) & mask));
 333
 334         WARN(contention_timeout <= 0, "Couldn't remove clamping");
 335
 336         return 0;
 337 }
 338
 339 static inline bool tegra_powergate_check_skip_list(int id)
 340 {
 341         return pg_ops->powergate_skip ?
 342                 pg_ops->powergate_skip(id) : false;
 343 }
 344
 345 /* EXTERNALY VISIBLE APIS */
 346
 347 bool tegra_powergate_is_powered(int id)
 348 {
 349         u32 status;
 350
 351         if (!pg_ops) {
 352                 pr_info("This SOC doesn't support powergating\n");
 353                 return -EINVAL;
 354         }
 355
 356         if (id < 0 || id >= pg_ops->num_powerdomains)
 357                 return -EINVAL;
 358
 359         if (pg_ops->powergate_is_powered)
 360                 return pg_ops->powergate_is_powered(id);
 361         else
 362                 status = pmc_read(PWRGATE_STATUS) & (1 << id);
 363
 364         status = pmc_read(PWRGATE_STATUS) & (1 << id);
 365
 366         return !!status;
 367 }
 368 EXPORT_SYMBOL(tegra_powergate_is_powered);
 369
 370 int tegra_cpu_powergate_id(int cpuid)
 371 {
 372         if (!pg_ops) {
 373                 pr_info("This SOC doesn't support powergating\n");
 374                 return -EINVAL;
 375         }
 376
 377         if (cpuid < 0 || cpuid >= pg_ops->num_cpu_domains) {
 378                 pr_info("%s: invalid powergate id\n", __func__);
 379                 return -EINVAL;
 380         }
 381
 382         if (pg_ops->cpu_domains)
 383                 return pg_ops->cpu_domains[cpuid];
 384         else
 385                 WARN_ON_ONCE("This SOC does not support CPU powergate\n");
 386
 387         return -EINVAL;
 388 }
 389 EXPORT_SYMBOL(tegra_cpu_powergate_id);
 390
 391 int tegra_powergate_partition(int id)
 392 {
 393         if (!pg_ops) {
 394                 pr_info("This SOC doesn't support powergating\n");
 395                 return -EINVAL;
 396         }
 397
 398         if (id < 0 || id >= pg_ops->num_powerdomains) {
 399                 pr_info("%s: invalid powergate id\n", __func__);
 400                 return -EINVAL;
 401         }
 402
 403         if (tegra_powergate_check_skip_list(id))
 404                 printk_once("%s: %s is in powergate skip list\n", __func__,
 405                         tegra_powergate_get_name(id));
 406
 407         if (pg_ops->powergate_partition)
 408                 return pg_ops->powergate_partition(id);
 409         else
 410                 WARN_ON_ONCE("This SOC doesn't support powergating");
 411
 412         return -EINVAL;
 413 }
 414 EXPORT_SYMBOL(tegra_powergate_partition);
 415
 416 int tegra_unpowergate_partition(int id)
 417 {
 418         if (!pg_ops) {
 419                 pr_info("This SOC doesn't support powergating\n");
 420                 return -EINVAL;
 421         }
 422
 423         if (id < 0 || id >= pg_ops->num_powerdomains) {
 424                 pr_info("%s: invalid powergate id\n", __func__);
 425                 return -EINVAL;
 426         }
 427
 428         if (tegra_powergate_check_skip_list(id))
 429                 printk_once("%s: %s is in powergate skip list\n", __func__,
 430                         tegra_powergate_get_name(id));
 431
 432         if (pg_ops->unpowergate_partition)
 433                 return pg_ops->unpowergate_partition(id);
 434         else
 435                 WARN_ON_ONCE("This SOC doesn't support un-powergating");
 436
 437         return -EINVAL;
 438 }
 439 EXPORT_SYMBOL(tegra_unpowergate_partition);
 440
 441 int tegra_powergate_partition_with_clk_off(int id)
 442 {
 443         if (!pg_ops) {
 444                 pr_info("This SOC doesn't support powergating\n");
 445                 return -EINVAL;
 446         }
 447
 448         if (id < 0 || id >= pg_ops->num_powerdomains) {
 449                 pr_info("%s: invalid powergate id\n", __func__);
 450                 return -EINVAL;
 451         }
 452
 453         if (tegra_powergate_check_skip_list(id))
 454                 printk_once("%s: %s is in powergate skip list\n", __func__,
 455                         tegra_powergate_get_name(id));
 456
 457         if (pg_ops->powergate_partition_with_clk_off)
 458                 return pg_ops->powergate_partition_with_clk_off(id);
 459         else
 460                 WARN_ON_ONCE("This SOC doesn't support powergating with clk off");
 461
 462         return -EINVAL;
 463 }
 464 EXPORT_SYMBOL(tegra_powergate_partition_with_clk_off);
 465
 466 int tegra_unpowergate_partition_with_clk_on(int id)
 467 {
 468         if (!pg_ops) {
 469                 pr_info("This SOC doesn't support powergating\n");
 470                 return -EINVAL;
 471         }
 472
 473         if (id < 0 || id >= pg_ops->num_powerdomains) {
 474                 pr_info("%s: invalid powergate id\n", __func__);
 475                 return -EINVAL;
 476         }
 477
 478         if (tegra_powergate_check_skip_list(id))
 479                 printk_once("%s: %s is in powergate skip list\n", __func__,
 480                         tegra_powergate_get_name(id));
 481
 482         if (pg_ops->unpowergate_partition_with_clk_on)
 483                 return pg_ops->unpowergate_partition_with_clk_on(id);
 484         else
 485                 WARN_ON_ONCE("This SOC doesn't support power un-gating with clk on");
 486
 487         return -EINVAL;
 488 }
 489 EXPORT_SYMBOL(tegra_unpowergate_partition_with_clk_on);
 490
 491 int tegra_powergate_mc_enable(int id)
 492 {
 493         if (!pg_ops) {
 494                 pr_info("This SOC doesn't support powergating\n");
 495                 return -EINVAL;
 496         }
 497
 498         if (id < 0 || id >= pg_ops->num_powerdomains) {
 499                 pr_info("%s: invalid powergate id\n", __func__);
 500                 return -EINVAL;
 501         }
 502
 503         if (pg_ops->powergate_mc_enable)
 504                 return pg_ops->powergate_mc_enable(id);
 505         else
 506                 WARN_ON_ONCE("This SOC does not support powergate mc enable");
 507
 508         return -EINVAL;
 509 }
 510 EXPORT_SYMBOL(tegra_powergate_mc_enable);
 511
 512 int tegra_powergate_mc_disable(int id)
 513 {
 514         if (!pg_ops) {
 515                 pr_info("This SOC doesn't support powergating\n");
 516                 return -EINVAL;
 517         }
 518
 519         if (id < 0 || id >= pg_ops->num_powerdomains) {
 520                 pr_info("%s: invalid powergate id\n", __func__);
 521                 return -EINVAL;
 522         }
 523
 524         if (pg_ops->powergate_mc_disable)
 525                 return pg_ops->powergate_mc_disable(id);
 526         else
 527                 WARN_ON_ONCE("This SOC does not support powergate mc disable");
 528
 529         return -EINVAL;
 530 }
 531 EXPORT_SYMBOL(tegra_powergate_mc_disable);
 532
 533 int tegra_powergate_mc_flush(int id)
 534 {
 535         if (!pg_ops) {
 536                 pr_info("This SOC doesn't support powergating\n");
 537                 return -EINVAL;
 538         }
 539
 540         if (id < 0 || id >= pg_ops->num_powerdomains) {
 541                 pr_info("%s: invalid powergate id\n", __func__);
 542                 return -EINVAL;
 543         }
 544
 545         if (pg_ops->powergate_mc_flush)
 546                 return pg_ops->powergate_mc_flush(id);
 547         else
 548                 WARN_ON_ONCE("This SOC does not support powergate mc flush");
 549
 550         return -EINVAL;
 551 }
 552 EXPORT_SYMBOL(tegra_powergate_mc_flush);
 553
 554 int tegra_powergate_mc_flush_done(int id)
 555 {
 556         if (!pg_ops) {
 557                 pr_info("This SOC doesn't support powergating\n");
 558                 return -EINVAL;
 559         }
 560
 561         if (id < 0 || id >= pg_ops->num_powerdomains) {
 562                 pr_info("%s: invalid powergate id\n", __func__);
 563                 return -EINVAL;
 564         }
 565
 566         if (pg_ops->powergate_mc_flush_done)
 567                 return pg_ops->powergate_mc_flush_done(id);
 568         else
 569                 WARN_ON_ONCE("This SOC does not support powergate mc flush done");
 570
 571         return -EINVAL;
 572 }
 573 EXPORT_SYMBOL(tegra_powergate_mc_flush_done);
 574
 575 const char *tegra_powergate_get_name(int id)
 576 {
 577         if (!pg_ops) {
 578                 pr_info("This SOC doesn't support powergating\n");
 579                 return NULL;
 580         }
 581
 582         if (id < 0 || id >= pg_ops->num_powerdomains) {
 583                 pr_info("invalid powergate id\n");
 584                 return "invalid";
 585         }
 586
 587         if (pg_ops->get_powergate_domain_name)
 588                 return pg_ops->get_powergate_domain_name(id);
 589         else
 590                 WARN_ON_ONCE("This SOC does not support CPU powergate");
 591
 592         return "invalid";
 593 }
 594 EXPORT_SYMBOL(tegra_powergate_get_name);
 595
 596 int tegra_powergate_init_refcount(void)
 597 {
 598         if ((!pg_ops) || (!pg_ops->powergate_init_refcount))
 599                 return 0;
 600
 601         return pg_ops->powergate_init_refcount();
 602 }
 603
 604 int __init tegra_powergate_init(void)
 605 {
 606         switch (tegra_chip_id) {
 607                 case TEGRA_CHIPID_TEGRA2:
 608                         pg_ops = tegra2_powergate_init_chip_support();
 609                         break;
 610
 611                 case TEGRA_CHIPID_TEGRA3:
 612                         pg_ops = tegra3_powergate_init_chip_support();
 613                         break;
 614
 615                 case TEGRA_CHIPID_TEGRA11:
 616                         pg_ops = tegra11x_powergate_init_chip_support();
 617                         break;
 618
 619                 case TEGRA_CHIPID_TEGRA14:
 620                         pg_ops = tegra14x_powergate_init_chip_support();
 621                         break;
 622
 623                 case TEGRA_CHIPID_TEGRA12:
 624                         pg_ops = tegra12x_powergate_init_chip_support();
 625                         break;
 626
 627                 default:
 628                         pg_ops = NULL;
 629                         pr_info("%s: Unknown Tegra variant. Disabling powergate\n", __func__);
 630                         break;
 631         }
 632
 633         tegra_powergate_init_refcount();
 634
 635         pr_info("%s: DONE\n", __func__);
 636
 637         return (pg_ops ? 0 : -EINVAL);
 638 }
 639
 640 #ifdef CONFIG_DEBUG_FS
 641
 642 static int powergate_show(struct seq_file *s, void *data)
 643 {
 644         int i;
 645         const char *name;
 646         bool is_pg_skip;
 647
 648         if (!pg_ops) {
 649                 seq_printf(s, "This SOC doesn't support powergating\n");
 650                 return -EINVAL;
 651         }
 652
 653         seq_printf(s, " powergate powered\n");
 654         seq_printf(s, "------------------\n");
 655
 656         for (i = 0; i < pg_ops->num_powerdomains; i++) {
 657                 name = tegra_powergate_get_name(i);
 658                 if (name) {
 659                         is_pg_skip = tegra_powergate_check_skip_list(i);
 660                         seq_printf(s, " %9s %7s\n", name,
 661                                 (is_pg_skip ? "skip" : \
 662                                 (tegra_powergate_is_powered(i) ? \
 663                                 "yes" : "no")));
 664                 }
 665         }
 666
 667         return 0;
 668 }
 669
 670 static int powergate_open(struct inode *inode, struct file *file)
 671 {
 672         return single_open(file, powergate_show, inode->i_private);
 673 }
 674
 675 static const struct file_operations powergate_fops = {
 676         .open           = powergate_open,
 677         .read           = seq_read,
 678         .llseek         = seq_lseek,
 679         .release        = single_release,
 680 };
 681
 682 int __init tegra_powergate_debugfs_init(void)
 683 {
 684         struct dentry *d;
 685
 686         d = debugfs_create_file("powergate", S_IRUGO, NULL, NULL,
 687                 &powergate_fops);
 688         if (!d)
 689                 return -ENOMEM;
 690
 691         return 0;
 692 }
 693
 694 #endif