ARM: tegra: add clamping status read.
[linux-3.10.git] / arch / arm / mach-tegra / powergate.c
1 /*
2  * arch/arm/mach-tegra/powergate.c
3  *
4  * Copyright (c) 2010 Google, Inc
5  * Copyright (c) 2011 - 2013, NVIDIA CORPORATION.  All rights reserved.
6  *
7  * Author:
8  *      Colin Cross <ccross@google.com>
9  *
10  * This software is licensed under the terms of the GNU General Public
11  * License version 2, as published by the Free Software Foundation, and
12  * may be copied, distributed, and modified under those terms.
13  *
14  * This program is distributed in the hope that it will be useful,
15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
17  * GNU General Public License for more details.
18  *
19  */
20
21 #include <linux/kernel.h>
22 #include <linux/module.h>
23 #include <linux/clk.h>
24 #include <linux/string.h>
25 #include <linux/debugfs.h>
26 #include <linux/delay.h>
27 #include <linux/err.h>
28 #include <linux/init.h>
29 #include <linux/io.h>
30 #include <linux/seq_file.h>
31 #include <linux/spinlock.h>
32 #include <linux/clk/tegra.h>
33 #include <trace/events/power.h>
34 #include <asm/atomic.h>
35
36 #include <mach/powergate.h>
37 #include <mach/hardware.h>
38
39 #include "clock.h"
40 #include "fuse.h"
41 #include "iomap.h"
42 #include "powergate-priv.h"
43
44 static struct powergate_ops *pg_ops;
45
46 #ifndef CONFIG_TEGRA_SIMULATION_PLATFORM
47 static spinlock_t *tegra_get_powergate_lock(void)
48 {
49         if (pg_ops && pg_ops->get_powergate_lock)
50                 return pg_ops->get_powergate_lock();
51         else
52                 WARN_ON_ONCE("This SOC does not export powergate lock");
53
54         return NULL;
55 }
56 #endif
57
58 int tegra_powergate_set(int id, bool new_state)
59 {
60 #ifndef CONFIG_TEGRA_SIMULATION_PLATFORM
61         bool status;
62         unsigned long flags;
63         spinlock_t *lock = tegra_get_powergate_lock();
64
65         /* 10us timeout for toggle operation if it takes affect*/
66         int toggle_timeout = 10;
67
68         /* 100 * 10 = 1000us timeout for toggle command to take affect in case
69            of contention with h/w initiated CPU power gating */
70         int contention_timeout = 100;
71
72         spin_lock_irqsave(lock, flags);
73
74         status = !!(pmc_read(PWRGATE_STATUS) & (1 << id));
75
76         if (status == new_state) {
77                 spin_unlock_irqrestore(lock, flags);
78                 return 0;
79         }
80
81         if (TEGRA_IS_CPU_POWERGATE_ID(id)) {
82                 /* CPU ungated in s/w only during boot/resume with outer
83                    waiting loop and no contention from other CPUs */
84                 pmc_write(PWRGATE_TOGGLE_START | id, PWRGATE_TOGGLE);
85                 spin_unlock_irqrestore(lock, flags);
86                 return 0;
87         }
88
89         pmc_write(PWRGATE_TOGGLE_START | id, PWRGATE_TOGGLE);
90         do {
91                 do {
92                         udelay(1);
93                         status = !!(pmc_read(PWRGATE_STATUS) & (1 << id));
94
95                         toggle_timeout--;
96                 } while ((status != new_state) && (toggle_timeout > 0));
97
98                 contention_timeout--;
99         } while ((status != new_state) && (contention_timeout > 0));
100
101         spin_unlock_irqrestore(lock, flags);
102
103         if (status != new_state) {
104                 WARN(1, "Could not set powergate %d to %d", id, new_state);
105                 return -EBUSY;
106         }
107
108         trace_power_domain_target(tegra_powergate_get_name(id), new_state,
109                         raw_smp_processor_id());
110 #endif
111
112         return 0;
113 }
114
115 int is_partition_clk_disabled(struct powergate_partition_info *pg_info)
116 {
117         u32 idx;
118         struct clk *clk;
119         struct partition_clk_info *clk_info;
120         int ret = 0;
121
122         for (idx = 0; idx < MAX_CLK_EN_NUM; idx++) {
123                 clk_info = &pg_info->clk_info[idx];
124                 clk = clk_info->clk_ptr;
125
126                 if (!clk)
127                         break;
128
129                 if (clk_info->clk_type != RST_ONLY) {
130                         if (tegra_is_clk_enabled(clk)) {
131                                 ret = -1;
132                                 break;
133                         }
134                 }
135         }
136
137         return ret;
138 }
139
140 int powergate_module(int id)
141 {
142         if (!pg_ops) {
143                 pr_info("This SOC doesn't support powergating\n");
144                 return -EINVAL;
145         }
146
147         if (id < 0 || id >= pg_ops->num_powerdomains)
148                 return -EINVAL;
149
150         tegra_powergate_mc_flush(id);
151
152         return tegra_powergate_set(id, false);
153 }
154
155 int unpowergate_module(int id)
156 {
157         if (!pg_ops) {
158                 pr_info("This SOC doesn't support powergating\n");
159                 return -EINVAL;
160         }
161
162         if (id < 0 || id >= pg_ops->num_powerdomains)
163                 return -EINVAL;
164
165         return tegra_powergate_set(id, true);
166 }
167
168 int partition_clk_enable(struct powergate_partition_info *pg_info)
169 {
170         int ret;
171         u32 idx;
172         struct clk *clk;
173         struct partition_clk_info *clk_info;
174
175         for (idx = 0; idx < MAX_CLK_EN_NUM; idx++) {
176                 clk_info = &pg_info->clk_info[idx];
177                 clk = clk_info->clk_ptr;
178                 if (!clk)
179                         break;
180
181                 if (clk_info->clk_type != RST_ONLY) {
182                         ret = tegra_clk_prepare_enable(clk);
183                         if (ret)
184                                 goto err_clk_en;
185                 }
186         }
187
188         return 0;
189
190 err_clk_en:
191         WARN(1, "Could not enable clk %s, error %d", clk->name, ret);
192         while (idx--) {
193                 clk_info = &pg_info->clk_info[idx];
194                 if (clk_info->clk_type != RST_ONLY)
195                         tegra_clk_disable_unprepare(clk_info->clk_ptr);
196         }
197
198         return ret;
199 }
200
201 void partition_clk_disable(struct powergate_partition_info *pg_info)
202 {
203         u32 idx;
204         struct clk *clk;
205         struct partition_clk_info *clk_info;
206
207         for (idx = 0; idx < MAX_CLK_EN_NUM; idx++) {
208                 clk_info = &pg_info->clk_info[idx];
209                 clk = clk_info->clk_ptr;
210
211                 if (!clk)
212                         break;
213
214                 if (clk_info->clk_type != RST_ONLY)
215                         tegra_clk_disable_unprepare(clk);
216         }
217 }
218
219 void get_clk_info(struct powergate_partition_info *pg_info)
220 {
221         int idx;
222
223         for (idx = 0; idx < MAX_CLK_EN_NUM; idx++) {
224                 if (!pg_info->clk_info[idx].clk_name)
225                         break;
226
227                 pg_info->clk_info[idx].clk_ptr = tegra_get_clock_by_name(
228                         pg_info->clk_info[idx].clk_name);
229         }
230 }
231
232 void powergate_partition_assert_reset(struct powergate_partition_info *pg_info)
233 {
234         u32 idx;
235         struct clk *clk_ptr;
236         struct partition_clk_info *clk_info;
237
238         for (idx = 0; idx < MAX_CLK_EN_NUM; idx++) {
239                 clk_info = &pg_info->clk_info[idx];
240                 clk_ptr = clk_info->clk_ptr;
241
242                 if (!clk_ptr)
243                         break;
244
245                 if (clk_info->clk_type != CLK_ONLY)
246                         tegra_periph_reset_assert(clk_ptr);
247         }
248 }
249
250 void powergate_partition_deassert_reset(struct powergate_partition_info *pg_info)
251 {
252         u32 idx;
253         struct clk *clk_ptr;
254         struct partition_clk_info *clk_info;
255
256         for (idx = 0; idx < MAX_CLK_EN_NUM; idx++) {
257                 clk_info = &pg_info->clk_info[idx];
258                 clk_ptr = clk_info->clk_ptr;
259
260                 if (!clk_ptr)
261                         break;
262
263                 if (clk_info->clk_type != CLK_ONLY)
264                         tegra_periph_reset_deassert(clk_ptr);
265         }
266 }
267
268 int tegra_powergate_reset_module(struct powergate_partition_info *pg_info)
269 {
270         int ret;
271
272         powergate_partition_assert_reset(pg_info);
273
274         udelay(10);
275
276         ret = partition_clk_enable(pg_info);
277         if (ret)
278                 return ret;
279
280         udelay(10);
281
282         powergate_partition_deassert_reset(pg_info);
283
284         partition_clk_disable(pg_info);
285
286         return 0;
287 }
288
289 bool tegra_powergate_check_clamping(int id)
290 {
291         if (!pg_ops || !pg_ops->powergate_check_clamping) {
292                 pr_info("This SOC can't check clamping status\n");
293                 return -EINVAL;
294         }
295
296         if (id < 0 || id >= pg_ops->num_powerdomains)
297                 return -EINVAL;
298
299         return pg_ops->powergate_check_clamping(id);
300 }
301
302 int tegra_powergate_remove_clamping(int id)
303 {
304         u32 mask;
305         int contention_timeout = 100;
306
307         if (!pg_ops) {
308                 pr_info("This SOC doesn't support powergating\n");
309                 return -EINVAL;
310         }
311
312         if (id < 0 || id >= pg_ops->num_powerdomains)
313                 return -EINVAL;
314
315         /*
316          * PCIE and VDE clamping masks are swapped with respect to their
317          * partition ids
318          */
319         if (id ==  TEGRA_POWERGATE_VDEC)
320                 mask = (1 << TEGRA_POWERGATE_PCIE);
321         else if (id == TEGRA_POWERGATE_PCIE)
322                 mask = (1 << TEGRA_POWERGATE_VDEC);
323         else
324                 mask = (1 << id);
325
326         pmc_write(mask, REMOVE_CLAMPING);
327         /* Wait until clamp is removed */
328         do {
329                 udelay(1);
330                 contention_timeout--;
331         } while ((contention_timeout > 0)
332                         && (pmc_read(REMOVE_CLAMPING) & mask));
333
334         WARN(contention_timeout <= 0, "Couldn't remove clamping");
335
336         return 0;
337 }
338
339 /* EXTERNALY VISIBLE APIS */
340
341 bool tegra_powergate_is_powered(int id)
342 {
343         u32 status;
344
345         if (!pg_ops) {
346                 pr_info("This SOC doesn't support powergating\n");
347                 return -EINVAL;
348         }
349
350         if (id < 0 || id >= pg_ops->num_powerdomains)
351                 return -EINVAL;
352
353         status = pmc_read(PWRGATE_STATUS) & (1 << id);
354
355         return !!status;
356 }
357 EXPORT_SYMBOL(tegra_powergate_is_powered);
358
359 int tegra_cpu_powergate_id(int cpuid)
360 {
361         if (!pg_ops) {
362                 pr_info("This SOC doesn't support powergating\n");
363                 return -EINVAL;
364         }
365
366         if (cpuid < 0 || cpuid >= pg_ops->num_cpu_domains) {
367                 pr_info("%s: invalid powergate id\n", __func__);
368                 return -EINVAL;
369         }
370
371         if (pg_ops->cpu_domains)
372                 return pg_ops->cpu_domains[cpuid];
373         else
374                 WARN_ON_ONCE("This SOC does not support CPU powergate\n");
375
376         return -EINVAL;
377 }
378 EXPORT_SYMBOL(tegra_cpu_powergate_id);
379
380 int tegra_powergate_partition(int id)
381 {
382         if (!pg_ops) {
383                 pr_info("This SOC doesn't support powergating\n");
384                 return -EINVAL;
385         }
386
387         if (id < 0 || id >= pg_ops->num_powerdomains) {
388                 pr_info("%s: invalid powergate id\n", __func__);
389                 return -EINVAL;
390         }
391
392         if (pg_ops->powergate_partition)
393                 return pg_ops->powergate_partition(id);
394         else
395                 WARN_ON_ONCE("This SOC doesn't support powergating");
396
397         return -EINVAL;
398 }
399 EXPORT_SYMBOL(tegra_powergate_partition);
400
401 int tegra_unpowergate_partition(int id)
402 {
403         if (!pg_ops) {
404                 pr_info("This SOC doesn't support powergating\n");
405                 return -EINVAL;
406         }
407
408         if (id < 0 || id >= pg_ops->num_powerdomains) {
409                 pr_info("%s: invalid powergate id\n", __func__);
410                 return -EINVAL;
411         }
412
413         if (pg_ops->unpowergate_partition)
414                 return pg_ops->unpowergate_partition(id);
415         else
416                 WARN_ON_ONCE("This SOC doesn't support un-powergating");
417
418         return -EINVAL;
419 }
420 EXPORT_SYMBOL(tegra_unpowergate_partition);
421
422 int tegra_powergate_partition_with_clk_off(int id)
423 {
424         if (!pg_ops) {
425                 pr_info("This SOC doesn't support powergating\n");
426                 return -EINVAL;
427         }
428
429         if (id < 0 || id >= pg_ops->num_powerdomains) {
430                 pr_info("%s: invalid powergate id\n", __func__);
431                 return -EINVAL;
432         }
433
434         if (pg_ops->powergate_partition_with_clk_off)
435                 return pg_ops->powergate_partition_with_clk_off(id);
436         else
437                 WARN_ON_ONCE("This SOC doesn't support powergating with clk off");
438
439         return -EINVAL;
440 }
441 EXPORT_SYMBOL(tegra_powergate_partition_with_clk_off);
442
443 int tegra_unpowergate_partition_with_clk_on(int id)
444 {
445         if (!pg_ops) {
446                 pr_info("This SOC doesn't support powergating\n");
447                 return -EINVAL;
448         }
449
450         if (id < 0 || id >= pg_ops->num_powerdomains) {
451                 pr_info("%s: invalid powergate id\n", __func__);
452                 return -EINVAL;
453         }
454
455         if (pg_ops->unpowergate_partition_with_clk_on)
456                 return pg_ops->unpowergate_partition_with_clk_on(id);
457         else
458                 WARN_ON_ONCE("This SOC doesn't support power un-gating with clk on");
459
460         return -EINVAL;
461 }
462 EXPORT_SYMBOL(tegra_unpowergate_partition_with_clk_on);
463
464 int tegra_powergate_mc_enable(int id)
465 {
466         if (!pg_ops) {
467                 pr_info("This SOC doesn't support powergating\n");
468                 return -EINVAL;
469         }
470
471         if (id < 0 || id >= pg_ops->num_powerdomains) {
472                 pr_info("%s: invalid powergate id\n", __func__);
473                 return -EINVAL;
474         }
475
476         if (pg_ops->powergate_mc_enable)
477                 return pg_ops->powergate_mc_enable(id);
478         else
479                 WARN_ON_ONCE("This SOC does not support powergate mc enable");
480
481         return -EINVAL;
482 }
483 EXPORT_SYMBOL(tegra_powergate_mc_enable);
484
485 int tegra_powergate_mc_disable(int id)
486 {
487         if (!pg_ops) {
488                 pr_info("This SOC doesn't support powergating\n");
489                 return -EINVAL;
490         }
491
492         if (id < 0 || id >= pg_ops->num_powerdomains) {
493                 pr_info("%s: invalid powergate id\n", __func__);
494                 return -EINVAL;
495         }
496
497         if (pg_ops->powergate_mc_disable)
498                 return pg_ops->powergate_mc_disable(id);
499         else
500                 WARN_ON_ONCE("This SOC does not support powergate mc disable");
501
502         return -EINVAL;
503 }
504 EXPORT_SYMBOL(tegra_powergate_mc_disable);
505
506 int tegra_powergate_mc_flush(int id)
507 {
508         if (!pg_ops) {
509                 pr_info("This SOC doesn't support powergating\n");
510                 return -EINVAL;
511         }
512
513         if (id < 0 || id >= pg_ops->num_powerdomains) {
514                 pr_info("%s: invalid powergate id\n", __func__);
515                 return -EINVAL;
516         }
517
518         if (pg_ops->powergate_mc_flush)
519                 return pg_ops->powergate_mc_flush(id);
520         else
521                 WARN_ON_ONCE("This SOC does not support powergate mc flush");
522
523         return -EINVAL;
524 }
525 EXPORT_SYMBOL(tegra_powergate_mc_flush);
526
527 int tegra_powergate_mc_flush_done(int id)
528 {
529         if (!pg_ops) {
530                 pr_info("This SOC doesn't support powergating\n");
531                 return -EINVAL;
532         }
533
534         if (id < 0 || id >= pg_ops->num_powerdomains) {
535                 pr_info("%s: invalid powergate id\n", __func__);
536                 return -EINVAL;
537         }
538
539         if (pg_ops->powergate_mc_flush_done)
540                 return pg_ops->powergate_mc_flush_done(id);
541         else
542                 WARN_ON_ONCE("This SOC does not support powergate mc flush done");
543
544         return -EINVAL;
545 }
546 EXPORT_SYMBOL(tegra_powergate_mc_flush_done);
547
548 const char *tegra_powergate_get_name(int id)
549 {
550         if (!pg_ops) {
551                 pr_info("This SOC doesn't support powergating\n");
552                 return NULL;
553         }
554
555         if (id < 0 || id >= pg_ops->num_powerdomains) {
556                 pr_info("invalid powergate id\n");
557                 return "invalid";
558         }
559
560         if (pg_ops->get_powergate_domain_name)
561                 return pg_ops->get_powergate_domain_name(id);
562         else
563                 WARN_ON_ONCE("This SOC does not support CPU powergate");
564
565         return "invalid";
566 }
567 EXPORT_SYMBOL(tegra_powergate_get_name);
568
569 int tegra_powergate_init_refcount(void)
570 {
571         if (!pg_ops->powergate_init_refcount)
572                 return 0;
573
574         return pg_ops->powergate_init_refcount();
575 }
576
577 int __init tegra_powergate_init(void)
578 {
579         switch (tegra_chip_id) {
580                 case TEGRA_CHIPID_TEGRA2:
581                         pg_ops = tegra2_powergate_init_chip_support();
582                         break;
583
584                 case TEGRA_CHIPID_TEGRA3:
585                         pg_ops = tegra3_powergate_init_chip_support();
586                         break;
587
588                 case TEGRA_CHIPID_TEGRA11:
589                         pg_ops = tegra11x_powergate_init_chip_support();
590                         break;
591
592                 case TEGRA_CHIPID_TEGRA14:
593                         pg_ops = tegra14x_powergate_init_chip_support();
594                         break;
595
596                 default:
597                         pg_ops = NULL;
598                         pr_info("%s: Unknown Tegra variant. Disabling powergate\n", __func__);
599                         break;
600         }
601
602         tegra_powergate_init_refcount();
603
604         pr_info("%s: DONE\n", __func__);
605
606         return (pg_ops ? 0 : -EINVAL);
607 }
608
609 #ifdef CONFIG_DEBUG_FS
610
611 static int powergate_show(struct seq_file *s, void *data)
612 {
613         int i;
614         const char *name;
615
616         if (!pg_ops) {
617                 seq_printf(s, "This SOC doesn't support powergating\n");
618                 return -EINVAL;
619         }
620
621         seq_printf(s, " powergate powered\n");
622         seq_printf(s, "------------------\n");
623
624         for (i = 0; i < pg_ops->num_powerdomains; i++) {
625                 name = tegra_powergate_get_name(i);
626                 if (name)
627                         seq_printf(s, " %9s %7s\n", name,
628                                 tegra_powergate_is_powered(i) ? "yes" : "no");
629         }
630
631         return 0;
632 }
633
634 static int powergate_open(struct inode *inode, struct file *file)
635 {
636         return single_open(file, powergate_show, inode->i_private);
637 }
638
639 static const struct file_operations powergate_fops = {
640         .open           = powergate_open,
641         .read           = seq_read,
642         .llseek         = seq_lseek,
643         .release        = single_release,
644 };
645
646 int __init tegra_powergate_debugfs_init(void)
647 {
648         struct dentry *d;
649
650         d = debugfs_create_file("powergate", S_IRUGO, NULL, NULL,
651                 &powergate_fops);
652         if (!d)
653                 return -ENOMEM;
654
655         return 0;
656 }
657
658 #endif