ARM: tegra: add support for powergate skip list
[linux-3.10.git] / arch / arm / mach-tegra / powergate.c
1 /*
2  * arch/arm/mach-tegra/powergate.c
3  *
4  * Copyright (c) 2010 Google, Inc
5  * Copyright (c) 2011 - 2013, NVIDIA CORPORATION.  All rights reserved.
6  *
7  * Author:
8  *      Colin Cross <ccross@google.com>
9  *
10  * This software is licensed under the terms of the GNU General Public
11  * License version 2, as published by the Free Software Foundation, and
12  * may be copied, distributed, and modified under those terms.
13  *
14  * This program is distributed in the hope that it will be useful,
15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
17  * GNU General Public License for more details.
18  *
19  */
20
21 #include <linux/kernel.h>
22 #include <linux/module.h>
23 #include <linux/clk.h>
24 #include <linux/string.h>
25 #include <linux/debugfs.h>
26 #include <linux/delay.h>
27 #include <linux/err.h>
28 #include <linux/init.h>
29 #include <linux/io.h>
30 #include <linux/seq_file.h>
31 #include <linux/spinlock.h>
32 #include <linux/clk/tegra.h>
33 #include <trace/events/power.h>
34 #include <asm/atomic.h>
35
36 #include <mach/powergate.h>
37 #include <mach/hardware.h>
38
39 #include "clock.h"
40 #include "fuse.h"
41 #include "iomap.h"
42 #include "powergate-priv.h"
43
44 static struct powergate_ops *pg_ops;
45
46 #ifndef CONFIG_TEGRA_SIMULATION_PLATFORM
47 static spinlock_t *tegra_get_powergate_lock(void)
48 {
49         if (pg_ops && pg_ops->get_powergate_lock)
50                 return pg_ops->get_powergate_lock();
51         else
52                 WARN_ON_ONCE("This SOC does not export powergate lock");
53
54         return NULL;
55 }
56 #endif
57
58 int tegra_powergate_set(int id, bool new_state)
59 {
60 #ifndef CONFIG_TEGRA_SIMULATION_PLATFORM
61         bool status;
62         unsigned long flags;
63         spinlock_t *lock = tegra_get_powergate_lock();
64
65         /* 10us timeout for toggle operation if it takes affect*/
66         int toggle_timeout = 10;
67
68         /* 100 * 10 = 1000us timeout for toggle command to take affect in case
69            of contention with h/w initiated CPU power gating */
70         int contention_timeout = 100;
71
72         spin_lock_irqsave(lock, flags);
73
74         status = !!(pmc_read(PWRGATE_STATUS) & (1 << id));
75
76         if (status == new_state) {
77                 spin_unlock_irqrestore(lock, flags);
78                 return 0;
79         }
80
81         if (TEGRA_IS_CPU_POWERGATE_ID(id)) {
82                 /* CPU ungated in s/w only during boot/resume with outer
83                    waiting loop and no contention from other CPUs */
84                 pmc_write(PWRGATE_TOGGLE_START | id, PWRGATE_TOGGLE);
85                 spin_unlock_irqrestore(lock, flags);
86                 return 0;
87         }
88
89         pmc_write(PWRGATE_TOGGLE_START | id, PWRGATE_TOGGLE);
90         do {
91                 do {
92                         udelay(1);
93                         status = !!(pmc_read(PWRGATE_STATUS) & (1 << id));
94
95                         toggle_timeout--;
96                 } while ((status != new_state) && (toggle_timeout > 0));
97
98                 contention_timeout--;
99         } while ((status != new_state) && (contention_timeout > 0));
100
101         spin_unlock_irqrestore(lock, flags);
102
103         if (status != new_state) {
104                 WARN(1, "Could not set powergate %d to %d", id, new_state);
105                 return -EBUSY;
106         }
107
108         trace_power_domain_target(tegra_powergate_get_name(id), new_state,
109                         raw_smp_processor_id());
110 #endif
111
112         return 0;
113 }
114
115 int is_partition_clk_disabled(struct powergate_partition_info *pg_info)
116 {
117         u32 idx;
118         struct clk *clk;
119         struct partition_clk_info *clk_info;
120         int ret = 0;
121
122         for (idx = 0; idx < MAX_CLK_EN_NUM; idx++) {
123                 clk_info = &pg_info->clk_info[idx];
124                 clk = clk_info->clk_ptr;
125
126                 if (!clk)
127                         break;
128
129                 if (clk_info->clk_type != RST_ONLY) {
130                         if (tegra_is_clk_enabled(clk)) {
131                                 ret = -1;
132                                 break;
133                         }
134                 }
135         }
136
137         return ret;
138 }
139
140 int powergate_module(int id)
141 {
142         if (!pg_ops) {
143                 pr_info("This SOC doesn't support powergating\n");
144                 return -EINVAL;
145         }
146
147         if (id < 0 || id >= pg_ops->num_powerdomains)
148                 return -EINVAL;
149
150         tegra_powergate_mc_flush(id);
151
152         return tegra_powergate_set(id, false);
153 }
154
155 int unpowergate_module(int id)
156 {
157         if (!pg_ops) {
158                 pr_info("This SOC doesn't support powergating\n");
159                 return -EINVAL;
160         }
161
162         if (id < 0 || id >= pg_ops->num_powerdomains)
163                 return -EINVAL;
164
165         return tegra_powergate_set(id, true);
166 }
167
168 int partition_clk_enable(struct powergate_partition_info *pg_info)
169 {
170         int ret;
171         u32 idx;
172         struct clk *clk;
173         struct partition_clk_info *clk_info;
174
175         for (idx = 0; idx < MAX_CLK_EN_NUM; idx++) {
176                 clk_info = &pg_info->clk_info[idx];
177                 clk = clk_info->clk_ptr;
178                 if (!clk)
179                         break;
180
181                 if (clk_info->clk_type != RST_ONLY) {
182                         ret = tegra_clk_prepare_enable(clk);
183                         if (ret)
184                                 goto err_clk_en;
185                 }
186         }
187
188         return 0;
189
190 err_clk_en:
191         WARN(1, "Could not enable clk %s, error %d", clk->name, ret);
192         while (idx--) {
193                 clk_info = &pg_info->clk_info[idx];
194                 if (clk_info->clk_type != RST_ONLY)
195                         tegra_clk_disable_unprepare(clk_info->clk_ptr);
196         }
197
198         return ret;
199 }
200
201 void partition_clk_disable(struct powergate_partition_info *pg_info)
202 {
203         u32 idx;
204         struct clk *clk;
205         struct partition_clk_info *clk_info;
206
207         for (idx = 0; idx < MAX_CLK_EN_NUM; idx++) {
208                 clk_info = &pg_info->clk_info[idx];
209                 clk = clk_info->clk_ptr;
210
211                 if (!clk)
212                         break;
213
214                 if (clk_info->clk_type != RST_ONLY)
215                         tegra_clk_disable_unprepare(clk);
216         }
217 }
218
219 void get_clk_info(struct powergate_partition_info *pg_info)
220 {
221         int idx;
222
223         for (idx = 0; idx < MAX_CLK_EN_NUM; idx++) {
224                 if (!pg_info->clk_info[idx].clk_name)
225                         break;
226
227                 pg_info->clk_info[idx].clk_ptr = tegra_get_clock_by_name(
228                         pg_info->clk_info[idx].clk_name);
229         }
230 }
231
232 void powergate_partition_assert_reset(struct powergate_partition_info *pg_info)
233 {
234         u32 idx;
235         struct clk *clk_ptr;
236         struct partition_clk_info *clk_info;
237
238         for (idx = 0; idx < MAX_CLK_EN_NUM; idx++) {
239                 clk_info = &pg_info->clk_info[idx];
240                 clk_ptr = clk_info->clk_ptr;
241
242                 if (!clk_ptr)
243                         break;
244
245                 if (clk_info->clk_type != CLK_ONLY)
246                         tegra_periph_reset_assert(clk_ptr);
247         }
248 }
249
250 void powergate_partition_deassert_reset(struct powergate_partition_info *pg_info)
251 {
252         u32 idx;
253         struct clk *clk_ptr;
254         struct partition_clk_info *clk_info;
255
256         for (idx = 0; idx < MAX_CLK_EN_NUM; idx++) {
257                 clk_info = &pg_info->clk_info[idx];
258                 clk_ptr = clk_info->clk_ptr;
259
260                 if (!clk_ptr)
261                         break;
262
263                 if (clk_info->clk_type != CLK_ONLY)
264                         tegra_periph_reset_deassert(clk_ptr);
265         }
266 }
267
268 int tegra_powergate_reset_module(struct powergate_partition_info *pg_info)
269 {
270         int ret;
271
272         powergate_partition_assert_reset(pg_info);
273
274         udelay(10);
275
276         ret = partition_clk_enable(pg_info);
277         if (ret)
278                 return ret;
279
280         udelay(10);
281
282         powergate_partition_deassert_reset(pg_info);
283
284         partition_clk_disable(pg_info);
285
286         return 0;
287 }
288
289 bool tegra_powergate_check_clamping(int id)
290 {
291         if (!pg_ops || !pg_ops->powergate_check_clamping) {
292                 pr_info("This SOC can't check clamping status\n");
293                 return -EINVAL;
294         }
295
296         if (id < 0 || id >= pg_ops->num_powerdomains)
297                 return -EINVAL;
298
299         return pg_ops->powergate_check_clamping(id);
300 }
301
302 int tegra_powergate_remove_clamping(int id)
303 {
304         u32 mask;
305         int contention_timeout = 100;
306
307         if (!pg_ops) {
308                 pr_info("This SOC doesn't support powergating\n");
309                 return -EINVAL;
310         }
311
312         if (id < 0 || id >= pg_ops->num_powerdomains)
313                 return -EINVAL;
314
315         /*
316          * PCIE and VDE clamping masks are swapped with respect to their
317          * partition ids
318          */
319         if (id ==  TEGRA_POWERGATE_VDEC)
320                 mask = (1 << TEGRA_POWERGATE_PCIE);
321         else if (id == TEGRA_POWERGATE_PCIE)
322                 mask = (1 << TEGRA_POWERGATE_VDEC);
323         else
324                 mask = (1 << id);
325
326         pmc_write(mask, REMOVE_CLAMPING);
327         /* Wait until clamp is removed */
328         do {
329                 udelay(1);
330                 contention_timeout--;
331         } while ((contention_timeout > 0)
332                         && (pmc_read(REMOVE_CLAMPING) & mask));
333
334         WARN(contention_timeout <= 0, "Couldn't remove clamping");
335
336         return 0;
337 }
338
339 static inline bool tegra_powergate_check_skip_list(int id)
340 {
341         return pg_ops->powergate_skip ?
342                 pg_ops->powergate_skip(id) : false;
343 }
344
345 /* EXTERNALY VISIBLE APIS */
346
347 bool tegra_powergate_is_powered(int id)
348 {
349         u32 status;
350
351         if (!pg_ops) {
352                 pr_info("This SOC doesn't support powergating\n");
353                 return -EINVAL;
354         }
355
356         if (id < 0 || id >= pg_ops->num_powerdomains)
357                 return -EINVAL;
358
359         status = pmc_read(PWRGATE_STATUS) & (1 << id);
360
361         return !!status;
362 }
363 EXPORT_SYMBOL(tegra_powergate_is_powered);
364
365 int tegra_cpu_powergate_id(int cpuid)
366 {
367         if (!pg_ops) {
368                 pr_info("This SOC doesn't support powergating\n");
369                 return -EINVAL;
370         }
371
372         if (cpuid < 0 || cpuid >= pg_ops->num_cpu_domains) {
373                 pr_info("%s: invalid powergate id\n", __func__);
374                 return -EINVAL;
375         }
376
377         if (pg_ops->cpu_domains)
378                 return pg_ops->cpu_domains[cpuid];
379         else
380                 WARN_ON_ONCE("This SOC does not support CPU powergate\n");
381
382         return -EINVAL;
383 }
384 EXPORT_SYMBOL(tegra_cpu_powergate_id);
385
386 int tegra_powergate_partition(int id)
387 {
388         if (!pg_ops) {
389                 pr_info("This SOC doesn't support powergating\n");
390                 return -EINVAL;
391         }
392
393         if (id < 0 || id >= pg_ops->num_powerdomains) {
394                 pr_info("%s: invalid powergate id\n", __func__);
395                 return -EINVAL;
396         }
397
398         if (tegra_powergate_check_skip_list(id))
399                 printk_once("%s: %s is in powergate skip list\n", __func__,
400                         tegra_powergate_get_name(id));
401
402         if (pg_ops->powergate_partition)
403                 return pg_ops->powergate_partition(id);
404         else
405                 WARN_ON_ONCE("This SOC doesn't support powergating");
406
407         return -EINVAL;
408 }
409 EXPORT_SYMBOL(tegra_powergate_partition);
410
411 int tegra_unpowergate_partition(int id)
412 {
413         if (!pg_ops) {
414                 pr_info("This SOC doesn't support powergating\n");
415                 return -EINVAL;
416         }
417
418         if (id < 0 || id >= pg_ops->num_powerdomains) {
419                 pr_info("%s: invalid powergate id\n", __func__);
420                 return -EINVAL;
421         }
422
423         if (tegra_powergate_check_skip_list(id))
424                 printk_once("%s: %s is in powergate skip list\n", __func__,
425                         tegra_powergate_get_name(id));
426
427         if (pg_ops->unpowergate_partition)
428                 return pg_ops->unpowergate_partition(id);
429         else
430                 WARN_ON_ONCE("This SOC doesn't support un-powergating");
431
432         return -EINVAL;
433 }
434 EXPORT_SYMBOL(tegra_unpowergate_partition);
435
436 int tegra_powergate_partition_with_clk_off(int id)
437 {
438         if (!pg_ops) {
439                 pr_info("This SOC doesn't support powergating\n");
440                 return -EINVAL;
441         }
442
443         if (id < 0 || id >= pg_ops->num_powerdomains) {
444                 pr_info("%s: invalid powergate id\n", __func__);
445                 return -EINVAL;
446         }
447
448         if (tegra_powergate_check_skip_list(id))
449                 printk_once("%s: %s is in powergate skip list\n", __func__,
450                         tegra_powergate_get_name(id));
451
452         if (pg_ops->powergate_partition_with_clk_off)
453                 return pg_ops->powergate_partition_with_clk_off(id);
454         else
455                 WARN_ON_ONCE("This SOC doesn't support powergating with clk off");
456
457         return -EINVAL;
458 }
459 EXPORT_SYMBOL(tegra_powergate_partition_with_clk_off);
460
461 int tegra_unpowergate_partition_with_clk_on(int id)
462 {
463         if (!pg_ops) {
464                 pr_info("This SOC doesn't support powergating\n");
465                 return -EINVAL;
466         }
467
468         if (id < 0 || id >= pg_ops->num_powerdomains) {
469                 pr_info("%s: invalid powergate id\n", __func__);
470                 return -EINVAL;
471         }
472
473         if (tegra_powergate_check_skip_list(id))
474                 printk_once("%s: %s is in powergate skip list\n", __func__,
475                         tegra_powergate_get_name(id));
476
477         if (pg_ops->unpowergate_partition_with_clk_on)
478                 return pg_ops->unpowergate_partition_with_clk_on(id);
479         else
480                 WARN_ON_ONCE("This SOC doesn't support power un-gating with clk on");
481
482         return -EINVAL;
483 }
484 EXPORT_SYMBOL(tegra_unpowergate_partition_with_clk_on);
485
486 int tegra_powergate_mc_enable(int id)
487 {
488         if (!pg_ops) {
489                 pr_info("This SOC doesn't support powergating\n");
490                 return -EINVAL;
491         }
492
493         if (id < 0 || id >= pg_ops->num_powerdomains) {
494                 pr_info("%s: invalid powergate id\n", __func__);
495                 return -EINVAL;
496         }
497
498         if (pg_ops->powergate_mc_enable)
499                 return pg_ops->powergate_mc_enable(id);
500         else
501                 WARN_ON_ONCE("This SOC does not support powergate mc enable");
502
503         return -EINVAL;
504 }
505 EXPORT_SYMBOL(tegra_powergate_mc_enable);
506
507 int tegra_powergate_mc_disable(int id)
508 {
509         if (!pg_ops) {
510                 pr_info("This SOC doesn't support powergating\n");
511                 return -EINVAL;
512         }
513
514         if (id < 0 || id >= pg_ops->num_powerdomains) {
515                 pr_info("%s: invalid powergate id\n", __func__);
516                 return -EINVAL;
517         }
518
519         if (pg_ops->powergate_mc_disable)
520                 return pg_ops->powergate_mc_disable(id);
521         else
522                 WARN_ON_ONCE("This SOC does not support powergate mc disable");
523
524         return -EINVAL;
525 }
526 EXPORT_SYMBOL(tegra_powergate_mc_disable);
527
528 int tegra_powergate_mc_flush(int id)
529 {
530         if (!pg_ops) {
531                 pr_info("This SOC doesn't support powergating\n");
532                 return -EINVAL;
533         }
534
535         if (id < 0 || id >= pg_ops->num_powerdomains) {
536                 pr_info("%s: invalid powergate id\n", __func__);
537                 return -EINVAL;
538         }
539
540         if (pg_ops->powergate_mc_flush)
541                 return pg_ops->powergate_mc_flush(id);
542         else
543                 WARN_ON_ONCE("This SOC does not support powergate mc flush");
544
545         return -EINVAL;
546 }
547 EXPORT_SYMBOL(tegra_powergate_mc_flush);
548
549 int tegra_powergate_mc_flush_done(int id)
550 {
551         if (!pg_ops) {
552                 pr_info("This SOC doesn't support powergating\n");
553                 return -EINVAL;
554         }
555
556         if (id < 0 || id >= pg_ops->num_powerdomains) {
557                 pr_info("%s: invalid powergate id\n", __func__);
558                 return -EINVAL;
559         }
560
561         if (pg_ops->powergate_mc_flush_done)
562                 return pg_ops->powergate_mc_flush_done(id);
563         else
564                 WARN_ON_ONCE("This SOC does not support powergate mc flush done");
565
566         return -EINVAL;
567 }
568 EXPORT_SYMBOL(tegra_powergate_mc_flush_done);
569
570 const char *tegra_powergate_get_name(int id)
571 {
572         if (!pg_ops) {
573                 pr_info("This SOC doesn't support powergating\n");
574                 return NULL;
575         }
576
577         if (id < 0 || id >= pg_ops->num_powerdomains) {
578                 pr_info("invalid powergate id\n");
579                 return "invalid";
580         }
581
582         if (pg_ops->get_powergate_domain_name)
583                 return pg_ops->get_powergate_domain_name(id);
584         else
585                 WARN_ON_ONCE("This SOC does not support CPU powergate");
586
587         return "invalid";
588 }
589 EXPORT_SYMBOL(tegra_powergate_get_name);
590
591 int tegra_powergate_init_refcount(void)
592 {
593         if ((!pg_ops) || (!pg_ops->powergate_init_refcount))
594                 return 0;
595
596         return pg_ops->powergate_init_refcount();
597 }
598
599 int __init tegra_powergate_init(void)
600 {
601         switch (tegra_chip_id) {
602                 case TEGRA_CHIPID_TEGRA2:
603                         pg_ops = tegra2_powergate_init_chip_support();
604                         break;
605
606                 case TEGRA_CHIPID_TEGRA3:
607                         pg_ops = tegra3_powergate_init_chip_support();
608                         break;
609
610                 case TEGRA_CHIPID_TEGRA11:
611                         pg_ops = tegra11x_powergate_init_chip_support();
612                         break;
613
614                 case TEGRA_CHIPID_TEGRA14:
615                         pg_ops = tegra14x_powergate_init_chip_support();
616                         break;
617
618                 case TEGRA_CHIPID_TEGRA12:
619                         pg_ops = tegra12x_powergate_init_chip_support();
620                         break;
621
622                 default:
623                         pg_ops = NULL;
624                         pr_info("%s: Unknown Tegra variant. Disabling powergate\n", __func__);
625                         break;
626         }
627
628         tegra_powergate_init_refcount();
629
630         pr_info("%s: DONE\n", __func__);
631
632         return (pg_ops ? 0 : -EINVAL);
633 }
634
635 #ifdef CONFIG_DEBUG_FS
636
637 static int powergate_show(struct seq_file *s, void *data)
638 {
639         int i;
640         const char *name;
641         bool is_pg_skip;
642
643         if (!pg_ops) {
644                 seq_printf(s, "This SOC doesn't support powergating\n");
645                 return -EINVAL;
646         }
647
648         seq_printf(s, " powergate powered\n");
649         seq_printf(s, "------------------\n");
650
651         for (i = 0; i < pg_ops->num_powerdomains; i++) {
652                 name = tegra_powergate_get_name(i);
653                 if (name) {
654                         is_pg_skip = tegra_powergate_check_skip_list(i);
655                         seq_printf(s, " %9s %7s\n", name,
656                                 (is_pg_skip ? "skip" : \
657                                 (tegra_powergate_is_powered(i) ? \
658                                 "yes" : "no")));
659                 }
660         }
661
662         return 0;
663 }
664
665 static int powergate_open(struct inode *inode, struct file *file)
666 {
667         return single_open(file, powergate_show, inode->i_private);
668 }
669
670 static const struct file_operations powergate_fops = {
671         .open           = powergate_open,
672         .read           = seq_read,
673         .llseek         = seq_lseek,
674         .release        = single_release,
675 };
676
677 int __init tegra_powergate_debugfs_init(void)
678 {
679         struct dentry *d;
680
681         d = debugfs_create_file("powergate", S_IRUGO, NULL, NULL,
682                 &powergate_fops);
683         if (!d)
684                 return -ENOMEM;
685
686         return 0;
687 }
688
689 #endif