video: tegra: dc: fix the logic for dis ref-count.
[linux-3.10.git] / arch / arm / mach-tegra / powergate.c
1 /*
2  * arch/arm/mach-tegra/powergate.c
3  *
4  * Copyright (c) 2010 Google, Inc
5  * Copyright (c) 2011 - 2013, NVIDIA CORPORATION.  All rights reserved.
6  *
7  * Author:
8  *      Colin Cross <ccross@google.com>
9  *
10  * This software is licensed under the terms of the GNU General Public
11  * License version 2, as published by the Free Software Foundation, and
12  * may be copied, distributed, and modified under those terms.
13  *
14  * This program is distributed in the hope that it will be useful,
15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
17  * GNU General Public License for more details.
18  *
19  */
20
21 #include <linux/kernel.h>
22 #include <linux/module.h>
23 #include <linux/clk.h>
24 #include <linux/string.h>
25 #include <linux/debugfs.h>
26 #include <linux/delay.h>
27 #include <linux/err.h>
28 #include <linux/init.h>
29 #include <linux/io.h>
30 #include <linux/seq_file.h>
31 #include <linux/spinlock.h>
32 #include <linux/clk/tegra.h>
33 #include <trace/events/power.h>
34 #include <asm/atomic.h>
35
36 #include <mach/powergate.h>
37 #include <mach/hardware.h>
38
39 #include "clock.h"
40 #include "fuse.h"
41 #include "iomap.h"
42 #include "powergate-priv.h"
43
44 static struct powergate_ops *pg_ops;
45
46 #ifndef CONFIG_TEGRA_SIMULATION_PLATFORM
47 static spinlock_t *tegra_get_powergate_lock(void)
48 {
49         if (pg_ops && pg_ops->get_powergate_lock)
50                 return pg_ops->get_powergate_lock();
51         else
52                 WARN_ON_ONCE("This SOC does not export powergate lock");
53
54         return NULL;
55 }
56 #endif
57
58 int tegra_powergate_set(int id, bool new_state)
59 {
60 #ifndef CONFIG_TEGRA_SIMULATION_PLATFORM
61         bool status;
62         unsigned long flags;
63         spinlock_t *lock = tegra_get_powergate_lock();
64
65         /* 10us timeout for toggle operation if it takes affect*/
66         int toggle_timeout = 10;
67
68         /* 100 * 10 = 1000us timeout for toggle command to take affect in case
69            of contention with h/w initiated CPU power gating */
70         int contention_timeout = 100;
71
72         spin_lock_irqsave(lock, flags);
73
74         status = !!(pmc_read(PWRGATE_STATUS) & (1 << id));
75
76         if (status == new_state) {
77                 spin_unlock_irqrestore(lock, flags);
78                 return 0;
79         }
80
81         if (TEGRA_IS_CPU_POWERGATE_ID(id)) {
82                 /* CPU ungated in s/w only during boot/resume with outer
83                    waiting loop and no contention from other CPUs */
84                 pmc_write(PWRGATE_TOGGLE_START | id, PWRGATE_TOGGLE);
85                 spin_unlock_irqrestore(lock, flags);
86                 return 0;
87         }
88
89         pmc_write(PWRGATE_TOGGLE_START | id, PWRGATE_TOGGLE);
90         do {
91                 do {
92                         udelay(1);
93                         status = !!(pmc_read(PWRGATE_STATUS) & (1 << id));
94
95                         toggle_timeout--;
96                 } while ((status != new_state) && (toggle_timeout > 0));
97
98                 contention_timeout--;
99         } while ((status != new_state) && (contention_timeout > 0));
100
101         spin_unlock_irqrestore(lock, flags);
102
103         if (status != new_state) {
104                 WARN(1, "Could not set powergate %d to %d", id, new_state);
105                 return -EBUSY;
106         }
107
108         trace_power_domain_target(tegra_powergate_get_name(id), new_state,
109                         raw_smp_processor_id());
110 #endif
111
112         return 0;
113 }
114
115 int is_partition_clk_disabled(struct powergate_partition_info *pg_info)
116 {
117         u32 idx;
118         struct clk *clk;
119         struct partition_clk_info *clk_info;
120         int ret = 0;
121
122         for (idx = 0; idx < MAX_CLK_EN_NUM; idx++) {
123                 clk_info = &pg_info->clk_info[idx];
124                 clk = clk_info->clk_ptr;
125
126                 if (!clk)
127                         break;
128
129                 if (clk_info->clk_type != RST_ONLY) {
130                         if (tegra_is_clk_enabled(clk)) {
131                                 ret = -1;
132                                 break;
133                         }
134                 }
135         }
136
137         return ret;
138 }
139
140 int powergate_module(int id)
141 {
142         if (!pg_ops) {
143                 pr_info("This SOC doesn't support powergating\n");
144                 return -EINVAL;
145         }
146
147         if (id < 0 || id >= pg_ops->num_powerdomains)
148                 return -EINVAL;
149
150         tegra_powergate_mc_flush(id);
151
152         return tegra_powergate_set(id, false);
153 }
154
155 int unpowergate_module(int id)
156 {
157         if (!pg_ops) {
158                 pr_info("This SOC doesn't support powergating\n");
159                 return -EINVAL;
160         }
161
162         if (id < 0 || id >= pg_ops->num_powerdomains)
163                 return -EINVAL;
164
165         return tegra_powergate_set(id, true);
166 }
167
168 int partition_clk_enable(struct powergate_partition_info *pg_info)
169 {
170         int ret;
171         u32 idx;
172         struct clk *clk;
173         struct partition_clk_info *clk_info;
174
175         for (idx = 0; idx < MAX_CLK_EN_NUM; idx++) {
176                 clk_info = &pg_info->clk_info[idx];
177                 clk = clk_info->clk_ptr;
178                 if (!clk)
179                         break;
180
181                 if (clk_info->clk_type != RST_ONLY) {
182                         ret = tegra_clk_prepare_enable(clk);
183                         if (ret)
184                                 goto err_clk_en;
185                 }
186         }
187
188         return 0;
189
190 err_clk_en:
191         WARN(1, "Could not enable clk %s, error %d", clk->name, ret);
192         while (idx--) {
193                 clk_info = &pg_info->clk_info[idx];
194                 if (clk_info->clk_type != RST_ONLY)
195                         tegra_clk_disable_unprepare(clk_info->clk_ptr);
196         }
197
198         return ret;
199 }
200
201 void partition_clk_disable(struct powergate_partition_info *pg_info)
202 {
203         u32 idx;
204         struct clk *clk;
205         struct partition_clk_info *clk_info;
206
207         for (idx = 0; idx < MAX_CLK_EN_NUM; idx++) {
208                 clk_info = &pg_info->clk_info[idx];
209                 clk = clk_info->clk_ptr;
210
211                 if (!clk)
212                         break;
213
214                 if (clk_info->clk_type != RST_ONLY)
215                         tegra_clk_disable_unprepare(clk);
216         }
217 }
218
219 void get_clk_info(struct powergate_partition_info *pg_info)
220 {
221         int idx;
222
223         for (idx = 0; idx < MAX_CLK_EN_NUM; idx++) {
224                 if (!pg_info->clk_info[idx].clk_name)
225                         break;
226
227                 pg_info->clk_info[idx].clk_ptr = tegra_get_clock_by_name(
228                         pg_info->clk_info[idx].clk_name);
229         }
230 }
231
232 void powergate_partition_assert_reset(struct powergate_partition_info *pg_info)
233 {
234         u32 idx;
235         struct clk *clk_ptr;
236         struct partition_clk_info *clk_info;
237
238         for (idx = 0; idx < MAX_CLK_EN_NUM; idx++) {
239                 clk_info = &pg_info->clk_info[idx];
240                 clk_ptr = clk_info->clk_ptr;
241
242                 if (!clk_ptr)
243                         break;
244
245                 if (clk_info->clk_type != CLK_ONLY)
246                         tegra_periph_reset_assert(clk_ptr);
247         }
248 }
249
250 void powergate_partition_deassert_reset(struct powergate_partition_info *pg_info)
251 {
252         u32 idx;
253         struct clk *clk_ptr;
254         struct partition_clk_info *clk_info;
255
256         for (idx = 0; idx < MAX_CLK_EN_NUM; idx++) {
257                 clk_info = &pg_info->clk_info[idx];
258                 clk_ptr = clk_info->clk_ptr;
259
260                 if (!clk_ptr)
261                         break;
262
263                 if (clk_info->clk_type != CLK_ONLY)
264                         tegra_periph_reset_deassert(clk_ptr);
265         }
266 }
267
268 int tegra_powergate_reset_module(struct powergate_partition_info *pg_info)
269 {
270         int ret;
271
272         powergate_partition_assert_reset(pg_info);
273
274         udelay(10);
275
276         ret = partition_clk_enable(pg_info);
277         if (ret)
278                 return ret;
279
280         udelay(10);
281
282         powergate_partition_deassert_reset(pg_info);
283
284         partition_clk_disable(pg_info);
285
286         return 0;
287 }
288
289 int tegra_powergate_remove_clamping(int id)
290 {
291         u32 mask;
292         int contention_timeout = 100;
293
294         if (!pg_ops) {
295                 pr_info("This SOC doesn't support powergating\n");
296                 return -EINVAL;
297         }
298
299         if (id < 0 || id >= pg_ops->num_powerdomains)
300                 return -EINVAL;
301
302         /*
303          * PCIE and VDE clamping masks are swapped with respect to their
304          * partition ids
305          */
306         if (id ==  TEGRA_POWERGATE_VDEC)
307                 mask = (1 << TEGRA_POWERGATE_PCIE);
308         else if (id == TEGRA_POWERGATE_PCIE)
309                 mask = (1 << TEGRA_POWERGATE_VDEC);
310         else
311                 mask = (1 << id);
312
313         pmc_write(mask, REMOVE_CLAMPING);
314         /* Wait until clamp is removed */
315         do {
316                 udelay(1);
317                 contention_timeout--;
318         } while ((contention_timeout > 0)
319                         && (pmc_read(REMOVE_CLAMPING) & mask));
320
321         WARN(contention_timeout <= 0, "Couldn't remove clamping");
322
323         return 0;
324 }
325
326 /* EXTERNALY VISIBLE APIS */
327
328 bool tegra_powergate_is_powered(int id)
329 {
330         u32 status;
331
332         if (!pg_ops) {
333                 pr_info("This SOC doesn't support powergating\n");
334                 return -EINVAL;
335         }
336
337         if (id < 0 || id >= pg_ops->num_powerdomains)
338                 return -EINVAL;
339
340         status = pmc_read(PWRGATE_STATUS) & (1 << id);
341
342         return !!status;
343 }
344 EXPORT_SYMBOL(tegra_powergate_is_powered);
345
346 int tegra_cpu_powergate_id(int cpuid)
347 {
348         if (!pg_ops) {
349                 pr_info("This SOC doesn't support powergating\n");
350                 return -EINVAL;
351         }
352
353         if (cpuid < 0 || cpuid >= pg_ops->num_cpu_domains) {
354                 pr_info("%s: invalid powergate id\n", __func__);
355                 return -EINVAL;
356         }
357
358         if (pg_ops->cpu_domains)
359                 return pg_ops->cpu_domains[cpuid];
360         else
361                 WARN_ON_ONCE("This SOC does not support CPU powergate\n");
362
363         return -EINVAL;
364 }
365 EXPORT_SYMBOL(tegra_cpu_powergate_id);
366
367 int tegra_powergate_partition(int id)
368 {
369         if (!pg_ops) {
370                 pr_info("This SOC doesn't support powergating\n");
371                 return -EINVAL;
372         }
373
374         if (id < 0 || id >= pg_ops->num_powerdomains) {
375                 pr_info("%s: invalid powergate id\n", __func__);
376                 return -EINVAL;
377         }
378
379         if (pg_ops->powergate_partition)
380                 return pg_ops->powergate_partition(id);
381         else
382                 WARN_ON_ONCE("This SOC doesn't support powergating");
383
384         return -EINVAL;
385 }
386 EXPORT_SYMBOL(tegra_powergate_partition);
387
388 int tegra_unpowergate_partition(int id)
389 {
390         if (!pg_ops) {
391                 pr_info("This SOC doesn't support powergating\n");
392                 return -EINVAL;
393         }
394
395         if (id < 0 || id >= pg_ops->num_powerdomains) {
396                 pr_info("%s: invalid powergate id\n", __func__);
397                 return -EINVAL;
398         }
399
400         if (pg_ops->unpowergate_partition)
401                 return pg_ops->unpowergate_partition(id);
402         else
403                 WARN_ON_ONCE("This SOC doesn't support un-powergating");
404
405         return -EINVAL;
406 }
407 EXPORT_SYMBOL(tegra_unpowergate_partition);
408
409 int tegra_powergate_partition_with_clk_off(int id)
410 {
411         if (!pg_ops) {
412                 pr_info("This SOC doesn't support powergating\n");
413                 return -EINVAL;
414         }
415
416         if (id < 0 || id >= pg_ops->num_powerdomains) {
417                 pr_info("%s: invalid powergate id\n", __func__);
418                 return -EINVAL;
419         }
420
421         if (pg_ops->powergate_partition_with_clk_off)
422                 return pg_ops->powergate_partition_with_clk_off(id);
423         else
424                 WARN_ON_ONCE("This SOC doesn't support powergating with clk off");
425
426         return -EINVAL;
427 }
428 EXPORT_SYMBOL(tegra_powergate_partition_with_clk_off);
429
430 int tegra_unpowergate_partition_with_clk_on(int id)
431 {
432         if (!pg_ops) {
433                 pr_info("This SOC doesn't support powergating\n");
434                 return -EINVAL;
435         }
436
437         if (id < 0 || id >= pg_ops->num_powerdomains) {
438                 pr_info("%s: invalid powergate id\n", __func__);
439                 return -EINVAL;
440         }
441
442         if (pg_ops->unpowergate_partition_with_clk_on)
443                 return pg_ops->unpowergate_partition_with_clk_on(id);
444         else
445                 WARN_ON_ONCE("This SOC doesn't support power un-gating with clk on");
446
447         return -EINVAL;
448 }
449 EXPORT_SYMBOL(tegra_unpowergate_partition_with_clk_on);
450
451 int tegra_powergate_mc_enable(int id)
452 {
453         if (!pg_ops) {
454                 pr_info("This SOC doesn't support powergating\n");
455                 return -EINVAL;
456         }
457
458         if (id < 0 || id >= pg_ops->num_powerdomains) {
459                 pr_info("%s: invalid powergate id\n", __func__);
460                 return -EINVAL;
461         }
462
463         if (pg_ops->powergate_mc_enable)
464                 return pg_ops->powergate_mc_enable(id);
465         else
466                 WARN_ON_ONCE("This SOC does not support powergate mc enable");
467
468         return -EINVAL;
469 }
470 EXPORT_SYMBOL(tegra_powergate_mc_enable);
471
472 int tegra_powergate_mc_disable(int id)
473 {
474         if (!pg_ops) {
475                 pr_info("This SOC doesn't support powergating\n");
476                 return -EINVAL;
477         }
478
479         if (id < 0 || id >= pg_ops->num_powerdomains) {
480                 pr_info("%s: invalid powergate id\n", __func__);
481                 return -EINVAL;
482         }
483
484         if (pg_ops->powergate_mc_disable)
485                 return pg_ops->powergate_mc_disable(id);
486         else
487                 WARN_ON_ONCE("This SOC does not support powergate mc disable");
488
489         return -EINVAL;
490 }
491 EXPORT_SYMBOL(tegra_powergate_mc_disable);
492
493 int tegra_powergate_mc_flush(int id)
494 {
495         if (!pg_ops) {
496                 pr_info("This SOC doesn't support powergating\n");
497                 return -EINVAL;
498         }
499
500         if (id < 0 || id >= pg_ops->num_powerdomains) {
501                 pr_info("%s: invalid powergate id\n", __func__);
502                 return -EINVAL;
503         }
504
505         if (pg_ops->powergate_mc_flush)
506                 return pg_ops->powergate_mc_flush(id);
507         else
508                 WARN_ON_ONCE("This SOC does not support powergate mc flush");
509
510         return -EINVAL;
511 }
512 EXPORT_SYMBOL(tegra_powergate_mc_flush);
513
514 int tegra_powergate_mc_flush_done(int id)
515 {
516         if (!pg_ops) {
517                 pr_info("This SOC doesn't support powergating\n");
518                 return -EINVAL;
519         }
520
521         if (id < 0 || id >= pg_ops->num_powerdomains) {
522                 pr_info("%s: invalid powergate id\n", __func__);
523                 return -EINVAL;
524         }
525
526         if (pg_ops->powergate_mc_flush_done)
527                 return pg_ops->powergate_mc_flush_done(id);
528         else
529                 WARN_ON_ONCE("This SOC does not support powergate mc flush done");
530
531         return -EINVAL;
532 }
533 EXPORT_SYMBOL(tegra_powergate_mc_flush_done);
534
535 const char *tegra_powergate_get_name(int id)
536 {
537         if (!pg_ops) {
538                 pr_info("This SOC doesn't support powergating\n");
539                 return NULL;
540         }
541
542         if (id < 0 || id >= pg_ops->num_powerdomains) {
543                 pr_info("invalid powergate id\n");
544                 return "invalid";
545         }
546
547         if (pg_ops->get_powergate_domain_name)
548                 return pg_ops->get_powergate_domain_name(id);
549         else
550                 WARN_ON_ONCE("This SOC does not support CPU powergate");
551
552         return "invalid";
553 }
554 EXPORT_SYMBOL(tegra_powergate_get_name);
555
556 int tegra_powergate_init_refcount(void)
557 {
558         if (!pg_ops->powergate_init_refcount)
559                 return 0;
560
561         return pg_ops->powergate_init_refcount();
562 }
563
564 int __init tegra_powergate_init(void)
565 {
566         switch (tegra_chip_id) {
567                 case TEGRA_CHIPID_TEGRA2:
568                         pg_ops = tegra2_powergate_init_chip_support();
569                         break;
570
571                 case TEGRA_CHIPID_TEGRA3:
572                         pg_ops = tegra3_powergate_init_chip_support();
573                         break;
574
575                 case TEGRA_CHIPID_TEGRA11:
576                         pg_ops = tegra11x_powergate_init_chip_support();
577                         break;
578
579                 case TEGRA_CHIPID_TEGRA14:
580                         pg_ops = tegra14x_powergate_init_chip_support();
581                         break;
582
583                 default:
584                         pg_ops = NULL;
585                         pr_info("%s: Unknown Tegra variant. Disabling powergate\n", __func__);
586                         break;
587         }
588
589         tegra_powergate_init_refcount();
590
591         pr_info("%s: DONE\n", __func__);
592
593         return (pg_ops ? 0 : -EINVAL);
594 }
595
596 #ifdef CONFIG_DEBUG_FS
597
598 static int powergate_show(struct seq_file *s, void *data)
599 {
600         int i;
601         const char *name;
602
603         if (!pg_ops) {
604                 seq_printf(s, "This SOC doesn't support powergating\n");
605                 return -EINVAL;
606         }
607
608         seq_printf(s, " powergate powered\n");
609         seq_printf(s, "------------------\n");
610
611         for (i = 0; i < pg_ops->num_powerdomains; i++) {
612                 name = tegra_powergate_get_name(i);
613                 if (name)
614                         seq_printf(s, " %9s %7s\n", name,
615                                 tegra_powergate_is_powered(i) ? "yes" : "no");
616         }
617
618         return 0;
619 }
620
621 static int powergate_open(struct inode *inode, struct file *file)
622 {
623         return single_open(file, powergate_show, inode->i_private);
624 }
625
626 static const struct file_operations powergate_fops = {
627         .open           = powergate_open,
628         .read           = seq_read,
629         .llseek         = seq_lseek,
630         .release        = single_release,
631 };
632
633 int __init tegra_powergate_debugfs_init(void)
634 {
635         struct dentry *d;
636
637         d = debugfs_create_file("powergate", S_IRUGO, NULL, NULL,
638                 &powergate_fops);
639         if (!d)
640                 return -ENOMEM;
641
642         return 0;
643 }
644
645 #endif