ARM: tegra: loki: fix build error due to warning
[linux-3.10.git] / arch / arm / mach-tegra / powerdetect.c
1 /*
2  * arch/arm/mach-tegra/powerdetect.c
3  *
4  * Copyright (c) 2011 - 2013, NVIDIA CORPORATION.  All rights reserved.
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License as published by
8  * the Free Software Foundation; version 2 of the License
9  *
10  * This program is distributed in the hope that it will be useful, but WITHOUT
11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13  * more details.
14  *
15  * You should have received a copy of the GNU General Public License along
16  * with this program; if not, write to the Free Software Foundation, Inc.,
17  * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
18  */
19
20 #include <linux/kernel.h>
21 #include <linux/delay.h>
22 #include <linux/spinlock.h>
23 #include <linux/io.h>
24 #include <linux/err.h>
25 #include <linux/notifier.h>
26 #include <linux/regulator/consumer.h>
27 #include <linux/module.h>
28 #include <linux/tegra-soc.h>
29
30 #include "board.h"
31 #include "fuse.h"
32 #include "iomap.h"
33
34 #define PMC_PWR_IO_DISABLE      0x44
35 #define PMC_PWR_DET_ENABLE      0x48
36 #define PMC_PWR_DET_LATCH       0x4C
37 #define PMC_PWR_DET_VAL         0xE4
38
39 struct pwr_detect_cell {
40         const char              *reg_id;
41         u32                     pwrdet_mask;
42         u32                     pwrio_mask;
43         u32                     package_mask;
44
45         struct notifier_block   regulator_nb;
46 };
47
48 static bool pwrdet_rails_found;
49 static bool pwrdet_always_on;
50 static bool pwrio_always_on;
51 static u32 pwrdet_val;
52 static u32 pwrio_val;
53 static u32 pwrio_disabled_mask;
54
55 static DEFINE_SPINLOCK(pwr_lock);
56
57 static void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
58
59 static inline void pmc_writel(u32 val, unsigned long addr)
60 {
61         writel(val, pmc_base + addr);
62 }
63 static inline u32 pmc_readl(unsigned long addr)
64 {
65         return readl(pmc_base + addr);
66 }
67
68
69 #define POWER_CELL(_reg_id, _pwrdet_mask, _pwrio_mask, _package_mask)   \
70         {                                                               \
71                 .reg_id = _reg_id,                                      \
72                 .pwrdet_mask = _pwrdet_mask,                            \
73                 .pwrio_mask = _pwrio_mask,                              \
74                 .package_mask = _package_mask,                          \
75         }
76
77 /* Some IO pads does not have power detect cells, but still can/should be
78  * turned off when no power - set pwrdet_mask=0 for such pads */
79 static struct pwr_detect_cell pwr_detect_cells[] = {
80 #ifndef CONFIG_ARCH_TEGRA_14x_SOC
81         POWER_CELL("pwrdet_nand",       (0x1 <<  1), (0x1 <<  1), 0xFFFFFFFF),
82 #endif
83         POWER_CELL("pwrdet_uart",       (0x1 <<  2), (0x1 <<  2), 0xFFFFFFFF),
84 #ifndef CONFIG_ARCH_TEGRA_14x_SOC
85         POWER_CELL("pwrdet_bb",         (0x1 <<  3), (0x1 <<  3), 0xFFFFFFFF),
86 #endif
87 #ifdef  CONFIG_ARCH_TEGRA_2x_SOC
88         POWER_CELL("pwrdet_vi",                   0, (0x1 <<  4), 0xFFFFFFFF),
89 #elif defined(CONFIG_ARCH_TEGRA_3x_SOC)
90         /* Tegra3 VI is connected on MID package only (id = 1, mask = 0x2) */
91         POWER_CELL("pwrdet_vi",                   0, (0x1 <<  4), 0x00000002),
92 #endif
93         POWER_CELL("pwrdet_audio",      (0x1 <<  5), (0x1 <<  5), 0xFFFFFFFF),
94 #if defined(CONFIG_ARCH_TEGRA_2x_SOC) || defined(CONFIG_ARCH_TEGRA_3x_SOC)
95         POWER_CELL("pwrdet_lcd",        (0x1 <<  6), (0x1 <<  6), 0xFFFFFFFF),
96 #endif
97 #ifdef  CONFIG_ARCH_TEGRA_2x_SOC
98         POWER_CELL("pwrdet_sd",                   0, (0x1 <<  8), 0xFFFFFFFF),
99 #endif
100 #ifndef CONFIG_ARCH_TEGRA_14x_SOC
101         POWER_CELL("pwrdet_mipi",                 0, (0x1 <<  9), 0xFFFFFFFF),
102 #endif
103 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
104         POWER_CELL("pwrdet_cam",        (0x1 << 10), (0x1 << 10), 0xFFFFFFFF),
105 #if defined(CONFIG_ARCH_TEGRA_3x_SOC) || defined(CONFIG_ARCH_TEGRA_12x_SOC)
106         POWER_CELL("pwrdet_pex_ctl",    (0x1 << 11), (0x1 << 11), 0xFFFFFFFF),
107 #endif
108         POWER_CELL("pwrdet_sdmmc1",     (0x1 << 12), (0x1 << 12), 0xFFFFFFFF),
109         POWER_CELL("pwrdet_sdmmc3",     (0x1 << 13), (0x1 << 13), 0xFFFFFFFF),
110         POWER_CELL("pwrdet_sdmmc4",               0, (0x1 << 14), 0xFFFFFFFF),
111 #if defined(CONFIG_ARCH_TEGRA_11x_SOC) || defined(CONFIG_ARCH_TEGRA_12x_SOC)
112         POWER_CELL("pwrdet_hv",         (0x1 << 15), (0x1 << 15), 0xFFFFFFFF),
113 #endif
114 #endif
115 };
116
117 static void pwr_detect_reset(u32 pwrdet_mask)
118 {
119         pmc_writel(pwrdet_mask, PMC_PWR_DET_ENABLE);
120         barrier();
121         pmc_writel(pwrdet_mask, PMC_PWR_DET_VAL);
122
123         pmc_readl(PMC_PWR_DET_VAL);
124         pmc_writel(0, PMC_PWR_DET_ENABLE);
125 }
126
127 static void pwr_detect_start(u32 pwrdet_mask)
128 {
129         pmc_writel(pwrdet_mask, PMC_PWR_DET_ENABLE);
130         udelay(4);
131
132         pmc_writel(1, PMC_PWR_DET_LATCH);
133         pmc_readl(PMC_PWR_DET_LATCH);
134 }
135
136 static void pwr_detect_latch(void)
137 {
138         pmc_writel(0, PMC_PWR_DET_LATCH);
139
140         pmc_readl(PMC_PWR_DET_VAL);
141         pmc_writel(0, PMC_PWR_DET_ENABLE);
142 }
143
144 static void pwr_io_enable(u32 pwrio_mask)
145 {
146         u32 val = pmc_readl(PMC_PWR_IO_DISABLE);
147         val &= ~pwrio_mask;
148         pmc_writel(val, PMC_PWR_IO_DISABLE);
149 }
150
151 static void pwr_io_disable(u32 pwrio_mask)
152 {
153         u32 val = pmc_readl(PMC_PWR_IO_DISABLE);
154         val |= pwrio_mask;
155         pmc_writel(val, PMC_PWR_IO_DISABLE);
156 }
157
158 static int pwrdet_always_on_set(const char *arg, const struct kernel_param *kp)
159 {
160         int ret;
161         unsigned long flags;
162
163         spin_lock_irqsave(&pwr_lock, flags);
164
165         ret = param_set_bool(arg, kp);
166         if (ret) {
167                 spin_unlock_irqrestore(&pwr_lock, flags);
168                 return ret;
169         }
170
171         if (pwrdet_always_on)
172                 pwr_detect_start(0xFFFFFFFF);
173         else
174                 pwr_detect_latch();
175
176         spin_unlock_irqrestore(&pwr_lock, flags);
177         return 0;
178 }
179
180 static int pwrio_always_on_set(const char *arg, const struct kernel_param *kp)
181 {
182         int ret;
183         unsigned long flags;
184
185         spin_lock_irqsave(&pwr_lock, flags);
186
187         ret = param_set_bool(arg, kp);
188         if (ret) {
189                 spin_unlock_irqrestore(&pwr_lock, flags);
190                 return ret;
191         }
192
193         if (pwrio_always_on)
194                 pwr_io_enable(0xFFFFFFFF);
195         else
196                 pwr_io_disable(pwrio_disabled_mask);
197
198         spin_unlock_irqrestore(&pwr_lock, flags);
199         return 0;
200 }
201
202 static int pwrdet_always_on_get(char *buffer, const struct kernel_param *kp)
203 {
204         return param_get_bool(buffer, kp);
205 }
206
207 static struct kernel_param_ops pwrdet_always_on_ops = {
208         .set = pwrdet_always_on_set,
209         .get = pwrdet_always_on_get,
210 };
211 static struct kernel_param_ops pwrio_always_on_ops = {
212         .set = pwrio_always_on_set,
213         .get = pwrdet_always_on_get,
214 };
215 module_param_cb(pwrdet_always_on, &pwrdet_always_on_ops,
216         &pwrdet_always_on, 0644);
217 module_param_cb(pwrio_always_on, &pwrio_always_on_ops,
218         &pwrio_always_on, 0644);
219
220 static int pwrdet_val_get(char *buffer, const struct kernel_param *kp)
221 {
222         pwrdet_val = pmc_readl(PMC_PWR_DET_VAL);
223         return param_get_ulong(buffer, kp);
224 }
225 static struct kernel_param_ops pwrdet_val_ops = {
226         .get = pwrdet_val_get,
227 };
228 module_param_cb(pwrdet_val, &pwrdet_val_ops, &pwrdet_val, 0444);
229
230 static int pwrio_val_get(char *buffer, const struct kernel_param *kp)
231 {
232         pwrio_val = pmc_readl(PMC_PWR_IO_DISABLE);
233         return param_get_ulong(buffer, kp);
234 }
235 static struct kernel_param_ops pwrio_val_ops = {
236         .get = pwrio_val_get,
237 };
238 module_param_cb(pwrio_val, &pwrio_val_ops, &pwrio_val, 0444);
239
240
241 static int pwrdet_notify_cb(
242         struct notifier_block *nb, unsigned long event, void *v)
243 {
244         unsigned long flags;
245         struct pwr_detect_cell *cell;
246
247         if (!pwrdet_rails_found)
248                 return NOTIFY_OK;
249
250         cell = container_of(nb, struct pwr_detect_cell, regulator_nb);
251
252         spin_lock_irqsave(&pwr_lock, flags);
253
254         if (event & REGULATOR_EVENT_PRE_ENABLE) {
255                 pwrio_disabled_mask &= ~cell->pwrio_mask;
256                 if (!pwrio_always_on)
257                         pwr_io_enable(cell->pwrio_mask);
258         }
259         if (event & (REGULATOR_EVENT_PRE_ENABLE |
260                      REGULATOR_EVENT_OUT_PRECHANGE)) {
261                 if (!pwrdet_always_on && cell->pwrdet_mask)
262                         pwr_detect_reset(cell->pwrdet_mask);
263         }
264         if (event & (REGULATOR_EVENT_POST_ENABLE |
265                      REGULATOR_EVENT_OUT_POSTCHANGE)) {
266                 if (!pwrdet_always_on && cell->pwrdet_mask) {
267                         pwr_detect_start(cell->pwrdet_mask);
268                         pwr_detect_latch();
269                 }
270         }
271         if (event & (REGULATOR_EVENT_DISABLE |
272                      REGULATOR_EVENT_FORCE_DISABLE)) {
273                 pwrio_disabled_mask |= cell->pwrio_mask;
274                 if (!pwrio_always_on)
275                         pwr_io_disable(cell->pwrio_mask);
276         }
277
278         pr_debug("tegra: %s: event %lu, pwrdet 0x%x, pwrio 0x%x\n",
279                 cell->reg_id, event,
280                 pmc_readl(PMC_PWR_DET_VAL), pmc_readl(PMC_PWR_IO_DISABLE));
281         spin_unlock_irqrestore(&pwr_lock, flags);
282
283         return NOTIFY_OK;
284 }
285
286 static int __init pwr_detect_cell_init_one(
287         struct pwr_detect_cell *cell, u32 *disabled_mask)
288 {
289         int ret;
290         struct regulator *regulator = regulator_get(NULL, cell->reg_id);
291
292         if (IS_ERR(regulator))
293                 return PTR_ERR(regulator);
294
295         cell->regulator_nb.notifier_call = pwrdet_notify_cb;
296         ret = regulator_register_notifier(regulator, &cell->regulator_nb);
297         if (ret) {
298                 regulator_put(regulator);
299                 return ret;
300         }
301
302         if (!regulator_is_enabled(regulator))
303                 *disabled_mask |= cell->pwrio_mask;
304
305         regulator_put(regulator);
306         return 0;
307 }
308
309 int __init tegra_pwr_detect_cell_init(void)
310 {
311         int i, ret;
312         u32 package_mask;
313         unsigned long flags;
314         bool rails_found = true;
315
316         if (!tegra_platform_is_silicon())
317                 return -ENOSYS;
318
319         i = tegra_package_id();
320         if ((i != -1) && (i & (~0x1F))) {
321                 pr_err("tegra: not supported package id %d - io power detection"
322                        " is left always on\n", i);
323                 return 0;
324         }
325         package_mask = (i == -1) ? i : (0x1 << i);
326
327         for (i = 0; i < ARRAY_SIZE(pwr_detect_cells); i++) {
328                 struct pwr_detect_cell *cell = &pwr_detect_cells[i];
329
330                 if (!(cell->package_mask & package_mask)) {
331                         pwrio_disabled_mask |= cell->pwrio_mask;
332                         continue;
333                 }
334
335                 ret = pwr_detect_cell_init_one(cell, &pwrio_disabled_mask);
336                 if (ret) {
337                         pr_err("tegra: failed to map regulator to power detect"
338                                " cell %s(%d)\n", cell->reg_id, ret);
339                         rails_found = false;
340                 }
341         }
342
343         if (!rails_found) {
344                 pr_err("tegra: failed regulators mapping - io power detection"
345                        " is left always on\n");
346                 return 0;
347         }
348         pwrdet_rails_found = true;
349
350         /* Latch initial i/o power levels, disable all detection cells
351            and not powered interfaces */
352         spin_lock_irqsave(&pwr_lock, flags);
353         if (!pwrdet_always_on)
354                 pwr_detect_latch();
355         if (!pwrio_always_on)
356                 pwr_io_disable(pwrio_disabled_mask);
357         spin_unlock_irqrestore(&pwr_lock, flags);
358
359         pr_info("tegra: started io power detection dynamic control\n");
360         pr_info("tegra: NO_IO_POWER setting 0x%x\n", pwrio_disabled_mask);
361
362         return 0;
363 }
364
365 fs_initcall(tegra_pwr_detect_cell_init);