2 * Copyright (C) 2012,2013 NVIDIA CORPORATION. All rights reserved.
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
18 #include <linux/kernel.h>
19 #include <linux/clk.h>
22 #include <linux/of_address.h>
23 #include <linux/export.h>
28 #define PMC_CTRL_INTR_LOW (1 << 17)
29 #define PMC_PWRGATE_TOGGLE 0x30
30 #define PMC_PWRGATE_TOGGLE_START (1 << 8)
31 #define PMC_REMOVE_CLAMPING 0x34
32 #define PMC_PWRGATE_STATUS 0x38
34 #define PMC_CPUPWRGOOD_TIMER 0xc8
35 #define PMC_CPUPWROFF_TIMER 0xcc
37 #define TEGRA_POWERGATE_PCIE 3
38 #define TEGRA_POWERGATE_VDEC 4
39 #define TEGRA_POWERGATE_CPU1 9
40 #define TEGRA_POWERGATE_CPU2 10
41 #define TEGRA_POWERGATE_CPU3 11
43 static u8 tegra_cpu_domains[] = {
44 0xFF, /* not available for CPU0 */
49 static DEFINE_SPINLOCK(tegra_powergate_lock);
51 static void __iomem *tegra_pmc_base;
52 static bool tegra_pmc_invert_interrupt;
53 #if defined(CONFIG_OF) && defined(CONFIG_COMMON_CLK)
54 static struct clk *tegra_pclk;
58 static struct pmc_pm_data pmc_pm_data;
60 struct pmc_pm_data *tegra_get_pm_data()
64 * Some boards have CONFIG_OF defined but no dts files
73 EXPORT_SYMBOL(tegra_get_pm_data);
75 static inline u32 tegra_pmc_readl(u32 reg)
77 return readl(tegra_pmc_base + reg);
80 static inline void tegra_pmc_writel(u32 val, u32 reg)
82 writel(val, tegra_pmc_base + reg);
85 static int tegra_pmc_get_cpu_powerdomain_id(int cpuid)
87 if (cpuid <= 0 || cpuid >= num_possible_cpus())
89 return tegra_cpu_domains[cpuid];
92 static bool tegra_pmc_powergate_is_powered(int id)
94 return (tegra_pmc_readl(PMC_PWRGATE_STATUS) >> id) & 1;
97 static int tegra_pmc_powergate_set(int id, bool new_state)
102 spin_lock_irqsave(&tegra_powergate_lock, flags);
104 old_state = tegra_pmc_powergate_is_powered(id);
105 WARN_ON(old_state == new_state);
107 tegra_pmc_writel(PMC_PWRGATE_TOGGLE_START | id, PMC_PWRGATE_TOGGLE);
109 spin_unlock_irqrestore(&tegra_powergate_lock, flags);
114 static int tegra_pmc_powergate_remove_clamping(int id)
119 * Tegra has a bug where PCIE and VDE clamping masks are
120 * swapped relatively to the partition ids.
122 if (id == TEGRA_POWERGATE_VDEC)
123 mask = (1 << TEGRA_POWERGATE_PCIE);
124 else if (id == TEGRA_POWERGATE_PCIE)
125 mask = (1 << TEGRA_POWERGATE_VDEC);
129 tegra_pmc_writel(mask, PMC_REMOVE_CLAMPING);
134 bool tegra_pmc_cpu_is_powered(int cpuid)
138 id = tegra_pmc_get_cpu_powerdomain_id(cpuid);
141 return tegra_pmc_powergate_is_powered(id);
144 int tegra_pmc_cpu_power_on(int cpuid)
148 id = tegra_pmc_get_cpu_powerdomain_id(cpuid);
151 return tegra_pmc_powergate_set(id, true);
154 int tegra_pmc_cpu_remove_clamping(int cpuid)
158 id = tegra_pmc_get_cpu_powerdomain_id(cpuid);
161 return tegra_pmc_powergate_remove_clamping(id);
164 #if defined(CONFIG_OF) && defined(CONFIG_COMMON_CLK) && defined(CONFIG_PM_SLEEP)
165 void set_power_timers(unsigned long us_on, unsigned long us_off)
167 unsigned long long ticks;
168 unsigned long long pclk;
170 static unsigned long tegra_last_pclk;
172 rate = clk_get_rate(tegra_pclk);
173 if (WARN_ON_ONCE(rate <= 0))
178 if ((rate != tegra_last_pclk)) {
179 ticks = (us_on * pclk) + 999999ull;
180 do_div(ticks, 1000000);
181 tegra_pmc_writel((unsigned long)ticks, PMC_CPUPWRGOOD_TIMER);
183 ticks = (us_off * pclk) + 999999ull;
184 do_div(ticks, 1000000);
185 tegra_pmc_writel((unsigned long)ticks, PMC_CPUPWROFF_TIMER);
188 tegra_last_pclk = pclk;
192 static const struct of_device_id matches[] __initconst = {
193 { .compatible = "nvidia,tegra124-pmc" },
194 { .compatible = "nvidia,tegra148-pmc" },
195 { .compatible = "nvidia,tegra114-pmc" },
196 { .compatible = "nvidia,tegra30-pmc" },
197 { .compatible = "nvidia,tegra20-pmc" },
201 static void tegra_pmc_parse_dt(void)
203 struct device_node *np;
205 enum tegra_suspend_mode suspend_mode;
206 u32 core_good_time[2] = {0, 0};
207 u32 lp0_vec[2] = {0, 0};
209 np = of_find_matching_node(NULL, matches);
212 tegra_pmc_base = of_iomap(np, 0);
214 tegra_pmc_invert_interrupt = of_property_read_bool(np,
215 "nvidia,invert-interrupt");
216 #if defined(CONFIG_OF) && defined(CONFIG_COMMON_CLK)
217 tegra_pclk = of_clk_get_by_name(np, "pclk");
218 WARN_ON(IS_ERR(tegra_pclk));
221 /* Grabbing the power management configurations */
222 if (of_property_read_u32(np, "nvidia,suspend-mode", &prop)) {
223 suspend_mode = TEGRA_SUSPEND_NONE;
227 suspend_mode = TEGRA_SUSPEND_LP0;
230 suspend_mode = TEGRA_SUSPEND_LP1;
233 suspend_mode = TEGRA_SUSPEND_LP2;
236 suspend_mode = TEGRA_SUSPEND_NONE;
241 if (of_property_read_u32(np, "nvidia,cpu-pwr-good-time", &prop))
242 suspend_mode = TEGRA_SUSPEND_NONE;
243 pmc_pm_data.cpu_good_time = prop;
245 if (of_property_read_u32(np, "nvidia,cpu-pwr-off-time", &prop))
246 suspend_mode = TEGRA_SUSPEND_NONE;
247 pmc_pm_data.cpu_off_time = prop;
249 if (of_property_read_u32_array(np, "nvidia,core-pwr-good-time",
250 core_good_time, ARRAY_SIZE(core_good_time)))
251 suspend_mode = TEGRA_SUSPEND_NONE;
252 pmc_pm_data.core_osc_time = core_good_time[0];
253 pmc_pm_data.core_pmu_time = core_good_time[1];
255 if (of_property_read_u32(np, "nvidia,core-pwr-off-time",
257 suspend_mode = TEGRA_SUSPEND_NONE;
258 pmc_pm_data.core_off_time = prop;
260 pmc_pm_data.corereq_high = of_property_read_bool(np,
261 "nvidia,core-power-req-active-high");
263 pmc_pm_data.sysclkreq_high = of_property_read_bool(np,
264 "nvidia,sys-clock-req-active-high");
266 pmc_pm_data.combined_req = of_property_read_bool(np,
267 "nvidia,combined-power-req");
269 pmc_pm_data.cpu_pwr_good_en = of_property_read_bool(np,
270 "nvidia,cpu-pwr-good-en");
272 if (of_property_read_u32_array(np, "nvidia,lp0-vec", lp0_vec,
273 ARRAY_SIZE(lp0_vec)))
274 if (suspend_mode == TEGRA_SUSPEND_LP0)
275 suspend_mode = TEGRA_SUSPEND_LP1;
277 pmc_pm_data.lp0_vec_phy_addr = lp0_vec[0];
278 pmc_pm_data.lp0_vec_size = lp0_vec[1];
280 pmc_pm_data.suspend_mode = suspend_mode;
283 void __init tegra_pmc_init(void)
287 tegra_pmc_parse_dt();
289 val = tegra_pmc_readl(PMC_CTRL);
290 if (tegra_pmc_invert_interrupt)
291 val |= PMC_CTRL_INTR_LOW;
293 val &= ~PMC_CTRL_INTR_LOW;
294 tegra_pmc_writel(val, PMC_CTRL);